WO2008037975A3 - Matrix multiplication - Google Patents

Matrix multiplication Download PDF

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Publication number
WO2008037975A3
WO2008037975A3 PCT/GB2007/003635 GB2007003635W WO2008037975A3 WO 2008037975 A3 WO2008037975 A3 WO 2008037975A3 GB 2007003635 W GB2007003635 W GB 2007003635W WO 2008037975 A3 WO2008037975 A3 WO 2008037975A3
Authority
WO
WIPO (PCT)
Prior art keywords
matrix
processor
output
elements
input
Prior art date
Application number
PCT/GB2007/003635
Other languages
French (fr)
Other versions
WO2008037975A2 (en
Inventor
Martin John Thompson
Original Assignee
Trw Ltd
Martin John Thompson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Trw Ltd, Martin John Thompson filed Critical Trw Ltd
Priority to EP07823926A priority Critical patent/EP2067100A2/en
Publication of WO2008037975A2 publication Critical patent/WO2008037975A2/en
Publication of WO2008037975A3 publication Critical patent/WO2008037975A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A matrix multiplication processor (1) for multiplying a first matrix with a second matrix to form an output matrix, each matrix comprising a plurality of elements in rows and columns, the matrix processor comprising: a memory (2) having a first area in which, in use, the first matrix is stored, a second area in which, in use, the second matrix is stored and a third area to which, in use, the output matrix is written, an accumulator (4) having an input and arranged to, in use, store a running total and add values at its input to the running total; a multiplier (3) having an input for two values and an output and arranged to, in use, multiply two values at its input and output the product of the two values at its output; and a control unit (5) arranged to control the operation of the matrix multiplication processor; in which the control unit is arranged, such that in use, it repeatedly chooses (102) an element from the first matrix and an element from the second matrix, causes the elements thus chosen to be passed (104) to the multiplier (3) and causes (106) the resultant product to be passed to the accumulator (4) to be added to the running total; wherein the elements of each matrix are stored, in use, in sequential memory locations of the respective memory area in row-wise and/or column- wise order; and in which the control unit selects the elements from the first and second matrix by moving stepwise (112-130) through the first and second memory areas. Also, a processing apparatus comprising a first processor (11) and a second processor (1) connected by a data bus (10), in which the first processor (11) is a general-purpose processor and the second processor (1) is more efficient than the first at calculating matrix multiplication. The processors thus disclosed may advantageously be used in video processing situations, such as road lane detection from vehicles.
PCT/GB2007/003635 2006-09-26 2007-09-26 Matrix multiplication WO2008037975A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP07823926A EP2067100A2 (en) 2006-09-26 2007-09-26 Matrix multiplication

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0618921A GB0618921D0 (en) 2006-09-26 2006-09-26 Matrix multiplication
GB0618921.1 2006-09-26

Publications (2)

Publication Number Publication Date
WO2008037975A2 WO2008037975A2 (en) 2008-04-03
WO2008037975A3 true WO2008037975A3 (en) 2009-05-22

Family

ID=37434671

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2007/003635 WO2008037975A2 (en) 2006-09-26 2007-09-26 Matrix multiplication

Country Status (3)

Country Link
EP (1) EP2067100A2 (en)
GB (1) GB0618921D0 (en)
WO (1) WO2008037975A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102541507B (en) * 2010-12-31 2015-12-16 联芯科技有限公司 Dimension can the data processing method of reprovision, system and matrix multiplication processor
US9384168B2 (en) 2013-06-11 2016-07-05 Analog Devices Global Vector matrix product accelerator for microprocessor integration
WO2018174936A1 (en) 2017-03-20 2018-09-27 Intel Corporation Systems, methods, and apparatuses for tile matrix multiplication and accumulation
US10338919B2 (en) 2017-05-08 2019-07-02 Nvidia Corporation Generalized acceleration of matrix multiply accumulate operations
DE102018110607A1 (en) 2017-05-08 2018-11-08 Nvidia Corporation Generalized acceleration of matrix multiplication and accumulation operations
WO2019009870A1 (en) 2017-07-01 2019-01-10 Intel Corporation Context save with variable save state size
CN113536220A (en) * 2020-04-21 2021-10-22 中科寒武纪科技股份有限公司 Operation method, processor and related product
CN112506567B (en) * 2020-11-27 2022-11-04 海光信息技术股份有限公司 Data reading method and data reading circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4956801A (en) * 1989-09-15 1990-09-11 Sun Microsystems, Inc. Matrix arithmetic circuit for processing matrix transformation operations
US5021987A (en) * 1989-08-31 1991-06-04 General Electric Company Chain-serial matrix multipliers
US20020138536A1 (en) * 2001-02-05 2002-09-26 Samsung Electronics Co., Ltd. Time-division type matrix calculator
US20040111587A1 (en) * 2002-12-09 2004-06-10 Nair Gopalan N Apparatus and method for matrix data processing
WO2005013025A1 (en) * 2003-07-31 2005-02-10 Trw Limited Sensing apparatus for vehicles

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5021987A (en) * 1989-08-31 1991-06-04 General Electric Company Chain-serial matrix multipliers
US4956801A (en) * 1989-09-15 1990-09-11 Sun Microsystems, Inc. Matrix arithmetic circuit for processing matrix transformation operations
US20020138536A1 (en) * 2001-02-05 2002-09-26 Samsung Electronics Co., Ltd. Time-division type matrix calculator
US20040111587A1 (en) * 2002-12-09 2004-06-10 Nair Gopalan N Apparatus and method for matrix data processing
WO2005013025A1 (en) * 2003-07-31 2005-02-10 Trw Limited Sensing apparatus for vehicles

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
ANALOG DEVICES: "ADSP-21000 Family Application Handbook Volume 1", 1994, XP002520457 *
BLERIS L G ET AL: "A co-processor FPGA platform for the implementation of real-time model predictive control", PROCEEDINGS OF THE 2006 AMERICAN CONTROL CONFERENCE 2006 (ACC'06), MINNEAPOLIS, MINESOTA, 14-16 JUNE 2006, 14 June 2006 (2006-06-14), pages 1912 - 1917, XP002520456 *
CORSONELLO P ET AL: "A matrix product coprocessor for FPGA embedded soft processors", PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS (ISSCS 2005), IASI, ROMANIA, 14-15 JULY 2005, vol. 2, 14 July 2005 (2005-07-14), pages 489 - 492, XP010837898, ISBN: 978-0-7803-9029-4 *
JENINGS A: "Matrix Computation for Engineers and Scientists", 1977, JOHN WILEY & SONS, XP008103984 *

Also Published As

Publication number Publication date
WO2008037975A2 (en) 2008-04-03
GB0618921D0 (en) 2006-11-08
EP2067100A2 (en) 2009-06-10

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