JP2022190215A - Semiconductor device - Google Patents

Abstract

To suppress controllability in switching operation from decreasing.SOLUTION: A semiconductor comprises semiconductor chips 20a, 20b which comprise control electrode on top surfaces, and top-surface wiring layers 33c, 33a which are striped in plan view and each have one end part opposed and electrically connected to the control electrode. At this time, the top-surface wiring layers 33c, 33a extend with their other-end parts in the opposite directions and the top-surface wiring layers 33c, 33a are equal in extension-directional length to each other. Consequently, the top-surface wiring layers 33a, 33c become substantially equal in inductance and electric resistance, and delay of control in switching operation, etc., are prevented to prevent controllability from decreasing.SELECTED DRAWING: Figure 4

Description

The present invention relates to semiconductor devices.

A semiconductor device includes a power semiconductor chip and functions as a power conversion device. A power semiconductor chip includes a switching element and a diode element. The switching elements are, for example, IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Further, the semiconductor device includes a printed circuit board or a connection unit to which the control electrodes of a plurality of semiconductor chips are connected by pin-shaped post electrodes. Such a printed circuit board or connection unit includes an external terminal to which a control signal is input from the outside, and a connection terminal connected to the control electrode of the semiconductor chip. Therefore, in the semiconductor device, control signals are input to the control electrodes of the semiconductor chip via the printed circuit board or the connection unit (see Patent Documents 1 and 2, for example). Control electrodes of the semiconductor chip and a plurality of lead frames arranged in one direction are connected by a wiring layer for control, and a control signal is input (see, for example, Patent Document 3).

JP 2020-047658 A JP 2017-098421 A WO2019/171684

When inputting control signals to the control electrodes of multiple semiconductor chips via a printed circuit board, the wiring length from the external terminal to the control electrode of each semiconductor chip depends on the wiring pattern (wiring layer) included in the printed circuit board. may differ. In this case, if the switching operation is performed, there is a possibility that a difference in control timing may occur due to the difference in wiring length. Therefore, the controllability during the switching operation is degraded. As a result, the reliability of the operation of the semiconductor device may deteriorate.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device in which deterioration of controllability during switching operation is suppressed.

According to one aspect of the present invention, the first semiconductor chip having the first control electrode on the front surface and the second semiconductor chip having the second control electrode on the front surface are formed in stripes in plan view. A first control wiring layer having one end opposed to the first control electrode and electrically connected to the first control wiring layer and having a striped shape in a plan view, and having one end opposed to the second control electrode, the main control wiring layer and a second control wiring layer electrically connected to the first control wiring layer, wherein the first control wiring layer and the second control wiring layer extend with the other end portions facing in opposite directions to each other, and the first control wiring layer A semiconductor device is provided in which the control wiring layer and the second control wiring layer have the same length in the extending direction.

According to the disclosed technique, it is possible to suppress deterioration in controllability during switching operation and prevent deterioration in reliability of the semiconductor device.

1 is a plan view of a semiconductor device according to a first embodiment; FIG. 1 is a side sectional view of a semiconductor device according to a first embodiment; FIG. 1 is a plan view of the inside of a semiconductor device according to a first embodiment; FIG. 2 is a plan view of the front surface of a printed circuit board included in the semiconductor device of the first embodiment; FIG. 2 is a plan view of the back surface of the printed circuit board included in the semiconductor device of the first embodiment; FIG. It is a top view of the semiconductor device of 2nd Embodiment. FIG. 10 is a side cross-sectional view of a semiconductor device according to a second embodiment; FIG. 10 is a plan view of the inside of a semiconductor device according to a second embodiment; FIG. 10 is a plan view of the front surface of a printed circuit board included in a semiconductor device according to a second embodiment; FIG. 11 is a plan view of the back surface of a printed circuit board included in a semiconductor device according to a second embodiment; It is a figure which shows the power converter device of 3rd Embodiment.

Embodiments will be described below with reference to the drawings. In the following description, "front surface" and "upper surface" represent the XY plane facing upward (+Z direction) in the semiconductor device shown in the figures. Similarly, "up" means the direction of the upper side (+Z direction) in the illustrated semiconductor device. “Back surface” and “lower surface” represent the XY plane facing downward (−Z direction) in the illustrated semiconductor device. Similarly, "downward" means the downward direction (-Z direction) in the illustrated semiconductor device. Similar directions are meant in other drawings as needed. "Front surface", "upper surface", "top", "back surface", "lower surface", "lower surface", and "side surface" are merely expedient expressions for specifying relative positional relationships. It does not limit the technical idea of For example, "above" and "below" do not necessarily mean perpendicular to the ground. That is, the "up" and "down" directions are not limited to the direction of gravity. In addition, in the following description, the term "main component" refers to the case of containing 80 vol% or more.

[First embodiment]
A semiconductor device according to the first embodiment will be described with reference to FIGS. 1 and 2. FIG. FIG. 1 is a plan view of the semiconductor device of the first embodiment, and FIG. 2 is a side sectional view of the semiconductor device of the first embodiment. 2 is a cross-sectional view taken along the dashed-dotted line XX in FIG. The dashed-dotted line XX is also a center line passing through the center of the short side of the semiconductor device 1 and parallel to the long side of the semiconductor device 1 .

A semiconductor device 1 includes a rectangular parallelepiped sealing body 2, and external connection terminals 3, 4, 5, control terminals 6a, 6b, and sense terminals 7a, 7b extend from a front surface 2e of the sealing body 2. It extends vertically upward (+Z direction) with respect to the front surface 2e.

The sealing body 2 has a substantially rectangular front surface 2e surrounded by side walls 2a to 2d on four sides in a plan view. The side walls 2a and 2c correspond to the longitudinal direction (long side) of the sealing body 2, and the side walls 2b and 2d correspond to the width direction (short side) of the sealing body 2, respectively. The connection points at the four corners of the side wall portions 2a to 2d do not necessarily have to be right angles, and may be rounded or chamfered. The joints between the front surface 2e and the side walls 2a to 2d are not necessarily right-angled, and may be rounded or chamfered.

The external connection terminals 3, 4, 5, the control terminals 6a, 6b, and the sense terminals 7a, 7b are cylindrical or prismatic. It forms a so-called pin shape. The external connection terminals 3, 4, 5, the control terminals 6a, 6b, and the sense terminals 7a, 7b are made of a highly conductive material. Such materials include, for example, silver, copper, nickel, or alloys containing at least one of these.

The external connection terminals 3, 4, and 5 are placed vertically upward (+Z direction) with respect to the front surface 2e, one by one across the dashed line XX, forming line symmetry with the dashed line XX. Each is extended. It should be noted that the external connection terminals 3, 4, and 5 are described as extending one by one across the dashed-dotted line XX. Not limited to this case, the external connection terminals 3, 4, and 5 may extend two or more each across the dashed-dotted line XX. The upper ends of the external connection terminals 3, 4 and 5 extend from the front surfaces of the terminal blocks 2f to 2h integrally formed with the front surface 2e. The lower ends of the external connection terminals 3, 4, 5 extend inside the sealing body 2 in the -Z direction.

The control terminals 6a and 6b extend vertically upward from the front surface 2e on the side walls 2b and 2d on the dashed line XX. Upper ends of the control terminals 6a and 6b extend from the front surfaces of the terminal blocks 2i and 2j integrally formed with the front surface 2e. The lower ends of the control terminals 6a and 6b extend vertically downward (-Z direction) inside the sealing body 2. As shown in FIG.

The sense terminals 7a and 7b are located on the dashed line XX, closer to the side walls 2b and 2d than the control terminals 6a and 6b, and vertically upward (+Z direction) with respect to the front surface 2e. Each is extended. Upper ends of the sense terminals 7a and 7b extend from the front surfaces of the terminal blocks 2i and 2j formed integrally with the front surface 2e. The lower ends of the sense terminals 7a and 7b extend vertically downward (-Z direction) inside the sealing body 2. As shown in FIG.

External connection terminals 3, 4, and 5 are main terminals for inputting and outputting a main current. The external connection terminal 3 is an input terminal (P terminal) connected to the positive electrode of the external power supply. The external connection terminal 3 is electrically connected to a main electrode (collector electrode) of a semiconductor chip 20b, which will be described later.

The external connection terminal 4 is an input terminal (N terminal) connected to the negative electrode of the external power supply. The external connection terminal 4 is electrically connected to a main electrode (emitter electrode) of a semiconductor chip 20a, which will be described later. The external connection terminal 5 is an output terminal (O terminal) through which an output current flows. The external connection terminal 5 is electrically connected to the main electrode (emitter electrode) of the semiconductor chip 20b and the main electrode (collector electrode) of the semiconductor chip 20a.

The control terminals 6a, 6b (G1, G2 terminals) are electrically connected to control electrodes of the semiconductor chips 20b, 20a via a printed circuit board 30, which will be described later. The sense terminals 7a, 7b (E1s, E2s terminals) are electrically connected to the emitter electrodes of the semiconductor chips 20b, 20a via the printed circuit board 30, respectively.

The sealing body 2, in which the external connection terminals 3, 4, 5, the control terminals 6a, 6b, and the sense terminals 7a, 7b are integrally molded, is provided with semiconductor chips 20a, 20b, etc., which will be described later, in a predetermined mold. It is configured by containing and sealing with resin. Such resins are mainly composed of thermoplastic resins. The thermoplastic resin is, for example, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyimide resin, or acrylonitrile butadiene styrene resin.

In such a semiconductor device 1, the insulating circuit boards 10a and 10b, the semiconductor chips 20a and 20b, and the printed circuit board 30 are sealed by the sealing body portion 2. As shown in FIG. The insulating circuit boards 10a and 10b include insulating plates 11a and 11b, metal plates 12a and 12b provided on the rear surfaces of the insulating plates 11a and 11b, and circuit patterns 13a1 and 13a2 provided on the front surfaces of the insulating plates 11a and 11b. , 13b. The insulating plates 11a, 11b and the metal plates 12a, 12b are rectangular in plan view. The corners of the insulating plates 11a and 11b and the metal plates 12a and 12b may be chamfered in an R shape or a C shape. The size of the metal plates 12a and 12b is smaller than the size of the insulating plates 11a and 11b in plan view, and they are formed inside the insulating plates 11a and 11b. The insulating plates 11a and 11b are made of a material having insulating properties and excellent thermal conductivity. Such insulating plates 11a and 11b are made of ceramics or insulating resin. Ceramics are, for example, aluminum oxide, aluminum nitride, and silicon nitride. The insulating resin is, for example, a paper phenol board, a paper epoxy board, a glass composite board, or a glass epoxy board. The thickness of the insulating plates 11a and 11b is 0.2 mm or more and 2.5 mm or less.

The metal plates 12a and 12b have an area smaller than that of the insulating plates 11a and 11b and a larger area than the regions where the circuit patterns 13a1, 13a2 and 13b are formed, and are rectangular like the insulating plates 11a and 11b. ing. Also, the corners may be chamfered in an R shape or a C shape. The metal plates 12a and 12b are smaller in size than the insulating plates 11a and 11b, and are formed on the entire surfaces of the insulating plates 11a and 11b except for the edges. The metal plates 12a and 12b are mainly composed of metal having excellent thermal conductivity. The metal is, for example, copper, aluminum, or an alloy containing at least one of these. Moreover, the thickness of the metal plates 12a and 12b is 0.1 mm or more and 2.5 mm or less. In order to improve the corrosion resistance of the metal plates 12a and 12b, plating may be performed. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, nickel-boron alloy.

The circuit patterns 13a1, 13a2, 13b are made of metal with excellent conductivity. Such metals are, for example, copper, aluminum, or alloys based on at least one of these. Moreover, the thickness of the circuit patterns 13a1, 13a2, 13b is 0.1 mm or more and 2.0 mm or less. Plating may be performed on the surfaces of the circuit patterns 13a1, 13a2, 13b in order to improve corrosion resistance. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, nickel-boron alloy. Note that the circuit patterns 13a1, 13a2, and 13b shown in FIG. 2 are examples. If necessary, the number, shape, size, etc. of the circuit patterns 13a1, 13a2, 13b may be appropriately selected.
Examples of the insulating circuit boards 10a and 10b having such a configuration include a DCB (Direct Copper Bonding) board, an AMB (Active Metal Brazed) board, and a resin insulating board.

In the semiconductor device 1, the rear surfaces of the metal plates 12a and 12b of the insulating circuit boards 10a and 10b are exposed. A cooling unit may be attached to the back surface of such a semiconductor device 1 via a bonding member.

The joining member used here is solder, brazing material, or sintered metal. Lead-free solder is used as the solder. Lead-free solder is mainly composed of an alloy containing at least two of tin, silver, copper, zinc, antimony, indium, and bismuth, for example. Furthermore, the solder may contain additives. Additives are, for example, nickel, germanium, cobalt or silicon. Additives in the solder improve wettability, gloss, and bonding strength, thereby improving reliability. The brazing filler metal contains, for example, at least one of aluminum alloy, titanium alloy, magnesium alloy, zirconium alloy, and silicon alloy as its main component. The insulated circuit boards 10a and 10b can be joined by brazing using such joining members. A metal sintered body has silver and a silver alloy as a main component, for example. Alternatively, the joining member may be a thermal interface material. Thermal interface materials are, for example, elastomeric sheets, room temperature vulcanization (RTV) rubbers, gels, adhesives including phase change materials. By attaching the semiconductor device 1 to the cooling unit through such a brazing material or thermal interface material, the heat dissipation of the semiconductor device 1 can be improved.

For the cooling unit, for example, a heat sink configured with a plurality of fins and a cooling device that cools with a coolant may be applied. A heat sink is mainly composed of a material having excellent thermal conductivity. Such materials include aluminum, iron, silver, copper, or alloys containing at least one of these. In order to improve corrosion resistance, the surface of the heat sink may be plated. At this time, plating materials used include, for example, nickel, nickel-phosphorus alloys, and nickel-boron alloys.

The semiconductor chips 20a, 20b include power device elements made of silicon or silicon carbide. Also, the thickness of the semiconductor chips 20a and 20b is, for example, 40 μm or more and 250 μm or less. A power device element combines the functions of a switching element and a diode element. Such power device elements may be RC (Reverse-Conducting)-IGBTs, IGBTs, and power MOSFETs. However, IGBTs and power MOSFETs contain parasitic diodes. When the semiconductor chips 20a and 20b are RC-IGBTs and IGBTs, they have a collector electrode as a main electrode on the back surface, and a gate electrode as a control electrode and an emitter electrode as a main electrode on the front surface. When the semiconductor chips 20a and 20b are power MOSFETs, they have a drain electrode as a main electrode on the back surface, and a gate electrode as a control electrode and a source electrode as a main electrode on the front surface. Details of the semiconductor chips 20a and 20b will be described later.

The rear surfaces of such semiconductor chips 20a and 20b are mechanically and electrically joined onto the circuit patterns 13a1 and 13b by joining members. The joining member used here is solder or a sintered metal. Lead-free solder is used as the solder. Lead-free solder is mainly composed of an alloy containing at least two of tin, silver, copper, zinc, antimony, indium, and bismuth, for example. Furthermore, the solder may contain additives. Additives are, for example, nickel, germanium, cobalt or silicon. Additives in the solder improve wettability, gloss, and bonding strength, thereby improving reliability. Metals used in the metal sintered body are, for example, silver and silver alloys.

The printed circuit board 30 includes an insulating layer 31 , a lower wiring layer 32 formed on the back surface of the insulating layer 31 , and an upper wiring layer 33 formed on the front surface of the insulating layer 31 . The insulating layer 31 includes a base material and a resin impregnated in the base material. The substrate is, for example, paper or glass cloth, or contains these. Resins are, for example, phenolic resins, epoxy resins, and polyimide resins. Specific examples include paper phenol substrates, paper epoxy substrates, glass epoxy substrates, composite base epoxy substrates, and glass polyimide substrates.

The lower wiring layer 32 and the upper wiring layer 33 are made of metal with excellent conductivity. Such metals are, for example, copper, aluminum, or alloys based on at least one of these. Such a printed circuit board 30 is arranged opposite to the front surfaces of the insulating circuit boards 10a and 10b with a predetermined gap therebetween. Note that each of the lower wiring layer 32 and the upper wiring layer 33 includes a plurality of layers. When they are not distinguished from each other, they are referred to as a lower wiring layer 32 and an upper wiring layer 33 . Details of the lower wiring layer 32 and the upper wiring layer 33 will be described later.

The semiconductor device 1 further includes main current post electrodes 8a to 8d, control post electrodes 9a and 9b, and detection post electrodes 9c and 9d (see FIG. 3). The main current post electrodes 8a to 8d, the control post electrodes 9a and 9b, and the detection post electrodes 9c and 9d are, for example, cylindrical or prismatic post-shaped. The main current post electrodes 8a to 8d, the control post electrodes 9a and 9b, and the detection post electrodes 9c and 9d are made of a highly conductive material. Such materials include, for example, silver, copper, nickel, or alloys containing at least one of these.

The main current post electrodes 8a-8d mechanically and electrically connect the printed board 30 with the main electrodes of the semiconductor chips 20a, 20b and the insulating circuit boards 10a, 10b. The control post electrodes 9a and 9b mechanically and electrically connect the printed circuit board 30 and the control electrodes of the semiconductor chips 20a and 20b. The detection post electrodes 9c and 9d mechanically and electrically connect the printed circuit board 30 and the main electrodes of the semiconductor chips 20a and 20b.

Next, details of the semiconductor chips 20a and 20b, the insulating circuit boards 10a and 10b, and the printed circuit board 30 will be described. First, the semiconductor chips 20a and 20b and the insulating circuit boards 10a and 10b will be described with reference to FIG. FIG. 3 is a plan view of the interior of the semiconductor device of the first embodiment. 3 is a plan view of the insulating circuit boards 10a and 10b to which the semiconductor chips 20a and 20b are bonded in the semiconductor device 1. FIG. The positions of the sealing body 2, the main current post electrodes 8a to 8d, the control post electrodes 9a and 9b, and the detection post electrodes 9c and 9d of the semiconductor device 1 are indicated by dashed lines.

As shown in FIG. 3, the semiconductor chips 20a and 20b are provided with control electrodes 21a and 21b at the central portions of the sides (first and second sides) of the front surface. Main electrodes 22a and 22b are provided on the front surfaces of the semiconductor chips 20a and 20b except for the control electrodes 21a and 21b.

The semiconductor chips 20a and 20b are arranged such that the sides on which the control electrodes 21a and 21b are formed are parallel to the circuit patterns 13a1 and 13b in plan view. In the case of FIG. 3, the semiconductor chips 20a and 20b are arranged so that the sides on which the control electrodes 21a and 21b are formed are flush with the circuit patterns 13a1 and 13b in a plan view. In other words, the semiconductor chips 20a and 20b are arranged with the control electrodes 21a and 21b facing the side wall portion 2a of the sealing body portion 2 with respect to the circuit patterns 13a1 and 13b. That is, the control electrodes 21a and 21b are oriented in the same direction.

Also, the semiconductor chip 20a is arranged substantially in the center of the circuit pattern 13a1. The semiconductor chip 20b is arranged in the center of the circuit pattern 13b in the X direction and on the side wall 2b in the Y direction.

Control post electrodes 9b, 9a are electrically and mechanically connected to the control electrodes 21a, 21b of the semiconductor chips 20a, 20b, and main current post electrodes 8d, 8a are electrically and mechanically connected to the main electrodes 22a, 22b. there is Detection post electrodes 9d and 9c are electrically and mechanically connected to areas of the main electrodes 22a and 22b adjacent to the control electrodes 21a and 21b of the semiconductor chips 20a and 20b, respectively. The detection post electrode 9d is provided on the side wall portion 2d side of the control electrode 21a, and the detection post electrode 9c is provided on the side wall portion 2d side of the control electrode 21b.

The insulating circuit board 10a has circuit patterns 13a1 and 13a2 formed on the front surface of an insulating plate 11a. Both of the circuit patterns 13a1 and 13a2 are rectangular in plan view. The circuit patterns 13a1 and 13a2 are formed over the width of the insulating plate 11a in the X direction. The circuit pattern 13a1 occupies about two-thirds of the Y-direction width of the front surface of the insulating plate 11a, and is formed on the side wall portion 2d side of the front surface of the insulating plate 11a. As described above, the semiconductor chip 20a is arranged in the central portion of the circuit pattern 13a1. A plurality of main current post electrodes 8c are electrically and mechanically connected along the X direction on the side wall portion 2b side of the semiconductor chip 20a of the circuit pattern 13a1 and slightly on the side wall portion 2c side. Further, the external connection terminals 5 are electrically and mechanically connected to the corners of the circuit pattern 13a1 on the side wall portion 2d.

The circuit pattern 13a2 occupies about one third of the Y-direction width of the front surface of the insulating plate 11a and is formed on the side wall portion 2b side of the front surface of the insulating plate 11a. A plurality of main current post electrodes 8b are electrically and mechanically connected along the X direction on the side of the side wall portion 2d of the circuit pattern 13a2 so as to face the main current post electrodes 8c. The external connection terminals 4 are electrically and mechanically connected to the corners of the circuit pattern 13a2 on the sidewall 2b side.

The circuit pattern 13b is formed over the entire front surface of the insulating plate 11b. As described above, the semiconductor chip 20b is arranged in the central portion of the circuit pattern 13b on the sidewall portion 2b side. The external connection terminals 3 are on the sides of the side walls 2a and 2c of the circuit pattern 13b and are electrically and mechanically connected between the semiconductor chip 20b and the side of the side wall 2d of the circuit pattern 13b. ing.

Next, the printed board 30 will be described with reference to FIGS. 4 and 5. FIG. 4 is a plan view of the front surface of the printed circuit board included in the semiconductor device of the first embodiment, and FIG. 5 is a plan view of the back surface of the printed circuit board included in the semiconductor device of the first embodiment. It is a top view. 4 shows the upper wiring layer 33 as viewed from the front surface of the printed board 30, and FIG. 5 shows the lower wiring layer 32 as viewed from the front surface of the printed board 30. FIG. 4 and 5, the components included in the sealing body 2, the semiconductor chips 20a and 20b, and the insulating circuit boards 10a and 10b are indicated by broken lines.

The printed circuit board 30 includes an insulating layer 31 and upper wiring layers 33a, 33b, and 33c formed on the front surface of the insulating layer 31, as shown in FIG. The insulating layer 31 has a rectangular shape in plan view. The length (long side) of the insulating layer 31 in the Y direction is a length that allows formation of the upper wiring layer 33 and the lower wiring layer 32 , and is shorter than the long side of the sealing body 2 . The width (short side) of the insulating layer 31 in the X direction may be shorter than the distance in the X direction between the external connection terminals 3, 4 and 5 formed on the insulating circuit boards 10a and 10b. In addition, when the width of the insulating layer 31 in the X direction is longer than the width of the insulating circuit boards 10a and 10b in the same direction or the width thereof, the insulating layer 31 (printed circuit board 30) is connected to the external connection terminals 3, 4, and 5. may be formed with openings (through holes) through which are inserted. However, the external connection terminals 3 , 4 , 5 inserted through the through holes must be electrically insulated from the upper wiring layer 33 and the lower wiring layer 32 .

The upper wiring layer 33a (first control wiring layer) has a striped shape (rectangular shape) with a length L2 in plan view. The width (short side) of the upper surface wiring layer 33a in the X direction is sufficient if at least a through hole through which the detection post electrode 9c and the sense terminal 7a penetrate can be formed. One end (the left end in the drawing) of the upper wiring layer 33a is electrically and mechanically connected to the control post electrode 9a. Accordingly, one end of the upper surface wiring layer 33a faces the control electrode 21b of the semiconductor chip 20b and is electrically connected via the control post electrode 9a. Further, the detection post electrode 9c penetrates the side wall portion 2b side of the control post electrode 9a without being electrically connected to one end portion of the upper surface wiring layer 33a.

The other end portion (the right end portion in the figure) of the upper surface wiring layer 33a extends to the side wall portion 2b along the side wall portions 2a and 2c. The other end of the upper wiring layer 33a is electrically and mechanically connected to the control terminal 6a. Further, the sense terminal 7a penetrates the side wall portion 2b side of the control terminal 6a without being electrically connected to the other end portion of the upper surface wiring layer 33a. At this time, the length Lc2 from the control post electrode 9a to the control terminal 6a and the length Ls2 from the detection post electrode 9c to the sense terminal 7a are the same length.

The upper wiring layer 33b has a stripe shape in plan view. The width (short side) of the upper wiring layer 33b in the X direction may be about the sum of the diameters of at least three main current post electrodes 8c. One end (the left end in the figure) of the upper wiring layer 33b is electrically and mechanically connected to the main current post electrode 8c. One end of the upper wiring layer 33b may be extended to the front of the main current post electrode 8d. In FIG. 4, one end of the upper wiring layer 33b extends to the front of the semiconductor chip 20a in the Y direction in plan view.

The other end portion (the right end portion in the figure) of the upper surface wiring layer 33b extends to the side wall portion 2b along the side wall portions 2a and 2c. The other end of the upper wiring layer 33b is electrically and mechanically connected to the main current post electrode 8a. Therefore, the upper wiring layer 33b faces the main electrode 22b of the semiconductor chip 20b and is electrically connected via the main current post electrode 8a. The other end of the upper wiring layer 33b extends to the extent that it does not exceed the semiconductor chip 20b. Further, the main current post electrode 8b penetrates through the side wall portion 2b side of the main current post electrode 8c of the upper wiring layer 33b without being electrically connected.

The upper wiring layer 33c (second control wiring layer) has a striped shape with a length L1 in plan view. Also, the length L1 and the length L2 are the same length. The width of the upper surface wiring layer 33c in the X direction is sufficient if at least a through hole through which the detection post electrode 9d and the sense terminal 7b penetrate can be formed. One end (right end in the drawing) of the upper wiring layer 33c is electrically and mechanically connected to the control post electrode 9b. Accordingly, one end of the upper wiring layer 33c faces the control electrode 21a of the semiconductor chip 20a and is electrically connected via the control post electrode 9b. Further, the detection post electrode 9d penetrates through the side wall portion 2d side of the control post electrode 9b without being electrically connected to one end portion of the upper surface wiring layer 33c.

The other end (the left end in the figure) of the upper surface wiring layer 33c extends to the side wall portion 2d along the side wall portions 2a and 2c. The other end of the upper wiring layer 33c is electrically and mechanically connected to the control terminal 6b. The sense terminal 7b penetrates the side wall portion 2d side of the control terminal 6b without being electrically connected to the other end portion of the upper surface wiring layer 33c. At this time, the length Lc1 from the control post electrode 9b to the control terminal 6b and the length Ls1 from the detection post electrode 9d to the sense terminal 7b are the same length.

Further, the printed circuit board 30 includes lower surface wiring layers 32a, 32b, 32c formed on the back surface of the insulating layer 31, as shown in FIG. The lower surface wiring layer 32a has a striped shape with a length L4 in plan view. Note that the length L4 is substantially the same length as the length L2 of the upper wiring layer 33a. The width of the lower surface wiring layer 32a in the X direction should be at least such that a through hole through which the control post electrode 9a and the control terminal 6a pass can be formed. That is, the lower wiring layer 32a has the same shape and size as the upper wiring layer 33a. Further, the lower surface wiring layer 32a is formed on the back surface of the same place as the upper surface wiring layer 33a with the insulating layer 31 interposed therebetween.

One end (the left end in the figure) of the lower surface wiring layer 32a is electrically and mechanically connected to the detection post electrode 9c. Therefore, one end of the lower surface wiring layer 32a faces the area of the main electrode 22b adjacent to the control electrode 21b of the semiconductor chip 20b and is electrically connected via the detection post electrode 9c. Further, the control post electrode 9a penetrates the side wall portion 2d side of the detection post electrode 9c without being electrically connected to one end portion of the lower surface wiring layer 32a.

The other end portion (right end portion in the figure) of the lower surface wiring layer 32a extends to the side wall portion 2b along the side wall portions 2a and 2c. The other end of the lower wiring layer 32a is electrically and mechanically connected to the sense terminal 7a. Further, the control terminal 6a penetrates the side wall portion 2d of the sense terminal 7a without being electrically connected to the other end portion of the lower surface wiring layer 32a. At this time, as described for the upper wiring layer 33a, the length Lc2 from the control post electrode 9a to the control terminal 6a and the length Ls2 from the detection post electrode 9c to the sense terminal 7a are the same.

The lower surface wiring layer 32b has a stripe shape in plan view. The width of the lower surface wiring layer 32b in the X direction may be about the sum of the diameters of at least three main current post electrodes 8c. One end (the left end in the drawing) of the lower surface wiring layer 32b is electrically and mechanically connected to the main current post electrode 8d. Accordingly, one end of the lower surface wiring layer 32b faces the main electrode 22a of the semiconductor chip 20a and is electrically connected via the main current post electrode 8d.

The other end portion (right end portion in the figure) of the lower surface wiring layer 32b extends along the side wall portions 2a and 2c to the side wall portion 2b to the main current post electrode 8b. The other end of the lower wiring layer 32b is electrically and mechanically connected to the main current post electrode 8b. Further, the main current post electrode 8c penetrates between one end and the other end of the lower surface wiring layer 32b without being electrically connected. Further, the lower surface wiring layer 32b is formed on the rear surface of the upper surface wiring layer 33b so as to be aligned with the upper surface wiring layer 33b with the insulating layer 31 interposed therebetween. Further, the lower wiring layer 32b partially overlaps with the upper wiring layer 33b.

The lower surface wiring layer 32c has a striped shape with a length L3 in plan view. Note that the length L3 is substantially the same length as the length L1 of the upper wiring layer 33c. The width of the lower surface wiring layer 32c in the X direction may be at least such that a through hole through which the control post electrode 9b and the control terminal 6b pass can be formed. That is, the lower wiring layer 32c has the same shape and size as the upper wiring layer 33c. Further, the lower surface wiring layer 32c is formed on the back surface at the same location as the upper surface wiring layer 33c with the insulating layer 31 interposed therebetween.

One end (the right end in the figure) of the lower surface wiring layer 32c is electrically and mechanically connected to the detection post electrode 9d. Accordingly, one end of the lower surface wiring layer 32c faces the area of the main electrode 22a adjacent to the control electrode 21a and is electrically connected via the detection post electrode 9d. The control post electrode 9b penetrates one end of the lower surface wiring layer 32c without being electrically connected to the side wall portion 2b side of the detection post electrode 9d.

The other end portion (the left end portion in the figure) of the lower surface wiring layer 32c extends to the side wall portion 2d along the side wall portions 2a and 2c. The other end of the lower wiring layer 32c is electrically and mechanically connected to the sense terminal 7b. Further, the control terminal 6b penetrates the side wall portion 2b side of the sense terminal 7b without being electrically connected to the other end portion of the lower surface wiring layer 32c. At this time, as described for the upper wiring layer 33c, the length Lc1 from the control post electrode 9b to the control terminal 6b and the length Ls1 from the detection post electrode 9d to the sense terminal 7b are the same.

Therefore, the control electrodes 21a, 21b of the semiconductor chips 20a, 20b are electrically connected to the control terminals 6b, 6a via the control post electrodes 9b, 9a and the upper wiring layers 33c, 33a.

The main electrode 22b of the semiconductor chip 20b is electrically connected to the external connection terminal 5 via the main current post electrode 8a, the upper wiring layer 33b, the main current post electrode 8c, and the circuit pattern 13a1.

The main electrode 22a of the semiconductor chip 20a is electrically connected to the external connection terminal 4 via the main current post electrode 8d, the lower wiring layer 32b, the main current post electrode 8b, and the circuit pattern 13a2.

The main electrode (back surface) of the semiconductor chip 20a is electrically connected to the main electrode 22b of the semiconductor chip 20b via the circuit pattern 13a1, the main current post electrode 8c, the upper wiring layer 33b, and the main current post electrode 8a. It is connected.

The main electrodes 22a, 22b of the semiconductor chips 20a, 20b are electrically connected to the sense terminals 7b, 7a via the detection post electrodes 9c, 9d and the lower wiring layers 32c, 32a.

Next, the operation of such a semiconductor device 1 will be described. In the following description, the semiconductor chips 20a and 20b are assumed to be RC-IGBTs. The external connection terminal 3 of the semiconductor device 1 is connected to the positive terminal of an external power source, and the external connection terminal 4 is connected to the negative electrode of the external power source. Control signals are input to the control terminals 6a and 6b at predetermined timings.

First, an input current is input from the external connection terminal 3 through the circuit pattern 13b to the main electrode (collector electrode) on the back surface of the semiconductor chip 20b. At this time, when the control signal to the control terminal 6a is ON and the control signal to the control terminal 6b is OFF, the control signal is transmitted from the control terminal 6a through the upper wiring layer 33a and the control post electrode 9a to the semiconductor chip 20b. is input to the control electrode 21b of . A main electrode 22b (emitter electrode) on the front surface of the semiconductor chip 20b outputs an output current. An output current is input from the main current post electrode 8a to the main current post electrode 8c via the upper wiring layer 33b. The output current is output from the external connection terminal 5 via the circuit pattern 13a1 from the main current post electrode 8c. An output current output from the main electrode 22b (emitter electrode) of the semiconductor chip 20b is output from the sense terminal 7a via the detection post electrode 9c and the lower wiring layer 32a.

After a while after the control signal for the control terminal 6a is turned off and the control signal for the control signal 6b is turned on, the circuit pattern 13a1 is connected from the external connection terminal 5 to the main electrode (collector electrode) on the back surface of the semiconductor chip 20a. Current is input through A main electrode 22a (emitter electrode) on the front surface of the semiconductor chip 20a outputs an output current. An output current is input from the main current post electrode 8d to the main current post electrode 8bc via the lower surface wiring layer 32b. The output current is output from the external connection terminal 4 via the circuit pattern 13a2 from the main current post electrode 8b. An output current output from the main electrode 22a (emitter electrode) of the semiconductor chip 20a is output from the sense terminal 7b via the detection post electrode 9d and the lower wiring layer 32c.

As described above, in the semiconductor device 1, an output current having a predetermined waveform is obtained from the external connection terminal 5 by inputting control signals to the control terminals 6a and 6b at predetermined timings. At this time, the distance Lc2 from the control terminal 6a to the control electrode 21b of the semiconductor chip 20b is substantially equal to the distance Lc1 from the control terminal 6b to the control electrode 21a of the semiconductor chip 20a. As a result, the inductance and electrical resistance of the upper wiring layers 33a and 33c are substantially equal, and control delays and the like during switching operations are prevented, thereby preventing deterioration in controllability.

Also, the distance Ls2 from the sense terminal 7a to the main electrode 22b of the semiconductor chip 20b and the distance Ls1 from the sense terminal 7b to the main electrode 22a of the semiconductor chip 20a are substantially equal. The lower wiring layers 32a and 32c through which the sense current is conducted have the same length as the upper wiring layers 33a and 33c through which the control signal is conducted. The lower wiring layers 32a and 32c are formed so as to be aligned with the rear surfaces of the upper wiring layers 33a and 33c with the insulating layer 31 interposed therebetween. The direction in which the sense current flows through the lower wiring layers 32a and 32c is opposite to the direction in which the control signal flows through the upper wiring layers 33a and 33c. Therefore, the mutual inductance caused by the control signal and the sense current cancels out. Therefore, electrical influence on the vicinity of upper wiring layers 33a and 33c can be suppressed.

The above-described semiconductor device 1 includes semiconductor chips 20a and 20b having control electrodes 21a and 21b on the front surfaces thereof, and semiconductor chips 20a and 20b having a stripe shape in a plan view, one end of which faces the control electrodes 21a and 21b and is electrically connected to the semiconductor chips 20a and 20b. and upper wiring layers 33c and 33a connected to the . At this time, the upper wiring layers 33c and 33a are extended with the other end portions facing opposite directions, and the lengths of the upper wiring layers 33c and 33a in the extending direction are equal to each other. As a result, the inductance and electrical resistance of the upper wiring layers 33a and 33c are substantially equal, and control delays and the like during switching operations are prevented, thereby preventing deterioration in controllability.

[Second embodiment]
In the second embodiment, the semiconductor chips 20a and 20b are rotated with respect to the insulating circuit boards 10a and 10b in the first embodiment. A semiconductor device according to the second embodiment will be described with reference to FIGS. 6 and 7. FIG. In addition, in the second embodiment, description will be made centering on changes to the semiconductor device of the first embodiment.

FIG. 6 is a plan view of the semiconductor device of the second embodiment, and FIG. 7 is a side sectional view of the semiconductor device of the second embodiment. 7 is a cross-sectional view taken along the dashed-dotted line XX in FIG. The dashed-dotted line XX is also a center line that passes through the center of the short side of the semiconductor device 1a and is parallel to the long side.

A semiconductor device 1a includes a rectangular parallelepiped sealing body 2, and external connection terminals 3, 4, 5, control terminals 6a, 6b, and sense terminals 7a, 7b extend from a front surface 2e of the sealing body 2. It extends vertically upward (+Z direction) with respect to the front surface 2e.

In the semiconductor device 1a, the control terminals 6a and 6b and the sense terminals 7a and 7b are arranged line-symmetrically with the positions shifted from the center line toward the side wall portion 2c. Control terminals 6a and 6b are provided on the side wall 2a, and sense terminals 7a and 7b are provided on the side wall 2c. Along with this, the terminal blocks 2i and 2j are also formed integrally with the front surface 2e so as to be symmetrical with respect to the center line and shifted toward the side wall portion 2c. Therefore, the upper ends of the control terminals 6a, 6b and the sense terminals 7a, 7b extend from the front surfaces of the terminal blocks 2i, 2j. The lower ends of the control terminals 6a and 6b and the sense terminals 7a and 7b extend vertically downward (-Z direction) inside the sealing body 2. As shown in FIG.

Next, details of the semiconductor chips 20a and 20b, the insulating circuit boards 10a and 10b, and the printed circuit board 30 will be described. First, the semiconductor chips 20a, 20b and the insulating circuit boards 10a, 10b will be described with reference to FIG. FIG. 8 is a plan view of the inside of the semiconductor device of the second embodiment. 8 is a plan view of the insulating circuit boards 10a and 10b to which the semiconductor chips 20a and 20b are bonded in the semiconductor device 1a. The positions of the sealing body 2 of the semiconductor device 1a, the main current post electrodes 8a to 8d, the control post electrodes 9a and 9b, and the detection post electrodes 9c and 9d are indicated by dashed lines.

Semiconductor chips 20a and 20b are arranged such that control electrodes 21a and 21b face opposite directions to circuit patterns 13a1 and 13b. That is, the sides of the semiconductor chips 20a and 20b on which the control electrodes 21a and 21b are provided are arranged so as to be close to the ends of the sealing body 2 facing each other in the longitudinal direction. More specifically, the semiconductor chips 20a and 20b are arranged such that the control electrodes 21a and 21b face the side wall portions 2d and 2b of the sealing body portion 2, respectively. Along with this arrangement of the semiconductor chips 20a, 20b, the main current post electrodes 8c, 8b are also arranged linearly with respect to the semiconductor chips 20a, 20b.

Next, the printed board 30 will be described with reference to FIGS. 9 and 10. FIG. 9 is a plan view of the front surface of a printed circuit board included in the semiconductor device of the second embodiment, and FIG. 10 is a plan view of the back surface of the printed circuit board included in the semiconductor device of the second embodiment. It is a top view. 9 shows the upper wiring layer 33 of the printed circuit board 30 viewed from the front surface of the printed circuit board 30, and FIG. This is the case when viewed from the side. 9 and 10, the sealing body 2, the semiconductor chips 20a and 20b, and the components included in the insulating circuit boards 10a and 10b are indicated by dashed lines.

The printed circuit board 30 includes an insulating layer 31 and upper wiring layers 33a, 33b, and 33c formed on the front surface of the insulating layer 31, as shown in FIG. The upper wiring layer 33a has a striped shape (a rectangular shape) with a length L2 in a plan view. The width of the upper wiring layer 33a in the X direction is such that at least the through hole through which the detection post electrode 9c (or the sense terminal 7a) penetrates and the control post electrode 9a (or the control terminal 6a) can be formed along the X direction. If it is

One end (the left end in the drawing) of the upper wiring layer 33a is electrically and mechanically connected to the control post electrode 9a. Accordingly, one end of the upper surface wiring layer 33a faces the control electrode 21b of the semiconductor chip 20b and is electrically connected via the control post electrode 9a. Further, the detection post electrode 9c penetrates through the side wall portion 2c side of the control post electrode 9a without being electrically connected to one end portion of the upper surface wiring layer 33a.

The other end portion (the right end portion in the figure) of the upper surface wiring layer 33a extends to the side wall portion 2b along the side wall portions 2a and 2c. The other end of the upper wiring layer 33a is electrically and mechanically connected to the control terminal 6a. The control terminal 6a is arranged so as to form a straight line with respect to the control post electrode 9a. Further, the sense terminal 7a penetrates the side wall portion 2c side of the control terminal 6a without being electrically connected to the other end portion of the upper surface wiring layer 33a. At this time, the length Lc2 from the control post electrode 9a to the control terminal 6a and the length Ls2 from the detection post electrode 9c to the sense terminal 7a are the same length.

The upper wiring layer 33b has a stripe shape in plan view. The width of the upper wiring layer 33b in the X direction may be about the sum of the diameters of at least three main current post electrodes 8c. One end (the left end in the figure) of the upper wiring layer 33b is electrically and mechanically connected to the main current post electrode 8c. One end of the upper wiring layer 33b may be extended to the front of the main current post electrode 8d. In FIG. 9, one end of the upper wiring layer 33b extends to the front of the semiconductor chip 20a in plan view.

The other end portion (the right end portion in the figure) of the upper surface wiring layer 33b extends to the side wall portion 2b along the side wall portions 2a and 2c. The other end of the upper wiring layer 33b is electrically and mechanically connected to the main current post electrode 8a. Therefore, the upper wiring layer 33b faces the main electrode 22b of the semiconductor chip 20b and is electrically connected via the main current post electrode 8a. The other end of the upper wiring layer 33b extends to the front of the control electrode 21b of the semiconductor chip 20b. Further, the main current post electrode 8b penetrates through the side wall portion 2b side of the main current post electrode 8c of the upper wiring layer 33b without being electrically connected.

The upper wiring layer 33c has a striped shape with a length L1 in plan view. Also, the length L1 and the length L2 are the same length. The width of the upper wiring layer 33c in the X direction is such that at least the through hole through which the detection post electrode 9d (or the sense terminal 7b) penetrates and the control post electrode 9b (or the control terminal 6b) can be formed along the X direction. Any degree is acceptable.

One end (right end in the drawing) of the upper wiring layer 33c is electrically and mechanically connected to the control post electrode 9b. Accordingly, one end of the upper wiring layer 33c faces the control electrode 21a of the semiconductor chip 20a and is electrically connected via the control post electrode 9b. Further, the detection post electrode 9d penetrates through the side wall portion 2c side of the control post electrode 9b without being electrically connected to one end portion of the upper surface wiring layer 33c.

The other end (the left end in the figure) of the upper surface wiring layer 33c extends to the side wall portion 2d along the side wall portions 2a and 2c. The other end of the upper wiring layer 33c is electrically and mechanically connected to the control terminal 6b. The sense terminal 7b penetrates the side wall portion 2c side of the control terminal 6b without being electrically connected to the other end portion of the upper surface wiring layer 33c. At this time, the length Lc1 from the control post electrode 9b to the control terminal 6b and the length Ls1 from the detection post electrode 9d to the sense terminal 7b are the same length.

Further, the printed circuit board 30 includes lower surface wiring layers 32a, 32b, 32c formed on the back surface of the insulating layer 31, as shown in FIG. The lower surface wiring layer 32a has a striped shape with a length L4 in plan view. Note that the length L4 is substantially the same length as the length L2 of the upper wiring layer 33a. The width of the lower surface wiring layer 32a in the X direction is at least such that the through hole through which the control post electrode 9a (or the control terminal 6a) penetrates and the detection post electrode 9c (or the sense terminal 7a) can be formed along the X direction. I wish I had. That is, the lower wiring layer 32a has the same shape and size as the upper wiring layer 33a. Further, the lower surface wiring layer 32a is formed on the back surface of the same place as the upper surface wiring layer 33a with the insulating layer 31 interposed therebetween.

One end (the left end in the figure) of the lower surface wiring layer 32a is electrically and mechanically connected to the detection post electrode 9c. Therefore, one end of the lower surface wiring layer 32a faces the area of the main electrode 22b adjacent to the control electrode 21b of the semiconductor chip 20b and is electrically connected via the detection post electrode 9c. Further, the control post electrode 9a penetrates through the side wall portion 2a side of the detection post electrode 9c without being electrically connected to one end portion of the lower surface wiring layer 32a.

The other end portion (right end portion in the figure) of the lower surface wiring layer 32a extends to the side wall portion 2b along the side wall portions 2a and 2c. The other end of the lower wiring layer 32a is electrically and mechanically connected to the sense terminal 7a. Further, the control terminal 6a penetrates the side wall portion 2d of the sense terminal 7a without being electrically connected to the other end portion of the lower surface wiring layer 32a. At this time, as described for the upper wiring layer 33a, the length Lc2 from the control post electrode 9a to the control terminal 6a and the length Ls2 from the detection post electrode 9c to the sense terminal 7a are the same.

The lower surface wiring layer 32b has a stripe shape in plan view. The width of the lower wiring layer 32b in the X direction may be about the sum of the diameters of at least three main current post electrodes 8d. One end (the left end in the drawing) of the lower surface wiring layer 32b is electrically and mechanically connected to the main current post electrode 8d. Accordingly, one end of the lower surface wiring layer 32b faces the main electrode 22a of the semiconductor chip 20a and is electrically connected via the main current post electrode 8d.

The other end portion (right end portion in the figure) of the lower surface wiring layer 32b extends along the side wall portions 2a and 2c to the side wall portion 2b to the main current post electrode 8b. The other end of the lower wiring layer 32b is electrically and mechanically connected to the main current post electrode 8b. Further, the main current post electrode 8c penetrates between one end and the other end of the lower surface wiring layer 32b without being electrically connected. Further, the lower surface wiring layer 32b is formed on the rear surface of the upper surface wiring layer 33b so as to be aligned with the upper surface wiring layer 33b with the insulating layer 31 interposed therebetween. Further, the lower wiring layer 32b partially overlaps with the upper wiring layer 33b.

The lower surface wiring layer 32c has a striped shape with a length L3 in plan view. Note that the length L3 is substantially the same length as the length L1 of the upper wiring layer 33c. Moreover, the length L3 and the length L4 are the same length. The width of the lower wiring layer 32c in the X direction is such that at least the through hole through which the control post electrode 9b (or the control terminal 6b) penetrates and the detection post electrode 9d (or the sense terminal 7b) can be formed along the X direction. Any degree is acceptable. That is, the lower wiring layer 32c has the same shape and size as the upper wiring layer 33c. Further, the lower surface wiring layer 32c is formed on the back surface at the same location as the upper surface wiring layer 33c with the insulating layer 31 interposed therebetween.

One end (the right end in the figure) of the lower surface wiring layer 32c is electrically and mechanically connected to the detection post electrode 9d. Accordingly, one end of the lower surface wiring layer 32c faces the area of the main electrode 22a adjacent to the control electrode 21a and is electrically connected via the detection post electrode 9d. The control post electrode 9b penetrates one end of the lower surface wiring layer 32c without being electrically connected to the side wall portion 2a side of the detection post electrode 9d.

The other end portion (the left end portion in the figure) of the lower surface wiring layer 32c extends to the side wall portion 2d along the side wall portions 2a and 2c. The other end of the lower wiring layer 32c is electrically and mechanically connected to the sense terminal 7b. Further, the control terminal 6b penetrates the side wall portion 2a side of the sense terminal 7b without being electrically connected to the other end portion of the lower surface wiring layer 32c. At this time, as described for the upper wiring layer 33c, the length Lc1 from the control post electrode 9b to the control terminal 6b and the length Ls1 from the detection post electrode 9d to the sense terminal 7b are the same.

Therefore, the control electrodes 21a, 21b of the semiconductor chips 20a, 20b are electrically connected to the control terminals 6b, 6a via the control post electrodes 9b, 9a and the upper wiring layers 33c, 33a.

In such a semiconductor device 1a as well, an output current having a predetermined waveform can be obtained from the external connection terminal 5 by inputting control signals to the control terminals 6a and 6b at predetermined timings. At this time, the distance Lc2 from the control terminal 6a to the control electrode 21b of the semiconductor chip 20b is substantially equal to the distance Lc1 from the control terminal 6b to the control electrode 21a of the semiconductor chip 20a. As a result, the inductance and electrical resistance of the upper wiring layers 33a and 33c are substantially equal, and control delays and the like during switching operations are prevented, thereby preventing deterioration in controllability.

Also, the distance Ls2 from the sense terminal 7a to the main electrode 22b of the semiconductor chip 20b and the distance Ls1 from the sense terminal 7b to the main electrode 22a of the semiconductor chip 20a are substantially equal. The lower wiring layers 32a and 32c through which the sense current is conducted have the same length as the upper wiring layers 33a and 33c through which the control signal is conducted. The lower wiring layers 32a and 32c are formed so as to be aligned with the rear surfaces of the upper wiring layers 33a and 33c with the insulating layer 31 interposed therebetween. The direction in which the sense current flows through the lower wiring layers 32a and 32c is opposite to the direction in which the control signal flows through the upper wiring layers 33a and 33c. Therefore, the mutual inductance caused by the control signal and the sense current cancels out. Therefore, electrical influence on the vicinity of upper wiring layers 33a and 33c can be suppressed.

Moreover, in the semiconductor device 1a, the lengths of the upper wiring layers 33a and 33b and the lower wiring layers 32a and 32c can be shortened. In the case of the semiconductor device 1, for example, there is an area where the upper wiring layer 33a and the upper wiring layer 33b overlap on the semiconductor chip 20b when viewed from the side. Therefore, there is a limit to reducing the width of the semiconductor device 1 in the X direction. In the semiconductor device 1a, since the upper wiring layer 33 and the lower wiring layer 32 are arranged in a straight line, the width in the X direction can be reduced. Therefore, the semiconductor device 1 a can be made smaller than the semiconductor device 1 .

In the semiconductor device 1a, the control terminals 6a and 6b are arranged on the center line (one-dot chain line XX), and the sense terminals 7a and 7b are displaced from the center line toward the side wall portion 2c. describes the case. Not limited to this case, the sense terminals 7a and 7b may be displaced from the control terminals 6a and 6b on the side wall portion 2a. 9 and 10, the sense terminals 7a and 7b are provided on the sidewall portion 2a side with respect to the control terminals 6a and 6b, and the detection post electrodes 9c and 9d are provided with respect to the control post electrodes 9a and 9b. are provided on the side wall portion 2a.

Further, the control terminals 6a, 6b and the sense terminals 7a, 7b may be arranged line-symmetrically with respect to the center line (chain line XX) with respect to the front surface 2e of the semiconductor device 1a. . In this case, for example, the semiconductor chips 20a and 20b shown in FIGS. 8 to 10 are shifted toward the side wall portion 2a.

[Third embodiment]
In the third embodiment, a power converter including a plurality of semiconductor devices 1 of the first embodiment will be described with reference to FIG. 11 and FIGS. 1 and 2. FIG. FIG. 11 is a diagram showing a power converter according to the third embodiment. Note that FIG. 11A shows a plan view of the power converter. FIG. 11B shows a cross-sectional view taken along the dashed-dotted line XX in FIG. 11A. Moreover, the power conversion device 40 includes the semiconductor device 1 of the first embodiment. Note that the reference numerals of the semiconductor device 1 are omitted. 1 and 2 can be referred to for the configuration of the semiconductor device 1. FIG. The power conversion device 40 is not limited to the semiconductor device 1 of the first embodiment, and may similarly use the semiconductor device 1a of the second embodiment.

The power conversion device 40 includes a plurality of semiconductor devices 1 and conductive substrates 41 to 44, 45a, 45b, and 45c electrically connected to the plurality of semiconductor devices 1. FIG. The plurality of semiconductor devices 1 are arranged in the X direction so that the short side wall portions 2d and 2b are on the same plane (parallel) and the long side wall portions 2a and 2c are opposed to each other. FIG. 11 shows the case where the semiconductor devices 1 are arranged in three rows.

The conductive substrates 41 to 44, 45a, 45b, 45c are plates containing conductors. The conductive boards 41 to 44, 45a, 45b, 45c are, for example, busbars and printed circuit boards. The conductive substrates 41 to 44, 45a, 45b, and 45c connect external devices such as driver circuits, power supplies, and output equipment with the external connection terminals 3, 4, and 5 of the semiconductor device 1, the control terminals 6a, 6b, and the sense terminals 7a, 7b. It can be electrically connected to control each semiconductor device 1 and input/output a voltage or the like to the semiconductor device 1 .

The conductive substrates 41 and 42 are electrically and mechanically connected to the control terminals 6a and 6b and the sense terminals 7a and 7b of the semiconductor device 1, respectively. Control signals are input to the control terminals 6a and 6b at predetermined timings by the conductive substrates 41 and 42, respectively. Sense currents are input to the conductive substrates 41 and 42 from the sense terminals 7a and 7b.

The conductive substrates 43 and 44 are electrically and mechanically connected to the external connection terminals 3 and 4 of the semiconductor device 1 . The conductive substrates 43 and 44 are connected to positive and negative external power supplies, respectively.

The conductive substrates 45a, 45b, 45c are electrically and mechanically connected to the external connection terminals 5 of the plurality of semiconductor devices 1, respectively. The conductive substrates 45a, 45b, and 45c input output currents output from the external connection terminals 5 of the plurality of semiconductor devices 1 to loads.

In the semiconductor device 1, upper wiring layers 33a and 33c are arranged facing opposite directions. For this reason, in the power conversion device 40, such semiconductor devices 1 are arranged in a necessary number so that the side wall portions 2d and 2b on the short sides are parallel and the side wall portions 2a and 2c on the long sides face each other. be able to.

Reference Signs List 1, 1a semiconductor device 2 sealing body 2a-2d side wall 2e front surface 2f-2j terminal block 3-5 external connection terminals 6a, 6b control terminals 7a, 7b sense terminals 8a-8d main current post electrodes 9a, 9b Control post electrode 9c, 9d Detection post electrode 10a, 10b Insulation circuit board 11a, 11b Insulation plate 12a, 12b Metal plate 13a1, 13a2, 13b Circuit pattern 20a, 20b Semiconductor chip 21a, 21b Control electrode 22a, 22b Main electrode 30 Print Substrate 31 Insulating layer 32, 32a to 32c Lower surface wiring layer 33, 33a to 33c Upper surface wiring layer 40 Power conversion device 41 to 44, 45a, 45b, 45c Conductive substrate

Claims (8)

a first semiconductor chip having a first control electrode on its front surface;
a second semiconductor chip having a second control electrode on the front surface;
a first control wiring layer having a striped shape in a plan view and having one end facing and electrically connected to the first control electrode;
a second control wiring layer which has a striped shape in a plan view and is mainly electrically connected when one end faces the second control electrode;
with
The first control wiring layer and the second control wiring layer extend with the other ends facing opposite directions, and the lengths of the first control wiring layer and the second control wiring layer in the extending direction are equal to each other,
semiconductor equipment. a printed circuit board including an insulating layer facing the first semiconductor chip and the second semiconductor chip and having the first control wiring layer and the second control wiring layer formed on a first main surface;
The semiconductor device of claim 1, further comprising: further comprising a first main electrode on the front surface of the first semiconductor chip,
further comprising a second main electrode on the front surface of the second semiconductor chip,
The printed circuit board further includes a first detection wiring layer and a second detection wiring layer formed on a second main surface opposite to the first main surface of the insulating layer,
the first detection wiring layer has a striped shape in a plan view, one end facing the first main electrode and electrically connected to the first main electrode;
the second detection wiring layer has a striped shape in a plan view, one end facing the second main electrode and electrically connected to the second main electrode;
The first detection wiring layer and the second detection wiring layer extend with the other ends facing opposite directions, and the lengths of the first detection wiring layer and the second detection wiring layer in the extending direction are equal to each other,
3. The semiconductor device according to claim 2. the lengths in the extending direction of the first detection wiring layer and the second detection wiring layer are the same as the lengths in the extending direction of the first control wiring layer and the second control wiring layer;
The first detection wiring layer and the second detection wiring layer are formed on the second main surface of the insulating layer facing the first control wiring layer and the second control wiring layer,
4. The semiconductor device according to claim 3. The first control electrode is provided on the first side of the front surface of the first semiconductor chip,
the second control electrode is provided on a second side of the front surface of the second semiconductor chip,
The first semiconductor chip and the second semiconductor chip are arranged such that the first side and the second side are parallel to each other,
5. The semiconductor device according to claim 1. The first side of the first semiconductor chip is arranged in series on an extension line of the second side of the second semiconductor chip,
6. The semiconductor device according to claim 5. The first side edge of the first semiconductor chip and the second side edge of the second semiconductor chip are arranged so as to be close to each other in the longitudinal direction of the semiconductor device,
6. The semiconductor device according to claim 5. a first insulating circuit board on which the first semiconductor chip is mounted;
a second insulated circuit board on which the second semiconductor chip is mounted;
further having
The first insulating circuit board includes a first insulating plate and a first circuit pattern formed on the front surface of the first insulating plate and bonded to the first semiconductor chip,
The second insulating circuit board includes a second insulating plate and a second circuit pattern formed on the front surface of the second insulating plate and bonded to the second semiconductor chip,
8. The semiconductor device according to claim 1.

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