JP2022162860A - Operator, operation system, and method for testing - Google Patents

Abstract

To specify a place of generation of an abnormality in hardware by a small number of test patterns.SOLUTION: The operator includes: a user circuit as a test target; a test pattern applying unit for inputting a test input as an input which toggles a signal in a test part in the user circuit, into the user circuit; a determination unit for determining whether the user circuit has an abnormality, on the basis of the output of the user circuit; and an abnormality part determination unit for specifying a place of generation of an abnormality in the hardware in the user circuit on the basis of the determination by the determination unit.SELECTED DRAWING: Figure 1

Description

The present invention relates to arithmetic devices, arithmetic systems, and test methods.

Compound-eye cameras and electronic control units for autonomous driving and advanced driver assistance systems need to process a large amount of sensing data, and the use of rewritable logic circuits is progressing as devices that handle data processing. In addition, with the spread of MaaS (Mobility-as-a-Service) such as car sharing, there is a demand for high operating rates of automobiles. It is necessary to carry out maintenance work and put it on the market as soon as possible after the renovation. However, there is a known problem that the number of combinations of element circuits increases significantly as the size of FPGA increases, and the number of test patterns for identifying failure factors increases, resulting in a longer test time. Patent Document 1 discloses a logic verification method for an information processing device, comprising steps of generating test data by referring to coverage information for managing completeness of logic verification of the information processing device; If it is determined that the test has been completed, the generated test data is determined to be invalid, and if it is determined that the generated test data has not been tested, the generated test data is determined to be valid. executing a pseudo test using the simulator of the information processing device using the generated test data determined to be valid to generate an expected value by the pseudo test; a step of updating coverage information with respect to the generated test data determined as; a step of executing a main test on an information processing device using the generated test data; and a main test executed on the information processing device. a step of comparing the result with the expected value to determine whether the test result is normal; performing a termination determination when the test result is determined to be normal; and logic when the termination condition is satisfied in the termination determination. A method is disclosed characterized by terminating the verification and repeating the above steps if the termination condition is not met.

JP 2014-164646 A

In the invention described in Patent Document 1, many test patterns are required to identify the location where the hardware abnormality occurs.

A computing device according to a first aspect of the present invention comprises a user circuit to be tested, a test pattern application unit for inputting a test input, which is an input toggling a signal at a test location in the user circuit, to the user circuit, and A determination unit that determines whether or not there is an abnormality in the user circuit based on the output of the user circuit, and an abnormal location determination unit that identifies a location of hardware abnormality in the user circuit based on the determination by the determination unit.
A computing system according to a second aspect of the present invention comprises a user circuit to be tested, a test pattern application section for inputting a test input, which is an input toggling a signal at a test location in the user circuit, to the user circuit, and A determination unit that determines whether or not there is an abnormality in the user circuit based on the output of the user circuit, and an abnormal location determination unit that identifies a location of hardware abnormality in the user circuit based on the determination by the determination unit.
A test method according to a third aspect of the present invention is executed by an arithmetic device comprising a user circuit to be tested and a test pattern applying unit for applying a test input, which is an input for testing the user circuit, to the user circuit. In the test method, the test pattern application unit inputs the test input that toggles the signal at the test location in the user circuit, and determines whether or not there is an abnormality in the user circuit based on the output of the user circuit. and identifying the location of the hardware failure in the user circuit.

According to the present invention, it is possible to specify the location of the occurrence of the hardware abnormality with a small number of test patterns.

Functional configuration diagram of the arithmetic unit in the first embodiment Diagram showing the concept of tests executed in the programmable logic unit Hardware configuration diagram of arithmetic unit and pre-calculation unit Diagram showing an example of test information Flowchart showing user circuit development processing by advance calculation device Flowchart showing test information creation processing Flowchart showing details of output route search processing Flowchart showing details of toggle pattern generation processing Diagram for explaining a specific example of test information creation processing Diagram for explaining a specific example of test information creation processing Functional Configuration Diagram of Arithmetic Device in Second Embodiment Functional configuration diagram of an arithmetic unit according to the third embodiment

-First Embodiment-
A first embodiment of an arithmetic device according to the present invention will be described below with reference to FIGS. 1 to 10. FIG.

FIG. 1 is a functional configuration diagram of an arithmetic device 70 according to the first embodiment. The arithmetic unit 70 includes a programmable logic unit 100 including a circuit to be tested, a test control unit 300 that controls test execution, and an error location determination unit 500 that specifies the location of hardware failure. Also, test information 400 is stored in the arithmetic unit 70 . Test information 400 is created by precomputer 80 .

FIG. 2 is a diagram showing the concept of a test executed in the programmable logic unit 100, and this test is widely known as BIST (Built-in Self Test). That is, the test pattern application unit 210 applies the test pattern to the second user circuit 222 to be tested, and the determination unit 230 compares the output result with the expected value. Before describing the details of the functional configuration of the arithmetic unit 70, the hardware configuration will be described.

FIG. 3 is a hardware configuration diagram of the arithmetic device 70 and the pre-calculation device 80. As shown in FIG. The arithmetic unit 70 includes a CPU 71 that is a central processing unit, a ROM 72 that is a read-only storage device, a RAM 73 that is a readable and writable storage device, a flash memory 74 that is a nonvolatile storage device, and a programmable logic circuit that is a rewritable logic circuit. A logic unit 100 and an output unit 75 are provided. The CPU 71 develops the program stored in the ROM 72 in the RAM 73 and executes the program, thereby realizing the test control section 300 and the abnormal point determination section 500 . Programmable logic unit 100 is, for example, an FPGA.

However, the arithmetic unit 70 uses FPGA (Field Programmable Gate Array), which is a rewritable logic circuit, or ASIC (Application Specific Integrated Circuit), which is an application specific integrated circuit, instead of the combination of CPU 71, ROM 72, and RAM 73. You may implement the function to Further, arithmetic device 70 may realize functions described later by combining different configurations, for example, by combining CPU 71 , ROM 72 , RAM 73 and FPGA instead of combining CPU 71 , ROM 72 and RAM 73 . Also, the FPGA referred to here may be the programmable logic unit 100 . The test information 400 may be stored in the flash memory 74 or may be stored in the ROM 72 .

The pre-calculation device 80 is a device that creates the test information 400 described above. The advance calculation device 80 includes a CPU 81, a ROM 82, a RAM 83, and a hard disk drive (HDD) 84, which is a non-volatile storage device. The CPU 81 develops the program stored in the ROM 82 in the RAM 83 and executes it, thereby realizing the functions described later. However, instead of the combination of the CPU 81, the ROM 82, and the RAM 83, the pre-calculation device 80 may implement functions described later by using FPGA, which is a rewritable logic circuit, or ASIC, which is an application-specific integrated circuit. Further, the pre-calculation device 80 may realize functions described later by combining different configurations, for example, by combining the CPU 81, the ROM 82, the RAM 83 and an FPGA, instead of the combination of the CPU 81, the ROM 82, and the RAM 83. Returning to FIG. 1, the description continues.

The programmable logic section 100 includes a test pattern application section 210 , a first user circuit 221 , a second user circuit 222 , a third user circuit 223 , a determination section 230 , a first selector 241 and a second selector 242 . In this embodiment, the second user circuit 222 is to be tested.

The first selector 241 connects the test pattern applying section 210 , the first user circuit 221 and the second user circuit 222 . For example, the first selector 241 connects the first user circuit 221 and the second user circuit 222 in an initial state, and upon receiving an operation command from the test control section 300, connects the test pattern applying section 210 and the second user circuit 222. Connecting. The second selector 242 connects the second user circuit 222 , the determination section 230 and the third user circuit 223 . For example, the second selector 242 connects the second user circuit 222 and the third user circuit 223 in an initial state, and connects the second user circuit 222 and the determination section 230 when an operation command is received from the test control section 300. .

The test information 400 includes input information 410 , expected value information 420 , and abnormal location identification information 430 . The input information 410 is information on signals to be input to the user circuit 220 for each test pattern. The input information 410 is transmitted to the test pattern application unit 210 through the test control unit 300 . The expected value information 420 is signal information describing that it is output from the user circuit 220 for each test pattern. Expected value information 420 is transmitted to determination section 230 via test control section 300 . The abnormal location identification information 430 is a combination of test patterns and abnormal locations. The abnormal location here is a configuration included in the second user circuit 222 .

The test control section 300 reads test information 400 , outputs input information 410 to the test pattern application section 210 , and outputs expected value information 420 to the determination section 230 . The test pattern application unit 210 outputs a signal to the second user circuit 222 based on the test pattern information received from the test control unit 300 . For example, the test pattern application unit 210 sequentially reads the list of test patterns from the top and outputs signals one after another every 100 ms.

The determination unit 230 determines whether the output of the second user circuit 222 matches the expected value based on the expected value information 420 received from the test control unit 300 . The determination unit 230 reads, for example, the list of expected values in order from the top, and evaluates on the premise that the next output is made every 100 ms. If the received signal does not match the expected value, the determining section 230 outputs test pattern information corresponding to the expected value to the abnormal location determining section 500 . Upon receiving the information of the test pattern, the abnormal location determination unit 500 refers to the abnormal location identification information 430 to identify the abnormal location.

(test information)
FIG. 4 is a diagram showing an example of test information 400. As shown in FIG. The test information 400 includes the input information 410, the expected value information 420, and the abnormal location identification information 430, as described above. In the example shown in FIG. 4, it is assumed that the second user circuit 222 to be tested has three or more inputs and two outputs. In the example shown in FIG. 4, the name of the test pattern is a combination of the test location and the number "1" or "2". Specifically, the "pattern A1" is the "1" test for the location "A", and the "pattern A2" is the "2" test for the location "A". Although only two test patterns are mainly described in FIG. 8, other test patterns such as "pattern B1", "pattern B2", and "pattern C1" may be included.

The input information 410 indicates input values to the second user circuit 222 for each test pattern. The expected value information 420 indicates the expected output value of the second user circuit 222 for each test pattern. The abnormal location identification information 430 stores information on the abnormal location for each test pattern.

An example of a test using the test information 400 illustrated in FIG. 4 will be described. The test pattern application unit 210 reads, for example, the test patterns described in the input information 410 in order from the top, and outputs the specified input value to the second user circuit 222 every 100 ms. The determination unit 230 reads the expected value information 420 and determines every 100 ms whether or not the output of the second user circuit 222 matches the output value described in the expected value information 420 every 100 ms. For example, the determination unit 230 determines whether the output of the second user circuit 222 matches the expected value of the pattern A1 for the first 100 ms, and the output of the second user circuit 222 matches the expected value of the pattern A2 for the next 100 ms. It is determined whether or not it matches with

When judging that the output of the second user circuit 222 and the expected value do not match, the judging section 230 outputs the name of the test pattern to the abnormal point judging section 500, for example. The determination unit 230 can identify the test pattern currently being tested, for example, based on the elapsed seconds from the start of the test and the information that the tests are executed in order from the top described in the expected value information 420 . Upon receiving the name of the test pattern from the determination unit 230, the abnormal location determination unit 500 refers to the abnormal location identification information 430 to identify the location where the hardware failure occurred.

(Creation of test information)
5 to 10, the process of creating test information 400 by pre-calculation device 80 and the process of developing a user circuit, which is the premise thereof, will be described. FIG. 5 is a flow chart showing the development processing of the user circuit by the pre-calculation device 80. As shown in FIG. The pre-computing device 80 develops at least the second user circuit 222 by the development process described below. Note that this development process uses the test information 400 obtained by the process described later. The execution subject of each step described below is the CPU 81 of the pre-calculation device 80 or a developer.

The developer first examines the specifications of the user circuit in step S1001, and then designs the logic in step S1002. The developer verifies the designed logic in step S1003, and optimizes the circuit, that is, performs logic synthesis in step S1004. Note that the information generated in step S1004 is hereinafter referred to as "logical information A". In the following step S1005, the layout and wiring of the logically synthesized circuit, that is, the layout and wiring are determined. The information generated in step S1005 is hereinafter referred to as "connection information B". In subsequent step S1006, logic information A and connection information B generated in steps S1004 and S1005 are output. These pieces of output information are used in test information generation processing, which will be described later.

In step S1007, a configuration file to be written to the programmable logic unit 100 is generated, and in step S1008, the operation is verified using the actual programmable logic unit 100. FIG. In subsequent step S1009, test information obtained by test information generation processing, which will be described later, is acquired, and in step S1010, the test information is stored in the arithmetic unit 70. FIG. The process of creating the test information 400 will be described below with reference to FIGS. 6 to 10. FIG.

9 and 10 are diagrams for explaining a specific example of the processing for creating the test information 400. FIG. The top center of FIG. 9 shows the configuration of the second user circuit 222 . FIGS. 9 and 10 will be referred to as needed to describe the specific processing of the flowcharts described below, and the configuration of the second user circuit 222 exemplified above will be described. The second user circuit 222 shown in FIG. 9 has a plurality of flip-flops hatched with dots and lookup tables (hereinafter also referred to as "LUTs") hatched with oblique lines.

Specifically, the second user circuit 222 includes first to eighth flip-flops F1 to F8 and first to fifth lookup tables L1 to L5. Inputs from the outside of the second user circuit 222 are input to the first to sixth flip-flops F1 to F6, respectively. The outputs of the first flip-flop F1 and the second flip-flop F2 are input to the first lookup table L1.

The outputs of the third flip-flop F3 and the fourth flip-flop F4 are input to the second lookup table L2. The outputs of the fifth flip-flop F5 and the sixth flip-flop F6 are input to the third lookup table L3. The output of the fourth lookup table L4 is input to the seventh flip-flop F7, and the output of the seventh flip-flop F7 becomes the first output of the second user circuit 222. FIG. The output of the fifth lookup table L5 is input to the eighth flip-flop F8, and the output of the eighth flip-flop F8 becomes the second output of the second user circuit 222. FIG.

The first lookup table L1 has two inputs and two outputs. The first lookup table L1 receives inputs from the first flip-flop F1 and the second flip-flop F2 and outputs to the fourth lookup table L4 and the fifth lookup table L5. The second lookup table L2 has two inputs and one output. The second lookup table L2 receives inputs from the third flip-flop F3 and the fourth flip-flop F4 and outputs to the fifth lookup table L5. The third lookup table L3 has two inputs and one output. The third lookup table L3 receives inputs from the fifth flip-flop F5 and the sixth flip-flop F6 and outputs to the fifth lookup table L5.

The fourth lookup table L4 has one input and one output. The fourth lookup table L4 receives input from the first lookup table L1 and outputs to the seventh flip-flop F7. The fifth lookup table L5 has 3 inputs and 1 output. The fifth lookup table L5 receives inputs from the first lookup table L1, the second lookup table L2, and the third lookup table L3 and outputs them to the eighth flip-flop F8.

FIG. 6 is a flowchart showing test information creation processing. The CPU 71 executes the processing shown in FIG. In the test information creation process, first, logic information A and connection information B are obtained in step S1021. In subsequent step S1022, the CPU 71 uses the connection information B to perform output route search processing. Details of the output route search processing will be described later. In subsequent step S1023, the CPU 71 selects an unprocessed route as a processing target. In subsequent step S1024, the CPU 71 performs toggle pattern generation processing for the route to be processed. The details of the toggle pattern generation process will be described later.

In subsequent step S1025, the CPU 71 determines whether or not all routes have been processed. If it is determined that all routes have been processed, the process proceeds to step S1025. return. In the final step S1026, the CPU 71 outputs the test information 400 created in the toggle pattern generation process, and terminates the process shown in FIG.

FIG. 7 is a flowchart showing details of the output route search process. First, in step S1201, the CPU 71 selects an unprocessed output pin. The output pins are the outputs of the user circuit under test, which are "output 1" and "output 2" in the second user circuit 222 shown in FIG. When step S1201 is executed for the first time, either "output 1" or "output 2" is selected, and when it is executed for the second time, the one that was not selected in the first time is selected. The output pin selected in this step is hereinafter referred to as a "selected pin".

In subsequent step S1202, the CPU 71 extracts the logic block connected to the selection pin toward the upstream. The "upstream" here is the input side to the user circuit, which is the left side in the example shown in FIG. In subsequent step S1203, the CPU 71 records the paths and logic blocks to all input terminals. For example, in the example shown in FIG. 9, the fifth lookup table L5 has three inputs, so the route branches into three when going upstream from "output 2", but all of them are traced to the input.

In subsequent step S1204, the CPU 71 determines whether or not all output pins have been selected. If the CPU 71 determines that all the output pins have been selected, it ends the processing shown in FIG. The above is the description of FIG. Through this output route search process, the first route 220A and the second route 220B are searched for in the example shown in FIG.

FIG. 8 is a flowchart showing details of the toggle pattern generation process in step S1024 of FIG. Note that the route to be processed is selected in step S1023 of FIG. 6 immediately before this process is executed. First, in step S1301, the CPU 71 identifies outputs of all lookup tables (LUTs) included in the path to be processed. For example, in the example shown in FIG. 9, when "output 1" is selected, two LUT outputs are identified: one output from the fourth lookup table L4 and one output from the first lookup table L1. be.

In subsequent step S1302, the CPU 71 selects one of the unprocessed outputs of the LUT among the outputs identified in step S1301 as a processing target. In subsequent step S1303, the CPU 71 reads the memory information of the LUT to which the selected output belongs. Memory information is a correspondence table of input values and output values in a lookup table. In the subsequent step S1304, the CPU 71 identifies the input value to the LUT that toggles the selected output value. In subsequent step S1305, the CPU 71 identifies and records the input value of the user circuit corresponding to the identified input value to the LUT. Note that the input value specified and recorded in this step is used for the input information 410 .

A specific example of steps S1303 to S1306 will be described. For example, when the output of the fourth lookup table L4 is selected for processing as shown in the upper part of FIG. 10, the CPU 71 reads memory information as shown in step S1303. In step S1304, the CPU 71 specifies "0" and "1" as input values to the fourth lookup table L4 that toggles the selected output. In subsequent step S1305, the CPU 71 identifies the inputs to the second user circuit 222 whose input values to the fourth lookup table L4 are "0" and "1".

For this identification, the CPU 71 first reads the memory information of the first lookup table L1 existing upstream of the fourth lookup table L4. Next, the CPU 71 specifies the values of "input 1" and "input 2" corresponding to the output "0" and the values of "input 1" and "input 2" corresponding to the output "1". Record. Note that in this case, there are a plurality of input values that cause the output of the first lookup table L1 to be "0" and "1", but the CPU 71 may select any of them. In addition, the second user circuit 222 shown in FIG. 9 has six inputs "input 1" to "input 6", and the values of "input 3" to "input 6" are specified within the scope of the description given here. not specified, these values are arbitrary.

Furthermore, as will be described later, when the output of the first lookup table L1 is selected as the next processing target by loop processing, in the example shown in FIG. 10, the combination of input values toggles the output of the fourth lookup table L4. may be the same as if However, in this embodiment, overlapping combinations of input values are allowed, and simplicity of processing is prioritized. The above is a description of a specific example of steps S1303 to S1305.

In subsequent step S1306, the CPU 71 identifies and records the output value of the user circuit corresponding to the input value of the user circuit identified in step S1305. Note that the output value specified and recorded in this step is used for the expected value information 420 . In the subsequent step S1307, the CPU 71 stores the combination of the input value specified in step S1304, the output value specified in step S1306, and the name of the lookup table to which the output to be processed selected in step S1302 belongs as part of the test information 400. Record.

Specifically, in step S1307, the combination of the input value specified in step S1304 and an arbitrary name is set as a new record of the input information 410. FIG. Also, the combination of the output value identified in step S1306 and the above arbitrary name is set as a new record of the expected value information 420. FIG. Furthermore, a combination of the arbitrary name described above and the name of the lookup table to which the output to be processed selected in step S1302 belongs is used as a new record of the abnormal location identification information 430 .

In subsequent step S1307, the CPU 71 determines whether or not all the outputs identified in step S1301 have been selected as processing targets. If the CPU 71 determines that all outputs have been selected as processing targets, it ends the processing of FIG.

(1) The arithmetic unit 70 includes a second user circuit 222 to be tested, a test pattern application unit 210 for inputting a test input, which is an input toggling a signal at a test location in the second user circuit 222, to the user circuit, A judgment unit 230 for judging whether or not there is an abnormality in the second user circuit 222 based on the output of the second user circuit 222; and a determination unit 500 . Therefore, it is possible to identify the location of the hardware abnormality with a small number of test patterns.

(2) The determination unit 230 determines whether there is an abnormality in the user circuit based on whether there is a change in the output of the user circuit. Therefore, the determination unit 230 can detect degeneracy in which the output is fixed to "0" or "1".

(3) A test point is each output of a lookup table contained in the user circuit.

(Modification 1)
In the first embodiment described above, the programmable logic unit 100 includes three user circuits, the first user circuit 221, the second user circuit 222, and the third user circuit 223. Of these, the second user circuit 222 only were tested. However, the entire user circuit may be tested. In this case, the first user circuit 221 in FIG. 2 replaces the input signal circuit to the user circuit, and the third user circuit 223 in FIG. 2 replaces the output signal circuit to the user circuit.

(Modification 2)
In the first embodiment described above, the programmable logic section 100 includes the test pattern application section 210 , the determination section 230 , the first selector 241 and the second selector 242 . However, since these are unnecessary except for testing, they need not always be arranged in the programmable logic section 100 . In that case, for example, the test pattern application unit 210, the determination unit 230, the first selector 241, and the second selector 242 are configured in the programmable logic unit 100 by partial reconfiguration, the test pattern application unit 210, and the determination unit. 230 , first selector 241 , and second selector 242 .

(Modification 3)
In the above-described first embodiment, the determination unit 230 detects the defect that the output of the lookup table is fixed, that is, the so-called 0/1 degeneracy. However, in addition to the 0/1 degeneracy, the determination unit 230 may further detect a delay fault, which is a fault in which a signal change is slower than specified. Since the expected value information 420 includes the expected value for each output, the delay when the expected value toggles, specifically at least one of the dead time and the time constant, is evaluated.

According to this modified example, the arithmetic unit 70 has the following effects.
(4) The determination unit 230 determines whether or not there is an abnormality in the user circuit based on the delay in change in the output of the user circuit. Therefore, the determination unit 230 can detect delay faults.

(Modification 4)
In the embodiment described above, the entire configuration shown in FIG. However, the configuration shown in FIG. 1 may be implemented by two or more pieces of hardware. For example, the programmable logic unit 100, the test control unit 300, and the abnormal location determination unit 500 may be configured as separate pieces of hardware such as an ECU or a microcomputer. In this case, the configuration shown in FIG. 1 can be called an arithmetic system.

(Modification 5)
In the above-described first embodiment, overlapping combinations of input values are allowed in the toggle pattern generation processing, and simplicity of processing is prioritized. However, a toggle pattern may be generated so that the total number of input values is reduced rather than simplicity of processing.

-Second Embodiment-
A second embodiment of the arithmetic device will be described with reference to FIG. In the following description, the same components as those in the first embodiment are assigned the same reference numerals, and differences are mainly described. Points that are not particularly described are the same as those in the first embodiment. The present embodiment is different from the first embodiment mainly in that the determination result of the abnormal location determination unit is transmitted.

FIG. 11 is a functional configuration diagram of an arithmetic unit 70A according to the second embodiment. In addition to the configuration of the arithmetic device 70 in the first embodiment, the arithmetic device 70A further has a transmission unit 700 that notifies the outside of the arithmetic device 70A, such as a server or data center, of the abnormality diagnosis result. Transmitter 700 is, for example, a wireless communication module compatible with 4G and 5G.

According to the second embodiment described above, the following effects are obtained.
(5) Arithmetic device 70A includes transmission section 700 that transmits the determination result of abnormal location determination section 500 . Therefore, it is possible to notify the server or data center of abnormal locations, and by analyzing logs and data, it is possible to identify areas that are prone to abnormalities, provide feedback to design, and facilitate maintenance.

-Third Embodiment-
A third embodiment of the arithmetic device will be described with reference to FIG. In the following description, the same components as those in the first embodiment are assigned the same reference numerals, and differences are mainly described. Points that are not particularly described are the same as those in the first embodiment. The present embodiment is different from the first embodiment mainly in that an arithmetic device is installed in a vehicle and notifies an occupant of the vehicle of an abnormality.

FIG. 12 is a functional configuration diagram of an arithmetic unit 70B in the third embodiment. In addition to the configuration of the arithmetic device 70 in the first embodiment, the arithmetic device 70B further has a notification unit 800 that notifies the driver of the vehicle in which the arithmetic device 70B is mounted of the determination result. The notification unit 800 may be a speaker for notification by sound, a light for notification by light, or an image display device for notification by video. The notification unit 800 notifies the driver of the vehicle of the determination result based on the determination result of the abnormal location determination unit 500 using at least one of sound, light, and video.

According to the third embodiment described above, the following effects are obtained.
(6) The electronic control unit 70B includes a notification unit 800 that notifies the vehicle occupant of the determination result of the abnormal location determination unit 500 . Therefore, it is possible to notify the driver in real time while the vehicle is in operation, enabling safety control and alerting.

In each of the embodiments and modifications described above, the configuration of the functional blocks is merely an example. Some functional configurations shown as separate functional blocks may be configured integrally, or a configuration represented by one functional block diagram may be divided into two or more functions. Further, a configuration may be adopted in which part of the functions of each functional block is provided in another functional block.

Each of the embodiments and modifications described above may be combined. Although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other aspects conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.

70, 70A, 70B...Arithmetic device 80...Pre-calculation device 100...Programmable logic unit 210...Test pattern applying unit 222...Second user circuit 230...Judging unit 300...Test control unit 400...Test information 410...Input information 420...Expectation Value information 430 Abnormal location identification information 500 Abnormal location determination unit 700 Transmission unit 800 Notification unit

Claims (8)

a user circuit under test;
a test pattern application unit for inputting a test input, which is an input toggling a signal at a test location in the user circuit, to the user circuit;
a determination unit that determines whether or not there is an abnormality in the user circuit based on the output of the user circuit;
An arithmetic device, comprising: an error location determination unit that specifies a location of occurrence of a hardware error in the user circuit based on determination by the determination unit. The arithmetic device according to claim 1,
The determination unit determines whether or not there is an abnormality in the user circuit based on whether or not there is a change in the output of the user circuit. The arithmetic device according to claim 1,
The determination unit determines whether or not there is an abnormality in the user circuit based on a delay in change in the output of the user circuit. The arithmetic device according to claim 1,
The arithmetic unit, wherein the test points are respective outputs of a lookup table included in the user circuit. The arithmetic device according to claim 1,
A computing device, further comprising a transmission unit that transmits a determination result of the abnormal location determination unit. The arithmetic device according to claim 1,
The computing device is mounted on a vehicle,
The electronic control device further comprising a notification unit that notifies an occupant of the vehicle of the determination result of the abnormal location determination unit. a user circuit under test;
a test pattern application unit for inputting a test input, which is an input toggling a signal at a test location in the user circuit, to the user circuit;
a determination unit that determines whether or not there is an abnormality in the user circuit based on the output of the user circuit;
An arithmetic system, comprising: an error location determination unit that identifies a location of hardware failure in the user circuit based on determination by the determination unit. A test method executed by an arithmetic device comprising a user circuit to be tested and a test pattern application unit that applies a test input for testing the user circuit to the user circuit,
the test pattern application unit inputs the test input that toggles a signal at a test location in the user circuit;
Determining whether or not there is an abnormality in the user circuit based on the output of the user circuit;
and identifying a location where a hardware anomaly occurs in the user circuit.

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