JP6446937B2 - Logic analysis terminal, logic analysis system, delay correction method, and program - Google Patents

Description

The present invention relates to a logic analysis terminal, a logic analysis system, a delay correction method, and a program.

  In the development of an ASIC (Application Specific IC), design verification is performed using a test in which individual blocks are assembled on a breadboard, a logic simulator, or the like. For example, as disclosed in Patent Document 1 and Patent Document 2, PLD (Programmable Logic Device) such as FPGA (Field Programmable Gate Array) has been developed. The FPGA is a large number of SRAM (Static RAM (Random Access Memory)) LUTs (Look-up Tables), flip-flops (FFs), and switch switches called Interconnects that connect them to each other. This is an LSI (Large Scale Integrated circuit) in which a matrix and other elements are integrated on one chip. By controlling the storage contents of the LUT and the internal wiring state by the interconnect, a desired logical operation can be realized within the range of the degree of integration. LUT and interconnect settings are programmable. That is, the logic operation of the FPGA can be rewritten any number of times. An FPGA may be incorporated into a final product, but is often used for trial production of a logic circuit to be manufactured as an ASIC.

  FIG. 1 is a diagram schematically showing a general configuration of an FPGA. The FPGA chip 1 includes a plurality of logic elements (LEs) 101 each including LUTs and FFs (not shown), and interconnects the LEs 101 and the I / O pins 103 with each other. ) 102 is provided. Some types have built-in dedicated macro blocks such as multipliers and memory blocks. The LE 101 includes an LUT and a flip-flop.

  FIG. 2 is a diagram schematically showing a general schematic configuration of the LE 101 of FIG. The LUT 110 includes a plurality of SRAM (Static RAM) cells 111 and a multiplexer 112 that selects one of two inputs. The plurality of SRAM cells 111 and the plurality of multiplexers 112 constitute an address decoder. The inputs IN [0] to IN [2] of the LUT 110 are selection signals for the respective stages of the multiplexer 112 connected to the third stage in the tournament system, and the output of the third stage multiplexer 112 is the output of the LUT 110. .

  FIG. 3 is a diagram schematically showing a general structure of the LUT 110 of FIG. The LUT can realize an arbitrary logical function (truth table) depending on the contents stored in the SRAM cell 111, which is called an LUT mask. The multiplexer 112-1, which receives the outputs of the SRAM cells 111-1, 111-2, the multiplexer 112-2, which receives the outputs of the SRAM cells 111-3, 111-4, and the outputs of the multiplexers 112-1, 112-2 Is input, the input X is the selection signal of the multiplexer 112-1, 112-2, the input Y is the selection signal of the multiplexer 112-3, and the output of the multiplexer 112-3 is the output Z of the LUT 110. It is said. The LUT 110 in FIG. 4A shows the contents of an LUT mask that has two inputs X and Y and implements an AND function (Z = AND (X, Y)) with a two-input LUT. FIG. 4B is a truth table of the AND function of FIG. FIG. 4A shows an example of a 2-input LUT, but it goes without saying that the number of inputs of the LUT is not limited to 2, 3 or the like. A complex combinational logic circuit (combination circuit) that cannot be realized with one LUT is configured such that the combinational logic output COUT of the LUT is connected to the input of another adjacent LUT via an interconnect and is connected in a dependent manner. realizable. Further, by adopting a configuration in which the LUT inputs are fixedly connected to ‘1’ or ‘0’, it is possible to simulate an LUT with a smaller number of inputs.

  With the recent progress of miniaturization of semiconductor technology and improvement of integration, the complexity of logic circuits tends to increase. For this reason, it has been difficult or impossible to achieve an error-free state from the beginning only by prior design verification using a general-purpose module or a logic simulator. In the current logic circuit design, assuming that errors are included in the initial stage, the logic circuit under trial production is written (or “set”) into a PLD (Programmable Logic Device) element such as an FPGA, and an actual machine test is performed. The method of repeating the work of removing errors (debugging work) has become the mainstream.

  As shown in FIG. 5, there is a method in which an internal node of an observation target circuit is drawn out to an I / O pin of a PLD and displayed by an external logic analyzer 50.

U.S. Pat. No. 4,870,302 US Pat. No. 4,642,487 Japanese Patent Laid-Open No. 11-296403 Japanese Patent No. 3868833 JP 2006-308584 A

"XC3000 Series Technical Information," XAPP 024 (Version 1.0), 1997/11/24, Internet (URL: http://www.xilinx.com/support/documentation/application_notes/xapp024.pdf)

  The analysis of related technology is given below.

  Although the method shown in FIG. 5 is widely used because of its simplicity, there are some problems.

  The first problem is that since the logic analyzer 50 is large and expensive, there is a difficulty in availability.

  The second problem is that the PLD (FPGA 20) uses as many I / O pins for monitoring as the number of internal nodes to be observed. For this reason, especially when a PLD with a small number of I / O pins is used, I / O pin conflict occurs between the purpose of fulfilling the originally required function and the purpose of observing internal signals. With the widespread use of FBGA (Fine-line Ball Grid Array) packages, FPGAs with about 2000 pins can be used. However, the routing of observation signals limits the layout of the board. This increases the size of the connector for connection.

  In order to partially solve this problem, for example, as shown in FIG. 5, a multiplexer 22 is installed inside the FPGA 20, and the observation target node is switched as necessary. Even if this method is used, the number of I / O pins for monitoring in the FPGA 20 cannot be less than the number of internal nodes to be observed simultaneously.

  The third problem is that it is difficult to achieve both the signal quality of the observation target signal (for example, the visibility as the observation target signal) and the ease of placement and wiring of the FPGA.

  Patent Document 3 discloses a configuration in which a signal can be captured both before and after a trigger condition (breakpoint) by embedding a logic (logic) analyzer in a programmable logic device. . In this configuration, the logic analyzer function is incorporated into the FPGA itself, and the function is controlled from an external host computer via the JTAG (Joint Test Action Group) port of the FPGA. The connection between the host computer and the FPGA uses an inexpensive and small product known as “Byte Blaster”, which eliminates the need for an external logic analyzer and is inexpensive and small. (Availability) is improved. Further, since it is not necessary to secure the I / O pin of the FPGA as a monitor pin, it can be said that the second problem is also improved. Furthermore, since the observation target signal is captured in synchronization with the clock edge, the inter-bit skew and asynchronous glitch do not impair the visibility of the observation target signal, and the third problem has been partially solved. I can say that.

  However, the configuration of Patent Document 3 has a problem that a large amount of FPGA placement and routing resources are used to store the observation target waveform therein. The storage capacity that can be secured inside the FPGA is limited. For this reason, for example, it is impossible to observe and store the observation target waveform for a long time.

  Patent Document 4 discloses a configuration in which an observation target signal is stored in a pod box unit and transferred from the pod box to a host computer instead of relying on the storage capacity inside the FPGA.

  In Patent Document 4, a synchronization flip-flop (“register”) is used to extract an observation target signal from a development target FPGA to a pod box unit. This is a problem in the design of large-scale FPGAs that use high-speed clocks. The use of the synchronization flip-flop means that the timing constraint of the path from the observation target node to the synchronization flip-flop is attached, and not only the monitor-related path but also the timing request of the entire FPGA. There is a high possibility that it will be difficult to satisfy.

  Patent Document 5 discloses a system that receives digital signals through channels each having a data receiver, and operates in at least one group including at least two channels and the data receivers of the two channels. , A method for selecting constrained sampling parameter values for the collection is disclosed. According to Patent Document 5, even if it is possible to determine the stable point of the monitor data with the monitor clock for each bit, the skew between the bits is large in the monitor data in which a plurality of bits are bundled to form a bus. In some cases, it is possible to mistake which clock cycle the stable point of each bit belongs to. For example, in FIG. 8, the change point of the parallel 4-bit data DATA [3] to [0] marked with a black circle ● belongs to the rising edge of the white circle ○ with the number “1” among the rising edges of the monitor clock. In the configuration of Document 5, there is a possibility that DATA [2] belongs to the rising edge with the number “0”, and DATA [0] belongs to the rising edge with the number “2”.

  Further, in Patent Document 5, when the placement and routing is performed on the monitor circuit with timing relaxation conditions, the delay in the FPGA is large for each monitor surface (for example, a bus of a set (collection) of signals to be monitored). It varies. For this reason, even if the monitor plane is switched to the test signal and the data capture phase is adjusted, if the delay amount in the FPGA shifts after switching to the monitor plane including the observation target node (especially one cycle). When the above changes), there is a problem that the phase is shifted from the correct data capturing phase.

  Therefore, the present invention has been made in view of the above problems, and an object thereof is to provide a logic analysis system that facilitates observation of an observation target signal.

According to one aspect of the present invention, a monitor circuit is mounted on a semiconductor device and monitors an internal state of the semiconductor device, and inputs a plurality of observation target signals of a plurality of observation target nodes inside the semiconductor device. A first multiplexer that selects and outputs an observation target signal according to a first selection signal; a second multiplexer that receives a plurality of clock signals and selects and outputs a monitoring clock signal according to a second selection signal; , And at least one of the first and second multiplexers includes a multiplexer configured to suppress glitch propagation to the output with respect to a change in polarity of at least one of the plurality of signal inputs. Including a monitor circuit ;
A logic analysis terminal that receives a signal from the monitor circuit,
A second clock source;
A serial receiving circuit that receives a signal transmitted serially from the monitor circuit and converts it into a parallel signal;
A second buffer unit for writing a parallel signal from the serial receiving circuit with a parallel clock signal from the serial receiving circuit and reading with a clock signal from the second clock source;
A second delay correction circuit for correcting a delay of a signal transmitted in parallel from the monitor circuit;
A fourth multiplexer that receives a clock signal selected by the second multiplexer of the monitor circuit or a clock signal from the second clock source and selects one based on a fourth selection signal;
A third buffer unit for writing the observation target signal received from the monitor circuit with the clock signal selected by the fourth multiplexer, and reading with the clock signal from the second clock source;
There is provided a logic analysis system including a logic analysis terminal including a storage unit for storing signals read from the second and third buffer units .

According to another aspect of the present invention, a transmission end that switches and transmits an observation target signal of an observation target node inside a semiconductor device and a test signal from a test signal generation circuit, and a reception end of a signal from the transmission end Compensation of delay in a circuit in which there is a delay between and using a computer,
A first delay analysis result: A is obtained from a timing analysis of a placement and routing result of a path from the drive clock source of the test signal generation circuit to the transmission end,
The second delay analysis result: B is acquired from the timing analysis of the placement and routing result of the path from the drive clock source of the observation target node to the transmission end,
When the test signal is transmitted, a delay correction value C is obtained when the test signal is normally received at the receiving end, and the observation target signal is normally received by A−B + C. A delay correction method for obtaining a delay correction value necessary for the above is provided.

According to another aspect of the present invention, a transmission end that switches and transmits an observation target signal of an observation target node inside a semiconductor device and a test signal from a test signal generation circuit, and a reception end of a signal from the transmission end A program for causing a computer to perform delay correction in a circuit having an unknown delay between
A process of obtaining a first delay analysis result: A from a timing analysis of a placement and routing result of a path from the drive clock source of the test signal generation circuit to the transmission end;
A process of acquiring a second delay analysis result: B from a timing analysis of a placement and routing result of a path from the drive clock source of the observation target node to the transmission end;
When the test signal is transmitted, a delay correction value C is obtained when the test signal is normally received at the receiving end, and the observation target signal is normally received by A−B + C. And a process for obtaining a delay correction value required for the program. According to the present invention, a computer-readable recording medium (for example, a medium such as a semiconductor memory or a magnetic / optical disk) on which the program is recorded is provided.

  According to the present invention, observation of a signal to be observed can be facilitated.

It is a figure explaining related technology. It is a figure explaining LE of FIG. It is a figure explaining LUT of FIG. (A) is a figure explaining LUT of FIG. 2, (B) is a truth table. (A) is a figure explaining related technology, (B) is a figure explaining the delay in (A). (A) is a figure explaining the example of arrangement | positioning wiring, (B) is a figure explaining the timing of (A). (A) is a figure explaining the example of arrangement | positioning wiring, (B) is a figure explaining the timing of (A). It is a figure explaining the skew between bits. (A) is a figure explaining the example arrangement wiring example which replaced 2-input MUX of the DNF format with the logic circuit, (B) is a figure which illustrates typically the signal waveform of (A). (A) is a figure explaining the example arrangement wiring example which replaced the 2-input MUX of the ANF format with the logic circuit, (B) is a figure which illustrates typically the signal waveform of (A). (A) is a figure explaining the monitor circuit of a two-stage pipeline structure, (B) is a figure explaining the delay in (A). FIG. 12 is a timing diagram illustrating the operation of FIG. 11. It is a figure explaining the structure of one Embodiment of this invention. It is a figure explaining the example of the bit conversion in one Embodiment of this invention. It is a figure explaining another example of the bit conversion in one embodiment of the present invention. It is a figure explaining the structure of one Embodiment of this invention. (A) is a configuration of a 2-input MUX configured with a 3-input LUT, (B) is a truth table, (C) is a signal waveform, and (D) and (E) are enlarged views of the waveform of (C). . (A) is a figure explaining the timing restrictions in one Embodiment of this invention, (B) is a figure which illustrates typically a signal waveform. It is a figure explaining the output of the test signal generation circuit in one Embodiment of this invention. (A) And (B) is a figure explaining the delay in FPGA in one Embodiment of this invention. It is a figure explaining the example of the delay correction | amendment in one Embodiment of this invention. (A) And (B) is a figure explaining the delay at the time of a test signal output in the parallel monitor circuit of one Embodiment of this invention. (A) And (B) is a figure explaining the delay at the time of observation object signal output in the parallel monitor circuit of one Embodiment of this invention. It is a figure explaining the delay measurement of the parallel monitor in one Embodiment of this invention. It is a flowchart (the 1) explaining the calculation procedure of the delay correction amount in one Embodiment of this invention. It is a flowchart (the 2) explaining the calculation procedure of the delay correction amount in one Embodiment of this invention.

  In the following, first, as a premise of the invention, the third problem described above will be described based on the analysis by the present inventor, and then the outline and embodiments of the invention will be described.

  As the operation clock speed of the observation target signal increases and the integration degree of the FPGA increases, it is difficult to achieve both the signal quality of the observation target signal (ease of being viewed as the observation target signal) and the ease of placement and wiring of the FPGA. Become. First, a typical FPGA development process will be described. The development process is, for example, a repetition of the following processes (1) to (6).

(1) VHDL (VHSIC (Very High-Speed Integrated Circuit)) A source code describing a desired logic operation is created by a hardware description language (HDL) such as Verilog.

(2) Separately define timing constraints for logic circuits and other circuit generation conditions.

(3) The source code is converted into a net list of a gate level lower than that of the hardware description language by logic synthesis software.

(4) The logic synthesis result is assigned to LUTs and interconnects scattered on the FPGA chip by the placement and routing software and converted into setting contents (configuration data) of the FPGA chip.

(5) The placement and routing result is verified by the timing analysis software, and it is confirmed whether or not the timing constraint given in (2) is satisfied. If not, the step (4) is repeated. At this time, by starting from an initial placement state different from the previous time, a placement and routing result (and thus a different timing analysis result) different from the previous time is obtained.

(6) As a result of timing analysis, if it can be confirmed that the placement and routing result satisfies the timing constraint, an actual machine test is performed to check whether there is an error in the logic circuit. If there is an error, the logic operation design of (1) is repeated.

  Note that the timing constraints and other circuit generation conditions given in (2) above are not only the timing analysis in (5) above, but also software in the logic synthesis in (3) above and the placement and routing steps in (4) above. Affects the behavior of

Here, timing constraints are roughly divided into
(A) a system (a “timing constraint” in a narrow sense) that defines the required specifications of the logic circuit, such as the minimum operating frequency to be satisfied by the logic circuit or the maximum allowable delay;
(B) A portion of the logic circuit that does not have a minimum operating frequency and does not require timing analysis (somewhat slow in operation speed is acceptable, as long as it is connected, it is expected to operate correctly) There is a system ("relaxation system timing constraint") that defines a circuit) as a relaxation condition.

  The timing constraint (A) is given as parameters such as the operating frequency and the maximum allowable delay.

  (B) is defined for each path as a false path (false path: path that can be ignored during timing analysis) designation or multicycle designation. For example, when multi-cycle constraints are specified, the severity of setup or hold verification is relaxed by the specified number of clock cycles.

  Both the timing constraints (A) and (B) can be defined by a well-known description language such as SDC (Synopsis Design Constraints) format of Synopsys Incorporated.

  In principle, all of the circuits are subject to restrictions on either system (A) or (B). Hereinafter, when simply referred to as a timing constraint, it refers to the timing constraint of (A).

  In order to satisfy the given condition, the circuit given the timing constraint is synthesized in a configuration that facilitates high-speed operation in the logic synthesis step (3). Also, in the placement and routing step (4), the circuit to which the timing constraint is applied receives preferential treatment over the other circuits in order to satisfy the requested timing.

  On the contrary, the circuit with the timing constraint of the relaxed system does not need to consider the timing performance in the logic synthesis process of (3) above, and is optimized in terms other than the speed, and the circuit area (for example, The number of LEs used) and power consumption are often reduced.

  In addition, in the placement and routing process of (4) above, the circuit to which the timing constraints of the relaxed system are given priority is given to the circuit with more severe timing requirements. This results in much worse than a constrained circuit. Originally, the timing constraints of the relaxation system are premised on being applied to a circuit having no timing requirement or a loose circuit. For this reason, even if the timing performance deteriorates, there is essentially no problem, but the situation is different when applied to a monitor circuit. More details will be described later.

  Note that if the usage rate of resources such as LUTs and interconnects integrated in the FPGA is high or the clock frequency is high, the above steps (4) to (5) may be executed once even if the process is executed only once. Placement and routing results that satisfy For this reason, it is often necessary to repeat the steps (4) to (5) a plurality of times while changing the initial arrangement. Even if the initial arrangement is changed slightly, the final timing analysis results will be different. For this reason, for example, the result of satisfying the timing constraint appears by performing many placement and routing trials while slightly changing the initial placement. Here, as a case where it is difficult to satisfy the timing requirement, a specific example is given below.

The equivalent number of integrated logic elements of the FPGA type used: 700,000,
Operation clock frequency of logic circuit mounted on FPGA: 250 MHz (Mega Herz),
Logic element usage ratio of the logic circuit mounted on the FPGA: 90%.

  The realization of the operation clock frequency of 250 MHz is often relatively easy because the degree of freedom of placement and routing is high while the usage ratio of the logic element LE is low. However, for example, in a situation where the usage rate is high such that 90% of the total usable number of logic elements LE is used, the degree of freedom of placement and routing is greatly reduced. For this reason, in general, it is almost impossible to satisfy the timing by several trials of placement and routing. That is, the number of placement and routing trials required to satisfy the timing requirement increases. For example, if the placement and routing trial is not repeated about 100 times, the placement and routing result may not satisfy the timing constraint. This may result in a computation amount that requires the machine time of a high-performance computer, for example, over several days. This can be a major factor in development costs.

  Applying timing constraints to the monitor signal further increases the difficulty of placement and routing. This is due to the following reason.

(A) The observation target circuit and the monitor data pin (see FIG. 5) are often separated on the FPGA chip, and even when a timing constraint is given, it is often impossible to satisfy the constraint.

(B) In order to suppress the number of monitor data pins because there are many circuits to be observed, a large number of monitor signals are input by a multiplexer (for example, 22 in FIG. 5) that selects a signal to be monitored, and a predetermined number of monitor signals are When selecting, the delay due to the multiplexer (for example, 22 in FIG. 5) becomes large, and it is often impossible to actually satisfy the condition even if timing constraints are given.

(C) In the process (4), since the monitor circuit is preferentially placed and routed so as to satisfy the timing constraint condition of the monitor circuit, the circuit to be observed by the monitor circuit cannot be applied to the monitor circuit. The circuit to be attracted to or not to be observed may be subject to subordinate treatment with respect to the monitor circuit, which affects the placement and routing.

(D) In some cases, the observation target circuit itself is arranged near the monitor data pin, so that the arrangement distance from the circuit necessary for realizing the original required function is increased, and the timing constraint can be satisfied. It may disappear.

  Here, if the timing relaxation condition is not added to the monitor circuit, not only the timing of the monitor circuit itself cannot be satisfied, but also the timing constraints of the circuit necessary for realizing the original required function of the chip are satisfied. Can be difficult.

  FIG. 6 is a diagram for explaining an example of placement and routing in which timing requirements cannot be satisfied due to unreasonable timing constraints. In FIG. 6A, a thick line (solid line) among the signal wirings represents a wiring with timing constraints. In FIG. 6A, general circuit symbols are used, but in the drawing, the relative distances of these circuit symbols represent the relative distances of resources arranged and wired on the FPGA chip. .

  In FIG. 6A, the output signal (FF1 output) from the output terminal (Q) of the flip-flop 120-1 (FF1) and the output signal (FF2) from the output terminal (Q) of the flip-flop 120-2 (FF2). The output node of the AND gate 123 taking the logical product of the output) is the observation target node. In this way, the output of the logic circuit is often used as a trigger condition (an opportunity to acquire a monitor waveform) of a logic analyzer (not shown). Here, everything from the output of the flip-flop 120-1 and the flip-flop 120-2 to the output of the monitor pin (monitor data pin) 125 is subject to timing constraints.

  The flip-flops 120-1 and 120-2 are required to have timing constraints with the observation target node. For this reason, both are arranged near the AND gate 123 in order to satisfy the timing constraint. On the other hand, the flip-flops 120-1 and 120-2 have their outputs (FF1 output and FF2 output) connected to the flip-flop 120-3 (FF3) in the next stage in order to realize the original required function. It is necessary to be connected to 120-4 (FF4), and each route has timing constraints. The flip-flops 120-3 and 120-4 need to satisfy the timing requirement with respect to the circuit ahead, and are arranged at a location close to the circuit ahead. Since the flip-flops 120-1 and 120-2 are “dragged” to the observation target node, the flip-flops 120-1 and 120-2 and the flip-flops 120-3 and 120-4 are separated from each other. There is a certain arrangement.

  FIG. 6B is a timing chart illustrating an operation example of the circuit in FIG. The delay from the “FF2 output” that is the output of the flip-flop 120-2 to the “FF4 input” that is the input of the flip-flop 120-4 exceeds one clock cycle, causing a timing violation.

  For the reasons described above, a relaxation system constraint condition must be added to the monitor circuit. For this reason, the logic circuit related to the monitor signal (the AND gate 123 in FIG. 6A) has a placement and routing result under a relaxed condition (in an inferior condition compared to a circuit with timing constraints of “results”), The quality of the monitor waveform that can be observed will deteriorate.

  Hereinafter, a description will be given with reference to FIG. FIG. 7A is a diagram illustrating an example in which the monitor circuit is arranged and wired with a timing relaxation condition. FIG. 7A schematically shows an example in which the placement and routing are performed by adding timing relaxation conditions to the paths from the flip-flops 120-1 and 120-2 to the AND gate 123. Note that in FIG. 7A, a thick solid line of the signal wiring represents a wiring with timing constraints. Wiring from the flip-flops 120-1 and 120-2 to the next-stage flip-flops 120-3 and 120-4 necessary for realizing the original required function is carried out without difficulty. The wiring to the AND gate 123 is arranged and wired under the condition that the timing constraint is relaxed, so that the wiring distance from the output of the flip-flop 120-2 (FF2 output) to the input of the AND gate 123 (AND input 2) is As compared with the wiring distance in FIG.

  As a result, as shown in FIG. 7B, the output of the flip-flop 120-2 (FF2 output) is shifted from the AND input 1 by one clock cycle or more at the input point of the AND gate 123 (AND2 input). ing. As a result, the output of the AND gate 123 remains at “0” at the timing when “1” should be output.

  The above is a case where the observation target signal is 1 bit. However, when the observation target signal is a bus in which a plurality of signals are bundled, timing skew between bits (hereinafter referred to as “skew”) is a serious problem. Become. The problem of skew between bits will be described again with reference to FIG. FIG. 5B shows the placement and routing delay in FIG.

Place and route delays related to the monitor data path
A delay Dclk_tgt from the clock source 11 to the flip-flop 21 whose output is connected to the observation target node,
The output of the observation target flip-flop 21, or in some cases, the delay Dtgt_dmux from the observation target node to the monitor data multiplexer 22 after passing through the combinational logic ahead of it,
Delay Ddmux_mpin from the monitor data multiplexer 22 to the monitor data pin 23,
It has become.

  Although no particular subscript is added, each delay described above exists individually from the observation target circuit to the monitor data multiplexer 22 by the product of the number of the monitor data pins 23 and the signal selected by the monitor data multiplexer 22. Accordingly, the number of the monitor data pins 23 is individually present with respect to the delay from the monitor data multiplexer 22.

On the other hand, the placement and routing delay related to the monitor clock signal used for the purpose of determining the sampling point of the monitor data multiplexer 22 by the logic analyzer 50 is
-Delay Dclk_cpin from the clock source 11 to the monitor clock pin 24
It has become.

  Note that a monitor clock multiplexer (for example, 207 in FIG. 13 referred to later) may be inserted in the middle of the monitor clock. In this case, there are individual delays from a plurality of clock sources to be selected by the monitor clock multiplexer to the monitor clock multiplexer (207 in FIG. 13).

  FIG. 8 is a diagram illustrating an example in which the inter-bit skew becomes an observation problem. The waveform shown in FIG. 8 is an example in which a parallel 4-bit signal DATA [3: 0] is externally extracted as a bus signal. In FIG. 8, the skew between bits is one clock cycle or more. When such signals are collectively displayed as DATA [3: 0] as 4 bits, as shown in FIG. 8, there is no place where the signals belonging to the same clock edge exist. As a result, no matter what the phase of the monitor clock is, it cannot be taken in synchronously as parallel 4-bit DATA [3: 0]. For this reason, it cannot be used as an observation signal. In such a case, the observation of the bus signal DATA [3: 0] in synchronization with the monitor clock is abandoned, and the capture is performed asynchronously with the free-running clock of the logic analyzer, for example. In this case, the skew remaining in the bus signal DATA [3: 0] is displayed as it is on the logic analyzer. For this reason, the person in charge of debugging must guess which clock edge the change point for each bit of DATA [3: 0] belongs to. When the operation speed of the FPGA is low, the skew between bits often becomes 1 clock cycle or less. As the operation speed inside the FPGA improves, skew between bits becomes a problem.

  In a combinational logic circuit, a thin whisker-like waveform called a glitch may be generated. The multiplexer used in the monitor circuit is also a kind of logic circuit, and a glitch may occur depending on the configuration. The signal quality of the signal under observation is degraded due to the occurrence of glitches. This problem will be described.

  In hardware description languages such as VHDL and Verilog HDL, high-level (high-level) description is possible, and usually the logic of a multiplexer is often described with the same number of lines as the input of the multiplexer. For this reason, it is unclear as to what logic circuit the multiplexer is finally mounted. In the synchronous design, even if a glitch occurs, it is assumed that the signal only needs to be settled at the timing when the signal is determined by the clock. For this reason, even if some timing constraint is added to the multiplexer, the possibility that the logic synthesis software synthesizes into a circuit format that generates a glitch cannot be denied. Note that even if a low-level description is made using only operators that are about the same as basic logic gates, logic synthesis software usually minimizes the chip area or operation speed (delay from input to output). The optimization of the logical expression (logical compression) is executed with the goal of this. For this reason, unless special consideration is given, it is expected that a logical synthesis result equivalent to a description with a high level of abstraction will be obtained.

  A specific example in which a glitch occurs will be described. For ease of explanation, an example in which individual logic gates are realized by a 2-input LUT and combined to form a 2-input multiplexer will be described. Here, it is assumed that the logic gate itself does not generate a glitch.

  Table 1 shows a truth table of the most basic two-input multiplexer among the multiplexers.

  When the selection input S is 0, the output Z has the same polarity as the X input, and when the selection input S is 1, the output Z has the same polarity as the Y input. The following logical expressions are given as representative Boolean algebra expressions corresponding to this truth table.

DNF: (S and Y) or (not S and X)

CNF: (not S or Y) and (S or X)

ANF: (S and X) xor (S and Y) xor X

NOR: (not S nor Y) nor (S nor X)

NAND: (S nand Y) nand (not S nand X)

AND: not (S and not Y) and not (not S and not X)

OR: not (not S or not Y) or not (S or not X)

DNF: Disjunctive Normal Form
CNF: Conjunctive Normal Form
ANF: Algebraic Normal Form or Reed-Muller standard type

  Here, a logical expression in which a 2-input multiplexer is expressed as a Boolean algebra in the DNF format and the ANF format is replaced with a logic circuit.

  FIG. 9A shows a circuit format in which the DNF format is replaced with a logic circuit. The 2-input LUTs 131-1 and 131-2 are AND operation circuits, and the 2-input LUT 132 is an OR operation circuit. FIG. 9B shows CLK, X, Y, S, X ′, Y ′, S & X ′, S = 1 in FIG. 9A when S = 1 (Y input selected). It is a figure which shows typically the waveform of S & Y ', (S & X') or (! S & Y ').

  As can be seen from FIG. 9A, in the DNF format, the result that the X input and the Y input are input to the AND gate together with the S input is input to the OR gate, so that the unselected input is blocked by the AND gate. . For this reason, even if a glitch that can generate a 2-input LUT itself that realizes an AND / OR gate is taken into consideration, the glitch does not occur if the polarity of the S input is constant.

  A glitch may occur at the moment when the S input changes. In order to avoid glitches, it is necessary to change the S input during a period (instant) in which the values (polarity) of the X input and Y input are constant. If the application as a monitor data multiplexer is considered, the monitor plane is not switched during observation of the waveform of interest (the S input is not switched). For this reason, the problem of glitches can be ignored.

  On the other hand, FIG. 10A illustrates a logic circuit in which the ANF format is replaced with a logic circuit. The 2-input LUTs 131-1 and 131-2 are AND operation circuits, and the 2-input LUTs 133-1 and 133-2 are XOR operation circuits. FIG. 10 (B) is the same as FIG. 10 (A), with CLK = 1, S = 1 (Y input selected), CLK, X, Y, S, X ′, S & X ′, S & Y, (S & X ′) xor (S & Y), ( FIG. 4 is a diagram illustrating a waveform of S & X ′) xor (S & Y) xorX. Thus, in the ANF format logic circuit, even if the S input is kept constant, glitches may occur due to the delay in the logic circuit. When switching between monitor surfaces using such a multiplexer, glitches may occur due to waveforms from other observation target circuits that are not the object of interest during observation. As a result, the quality of the observed waveform may be degraded.

  As described above, when the number of signals to be observed exceeds a certain level, it becomes difficult to converge the timing of the monitor circuit itself and other circuits. If a constraint that relaxes the timing of the monitor circuit is added, the quality of the monitor waveform cannot be guaranteed.

  A general technique is used in which a synchronization flip-flop is inserted on the way from the observation target node to the monitor data pin. This is well known as a pipelining technique. When pipelined, the FF is driven by a flip-flop (pipeline stage) inserted at an intermediate point before the monitor waveform delay or inter-bit skew (when observing the bus signal) exceeds the allowable range. Data change points are aligned with clock edges. Also, glitches can be removed by pipeline stages (also called “retiming effect” etc.).

FIG. 11A is a diagram schematically showing an example in which the monitor circuit of FIG. 5A is two-stage pipelined. In FIG. 11A, the flip-flops 21-3 and 21-4 are the first stage of the pipeline, and the flip-flop 21-5 at the rear stage of the monitor data multiplexer 22 is the second stage of the pipeline. In FIG. 11B,
(1) is the data path delay (Dclk_tgt + Dtgt_pl1) from the observation target circuit to the first stage of the pipeline.
(2) is the delay of the clock path from the clock source 25 to the first stage of the pipeline (Dclk_pl1),
(3) Dpl1-pl2 is the delay of the data path from the first stage of the pipeline to the second stage of the pipeline.
(4) is the clock path delay (Dclk_pl2) from the clock source 25 to the second stage of the pipeline,
(5) Dpl2-mpin is the delay of the data path from the second stage of the pipeline to the output (connector end) of the monitor data pin 23,
(6) is a delay (Dclk-cpin) of the clock path from the clock source 25 to the output (connector end) of the monitor clock pin 24.

Considering the delay from the observation target circuit of FIG. 11A to the first stage pipeline, the delay of the data path is as shown in (1) of FIG.
A delay Dclk_tgt from the clock source 25 to the flip-flop 21-1 (21-2) of the observation target circuit;
Delay Dtgt_pl1 from the flip-flop 21-1 (21-2) of the observation target circuit to the flip-flop 21-3 (21-4) in the first stage of the pipeline
Sum of:
Dclk_tgt + Dtgt_pl1
It becomes.

The delay of the clock path is as shown in (2) of FIG.
A delay Dclk_pl1 from the clock source 25 to the flip-flop 21-3 (21-4) in the first stage of the pipeline.

  Here, if the delay of the data path: Dclk_tgt + Dtgt_pl1 becomes equal to or less than the delay of the clock path: Dclk_pl1, a violation of the hold time of the flip-flop (FF) 21-3 (21-4) at the first stage of the pipeline occurs. If the delay of the data path is 1 CLK period or more than the delay of the clock path, the setup time of the flip-flops (FFs) 21-3 and 21-4 in the first stage of the pipeline is violated.

0 <Dclk_tgt + Dtgt_pl1-Dclk_pl1 <(1 clock cycle)
As long as this holds, retiming can be performed at the outputs of the flip-flops (FF) 21-3 and 21-4 in the first stage of the pipeline.

  Pipeline first-stage flip-flop (FF) 21-3, 21-4 to second-stage flip-flop (FF) 21-5, and second-stage flip-flop (FF) 21-5 to monitor The timing to the clock pin 24 can be retimed under the same conditions.

  FIG. 12 is a diagram schematically showing the effect of retiming by the pipelining of FIG. As the number of pipeline stages is increased and the number of stages from the observation target circuit (departure point) to the monitor pin (destination point) is finely divided, retiming can occur before a delay of 1 clock cycle or more and skew between bits occur. This makes it possible to absorb and level them.

  However, pipelining requires a larger number of flip-flops as the number of stages increases. When the FPGA to be developed has reached a state where there are almost no flip-flops necessary for pipelining, if the pipelining is performed, the flip-flops are consumed and the degree of freedom of placement and routing is reduced. Furthermore, although pipelining facilitates satisfying the timing constraint, the degree of freedom of placement and routing may not increase as much as placement and routing with timing relaxation conditions.

<Outline of the invention>
An outline of the invention that solves at least one of the first to third problems described above will be described below.

  According to an aspect of the present invention, the monitor circuit is mounted on a semiconductor device (for example, FPGA) and monitors an internal state of the semiconductor device, and a plurality of observation target signals of a plurality of observation target nodes inside the semiconductor device. The first multiplexer (monitor data multiplexer: 205 and 206 in FIG. 13) that selects and outputs the observation target signal according to the first selection signal, and the plurality of clock signals are input according to the second selection signal And a second multiplexer (monitor clock multiplexer: 207 in FIG. 13) that selects and outputs a monitor clock signal, and at least one of the first and second multiplexers is, for example, a plurality of input signals Output for a polarity change of at least one of the input signals, such as a polarity change of an unselected input signal. A multiplexer which is configured to prevent the propagation of glitches to. At least the path from the observation target node to the output of the first multiplexer may be arranged and wired with a relaxation condition regarding timing constraints.

  According to an aspect of the present invention, the monitor circuit of the semiconductor device includes a test signal generation circuit (209 in FIG. 13) that outputs a test signal in synchronization with the clock signal output from the second multiplexer, and the test signal. And a third multiplexer (208 in FIG. 13) that inputs the observation target signal selected by the first multiplexer and selects and outputs one of the signals in accordance with the third selection signal.

  According to an aspect of the present invention, the semiconductor device further includes a combinational logic circuit, the observation target node is an output node of the combinational logic circuit, and a skew between signals in a path leading to the output of the combinational logic circuit May be configured to be within one cycle of the observation target signal.

  According to an aspect of the present invention, the monitor circuit of the semiconductor device corrects a delay with respect to the observation target signal output from the first multiplexer (206 in FIG. 13) and outputs the first delay correction circuit ( 13, 212) and the observation target signal whose delay is corrected by the first delay correction circuit, and the clock signal selected by the second multiplexer (207 of FIG. 13) is used as the write clock signal. A first buffer unit (216 in FIG. 13) that writes an observation target signal and performs reading according to a read clock, and inputs the observation target signal read from the first buffer unit, and performs bit width and rate conversion. The bit width / rate conversion unit (214 in FIG. 12) to be performed and the observation target signal output from the bit width / rate conversion unit are converted into serial signals. An output terminal of to the semiconductor device serial transmission circuit for serial output from the (221 in FIG. 13) (215 in FIG. 13), may be configured to include. The signal selected and output by the third multiplexer (208 in FIG. 13) may be output in parallel from the output terminal (220 in FIG. 13) of the semiconductor device.

  According to one aspect of the present invention, a logic analysis terminal (30 in FIG. 16) that receives a signal from a monitor circuit, which is serially transmitted from the second clock source (313 in FIG. 16) and the monitor circuit. A serial receiving circuit (307 in FIG. 16) that receives a signal and converts it into a parallel signal, and writes a parallel signal from the serial receiving circuit as a parallel clock signal from the serial receiving circuit, and a clock from the second clock source. A second buffer section (311 in FIG. 16) to be read as a signal, a second delay correction circuit (306, 308 in FIG. 16) for correcting the delay of the signal transmitted in parallel from the monitor circuit, and the monitor circuit The clock signal selected by the second multiplexer or the clock signal from the second clock source (313) is received and based on the fourth selection signal. The fourth multiplexer (309 in FIG. 16) for selecting one and the observation target signal received from the monitor circuit are written with the clock signal selected by the fourth multiplexer, and the clock signal from the second clock source is used. It is good also as a structure containing the 3rd buffer part (310 of FIG. 16) to read, and the memory | storage part (316 of FIG. 16) which memorize | stores the signal read from the said 2nd and 3rd buffer part. Furthermore, an interface unit (318 in FIG. 16) connected to the host computer, a read control circuit (317 in FIG. 16) that reads the contents of the storage unit and transmits them to the host computer, and starts writing signals to the storage unit -It is good also as a structure provided with the control part (312 of FIG. 16) which performs stop control.

According to one aspect of the present invention, the host computer (40 in FIG. 16) may be configured to, for example, use the second delay correction circuit (306 and 308 in FIG. 22 and FIG. 23) of the logic analysis terminal (30 in FIGS. 22 and 23). ) To control the delay compensation,
(A) From the timing analysis result after the placement and routing of the semiconductor device, the test signal generation circuit (209 in FIG. 22) in the semiconductor device (20 in FIG. 22) to the output terminal (220 in FIG. 22). ) And the delay of the path from the observation target node in the semiconductor device (20 in FIG. 23) to the output terminal (220 in FIG. 23) of the semiconductor device, and stored.
(B) The test signal of the test signal generation circuit (209 in FIG. 22) in the semiconductor device (20 in FIG. 22) is monitored, and the second delay correction circuit (306 and 308 in FIG. 22) is monitored. Initialize the delay amount to zero,
(C) It is determined whether the data pattern received from the test signal generation circuit (209 in FIG. 22) in the semiconductor device (20 in FIG. 22) matches a known test signal pattern, and the known test signal pattern When the received data pattern matches the known test signal pattern, the second delay correction circuit at that time is increased by increasing the delay amount with respect to the second delay correction circuit (306 and 308 in FIG. 22). The delay amount set in (306, 308 in FIG. 22) is stored,
(D) With respect to the delay amount set in the second delay correction circuit (306 and 308 in FIG. 23), the observation target signal from the observation target node in the semiconductor device (20 in FIG. 23) is a monitoring target. The test signal in the semiconductor device (20 in FIG. 22) from the delay of the path from the observation target node in the semiconductor device (20 in FIG. 23) to the output terminal (220 in FIG. 23) of the semiconductor device. The delay amount obtained by adding the value obtained by subtracting the delay of the path from the generation circuit (209 in FIG. 22) to the output terminal (220 in FIG. 22) of the semiconductor device is used as the second delay correction circuit (in FIGS. 22 and 23). 306, 308) may be set.

  As described above, according to the present invention, the monitor circuit is placed and routed with a timing relaxation condition, and after that, by performing a delay correction by a separate means, without compromising the ease of placement and routing, The monitor data stable point is identified by the monitor clock.

  According to the present invention, the monitor circuit mounted on the observation target FPGA eliminates the flip-flop in the path from the observation target node to the circuit (parallel monitor reception circuit) that receives the parallel monitor signal in parallel. Also, no timing constraint is applied to the path from the observation target node to the parallel monitor receiving circuit in the monitor circuit. The multiplexer for switching the monitor plane included in the monitor circuit is composed of a glitch free multiplexer. The multiplexer may be configured by connecting a plurality of glitch free multiplexers in a binary tree form.

  According to the present invention, the logic analysis system includes a test signal generation circuit for analyzing a delay time for each bit and a delay correction circuit.

  In the present invention, the monitor circuit includes a serial transmission circuit for converting the parallel monitor signal into a serial signal for transmission to the logic analysis terminal. The monitor circuit does not convert some of the monitor signals into serial signals, but outputs them directly to the external pins of the FPGA as parallel signals.

  In the present invention, the logic analysis terminal receives a serial signal from the monitor circuit serially and converts it into a parallel signal, a memory for storing the received data, and monitors the received data to obtain a predetermined trigger condition. Has a control circuit that stops writing to the memory when this occurs. In addition to the serial reception circuit, the logic analysis terminal includes an input pin that receives a parallel monitor signal output from an external pin of the observation target FPGA, and a delay correction circuit that corrects the delay of the received parallel monitor signal.

A delay correction method of the present invention is a delay correction method of a delay correction circuit for delaying a monitor output from a semiconductor device,
From the timing analysis result after the placement and routing of the semiconductor device, the delay of the path from the test signal generation circuit in the semiconductor device to the output pin of the semiconductor device, and the output of the semiconductor device from the observation target node in the semiconductor device Get and store the delay of the route to the pin,
The test signal of the test signal generation circuit is to be monitored, the delay amount for the delay correction circuit is initialized to zero,
Determining whether a data pattern from the test signal generation circuit in the semiconductor device matches a known test signal pattern, and increasing a delay amount with respect to the delay correction circuit until it matches a known test signal pattern; When the received data pattern matches the known test signal pattern, the delay amount set in the delay correction circuit at that time is stored,
From the delay of the path from the observation target node to the output pin of the semiconductor device, with respect to the delay amount set in the delay correction circuit, with the observation target signal from the observation target node in the semiconductor device as a monitoring target, A delay amount obtained by adding a value obtained by subtracting the delay of the path from the test signal generation circuit to the output pin of the semiconductor device is set for the delay correction circuit.

  Hereinafter, embodiments will be described in detail with reference to the drawings.

<Embodiment 1>
FIG. 13 is a diagram illustrating a configuration of a monitor circuit to be mounted on an FPGA to be observed in an embodiment of the present invention. In this embodiment, an example is shown in which two types of high-speed serial monitor using a serial transmission circuit and a serial reception circuit and a parallel monitor using a normal I / O pin are mounted at the same time. It is good also as a structure provided with. In order to reduce the number of I / O pins used in the monitor circuit, it is preferable to mount a high-speed serial monitor. When using a variety of FPGAs that do not have a serial transmission circuit, or when monitoring asynchronous signals, it is effective to use an appropriate number of parallel monitors.

  An observation target FPGA 20 is mounted on the observation target board 10, and a monitor circuit related signal drawn from the observation target FPGA 20 is connected to a monitor analysis terminal described later via a connector 12 and a cable 13. Note that the wirings, connectors, and cables on the substrate 10 have electrical characteristics corresponding to transmission of related signals.

  The observation target FPGA 20 is an FPGA on which the observation target circuit 200 and the monitor circuit block 210 are mounted.

  The observation target circuit 200 is a circuit that is mounted in order for the FPGA 20 to realize the original required function, and is a circuit to be debugged. The observation target node is a debug target portion. The observation target node may be an output of the flip-flop (FF) 201 or a place after passing through the combinational logic circuit 202. In either case, it is better to use the output of the flip-flop 201 in order to reduce the difficulty of placement and routing and improve the monitor quality.

  Monitor data multiplexers 205 and 206 are multiplexers of bus signals (a set of a plurality of bits) for switching monitor surfaces. The monitor data multiplexer 205 is for asynchronous signals, and the monitor data multiplexer 206 is for synchronous signals.

  The monitor plane refers to a set of observation target signal buses necessary for debugging an observation target circuit of interest. One signal is a signal line, but since the bus can be regarded as a surface where a plurality of signals are bundled, the signal to be monitored (one or more) is referred to as a monitor surface.

  When there are a plurality of observation target circuits 200 and it is not necessary to observe them simultaneously, the observation target nodes of the respective circuits are assigned to different planes (other inputs) of the monitor data multiplexers 205 and 206, and the monitor data multiplexer 205 , 206, the monitor surface to be selected is switched by the monitor surface selection signal, and observation can be performed.

  The monitor clock multiplexer 207 is for selecting a clock to be guided to the monitor circuit according to the clock domain of the observation target circuit 200. The clock signal selected by the monitor clock multiplexer 207 is also used as a drive source clock for the test signal generation circuit 209. The clock signal selected by the monitor clock multiplexer 207 is also input to a dual clock FIFO (First In First Out) 213, and further connected to the connector 12 from the monitor clock pin 223 via the substrate wiring 14.

  The test signal multiplexer 208 is for switching to the original monitor data based on the test signal selection signal when transmitting a test signal for delay adjustment, and has the same configuration as the monitor data multiplexer. The test signal multiplexer 208 is omitted when the test signal plane is included in the monitor data multiplexer 205 plane.

  Each of the monitor data multiplexers 205 and 206, the monitor clock multiplexer 207, and the test signal multiplexer 208 is composed of a glitch free multiplexer to prevent the occurrence of glitches as will be described later. Although not particularly limited, each multiplexer is configured, for example, by connecting a plurality of glitch-free multiplexers that select one of two inputs in a tree form.

  For example, the monitor planes of the monitor data multiplexers 205 and 206, the monitor clock multiplexer 207, and the test signal multiplexer 208 are switched from a host computer (not shown) via a logic analysis terminal to a JTAG I / F (Joint Test Action Group Interface). At 216. The output of the test signal multiplexer 208 is connected to the connector 12 from the output terminal (parallel monitor pin) 220 via the substrate wiring 14.

  The delay correction circuit 211 corrects monitor data delay and adjusts skew between bits. The delay amount of the delay correction circuit 211 is performed by a JTAG I / F 216 from a host computer (not shown) via a logic analysis terminal.

  In this embodiment, the delay correction circuit 211 is provided with a plurality of taps (delay times are different from each other) on the delay line, the multiplexer 212 selects one tap, and selects the delay amount to be corrected. Of course, the configuration may be realized.

  The dual clock FIFO 213 is a buffer for performing clock transfer from the clock domain of the observation target circuit 200 (clock signal selected by the monitor clock multiplexer 207) to the clock domain of the serial transmission circuit 215.

  The serial transmission circuit 215 performs parallel-to-serial conversion of input parallel data into a serial bit string, serially outputs it from an output terminal (monitor data pin) 221, and differentially outputs it to a transmission path on the substrate 10 on which the FPGA 20 is mounted. . Depending on the product type, for example, a built-in FPGA standard hard macro can be used. The parallel clock signal from the serial transmission circuit 215 corresponds to a clock signal obtained by dividing the serial bit driving clock signal by m. Serial data (differential signal) from the monitor data pin 221 is connected to the connector 12 via the substrate wiring 14.

  Of the circuit blocks 210 from the delay correction circuit 211 to the serial transmission circuit 215, circuits other than the serial transmission circuit 215 can be realized by resources integrated in a normal FPGA. However, since the circuit in the circuit block 210 needs to satisfy a predetermined timing condition, it must be excluded from the targets to which the timing relaxation condition is attached. For this reason, it is conceivable that the difficulty of placement and wiring of the FPGA increases. Therefore, it is desirable to integrate the entire circuit block 210 on the FPGA chip in advance as a hard macro for debugging support.

  The role of the bit width / rate conversion unit 214 will be exemplified below.

(1) Bit width conversion: Generally, the serial transmission circuit 215 operates at several Gbps to 28.05 Gbps (Giga bits per second), whereas the operation clock inside the FPGA is limited to several hundred MHz at most. Data exchange within the FPGA is performed as parallel data by combining several serial data bits to obtain a necessary transmission bandwidth. A clock used for input / output of parallel data is a parallel clock. As described above, since the data width of the parallel data is determined according to the transfer rate of the serial transmission circuit 215 and the like, the bit width of the monitor data and the parallel data width of the serial transmission circuit 215 do not necessarily match. For this reason, it is necessary to arrange the bit widths.

(2) Rate conversion: The monitor clock signal and the parallel clock of the serial transmission circuit 215 are not necessarily frequency tuned. For this reason, data is transferred between clock domains using the dual clock FIFO 213.

  The FPGA designer determines that the transmission bandwidth required for transmission of the monitor data after bit width conversion is the effective transmission bandwidth of the serial transmission circuit (8b10b conversion (8-bit data is converted into a 10-bit symbol and transmitted) or 64b66b. The monitor data width is selected so as not to exceed the conversion (substantial transmission bandwidth excluding overhead due to encoding, such as conversion of 64 bits (8 × 8 bits) data to 66 bits). If data is read from the dual clock FIFO 213 for each parallel clock, the dual clock FIFO 213 causes an underflow (data depletion). For this reason, a speed control mechanism is required.

  Specifically, when there is no more data that can be read from the dual clock FIFO 213, a skip code that can be distinguished from other data is inserted into the output data so that it can be discriminated on the receiving side.

  An operation example of the bit width rate conversion unit 214 will be described. FIG. 14 shows an example in which the serial transmission circuit 215 has a parallel data bit width of 32 bits and a monitor data bit width of 60 bits. In FIG. 14, the bit width conversion operation is performed with 128 bits per frame.

  Two monitor data (120 bits) are stored across four parallel data (32 × 4 = 128 bits), and the last 8 bits are filled with filler (unused) bits.

  If the serial transmission circuit 215 supports an effective transmission bandwidth of 10 Gbps, the parallel data clock is 312.5 MHz. Since the monitor data width including the filler bits is equivalent to 64 bits, a monitor clock up to 156.25 MHz can be supported. If the frame for bit width conversion is configured with the number of bits that is the least common multiple of the parallel data bit width and the monitor data width, waste due to filler bits can be eliminated. However, this corresponds to the circuit scale (whether or not the increase in the circuit scale is balanced with the waste elimination by the filler bit).

  In this example, if one frame is composed of 480 bits, filler bits are not necessary, and a monitor data width of 64 bits can be realized.

  The start symbol is a special symbol for determining the start of the frame. For example, if a K (comma) code of the 8b10b encoding method is used, it can be identified as normal data. Since the start symbol need only be transmitted at the beginning of data transmission, it does not affect the required transmission band.

  The skip symbol is used for speed control, and the bit width conversion unit monitors the data storage state of the dual clock FIFO 213 and inserts it when the remaining data is almost exhausted, thereby preventing underflow. The skip symbol can also be identified as normal data by using a K code or the like.

  FIG. 15 shows an example in which the serial transmission circuit 215 has a parallel data width of 128 bits and a monitor data width of 120 bits. Here, the bit width conversion operation is performed with 256 bits per frame.

  Two monitor data (120 × 2 bits) are stored across two parallel data, and the last 16 bits are filled with filler (unused) bits.

  If the serial transmission circuit 215 has an effective transmission bandwidth of 27.2 Gbps, the parallel data clock is 212.5 MHz. Since the monitor data width including the filler bits is equivalent to 128 bits, a monitor clock up to 212.5 MHz can be supported.

  FIG. 16 is a block diagram showing a configuration of the logic analysis terminal 30 in the present embodiment. Although not particularly limited, the apparatus (terminal) in FIG. 16 can be mounted on a large postcard board, for example.

  In FIG. 16, a serial reception circuit 307 converts a serial bit string input from a differential transmission path on a substrate into parallel data from serial to parallel. Although not particularly limited, the serial reception circuit 307 reproduces a clock signal synchronized with the data from the reception data (serial bit) input from the serial monitor input 304 (clock not shown). and data recovery) circuit. The clock / data recovery circuit regenerates the clock by synchronizing a clock signal (internal clock) generated from a PLL (Phase Locked Loop) circuit (not shown) with the received data, and uses the recovered clock to receive the received data. Is converted to serial / parallel, and parallel data is output as write data together with a parallel clock signal. When converting an m-bit serial bit string into parallel data, the parallel clock signal corresponds to a signal obtained by frequency-dividing the synchronous clock signal of the serial bit string by m.

  The delay correction circuit 306 adjusts the skew between bits of the parallel monitor input output from the observation target FPGA without passing through the serial transmission circuit 215. The delay correction circuit 306 has the same function as the delay correction circuit 211 on the observation target FPGA side in FIG.

  The dual clock FIFOs 311 and 310 are buffers for performing clock transfer from the clock domain on the serial reception circuit 307 or parallel monitor input side to the memory clock domain. The dual clock FIFO 311 writes the parallel signal from the serial reception circuit 307 with the parallel clock signal from the serial reception circuit 307 and reads out with the clock signal from the memory clock source 313. The clock multiplexer 309 receives the monitor clock signal (input from the input pin 303) transmitted from the FPGA 20 or the clock signal from the memory clock source 313, selects the clock signal, and supplies it to the dual clock FIFO 310 as a write clock. The dual clock FIFO 310 writes a signal obtained by correcting the parallel monitor data from the parallel monitor input pin 302 by the delay correction circuit 306 and the multiplexer 308 as write data using the clock from the clock multiplexer 309 and the clock signal from the memory clock source 313. Is read out as a read clock.

  The run / stop / trigger control circuit 312 starts / stops writing the received data read from the dual clock FIFOs 310 and 311 to the memory 316 in accordance with an instruction from the host computer 40, monitors the received data, and previously monitors the host computer. When a condition that matches the trigger condition set by 40 is found, writing to the memory 316 is stopped.

  The time base circuit 314 creates time information by counting the monitor clock and the memory clock. In particular, the reference edge position when determining the polarity while changing the delay of the reference bit described later is obtained by counting the monitor clock by the time base circuit 314.

  The time stamp addition circuit 315 outputs the time information received from the time base circuit 314 to the memory 316 along with the received monitor data.

  The memory 316 has a function of capturing and holding the received monitor data in real time, such as DDR3 (Double Data Rate 3) SDRAM (Synchronous Dynamic Random Access Memory), QDR (Quad Data Rate) SRAM (Static Random Access Memory), etc. Realized.

  The read control circuit 317 reads monitor data stored in the memory 316 in response to a request from the host computer 40 and transmits it to the host computer 40 via the host I / F 318.

  The host I / F 318 sends commands from the host computer 40 to each unit of the logic analysis terminal, and returns responses from these units to these commands to the host computer 40.

  The JTAG bridge 305 is installed between the observation target FPGA 20 and the host I / F 318, thereby sending commands from the host computer 40 to the observation target FPGA and returning responses to those commands to the host computer 40.

  Next, the configuration of the monitor data multiplexer, the monitor clock multiplexer, and the test data multiplexer will be described.

  When the observation target FPGA is a product having a 2-input LUT, the 2-input multiplexer in the DNF format already described can be used as a unit glitch-free multiplexer. However, FPGAs often have more input LUTs, and using these LUTs as 2-input LUTs is not impossible, but uneconomical. Therefore, consider forming a glitch-free multiplexer with one LUT having three or more inputs.

  The condition for signal transition that does not cause the glitch in the LUT is, for example, the following (I) or (II).

(I) The polarity of any one of the inputs is inverted.

(II) In the case where a plurality of inputs simultaneously invert the polarity, the polarity of the bit held by the LUT mask (SRAM cell) referenced by all input combinations that may occur due to a minute delay between the inputs is They have the same polarity.

  Here, an example in which a two-input multiplexer is realized using a three-input LUT as shown in FIG. In the example of FIG. 17, the LUT mask (stored contents of the SRAM cell) has the same polarity as the polarity of the X input at the Z output when the S input is 0. When the S input is 1, the polarity of the Y input appears in the Z output. In general multiplexers, when the polarity of the selected input is changed by the S input, the output is inverted several times from 0 → 1 → 0 →... → 1 → 0 → 1 and a glitch occurs. Exists. The multiplexer shown in FIG. 17A satisfies the above condition (I), so that this problem does not occur.

  From the truth table of FIG. 17B, when the X and Y inputs change simultaneously, the condition (I) is not met, but the condition (II) is met as long as the S input is constant. I understand that.

  A first enlarged view (FIG. 17D) of the timing chart of FIG. 17C shows a state in which no glitch occurs even when X and Y change simultaneously when S = 0 is constant. This is not the case when the S input changes. As shown in the enlarged view (FIG. 17E) of the timing chart of FIG. 17C, before reaching the final static state due to the influence of the delay. A glitch occurs because another input state occurs for a moment.

  However, in normal debugging work, the monitor waveform at the moment of switching to the monitor surface is not an object of interest. For this reason, the glitch generated due to the change of the S input can be ignored.

  Note that the LUT structure differs depending on the type of FPGA, and thus the above behavior is not always obtained. Note that when such a unit glitch free multiplexer is described in a hardware description language, it is necessary to pay attention to the behavior of logic circuit optimization by logic synthesis software.

  List 1 below describes a 2-input glitch-free multiplexer in the VHDL language. Normally, even if a large number of modules are arranged, the logic synthesis software may change the configuration of the logic circuit with priority given to area, speed, or power consumption, and it is not always implemented as intended.

  Therefore, for example, as shown in List 2, there is known a method of creating an intermediate node given a “keep attribute”. The “keep attribute” is an attribute that prevents the logic synthesis software from erasing the node to which the attribute is attached during the optimization process.

  Although the behavior differs depending on the logic synthesis software, the logic synthesis software used in the verification of this embodiment shows that the intermediate node given the “keep attribute” is always left unoptimized as the output of the LUT. ing. Therefore, the multiplexer can be as intended.

[List 1]
library ieee;
use ieee.std_logic_1164.all;

entity MUX2to1 is port (
X, Y: in std_logic;
S: in std_logic;
Z: out std_logic;
end MUX2to1;

architecture RTL of MUX2to1 is

begin

process (S, X, Y)
begin
case S is
when '0'=> Z <= X;
when '1'=> Z <= Y;
end case;
end process;

end RTL;
[End of List 1]

[List 2]
library ieee;
use ieee.std_logic_1164.all;

entity MUX2to1_no_opt is port (
X, Y: in std_logic;
S: in std_logic;
Z: out std_logic;
end MUX2to1_no_opt;

architecture RTL of MUX2to1_no_opt is

signal Z_int: std_logic;
attribute keep: boolean;
attribute keep of Z_int: signal is true;

begin

process (S, X, Y)
begin
case S is
when '0'=> Z_int <= X;
when '1'=> Z_int <= Y;
end case;
end process;

Z <= Z_int;

end RTL;
[End of List 2]

  The above lists 1 and 2 are for a three-input LUT, but can be expanded in the same way for a LUT with a larger number of inputs. For example, if a 6-input LUT is used, a 4-input multiplexer that selectively outputs 4-bit data input by 2-bit selection signal input can be configured.

  In addition, as a multiplexer for clock signals, so-called glitch free switch-over, in which no glitch propagates to the output, including when the polarity of the selection signal input of the multiplexer is switched, is possible. A configuration may be used. The operation at the time of switching the polarity of the selection signal input of the multiplexer is not important, and if necessary, the associated circuit may be reset and restored after switching the monitor clock. As with the monitor data multiplexer, it is sufficient to ensure that no glitches occur when the selection signal input is in a static state.

  Next, timing constraints when the observation target node is the output of the combinational logic circuit will be described.

  In the present embodiment, the route from the observation target node to the delay correction circuit can be placed and routed with a timing relaxation condition. When the observation target node is an output of a combinational logic circuit, the intended waveform may not be obtained due to the influence of skew. For this reason, it is necessary to place a timing constraint on the path from the flip-flop that drives the input signal of the combinational logic circuit to the observation target node so that the skew does not become a problem. Such restrictions can be given by the known SDC format described above.

  FIG. 18 is a diagram for explaining how to apply timing constraints in the embodiment. The range of timing constraints is limited from the outputs (FF1 output and FF2 output) of the flip-flops 120-1 and 120-2 to the output (observation target node) of the AND gate 123 that is the observation target. For this reason, the skew between the two inputs (AND inputs 1 and 2) of the AND gate 123 is within an allowable range, and does not have a great adverse effect on the overall arrangement and wiring. After the output of the AND gate 123, no timing constraint is imposed (placed and routed under timing relaxation conditions).

  However, as shown in FIG. 18B, even if a delay of one clock cycle or more occurs in the observation target node (the output of the AND gate 123), the delay correction circuit 211 delays other monitor bits. It is possible to align relative time relationships. For this reason, there is no problem in waveform observation. When the output of the combinational logic circuit becomes an observation node, the node may disappear as a result of optimization of logic synthesis software. In such a case, optimization can be suppressed using a keep attribute or the like.

  FIG. 19 shows an output waveform of the test signal generation circuit (209 in FIG. 15) in the present embodiment. This waveform is obtained by inverting the polarity every 16 periods of the clock of the monitor clock (one period is 32 monitor clock clock cycles). Such a waveform can be generated using MSB (Most Significant Bit) of a 5-bit counter circuit. Note that only one test signal generation circuit 209 is installed, and the same test signal is distributed to each bit of the monitor data.

  Next, the principle of monitor data delay correction will be described in detail. In the present embodiment, the delay correction location includes the delay correction circuit 211 in the FPGA 20 of FIG. 13 that corrects the delay for the high-speed serial monitor transmitted by the serial transmission circuit 215 and the I / O pin of the FPGA 20. There are two types of delay correction of the parallel monitor signal output to (220 in FIG. 13) by the delay correction circuit (306 and 308 in FIG. 18) in the logic analysis terminal 30.

  The serial monitor exists on the same FPGA chip 20 as the observation target node, and the calculation of the delay correction value is completed only by the result obtained by analyzing the FPGA placement and routing result by the timing analysis software.

  FIGS. 20A and 20B schematically show delays in the FPGA 20 in FIG. 13 that are arranged by focusing on a specific bit n on a specific monitor surface for a high-speed serial monitor including the serial transmission circuit 215 in the monitor path. FIG. As shown in FIG. 20B, the delay Y (n) related to the monitor clock path can be decomposed into the following elements.

Dclk_cmux: Delay from the clock source 204 that drives the circuit to be observed to the monitor clock multiplexer 207.

Dcmux_FIFO: Delay from the monitor clock multiplexer 207 to the dual clock FIFO 213.

  The delay X (n) related to the monitor data path can be decomposed into the following elements.

Dclk_tgt (n): Delay from the clock source 204 that drives the observation target circuit to the observation target circuit output stage FF201.

Dtgt_dmux (n): Delay from the observation target circuit (including combination logic if any) to the monitor data multiplexer 206.

Ddmux_adj (n): Delay from the monitor data multiplexer 206 to the delay correction circuit 211.

Dadj (n): Delay correction value by the delay correction circuit 211 and the multiplexer 212.

  In order to eliminate the delay skew between the monitor data and the monitor clock at the data input point of the dual clock FIFO 213, the following equation (1) may be satisfied. The left side shows the delay Y (n) of the clock path, and the right side shows the delay X (n) of the data path.

(Dclk_cmux + Dcmux_FIFO) = (Dclk_tgt (n) + Dtgt_dmux (n) + Ddmux_adj (n) + Dadj (n)) (1)

  Therefore, the delay correction circuit 211 and the multiplexer 212 may perform the following delay correction.

Dadj (n) = (Dclk_cmux + Dcmux_FIFO)-(Dclk_tgt (n) + Dtgt_dmux (n) + Ddmux_adj (n)) (2)

  However, in practical use, the above equation (2) is not directly used. The reason is that Dadj (n) has a negative value and may not be realized as a delay correction circuit, and the skew between bits cannot be corrected to align the signal timing as a bus. is there.

  In the above equation (2), the delay correction value Dadj (n) is a value that matches the phase of the monitor clock at the dual clock FIFO 213 point with the clock edge where the observation target signal is initially set up.

If the monitor clock delay is larger than the monitor data delay, that is,
(Dclk_cmux + Dcmux_FIFO) <(Dclk_tgt (n) + Dtgt_dmux (n) + Ddmux_adj (n))
... (3)
In this case, Dadj (n) is a negative value.

  In practice, the clock edge that identifies the monitor data need not coincide with the edge on which the monitor data was set up. Therefore, as described below, the edge may be shifted so that the delay correction value Dadj (n) becomes positive (see FIG. 21).

  In FIG. 21, when the delay of the monitor clock path is divided into a component of one monitor clock period Tmonclk or more and a component less than that, the latter X is calculated.

X = (Dclk_cmux + Dcmux_FIFO)-Tmonclk * Floor {(Dclk_cmux + Dcmux_FIFO) / Tmonclk} (4)

  Here, Floor (x) represents truncation of x to an integer value.

Next, monitor data path delay
Y (n) = Dclk_tgt (n) + Dtgt_dmux (n) + Ddmux_adj (n) (5)
And calculate the minimum Z (n) which is larger than Y (n) and becomes an integral multiple of the monitor clock cycle.

Z (n) = Tmonclk * Ceil [Y (n) / Tmonclk] (6)

  Here, Ceil (x) represents rounding up of x to an integer value.

Then the following W (n):
W (n) = Z (n) + X-Y (n) (7)
Gives a delay correction amount for identifying the polarity of monitor data at a non-negative and stable point of monitor bit n.

  However, since this delay amount does not consider the skew with other bits, a correct observation result is not obtained when the bit n is observed as a bus signal together with other monitor bits. Therefore, the number of monitor clock cycles necessary to match the bit with the longest delay is obtained as CYCalign (n) in the following equation (8).

CYCalign (n) = Ceil [Max {Z (m) + X, m = 0, m = mmax} / Tmonclk]-Ceil [{Z (n) + X} / Tmonclk]
(8)

  Here, Max {x (w), w = y, w = z} represents the maximum value of each x (w) obtained by moving the subscript w of x (w) from y to z. . The bit number of the high-speed serial monitor starts from 0, and the maximum value of the bit number is mmax + 1.

  Eventually, the following equation (9) in which a correction term for increasing the delay amount by the CYCalign (n) period is introduced into W (n) is the delay amount Dadj (n) to be applied to bit n.

Dadj (n) = W (n) + CYCalign (n) * Tmonclk (9)

  FIG. 21 shows an example in which delay correction is performed for a 2-bit (mmax = 1) observation target signal while taking into account the skew between the two bits.

X = (Dclk_cmux + Dcmux_FIFO)-Tmonclk * Floor {(Dclk_cmux + Dcmux_FIFO) / Tmonclk} (10)

Y (0) = Dclk_tgt (0) + Dtgt_dmux (0) + Ddmux_adj (0) (11)

Z (0) = Tmonclk * Ceil [Y (0) / Tmonclk] (12)

W (0) = Z (0) + X-Y (0) (13)

CYCalign (0) = Ceil [Max {Z (m) + X, m = 0, m = 1} / Tmonclk]-Ceil [{Z (0) + X} / Tmonclk]
= 2-2 = 0 ・ ・ ・ (14)

Dadj (0) = W (0) + CYCalign (0) * Tmonclk = W (0) (15)

CYCalign (1) = Ceil [Max {Z (m) + X, m = 0, m = 1} / Tmonclk]-Ceil [{Z (1) + X} / Tmonclk]
= 2-1 = 1 ・ ・ ・ (16)

Dadj (1) = W (1) + CYCalign (1) * Tmonclk = W (1) + Tmonclk (17)

  Focusing only on the observation target signal n = 1, the delay of the path from the clock source 204 to the input of the delay correction circuit 211 is less than one clock cycle. The delay of the path from the clock source 204 of the observation target signal n = 0 to the input point of the delay correction circuit 211 is larger than one clock cycle.

For this reason, for the observation target signal n = 1,
CYCalign (1) = 1
As shown, the observation target signal n = 0.

  Next, the delay correction procedure for the parallel monitor will be described. In the present embodiment, since there are connectors and cables used for wiring and connection on the substrate on the path of the parallel monitor, there are delay elements that are unknown only by analyzing the timing of the observation target FPGA.

  This unknown delay element is taken as the time point when the known pattern of the test signal is detected by taking in the delay amount of the waveform generated by the test signal generation circuit with respect to the monitor clock while gradually changing the delay amount by the delay correction circuit. Can do. Various methods for automatically adjusting the data acquisition phase using known test signals are known.

  In the embodiment, a timing relaxation condition is attached to the monitor circuit in order to facilitate the placement and routing of the FPGA. For this reason, the delay of each path varies greatly even inside the FPGA during the selection of the test signal and the selection of the signal under observation (selected by the test signal multiplexer). For this reason, even if the phase can be adjusted so that the data can be stably captured by the test signal, the amount of delay inside the FPGA changes at the time of switching to the monitor surface including the observation target node, and the optimum data capturing phase is shifted. May end up. Therefore, in the present embodiment, the internal delay when outputting the test signal, which is obtained by calculation from the timing analysis, and the output time when the monitor signal to be observed is output with respect to the delay correction amount obtained using the test signal. The solution is to include the difference in internal delay.

  FIG. 22 shows the delays of the respective parts arranged by focusing on a specific bit when the FPGA 20 is outputting a test signal in the parallel monitor. First, the delay associated with the monitor clock path can be broken down into the following elements.

Dclk_cmux: Determined by timing analysis. Delay from the clock source 204 that drives the observation target circuit to the monitor clock multiplexer 207.

-Dcmux_cpin: Determined by timing analysis. Delay from monitor clock multiplexer 27 to monitor clock pin output.

• D ^u cpin_anl: Indeterminate delay. Delay from the observation target drive clock source to the dual clock FIFO 310 of the logic analysis terminal 30.

  The superscript u (uncertain) indicates that the delay represented by the symbol is an indeterminate delay (caused by intermediate elements such as wiring on the observation target board or cable) that cannot be clarified by timing analysis. Show.

  Next, the delay associated with the path of the monitor data when the test signal plane is selected can be decomposed into the following elements.

• Dclk_tst: Determined by timing analysis. Delay from the observation target drive clock source 204 to the test signal generation circuit 209.

Dtst_tmux (n): Determined by timing analysis. Delay from test signal generation circuit 209 to test signal multiplexer 208.

Ddmux_mpin (n): Determined by timing analysis. Delay from test signal multiplexer 208 to parallel monitor pin (monitor output) 220.

· D ^u mpin_anl (n): uncertain delay: Parallel monitoring pin delay to (monitor output) 220 Carrara monitor input of the logic analysis device 30.

Dtstadj (n): determined by a search procedure to be described later: a delay from the monitor input of the logic analysis terminal 30 to the dual clock FIFO 310 (delay when the test signal can be normally received).

  The test signal has only one circuit common to all monitor bits, and the same signal is distributed to each monitor bit. For this reason, there is no subscript n in DClk_tst.

  Here, in the first stage of the calculation procedure, a test signal is received by the logic analysis terminal 30 as described later.

  The condition that clock and data skews are equal is given by the following equation (18). The left side represents the delay of the clock path, and the right side represents the delay of the monitor data path.

(Dclk_cmux + Dcmux_cpin + D ^u cpin_anl) = (Dclk_tst + Dtst_tmux (n) + Dmux_mpn (n) + D ^u mpin_anl (n) + Dtstadj (n)) (18)

here,
A (n) = Dclk_tst + Dtst_tmux (n) + Dmux_mpn (n) (19)

C (n) = Dtstadj (n) (20)

U (n) = D ^u cpin_anl-D ^u mpin_anl (n) (21)

V (n) = Dclk_cmux + Dcmux_cpin (22)

Then, an uncertain component U (n) due to an intermediate element such as a connector or a cable among the clock-data skews can be calculated as the following equation (23).

U (n) = A (n) + C (n)-V (n) (23)

  In Expression (23), C (n) = Dtstadj (n) on the right side is determined by executing a delay measurement procedure described later.

  On the other hand, FIG. 23 shows the delay of each part arranged focusing on one specific bit when the FPGA is outputting the observation target signal regarding the parallel monitor. The delay of the monitor clock path is the same as when the test signal is output.

  Data path delay is broken down into the following elements:

Dclk_tgt (n): Delay from the observation target drive clock source 204 to the output stage flip-flop 201 of the observation measurement target circuit. Confirm by timing analysis.

Dtgt_dmux (n): Observation target node (in some cases, a delay from the output of the combinational logic circuit to the monitor data multiplexer 206. Determined by timing analysis.

Ddmux_tmux (n): Delay from the monitor data multiplexer 206 to the test signal multiplexer 208. Confirm by timing analysis.

Dmux_mpin (n): Delay from the test signal multiplexer 208 to the parallel monitor pin (monitor output) 220. Confirm by timing analysis.

D ^u mpin_anl (n): Delay from the parallel monitor pin (monitor output) 220 to the logic analysis terminal 30. Indefinite delay.

Dtgtadj (n): The delay correction value that is finally calculated.

  The condition that the clock edge and the data edge are aligned is given by the following equation (24). The left side represents the delay of the monitor clock path, and the right side represents the delay of the monitor data path.

(Dclk_cmux + Dcmux_cpin + D ^u cpin_anl) = (Dclk_tgt (n) + Dtgt_dmux (n) + Ddmux_tmux (n) + Dmux_mpin (n) + D ^u mpin_anl (n) + Dtgtadj (n)) (24)

  Therefore, the optimum delay correction amount for aligning the clock edge and the data edge is expressed by the following equation (25).

Dtgtadj (n) = (Dclk_cmux + Dcmux_cpin)-(Dclk_tgt (n) + Dtgt_dmux (n) + Ddmux_tmux (n) + Dmux_mpin (n)) + (D ^u cpin_anl-D ^u mpin_anl (n)) ... (25 )

B (n) = Dclk_tgt (n) + Dtgt_dmux (n) + Ddmux_tmux (n) + Dmux_mpin (n) (26)
Then, the above equation (25) is expressed by the following equation (27).

Dtgtadj (n) = V (n)-B (n) + U (n) (27)

Here, U (n), which is an uncertain delay component, is as described above.
U (n) = A (n) + C (n)-V (n) (28)
Therefore, the final delay correction value Dtgtadj (n) is given by the following equation (29).

Dtgtadj (n) = A (n)-B (n) + C (n) (29)

  Since each component of A (n) and B (n) is given from the timing analysis and C (n) has been measured by the delay measurement procedure, Dtgtadj (n) can be calculated.

  Note that the delay V (n) related to the monitor clock disappears in the calculation process. This is also clear from the fact that the path related to the monitor clock is unchanged when the test signal is received and when the observation target is received.

  Similarly, in the case of a high-speed serial monitor, in order to prevent the delay correction value Dtgtadj (n) from becoming a negative value and absorb the skew between bits, in practice, Dtgtadj (n) It is necessary to include a correction term that adds a delay that is an integral multiple of the monitor clock. The calculation method of Dtgtadj (n) including this delay is automatically considered in the process of performing the following procedure.

  A procedure for measuring a delay correction value to be applied to each monitor bit on a monitor surface having a parallel monitor using the above principle will be described below. In the following description, reference is made to FIG. FIG. 24 is a diagram for explaining the delay measurement procedure of the parallel monitor.

  In order to absorb inter-bit skew and ensure alignment between bits, one bit is selected as a representative bit for alignment (hereinafter referred to as reference bit M). This can be any bit.

In FIG.
(A) is the monitor clock (test signal generation circuit input point),
(B) is a test signal generation circuit output,
(C) is the monitor clock (logic analysis terminal FIFO point),
(D) is a test signal (test signal generation circuit point),
(E) is a data bit M (reference bit) (before passing through the delay correction circuit),
(F) is a data bit M (reference bit) (after passing through the delay correction circuit, immediately after starting the 1 → 0 change point search),
(G) is data bit M (reference bit) (after delay correction circuit, when 1 → 0 change point search is completed), (h) is data bit N (subordinate bit) (before passing through delay correction circuit),
(I) is data bit N (subordinate bit) (after passing through the delay correction circuit, immediately after 1 → 0 change point search is started),
(J) is a waveform of data bit N (dependent bit) (after completion of delay correction circuit, when 1 → 0 change point search is completed).

  (1) of the monitor clock (1): Immediately after starting the search for the change point of 1 → 0, the edge at which the polarity of the test signal switches from 0 → 1 is set as the reference for the alignment between bits.

(1) in (g): The search is completed when the polarity of the signal received at the inter-bit alignment reference edge is switched from 1 to 0.

  In (i), the dependent bit starts searching from delay correction 0.

  (J) (1): The search is completed when the polarity of the signal received at the inter-bit alignment reference edge is switched from 1 to 0.

  FIG. 25 is a flowchart showing a procedure for calculating the optimum delay correction amount of the reference bit M in the embodiment of the present invention.

First, software operating on the host computer (not shown) reads the timing analysis result of the observation target FPGA write No (step S1).

  For the reference bit M, the delay analysis result A (M) of the path from the clock source 204 that drives the test signal generation circuit 209 of FIG. 22 to the monitor data pin 220 of the reference bit M is retrieved and stored (step S2).

  In FIG. 23, the delay analysis result B (M) of the path from the clock source 204 that drives the observation target node M on the monitor surface X to the monitor data pin 220 of the reference bit M is retrieved and stored (step S3). .

Delay analysis result A (M) = Dclk_tst + Dtst_dmux (M) + Ddmux_mpn (M) (30)

Delay analysis result B (M) = Dclk_tgt (M) + Dtgt_dmux (M) + Ddmux_tmux (M) + Dmux_mpin (M) (31)

  Next, the software 402 operating on the host computer 40 transmits a command to switch the monitor surface to the test signal surface through the logic analysis terminal 30 to the observation target FPGA 20 (step S4).

  Here, in order to avoid that the delay correction amount becomes negative and cannot be realized, each bit is corrected in advance by a delay correction circuit (306 in FIGS. 22 and 23) in the process of calculating the delay correction amount. A delay offset corresponding to half of the maximum possible delay amount is added so that the finally applied delay correction amount is distributed in the vicinity of the delay amount that is about half of the maximum delay amount.

  For this purpose, the logic analysis software (software) 402 operating on the host computer 40 instructs the delay correction circuit 306 in the logic analysis terminal 30 to set a delay corresponding to half of the maximum delay that can be set. Transmit (step S5). It is assumed that the maximum delay amount that can be set in the delay correction circuit 306 is sufficiently larger than the delay amount to be corrected.

  At this time, since the test signal is received in the logic analysis terminal 30, the logic analysis software 402 operating on the host computer 40 sends a Run command (to the Run / Stop / trigger control circuit 312 of the logic analysis terminal 30. A command to start writing to the memory 316) is transmitted, and the test signal received via the read control circuit 317 is captured.

  The logic analysis software 402 operating on the host computer 40 analyzes the captured test signal, identifies the edge of the monitor clock whose signal polarity changes from 0 to 1, and sets this as the “reference edge” (step) S6).

  With this reference edge, a counter (not shown) in the time base circuit 314 is initialized, and thereafter, the counter (not shown) in the time base circuit 314 performs a counting operation in synchronization with the monitor clock.

  A counter (not shown) in the time base circuit 314 is initialized again at the same cycle as the test signal (32 monitor clock cycles), and this timing is set as a reference edge in the next cycle.

  The host computer 40 can recognize a change in the polarity switching point of the test signal by using the reference edge as a reference.

  Next, the logic analysis software 402 operating on the host computer 40 sends a command to the delay correction circuit 306 in the logic analysis terminal 30 to increase the delay by one step, and takes in the test signal (step). S7).

  Here, it is determined whether the signal polarity received at the time of occurrence of the inter-bit alignment reference edge is 1 or 0 (determining whether the signal polarity at the reference edge has changed from 1 to 0) (step S8). In step S7, the delay is increased by one step until the signal polarity that does not change becomes zero.

  When the signal polarity at the inter-bit alignment reference edge changes to 0, the delay amount C (M) at that time is stored (step S9).

  Next, the logic analysis software 402 operating on the host computer 40 calculates the following delay amount (step S10).

  Delay analysis result A (M)-Delay analysis result B (M) + Delay amount C (M) (32)

  This delay amount becomes the optimum delay correction amount Dtgtadj (M) (see FIG. 23B) for aligning the clock edge and the data edge with respect to the reference bit.

  When the calculation of the optimum delay correction amount of the reference bit is completed, the procedure for calculating the optimum delay amount of all the remaining monitor bits (hereinafter “subordinate data bit N”) is executed.

  FIG. 26 is a flowchart for explaining the delay correction amount calculation procedure for the dependent bit N.

  The procedure until the delay analysis results A and B are stored is the same as the reference bit procedure (steps S1 to S3) in FIG. 25 (steps S21 to S23).

  Next, the logic analysis software 402 operating on the host computer 40 transmits a command to switch the monitor surface to the test signal surface through the logic analysis terminal 30 to the observation target FPGA 20 (step S24).

  Next, the logic analysis software 402 operating on the host computer 40 transmits a command to set the delay amount to zero to the delay correction circuit 306 in the logic analysis terminal 30 (step S25). At this time, when the test signal received via the read control circuit 317 in the logic analysis terminal 30 is captured, the polarity of the test signal is 1 at the reference edge time. As the “reference edge”, the one determined when the delay of the reference bit M is measured is used.

  Next, the logic analysis software 402 operating on the host computer 40 sends a command to the delay correction circuit 306 in the logic analysis terminal 30 to increase the delay by one step, and takes in the test signal (step) S26).

  Here, it is determined whether the signal polarity received at the time of occurrence of the reference edge is 1 or 0 (step S27). If the signal polarity is 1, the process returns to step S26, and the delay is increased by one step. And repeat until the signal polarity becomes zero.

  When the signal polarity changes to 0 at the reference edge, the delay amount C at that time is stored (step S28).

  Next, the logic analysis software 402 operating on the host computer 40 calculates the delay amount of the following equation (33) (step S29).

  Delay analysis result A (N)-Delay analysis result B (N) + Delay amount C (N) (33)

  This delay amount becomes the optimum delay correction amount Dtgtadj (N) (see FIG. 23) for aligning the clock edge and the data edge with respect to the dependent bits.

  When the above calculation procedure is completed, the logic analysis software 402 operating on the host computer 40 transmits an instruction to switch to the observation target monitor plane X to the observation target FPGA 20 via the logic analysis terminal 30, and the logic analysis software 30 in the logic analysis terminal 30. A command to set an individual optimum delay correction amount Dtgtadj (N) is transmitted to the delay correction circuit 306 for each reference bit and dependent bit.

  In the above embodiment, the configuration of the monitor circuit to be mounted on the FPGA 20 to be observed shown in FIG. 13 is the circuit to be observed (on the FPGA concerned) on one FPGA (that is, one semiconductor chip). However, a part of the monitor circuit may be cut out using the I / O pin of the FPGA and mounted on another chip. By doing this, the difficulty of placement and wiring of the circuit to be observed is further reduced, and when debugging is completed, the chip on which the monitor circuit is mounted is removed from the observation target board, thereby observing the target board. It is expected to help reduce manufacturing costs, power consumption, dimensions, etc.

  In particular, recently, an element in which a plurality of semiconductor chips are stacked and an I / O pin and a package are shared has been developed. Therefore, development is executed with a circuit to be observed mounted on one side of the laminated chip and a monitor circuit mounted on the other side. When the monitor circuit becomes unnecessary, only the chip on which the circuit to be observed is mounted is switched to the sealed element. By doing so, it is expected that the manufacturing cost and power consumption can be reduced without revising the layout of the observation target substrate.

  In the above embodiment, the high-speed serial monitor (the monitor circuit including the serial transmission circuit) exists on the same chip as the FPGA in which the observation target node exists, and therefore there is no indefinite delay element in the middle. Therefore, the delay correction is calculated using only the timing analysis result without using the test signal. When an indefinite delay element is inserted in the route for some reason, the delay correction value may be determined using a test signal as in the parallel monitor of the embodiment.

  In the above embodiment, the high-speed serial monitor and the parallel monitor are provided together, but only one of them may be mounted. As a result, an FPGA without a serial transmission circuit or a serial transmission circuit is mounted, but the present invention can be applied even to an FPGA with insufficient I / O pins for mounting a parallel monitor.

  In the above embodiment, the number of serial transmission circuits and high-speed serial reception circuits is one pair. However, these numbers may be arbitrarily increased so that more monitor data can be observed simultaneously.

  In the above-described embodiment, the connector and cable used for connection between the analysis target board and the logic analysis terminal use a product having a specified characteristic impedance in order to support high-speed serial transmission. Even if such a product is used, it may be difficult to use in combination with a transceiver (for example, 28.05 Gbps) having the highest transmission bandwidth at the current state of the art. Therefore, instead of using an electrical connection, optical transmission may be used. Specifically, an O / E (optic-electric) conversion may be performed using an SFP (small form-factor pluggable) connector as the connector, and an optical fiber may be used as the cable.

  Since the FPGA 20 shown in FIG. 13 is equipped with a JTAG IF 216, this function is used to set the configuration data from the host computer 40 to the development target FPGA and to use other JTAG functions. You may deform | transform so that it can be used for the use of. Specifically, functions provided by products such as the well-known product “USB Blaster” (manufactured by Altera Corporation) and “Platform Cable USB II” (manufactured by Xilinx Incorporated) may be incorporated into the logic analysis terminal.

  According to the above embodiment, the use of FPGA placement and routing resources related to the monitor circuit and the number of FPGA I / O pins used for the monitor circuit are suppressed, and the difficulty of placement and routing of the entire FPGA to be observed is increased. Therefore, it is possible to mount a monitor circuit.

  In addition, according to the above-described embodiment, the signal observability can be kept high by using the observation target signal with less degradation of the observation signal due to the occurrence of glitches and less skew between bits in the bus signal.

  According to the embodiment, it is possible to obtain a logic analysis system that can be easily carried without using a logic analyzer.

  The disclosures of the above-mentioned patent documents and non-patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. . That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Observation object board | substrate 11 Clock source 12 Connector 13 Cable 14 Board | substrate wiring 20 FPGA (observation object FPGA)
21 Flip-flop 22 Monitor data multiplexer (MUX)
23 Monitor data pin (monitor pin)
24 monitor clock pin 25 clock source 30 logic analysis terminal 40 host computer 50 logic analyzer 101 LE
102 interconnect 103 I / O pin 110 LUT
111 SRAM cell 112 Multiplexer 113 Flip-flop (D-FF)
120 flip-flop (D-FF)
121, 122 Combinational logic circuit 123 AND gate 124 Intermediate path 125 Monitor pins 131-133 2-input LUT
200 observation target circuit 201 flip-flop 202 combinational logic circuit 203 parallel monitor target signal 204 clock source 205, 206 monitor data multiplexer 207 monitor clock multiplexer 208 test signal multiplexer 209 test signal generation circuit 210 circuit block 211 delay correction circuit 212 multiplexer 213 dual clock FIFO
214 Bit width / rate conversion unit 215 Serial transmission circuit 216 JTAG IF
220 Parallel monitor pin (monitor output)
221 Monitor data pin 222 Input / output pin 223 Monitor clock pin (monitor clock output)
230 Cable 300 Connector 302 Parallel monitor pin 303 Monitor clock input 304 Serial monitor input 305 JTAG bridge 306 Delay correction circuit 307 Serial reception circuit 308 Multiplexer 309 Clock multiplexer 310, 311 Dual clock FIFO
312 Run / Stop / Trigger control circuit 313 Memory clock (clock source)
314 Time base circuit 315 Time stamp addition circuit 316 Memory 317 Read control circuit 318 Host I / F
319, 401 USB connector 402 Logic analysis software

Claims (10)

A semiconductor device comprising a monitor circuit for monitoring the internal state of the semiconductor device;
A logic analysis terminal for receiving a signal from the monitor circuit;
With
The monitor circuit is
A first multiplexer that inputs a plurality of observation target signals of a plurality of observation target nodes inside the semiconductor device, and selects and outputs an observation target signal according to a first selection signal;
A second multiplexer for inputting a plurality of clock signals and selecting and outputting a monitoring clock signal in accordance with the second selection signal;
And at least one of the first and second multiplexers includes a multiplexer configured to suppress glitch propagation to the output with respect to a change in polarity of at least one of the plurality of signal inputs. See
The logic analysis terminal is
A second clock source;
A serial receiving circuit that receives a signal transmitted serially from the monitor circuit and converts it into a parallel signal;
A second buffer unit for writing a parallel signal from the serial receiving circuit with a clock signal for parallel writing from the serial receiving circuit and for reading with a clock signal from the second clock source;
A second delay correction circuit for correcting a delay of a signal transmitted in parallel from the monitor circuit;
A fourth multiplexer that receives a clock signal selected by the second multiplexer of the monitor circuit or a clock signal from the second clock source and selects one based on a fourth selection signal;
The parallel observation target signal received from the monitor circuit is delay-corrected by a delay compensation circuit, and a signal through the fifth multiplexer is written with the clock signal selected by the fourth multiplexer, and the clock from the second clock source is written. A third buffer section to be read with a signal;
A storage unit for storing signals read from the second and third buffer units;
A logic analysis system characterized by including: 2. The monitor circuit according to claim 1, wherein at least a path from the observation target node to the output of the first multiplexer is arranged and routed without timing constraints regarding an operating frequency and a maximum allowable delay. Logic analysis system . The monitor circuit is
A test signal generation circuit for outputting a test signal in synchronization with a clock signal output from the second multiplexer;
A third multiplexer that inputs the test signal and the observation target signal selected by the first multiplexer, and selects and outputs one in accordance with a third selection signal;
The logic analysis system according to claim 1, further comprising: The monitor circuit is
A first delay correction circuit that corrects and outputs a delay to the observation target signal output from the first multiplexer;
The observation target signal whose delay has been corrected by the first delay correction circuit is received, the observation target signal is written using the clock signal selected by the second multiplexer as a write clock signal, and reading is performed according to a read clock. A first buffer unit;
A bit width / rate conversion unit that inputs the observation target signal read from the first buffer unit and performs bit width and rate conversion;
A serial transmission circuit that converts the observation target signal output from the bit width / rate conversion unit into a serial signal and serially outputs it from an output terminal of the semiconductor device;
With
4. The logic analysis system according to claim 3 , wherein the signal selected and output by the third multiplexer is output in parallel from an output terminal of the semiconductor device. The semiconductor device further comprises a combinational logic circuit,
The observation target node is an output node of the combinational logic circuit;
Skew between the plurality of inputs of the combinatorial logic path leading to the output node of the combinational logic circuit, according to claim 3 or 4, wherein said is within one cycle of the clock signal, it Logic analysis system . The logic analysis terminal is
An interface unit connected to the host computer;
A read control circuit for reading the content of the storage unit and transmitting it to the host computer;
A control unit that performs start / stop control of signal writing to the storage unit;
The logic analysis system according to claim 3 , further comprising: A host computer connected to the logic analysis terminal;
The host computer is
In controlling the delay correction of the second delay correction circuit of the logic analysis terminal,
From the timing analysis result after the placement and routing of the semiconductor device, a delay A of the path from the test signal generation circuit in the semiconductor device to the output terminal of the semiconductor device, and the observation target node in the semiconductor device to the semiconductor The delay of the path to the output terminal of the device : B is acquired and stored,
The test signal of the test signal generation circuit in the semiconductor device is monitored, and the delay amount is initialized to zero for the second delay correction circuit of the logic analysis terminal,
It is determined whether a received data pattern from the test signal generation circuit in the semiconductor device matches a known test signal pattern, and a delay amount is set with respect to the second delay correction circuit until it matches a known test signal pattern. is varied, if the received data pattern matches the known test signal pattern, the logic analysis delay set in the second delay compensation circuit of the terminal at that time: storing C,
The observed target signal from the observation nodes in the semiconductor device as a monitor object, the delay amounts: and C, the delay of the path from the test signal generating circuit in the semiconductor device to an output terminal of the semiconductor device: A From the observation node in the semiconductor device to the output terminal of the semiconductor device, a delay amount : A−B + C obtained by adding a value obtained by subtracting B is the second delay correction of the logic analysis terminal. The logic analysis system according to claim 6 , further comprising means for setting the circuit. A monitor circuit mounted on a semiconductor device and monitoring an internal state of the semiconductor device, wherein a plurality of observation target signals of a plurality of observation target nodes inside the semiconductor device are input and an observation target signal is received according to a first selection signal A first multiplexer that selects and outputs a plurality of clock signals, and a second multiplexer that receives a plurality of clock signals and selects and outputs a monitoring clock signal according to the second selection signals, At least one of the two multiplexers receives a signal from a monitor circuit including a multiplexer configured to suppress propagation of a glitch to the output with respect to a change in polarity of at least one of the plurality of signal inputs. A terminal,
A second clock source;
A serial receiving circuit that receives a signal transmitted serially from the monitor circuit and converts it into a parallel signal;
A second buffer unit for writing a parallel signal from the serial receiving circuit with a clock signal for parallel writing from the serial receiving circuit and for reading with a clock signal from the second clock source;
A second delay correction circuit for correcting a delay of a signal transmitted in parallel from the monitor circuit;
A fourth multiplexer that receives a clock signal selected by the second multiplexer of the monitor circuit or a clock signal from the second clock source and selects one based on a fourth selection signal;
The parallel observation target signal received from the monitor circuit is delay-corrected by a delay compensation circuit, and a signal through the fifth multiplexer is written with the clock signal selected by the fourth multiplexer, and the clock from the second clock source is written. A third buffer section to be read with a signal;
A storage unit for storing signals read from the second and third buffer units;
A logic analysis terminal characterized by including. The observed target signal of the semiconductor device inside the observation target node, a transmitting end for transmitting a signal from the toggle its switching circuit and a test signal from the test signal generating circuit, between the receiving end of the signal from the transmitting end the correction of the delay of the signal from the transmitting stage in the circuit delay is present, a method using a computer,
The computer, the semiconductor from the timing analysis results after placement and routing of the apparatus, prior Symbol test signal generating circuit of the drive clock source the lead to the transmitting end path for the first delay analysis Results: and A, of the observed object node drive clock source the lead to the transmitting end path for the second delay analysis results: storing acquired by the B,
The computer, the switching circuit is set to the test signal side, from said test signal generating circuit of the known fetches the reception data patterns in our Keru the test signal to the receiving end when said test signal is being transmitted It is determined whether or not a test signal pattern is matched, and a delay amount of a delay correction circuit that corrects a delay of the signal from the transmission end is varied until the received data pattern matches the known test signal pattern, and received data delay correction value when the pattern is matched to the known test signal patterns: storing C,
Delay correction method the computer, the A-B + C, as the delay correction value required to receive before Symbol observation target signal, to set to the delay correction circuit, characterized in that. The observed target signal of the semiconductor device inside the observation target node, a transmitting end for transmitting a signal from the toggle its switching circuit and a test signal from the test signal generating circuit, between the receiving end of the signal from the transmitting end A program for causing a computer to correct the delay of the signal from the transmitting end in a circuit in which a delay exists,
The timing analysis of the semiconductor device, prior Symbol test signal generating circuit of the drive clock source the transmitting stage path first delay analysis results for leading from: and A, to the transmitting end from the drive clock source of the observed object node A second delay analysis result regarding the route to reach: a process of acquiring and storing B;
Switching the switching circuit to the test signal side, it matches the known test signal pattern fetches the received data pattern in our Keru the test signal to the receiving end when the test signal from the test signal generating circuit is transmitted Until the received data pattern matches the known test signal pattern, a delay amount of a delay correction circuit for correcting a delay of the signal from the transmission end is varied, and the received data pattern is changed to the known data pattern. A process of storing a delay correction value: C when it matches the test signal pattern ;
The A-B + C, as the delay correction value required to receive before Symbol observation target signal, including the processing and to set to the delay correction circuit, program.

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