CN117725869A

CN117725869A - Assertion development method, chip verification method, device, equipment and medium

Info

Publication number: CN117725869A
Application number: CN202311785344.3A
Authority: CN
Inventors: 宋昆璐; 曹铸; 刘洁
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2023-12-22
Filing date: 2023-12-22
Publication date: 2024-03-19

Abstract

The application discloses an assertion development method, a chip verification method, a device, equipment and a medium, and relates to the technical field of chip verification. Applied to a formal verification platform, the method comprises the following steps: determining a target level in a design to be tested for chip verification to obtain a verification level; determining a target logic verification module in the verification hierarchy and extracting a target port signal in the target logic verification module; configuring and restraining the target port signal by utilizing a configuration requirement standard rule to generate a design file, and classifying and packaging the design file by utilizing a macro definition rule to generate a verification file; and binding the verification file into a verification environment so that the form verification platform performs chip verification on the design to be tested according to the macro definition rule and the configuration requirement specification rule when compiling the verification file. Through the technical scheme of the application, assertion development can be generated rapidly, and the reliability and operability of chip verification are improved greatly.

Description

Assertion development method, chip verification method, device, equipment and medium

Technical Field

The present invention relates to the field of chip verification technologies, and in particular, to an assertion development method, a chip verification method, a device, equipment, and a medium.

Background

With the development of new technologies such as artificial intelligence, internet of things and 5G, the chip industry gradually becomes one of the most important industries in the world nowadays, and the integrated circuit industry also faces new opportunities and new challenges. The chip verification is an important ring for the front-end development of the chip, takes an important ring in the accelerated development process of the integrated circuit, occupies nearly half of time and energy in the chip design development, and confirms whether the chip virtual version realized by a chip design team accords with the overall blueprint of an architect before chip streaming and manufacturing, which is also the key of the chip design verification. With the complexity of chip design modules, chip front-end verifiers have developed many different verification methods for different design modules during verification.

Currently, conventional verification methods are used for a design under test (Design Under Test, DUT) module with a multi-level complex topology structure with strict logic, such as excessively long compiling time, and failure to completely cover all verification logic. For this disadvantage, static verification can be implemented using a form platform (Formal Verification, formal verification platform). However, generic form verification is to acquire the top-level signals of the module, and to detect signal propagation using assertions based on design description specifications, for the entire DUT. For a design module of a multi-level topology structure, logic of each level inside the module needs to be verified, port signals of a certain logic level to be verified cannot be directly obtained at a top port, and therefore the design logic of the level cannot be directly verified.

Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.

Disclosure of Invention

In view of the above, the present invention aims to provide an assertion development method, a chip verification method, a device, equipment and a medium, which can solve the limitation of verifying a design module of a multi-level topological structure aiming at strict logic, and realize direct verification of design logic of each level in a design to be tested. The specific scheme is as follows:

in a first aspect, the present application discloses an assertion development method, applied to a formal verification platform, including:

determining a design to be tested for chip verification, and determining a target level in the design to be tested to obtain a verification level; the design to be tested internally comprises a plurality of internal levels, and each internal level corresponds to a respective signal propagation rule;

determining a target logic verification module in the verification hierarchy and extracting a target port signal in the target logic verification module;

configuring and restraining the target port signal by utilizing a configuration requirement standard rule to generate a design file, and classifying and packaging the design file by utilizing a macro definition rule to generate a verification file;

And binding the verification file into a verification environment, so that the form verification platform performs chip verification on the design to be tested according to the macro definition rule and the configuration requirement specification rule when compiling the verification file.

Optionally, the determining the design to be tested for chip verification includes:

determining a port control logic circuit corresponding to a target connection point on the chip for chip verification;

correspondingly, the determining the target logic verification module in the verification hierarchy and extracting the target port signal in the target logic verification module includes:

and determining port control logic inside the port control logic circuit in the verification level, and extracting a clock signal, a reset signal and a first port signal for performing functional configuration in the port control logic.

Optionally, acquiring the configuration requirement specification rule includes:

acquiring a related pin template table predefined for the design to be tested; the relevant pin template table records port signals corresponding to different pins and mode configuration corresponding to the port signals;

extracting a target pin corresponding to the target logic verification module in the related pin template table, and determining the corresponding target port signal according to the target pin;

And acquiring corresponding target mode configuration from the related pin template table by utilizing the target port signal determined according to the target pin so as to determine the configuration requirement specification rule by utilizing the target port signal and the target mode configuration.

Optionally, the determining a target logic verification module in the verification hierarchy and extracting a target port signal in the target logic verification module includes:

defining a top-level virtual verification platform and instantiating the design to be tested based on the top-level virtual verification platform to determine top-level signals of the design to be tested;

determining a target logic verification module in the verification hierarchy, and extracting a target port signal in the target logic verification module based on the top-level signal;

correspondingly, the configuring constraint is performed on the target port signal by using a configuring requirement specification rule to generate a design file, and the design file is classified and packaged by using a macro definition rule to generate a verification file, which comprises the following steps:

performing configuration constraint on the target port signal by using a configuration requirement specification rule to generate a design file;

determining a second port signal which can be multiplexed in the design file and acquiring configuration constraints corresponding to the second port signal;

Obtaining macro definition parameters for macro definition, and encapsulating the macro definition parameters by using a preset encapsulation command based on the second port signal, configuration constraint corresponding to the second port signal and the macro definition parameters to obtain a macro definition file;

the macro definition file is validated by a checker component to generate the validation file.

Optionally, after determining the target logic verification module in the verification hierarchy, the method further includes:

and closing the high-performance bus in the top-level virtual verification platform so as to acquire a default value which is not modified by the write operation of the high-performance bus from a register when the chip verification is performed based on the verification level.

determining a target logic verification module in the verification hierarchy, and extracting a target port signal in the target logic verification module through a preset assertion verification creation interface; the preset assertion verification creation interface is an interface for extracting signals according to port signals input by the terminal;

Or determining a target logic verification module in the verification hierarchy, acquiring a port signal extraction script through a preset script creation interface, and automatically extracting a target port signal in the target logic verification module through the port signal extraction script.

In a second aspect, the present application discloses a chip verification method, applied to a form verification platform, including:

acquiring a verification file bound in a verification environment of the form verification platform; the verification file is obtained by using the assertion development method;

analyzing the verification file to determine a macro definition rule corresponding to the verification file, and determining a corresponding design file and a configuration requirement specification rule in the design file for performing configuration constraint on a target port signal according to the macro definition rule; wherein the target port signal is a signal extracted from a target logic verification module located at a verification level; the verification level is a target level in a design to be tested for chip verification; the design to be tested internally comprises a plurality of internal levels, and each internal level corresponds to a respective signal propagation rule;

And carrying out chip verification on the design to be tested according to the macro definition rule and the configuration requirement specification rule.

In a third aspect, the present application discloses an assertion development device, applied to a formal verification platform, including:

the verification level determining module is used for determining a design to be tested for chip verification and determining a target level in the design to be tested to obtain a verification level; the design to be tested internally comprises a plurality of internal levels, and each internal level corresponds to a respective signal propagation rule;

the signal extraction module is used for determining a target logic verification module in the verification hierarchy and extracting a target port signal in the target logic verification module;

the assertion development module is used for carrying out configuration constraint on the target port signal by utilizing a configuration requirement specification rule to generate a design file, and classifying and packaging the design file by utilizing a macro definition rule to generate a verification file;

and the chip verification module is used for binding the verification file into a verification environment, so that the form verification platform performs chip verification on the design to be tested according to the macro definition rule and the configuration requirement specification rule when compiling the verification file.

In a fourth aspect, the present application discloses an electronic device comprising a processor and a memory; wherein the memory is for storing a computer program that is loaded and executed by the processor to implement the method as described above.

In a fifth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements a method as described above.

The application provides an assertion development method which is applied to a form verification platform and comprises the following steps: determining a design to be tested for chip verification, and determining a target level in the design to be tested to obtain a verification level; the design to be tested internally comprises a plurality of internal levels, and each internal level corresponds to a respective signal propagation rule; determining a target logic verification module in the verification hierarchy and extracting a target port signal in the target logic verification module; configuring and restraining the target port signal by utilizing a configuration requirement standard rule to generate a design file, and classifying and packaging the design file by utilizing a macro definition rule to generate a verification file; and binding the verification file into a verification environment, so that the form verification platform performs chip verification on the design to be tested according to the macro definition rule and the configuration requirement specification rule when compiling the verification file.

The beneficial technical effects of this application are: by means of the formal verification platform, the monitoring of the internal logic can be performed for different internal levels within the design under test. The design to be tested for chip verification is a multi-level complex structure with strong logic and tight structure, and each internal level corresponds to a respective signal propagation rule. Further, in a plurality of hierarchical structures inside the design to be tested, data monitoring and rule checking are individually carried out on internal logic of a certain internal hierarchy, the internal logic is taken as a verification hierarchy, and a target logic verification module in the internal logic is determined. Giving up random excitation, extracting a target port signal in a target logic verification module, and carrying out configuration constraint on the port signal of the level by utilizing a configuration requirement specification rule, so that the influence of the random port signal change of the top level or other levels on the internal configuration of the current logic verification module is avoided; and secondly, classifying and packaging design files by adopting macro definition rules, realizing batch development of assertions, improving operability of verification work and enhancing reusability of attribute assertions. The scheme can be directly used for modules with multi-level load topological structures, and assertion development can be rapidly generated by only calling different packaging attributes according to different inspection rules, so that the reliability and operability of verification are greatly improved.

In addition, the chip verification method, the assertion development device, the equipment and the storage medium provided by the application correspond to the assertion development method and have the same effects.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of an assertion development method disclosed in the present application;

FIG. 2 is a schematic diagram of port signal extraction disclosed herein;

FIG. 3 is a schematic diagram of a PAD port control logic circuit format verification disclosed herein;

FIG. 4 is a flowchart of a specific assertion development method disclosed herein;

FIG. 5 is a schematic diagram of macro definition attribute and assertion coverage development disclosed in the present application;

FIG. 6 is a schematic diagram of an inspection file verification hierarchy disclosed herein;

FIG. 7 is a schematic diagram of a binding of a check file to a verification environment disclosed herein;

FIG. 8 is a flow chart of a chip verification method disclosed in the present application;

FIG. 9 is a schematic diagram of a compiling command for a design module disclosed herein;

FIG. 10 is a schematic diagram of an assertion development device disclosed in the present application;

fig. 11 is a block diagram of an electronic device disclosed in the present application.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Currently, with the complexity of chip design modules, chip front-end verifiers develop many multiple verification methods for different design modules in the verification process, and the common verification methods include the following methods:

(1) And developing a perfect testbench (top virtual verification platform) according to external interface signals, external clocks and reset input signals of the design module to be tested, generating a directional or random excitation vector according to an interface protocol and combining a test scene, and receiving a response of the DUT to the excitation. the monitor in testbench will input and output data from the DUT being monitored and send it to the checker for data prediction and comparison. The test platform is written in Verilog language.

(2) UVM (Universal Verification Methodology ) verification methods can be used for complex structure designs under test. According to the design module architecture, a UVM related component is created, a UVM block diagram is confirmed, each component is sequentially built from bottom to top, directional or random test excitation is generated, input and output data of the DUT module are monitored through a monitor, and the input and output data are sent to a scoreboard for inspection. The UVM verification method uses SV (System Verilog, a hardware design and verification language) as a main body for platform construction, utilizes reusable components to construct a standardized hierarchical structure, can generate random test excitation and random constraint, and realizes the verification of the DUT by means of object-oriented.

However, the increase of the chip scale also causes the increase of the proportion and importance of the verification work in the whole chip development process, so that the improvement of the efficiency of the verification work and the establishment of a proper and efficient verification platform for different design modules become important. For a design module to be tested with a multi-level complex topological structure and strict logic, if the conventional verification method is used, some defects appear, compared with the method (1), the method (2) is realized by means of a UVM library, all components are realized based on class, and the risk can be efficiently reduced and the simulation speed can be increased by using the existing framework and advanced verification technology. However, the limitation is that the compiling time is too long, and the random stimulus is used for verification, and it is impossible to verify all logic combinations by the directional stimulus, and all logic cannot be covered completely, so that the static verification can be realized by using a format platform.

Generic form verification is the detection of signal propagation using assertions based on design description specifications, for the entire DUT, to acquire the top-level signals of the module. However, for a design module of a multi-level topology structure, logic of each level inside the module needs to be verified, a port signal of a certain logic level to be verified cannot be directly obtained at a top port, and thus the design logic of the level cannot be directly verified.

Therefore, the application provides an assertion development scheme, which can solve the limitation of the traditional verification platform and the verification thought on the verification of the multi-level topological structure design module with strict logic, uses a static verification method, gives up random excitation by means of a form verification platform, acquires port signals of each level in the design to be tested, and uses assertion to verify output data and internal logic.

The embodiment of the invention discloses an assertion development method, which is shown in FIG. 1 and is applied to a form verification platform, and the method comprises the following steps:

step S11: determining a design to be tested for chip verification, and determining a target level in the design to be tested to obtain a verification level; the design to be tested internally comprises a plurality of internal levels, and each internal level corresponds to a respective signal propagation rule.

In the embodiment of the application, the method is applied to the form verification platform to realize static verification, and a complex dynamic verification platform is not needed. The condition of lower verification efficiency caused by overlong compiling time is avoided, only the correct connection between the form verification platform and the design module is ensured, and the verification time and the cost on personnel are reduced.

First, a design under test for chip verification is determined. For a design module with strict logic, the interior of the design to be tested comprises a plurality of internal levels, and each internal level corresponds to a respective signal propagation rule. In the embodiment of the present application, a port control logic circuit (pad_pcl, pad and Port control logic, hereinafter collectively referred to as pad_pcl) corresponding to a target connection point on a chip is taken as an example for performing chip verification. The reason for choosing it as chip verification is the following two points: first, the DUT is internally composed of multiple internal levels, the external clock reset stimulus is directly connected to one level internally, such as group 1, the output signal of that level in turn serves as the clock and reset input of another level, and DUT external AHB (Advanced High Performance Bus, advanced high-performance bus) bus access to bridges of the internal levels also requires the clock reset output of group 1 as a stimulus. Second, each hierarchy has a logically tight signal propagation rule.

It should be noted that the verification methods and solutions described in embodiments of the present application include, but are not limited to, simulation verification of a PAD_PCL module, and other DUTs having multi-level topology logic designs or clock reset cross-levels may also be used. It can be understood by those skilled in the art that the chip verification method based on pad_pcl is only schematic and does not limit the above-mentioned design to be tested for chip verification, and in the following embodiments, the design to be tested of pad_pcl is taken as an example for illustration, and will not be described in detail.

In the embodiment of the application, a certain hierarchy of the concerned logic block pad_pcl is selected as a verification hierarchy, and assertion development is performed based on the verification hierarchy.

Step S12: and determining a target logic verification module in the verification hierarchy, and extracting a target port signal in the target logic verification module.

In the embodiment of the application, since the pad_pcl is selected as the design to be tested for chip verification, further, a suitable target logic verification module is selected from the verification level of the pad_pcl for attribute development and assertion verification. At this time, port control logic (pcl_logic, pad control logic, hereinafter collectively referred to as pcl_logic) inside the port control logic circuit in the verification hierarchy is determined. It should be noted that pcl_logic is a logic unit of an internal hierarchy in pad_pcl.

In the embodiment of the application, after determining that pcl_logic is the target logic verification module of pad_pcl, the target port signal is extracted. The target port signals comprise clock signals, reset signals and first port signals used for functional configuration in pcl_logic. As shown in fig. 2, an extracted global signal schematic is exemplarily provided.

It should be noted that, in the formal verification platform, random traversal of the top-level signal of the top-level virtual verification platform (testbench, hereinafter collectively referred to as testbench) may cause internal configuration in other levels to change. Therefore, in order to enable the assertion development method in the embodiment of the present application to adapt to all internal levels, special configurations are performed for different verification rules. Specifically, after determining a target logic verification module in the verification hierarchy, closing the higher-level high-performance bus in the top-level virtual verification platform so as to obtain a default value which is not modified by a write operation of the higher-level high-performance bus from a register when performing chip verification based on the verification hierarchy.

That is, the top level port signals are constrained, and the relevant signals are configured to a fixed value to ensure that the validation level checking rules are not changed. In this way, the influence of random signals of other levels on the internal configuration of the current verification level is avoided. For example, in the embodiment of the present application, when verifying the default_value for the pcl_logic internal level, the top-level AHB bus behavior may be turned off, and when acquiring the register value for the g2 (group 2) level or other levels, a default value that is not modified by the AHB bus write operation may be obtained. It can be seen that the stimulus signals of the modules between different levels of the DUT are constrained, and the configuration of the internal configuration of the verified level is prevented from being changed due to the change of random port signals of the top level or other levels by using the constraint mode of the related signal configuration of the top level.

Step S13: and carrying out configuration constraint on the target port signal by using a configuration requirement specification rule to generate a design file, and classifying and packaging the design file by using a macro definition rule to generate a verification file.

In the embodiment of the application, after the target port signal of the pcl_logic to be verified is extracted, the target port signal is subjected to configuration constraint by using a configuration requirement specification rule to generate a design file. The configuration requirement specification rule records the performance requirement on pcl_logic, relevant assertion development is carried out based on the configuration requirement specification rule, and concurrent assertion is used for verifying functional correctness in a specific configuration mode.

In general, in the chip design process, a data port is generally configured as a GPIO (general purpose input/output, general purpose input/output port) and is directly connected to an input/output signal of an internal module of the chip, and a plurality of different function modules in the chip multiplex a general purpose PAD to connect to the general purpose port, so that a control module is required to configure a control register, and further control a logic relationship between the PAD and each internal function module of the chip to work normally. In order to verify pcl_logic, when obtaining the configuration requirement specification rule, the embodiment of the application specifically includes: acquiring a related pin template table predefined for the design to be tested; the relevant pin template table records port signals corresponding to different pins and mode configuration corresponding to the port signals; extracting a target pin corresponding to the target logic verification module in the related pin template table, and determining the corresponding target port signal according to the target pin; and acquiring corresponding target mode configuration from the related pin template table by utilizing the target port signal determined according to the target pin so as to determine the configuration requirement specification rule by utilizing the target port signal and the target mode configuration.

It can be seen that by extracting the relevant pcl_logic module interface signals and mode configuration in the PAD preset definition template table (pinlist), assertions are developed in the form verification environment, and the functional correctness of the PAD control logic module is verified in a static verification manner.

Furthermore, for the interface signals of the same PAD which can be multiplexed in the generated design file, the property definition of each mode can be packaged by utilizing a macro form in the logic verification process to realize the batch development of the assertion so as to generate the verification file. Therefore, according to the signal propagation rule of the verification level, the developed attributes are comprehensively classified and packaged in a macro definition mode, and in the logic inspection process, only proper macros are needed to be selected to efficiently and accurately finish assertion development in batches. In this way, the operability of verification work is improved, and the reusability of attribute assertion is enhanced.

Step S14: and binding the verification file into a verification environment, so that the form verification platform performs chip verification on the design to be tested according to the macro definition rule and the configuration requirement specification rule when compiling the verification file.

In the embodiment of the application, the checking file is bound to a format verification environment and is used for functional checking of the design module or constraint of port signals by the checker in the simulation process. When the form verification platform compiles the verification file, chip verification can be carried out on the design to be tested according to the macro definition rule and the configuration requirement specification rule.

The overall implementation flow steps are shown in fig. 3. Firstly, extracting port signals and developing assertion; and then integrated into a formal verification environment for compiling and simulating. In order to avoid the change of the random port signal of the top layer or other layers, which causes the change of the configuration in the verified layer, special processing is performed on the port signal, and the detailed implementation process is disclosed with reference to the foregoing steps in the embodiment, which is not described herein.

In a specific embodiment, the determining the target logic verification module in the verification hierarchy and extracting the target port signal in the target logic verification module includes:

step one: determining a target logic verification module in the verification hierarchy, and extracting a target port signal in the target logic verification module through a preset assertion verification creation interface; the preset assertion verification creation interface is an interface for extracting signals according to port signals input by the terminal.

Or, step two: and determining a target logic verification module in the verification hierarchy, acquiring a port signal extraction script through a preset script creation interface, and automatically extracting a target port signal in the target logic verification module through the port signal extraction script.

For convenience of description, the above two steps are described in combination.

In the embodiment of the application, the preset assertion verification creation interface is used for manually generating assertion verification obtained according to macro definition content in batches; the preset script creation interface directly extracts port signals of the verification level in a script mode and realizes assertion development in an automatic mode. Although manual batch generation of assertion verification from macro definition content can greatly improve operability. But requires a certain degree of knowledge of the port signals of all PADs by the user. The method can be optimized to automatically extract the target port signal in the target logic verification module in the manner of a port signal extraction script.

Therefore, the assertion development method described in the embodiment of the application improves the operability and completeness of chip verification, and can improve the efficiency and accuracy of code coverage rate collection. The use is not limited to DUTs of the type of multi-level topology referred to herein, but may be used with other level types of DUTs, or other design modules having strict logic. In a plurality of hierarchical structures in the DUT, data monitoring and rule checking can be independently carried out on internal logic of a certain hierarchical structure, and completeness checking of the DUT can be achieved by traversing the plurality of hierarchical structures.

The embodiment of the application discloses a specific assertion development method, which is shown in fig. 4, and includes:

step S21: determining a design to be tested for chip verification, and determining a target level in the design to be tested to obtain a verification level; the design to be tested internally comprises a plurality of internal levels, and each internal level corresponds to a respective signal propagation rule.

For more specific processing in step S21, reference may be made to the corresponding content disclosed in the foregoing embodiment, and no further description is given here.

Step S22: defining a top-level virtual verification platform and instantiating the design to be tested based on the top-level virtual verification platform to determine top-level signals of the design to be tested.

In the embodiment of the application, when the assertion is developed, a formal verification environment is first built, including a top layer testbench, checker and a compiling script file. Instantiating the design under test in testbench and defining a top-level signal of the design under test.

Step S23: and determining a target logic verification module in the verification hierarchy, and extracting a target port signal in the target logic verification module based on the top-level signal.

In the embodiment of the present application, the working principle of the form verification is to determine a target logic verification module in a verification level according to the design to be tested instantiated in the testbench, and extract a clock, a reset signal and a first port signal for performing functional configuration in the target logic verification module.

As shown in FIG. 5, for the multi-level structure of the PAD_PCL module, an appropriate level is selected for attribute development and assertion verification. In fig. 5, the top layer of the design under Test is instantiated in a format TB (Test bed), and then an internal module, pcl_logic, is selected as a verification level, and the port signals of the level are acquired, including the input and output directions of the register configuration, the functional mode of the register configuration, the output signals of the logic unit, and the like, which are associated with the internal logic.

Step S24: performing configuration constraint on the target port signal by using a configuration requirement specification rule to generate a design file; and determining a second port signal which can be multiplexed in the design file and acquiring configuration constraints corresponding to the second port signal.

In the embodiment of the application, on the basis of the extracted target port signal, the assertion is developed based on the configuration requirement specification rule, so that the monitoring and judgment of signal propagation are realized. And carrying out configuration constraint on the target port signal by using a configuration requirement specification rule to generate a design file. The configuration requirement specification rule records the performance requirement on pcl_logic, relevant assertion development is carried out based on the configuration requirement specification rule, and concurrent assertion is used for verifying functional correctness in a specific configuration mode.

In the embodiment of the application, aiming at the interface signals of the same PAD which can be multiplexed, the property definition of each mode is packaged by utilizing a macro form in the logic verification process to realize batch development of assertion, so that the operability of verification work is improved, and the reusability of attribute assertion is enhanced. Therefore, a second port signal capable of multiplexing in the design file is determined and a configuration constraint corresponding to the second port signal is acquired.

Step S25: obtaining macro definition parameters for macro definition, and encapsulating the macro definition parameters by using a preset encapsulation command based on the second port signal, configuration constraint corresponding to the second port signal and the macro definition parameters to obtain a macro definition file; the macro definition file is validated by a checker component to generate the validation file.

In this embodiment, taking the GPIO mode assertion development of a PAD interface signal in fig. 6 as an example, firstly, a concurrent assertion attribute in a GPIO INPUT mode is defined, and then, the gpio_input_astcov macro is used for encapsulation, and according to macro definition parameters transmitted in the macro: parameters such as PAD name, default value of output signal, coverage development or assertion development can be used for completing the test development of the input modes of a plurality of PAD signals GPIO to obtain a macro definition file.

Further, the macro definition file is assertion verified by a checker component (checker) to generate the verification file. The checker can implement the generation of a check file with SV syntax, aggregating the port signals, properties, and authentication/coverage of the verified hierarchy. Then, as shown in fig. 7, the step of binding the verification file into the verification environment is performed.

Step S26: and binding the verification file into a verification environment, so that the form verification platform performs chip verification on the design to be tested according to the macro definition rule and the configuration requirement specification rule when compiling the verification file.

For more specific processing in step S26, reference may be made to the corresponding content disclosed in the foregoing embodiment, and no further description is given here.

The embodiment of the application discloses a chip verification method which is applied to a form verification platform, and is shown in fig. 8, and the method comprises the following steps:

step S31: and acquiring the verification file bound in the verification environment of the form verification platform.

In the embodiment of the application, after the development of the chip verification assertion is completed, the chip verification is performed on the form verification platform in the same way. First, a verification file bound in a verification environment of a formal verification platform is acquired. The verification file is obtained by the assertion development method.

Step S32: analyzing the verification file to determine a macro definition rule corresponding to the verification file, and determining a corresponding design file and a configuration requirement specification rule for configuring and restraining a target port signal in the design file according to the macro definition rule.

Wherein the target port signal is a signal extracted from a target logic verification module located at a verification level; the verification level is a target level in a design to be tested for chip verification; the design under test internally comprises a plurality of internal levels, and each internal level corresponds to a respective signal propagation rule.

In the embodiment of the application, related design files and verification files are compiled, a verification mode is selected, the structure of the design files is read, a VCS (compiling type Verilog simulator) is called, a clock cycle and reset signal reset state is configured, constraints are configured, and check_fv is started.

It can be understood that the macro definition rule corresponding to the verification file can be determined after the verification file is analyzed, so that assertion development can be quickly generated by calling different encapsulation attributes for different inspection rules, and the reliability and operability of verification are greatly improved. Meanwhile, according to the macro definition rule, a corresponding design file and a configuration requirement specification rule for performing configuration constraint on the target port signal in the design file can be determined.

Step S33: and carrying out chip verification on the design to be tested according to the macro definition rule and the configuration requirement specification rule.

In the embodiment of the application, after the macro definition rule and the configuration requirement specification rule are determined, chip verification is performed on the design to be tested according to the macro definition rule and the configuration requirement specification rule. It should be noted that, considering the design to be tested of the multi-level complex topological structure mentioned in the embodiment of the present application, the relevant design file compiling option configuration part includes two aspects, namely, on one hand, the design file of the current development verification level and on the other hand, the excitation source module of the top-level boundary signal of the current verification level, so as to ensure that the level can still accept input excitation from the testbench top after passing through multiple levels. The implementation of command code in a specific TCL (Tool Command Language, a scripting language for interpretation execution) script is shown in fig. 9.

As can be seen, formal verification uses an attribute specification language to define system module requirements, such as SVAs (System Verilog Assertion, assertions), creates a relevant mathematical model, uses a checker to compare the system requirements to the created mathematical model, and monitors whether the requirements are met. The constructed mathematical model can be used for verifying DUT logic to be tested more perfectly, and can be used for carrying out error checking on the design, so that the visibility of a design module is improved, and the verification of the code coverage rate of the design module is improved. The embodiment of the application describes a formal platform construction, excitation generation and the like in the chip verification process of the design to be tested with the strong logic multi-level complex topological structure; and secondly involves problems and solutions involved in the complex structure verification process. In addition, for the design module capable of resetting excitation by using a cross-level clock among a plurality of internal hierarchical structures, compiling including but not limited to a module of a last level is added in the verification process, and the creation of a system model is performed on the basis of ensuring traceability of excitation sources of a current verification level.

Correspondingly, the embodiment of the application also discloses an assertion development device which is applied to the form verification platform, and referring to fig. 10, the device comprises:

A verification level determining module 11, configured to determine a design to be tested for chip verification, and determine a target level in the design to be tested to obtain a verification level; the design to be tested internally comprises a plurality of internal levels, and each internal level corresponds to a respective signal propagation rule;

a signal extraction module 12, configured to determine a target logic verification module in the verification hierarchy, and extract a target port signal in the target logic verification module;

the assertion development module 13 is configured to perform configuration constraint on the target port signal by using a configuration requirement specification rule to generate a design file, and classify and package the design file by using a macro definition rule to generate a verification file;

the chip verification module 14 is configured to bind the verification file to a verification environment, so that the form verification platform performs chip verification on the design to be tested according to the macro definition rule and the configuration requirement specification rule when compiling the verification file.

The more specific working process of each module may refer to the corresponding content disclosed in the foregoing embodiment, and will not be described herein.

It can be seen that, by the above scheme of the present embodiment, the application to the formal verification platform includes: determining a design to be tested for chip verification, and determining a target level in the design to be tested to obtain a verification level; the design to be tested internally comprises a plurality of internal levels, and each internal level corresponds to a respective signal propagation rule; determining a target logic verification module in the verification hierarchy and extracting a target port signal in the target logic verification module; configuring and restraining the target port signal by utilizing a configuration requirement standard rule to generate a design file, and classifying and packaging the design file by utilizing a macro definition rule to generate a verification file; and binding the verification file into a verification environment, so that the form verification platform performs chip verification on the design to be tested according to the macro definition rule and the configuration requirement specification rule when compiling the verification file.

Further, the embodiment of the present application further discloses an electronic device, and fig. 11 is a block diagram of an electronic device 20 according to an exemplary embodiment, where the content of the figure is not to be considered as any limitation on the scope of use of the present application.

Fig. 11 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. Wherein the memory 22 is configured to store a computer program that is loaded and executed by the processor 21 to implement the relevant steps in the assertion development method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in the present embodiment may be a computer.

In this embodiment, the power supply 23 is configured to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and the communication protocol to be followed is any communication protocol applicable to the technical solution of the present application, which is not specifically limited herein; the input/output interface 25 is used for acquiring external input data or outputting external output data, and the specific interface type thereof may be selected according to the specific application requirement, which is not limited herein.

The memory 22 may be a carrier for storing resources, such as a read-only memory, a random access memory, a magnetic disk, or an optical disk, and the resources stored thereon may include an operating system 221, a computer program 222, data 223, and the like, and the data 223 may include various data. The storage means may be a temporary storage or a permanent storage.

The operating system 221 is used for managing and controlling various hardware devices on the electronic device 20 and computer programs 222, which may be Windows Server, netware, unix, linux, etc. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the assertion development method performed by the electronic device 20 disclosed in any of the foregoing embodiments.

Further, embodiments of the present application disclose a computer readable storage medium, where the computer readable storage medium includes random access Memory (Random Access Memory, RAM), memory, read-Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, magnetic disk, or optical disk, or any other form of storage medium known in the art. Wherein the computer program, when executed by a processor, implements the aforementioned assertion development method. For specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.

The steps of a method or algorithm for developing assertions described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above description of the present invention provides a method for developing assertion, a method for verifying chip, a device, equipment and a medium, and specific examples are applied to illustrate the principle and implementation of the present invention, and the description of the above examples is only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims

1. An assertion development method, which is applied to a formal verification platform, comprising:

2. The assertion development method of claim 1, wherein the determining a design under test for chip verification includes:

3. The assertion development method of claim 1, wherein acquiring the configuration requirement specification rule includes:

4. The assertion development method of claim 1, wherein the determining a target logical verification module in the verification hierarchy and extracting a target port signal in the target logical verification module includes:

5. The assertion development method of claim 4, after the determining a target logic verification module in the verification hierarchy, further comprising:

6. The assertion development method according to any one of claims 1 to 5, characterized in that the determining a target logic verification module in the verification hierarchy and extracting a target port signal in the target logic verification module includes:

7. A chip verification method, which is applied to a form verification platform, comprising:

acquiring a verification file bound in a verification environment of the form verification platform; the verification document is a verification document obtained by using the assertion development method of any one of claims 1 to 6;

8. An assertion development device, applied to a formal verification platform, comprising:

9. An electronic device comprising a processor and a memory; wherein the memory is for storing a computer program to be loaded and executed by the processor to implement the method of any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program; wherein the computer program when executed by a processor implements the method of any of claims 1 to 7.