JP7272919B2 - self-diagnostic circuit - Google Patents

Description

The invention disclosed in this specification relates to a self-diagnostic circuit (so-called BIST [built in self test] circuit) mounted on a semiconductor device (such as an in-vehicle LSI).

2. Description of the Related Art Conventionally, various self-diagnostic circuits have been proposed for use in mass production tests of semiconductor devices and failure diagnosis at startup or during operation.

As an example of conventional technology related to the above, Patent Document 1 can be cited.

JP 2016-176843 A

In recent years, in the field of in-vehicle LSIs, compliance with the ISO26262 standard, which defines processes for achieving vehicle functional safety, has become essential. Fault diagnosis used as a safety mechanism is very important to achieve functional safety of vehicles. A self-diagnostic circuit is often used as one of these failure diagnosis methods, but the ISO 26262 standard defines the failure coverage that must be achieved depending on the magnitude of the impact of the failure.

FIG. 13 is a diagram showing SPFM [single point fault metrics] and LFM [latent fault metrics] set for each ASIL [automotive safety integrity] level.

Although SPFM and LFM are not the fault coverage of the self-diagnostic circuit itself, they are indices that greatly depend on the fault coverage, and target values are set for each ASIL level.

The ASIL level is an index indicating the severity of the impact when the system becomes unsafe. degree increases. Therefore, the D level (ASIL D), which has the highest degree of severity, inevitably requires the highest fault coverage.

On the other hand, failure detection time is also required for each system, and an in-vehicle LSI must meet this requirement. Therefore, a conventional semiconductor device is equipped with a self-diagnostic circuit that can satisfy the failure detection rate and failure detection time required by the system.

However, in conventional self-diagnostic circuits, the fault coverage and fault detection time are determined in advance before mounting on the semiconductor device (at the time of designing the self-diagnostic circuit), and the fault coverage and fault detection time are determined after mounting on the semiconductor device. It was not possible to adjust the detection time at all. Therefore, the application of the semiconductor device is basically limited to the use in the system assumed in advance.

In view of the above-described problems found by the inventors of the present application, the invention disclosed in the present specification is a self-diagnostic device capable of arbitrarily adjusting the fault detection rate and fault detection time even after being mounted on a semiconductor device. The purpose is to provide a circuit.

The self-diagnostic circuit disclosed in this specification includes a scan chain incorporated in a test target circuit, a test pattern generation unit that sequentially generates test patterns and inputs them to the scan chain, and the number of patterns of the test pattern. and a control unit that variably sets the (first configuration).

In the self-diagnostic circuit having the first configuration, the control unit includes a register for storing rewritable set values and a counter for counting the number of test patterns. The configuration (second configuration) may be such that the test pattern generation unit is controlled to sequentially generate the test patterns until the number reaches the set value.

In the self-diagnostic circuit having the first or second configuration, the test pattern generator includes a pseudorandom number pattern generator that sequentially generates a pseudorandom number pattern, and outputs the pseudorandom number pattern as the test pattern. Alternatively, the test pattern may be generated from the pseudo-random number pattern (third configuration).

Further, in the self-diagnostic circuit having the third configuration, the test pattern generation section further includes a weighting processing section for weighting the pseudo-random number pattern according to an additional weight (fourth configuration). good.

Further, in the self-diagnostic circuit having the fourth configuration, the control section controls the weighting processing section so as to switch the additional weight during a scan test using the pseudorandom number pattern (fifth configuration). configuration).

Further, in the self-diagnostic circuit having any one of the third to fifth configurations, the test pattern generation unit includes a pattern development unit that sequentially develops the encoded additional patterns, and a pseudo-random number pattern and the additional pattern. a selector for outputting one as a selected pattern, and outputting the selected pattern as the test pattern or generating the test pattern from the selected pattern (sixth configuration).

Further, in the self-diagnostic circuit having the sixth configuration, the control unit sets the pseudo-random number pattern so as to perform the scan test using the additional pattern after performing the scan test using the pseudo-random number pattern. A configuration (seventh configuration) that controls the generator and the selector is preferable.

Further, the self-diagnostic circuit having any one of the first to seventh configurations includes a test response compression unit that compresses the test response pattern output from the scan chain to generate a signature, and the signature and the expected value. and a comparison unit for comparison, wherein the control unit variably sets both the number of patterns of the test pattern and the expected value (eighth configuration).

Further, the semiconductor device disclosed in this specification has a configuration (ninth configuration) including a self-diagnostic circuit having any one of the first to eighth configurations and the circuit to be tested. .

Further, the semiconductor device disclosed in this specification includes a self-diagnostic circuit having the fourth or sixth configuration, the circuit to be tested, and an external interface for receiving an external input of the additional weight or the additional pattern. and a face (tenth configuration).

According to the invention disclosed in this specification, it is possible to provide a self-diagnostic circuit that can arbitrarily adjust the fault detection rate and fault detection time even after being mounted on a semiconductor device.

Diagram showing the basic configuration of the self-diagnostic circuit Diagram showing a configuration example of a pseudo-random number pattern generator Diagram showing an overview of the scan test The figure which shows 1st Embodiment of a self-diagnostic circuit FIG. 4 is a diagram showing an example of self-diagnostic operation in the first embodiment; A diagram showing an example of a failure that is difficult to detect with a pseudo-random number pattern The figure which shows 2nd Embodiment of a self-diagnostic circuit A diagram showing an example of self-diagnostic operation in the second embodiment. The figure which shows 3rd Embodiment of a self-diagnostic circuit A diagram showing an example of self-diagnostic operation in the third embodiment. Diagram showing an example of introducing an external interface Diagram showing the appearance of the vehicle Diagram showing SPFM and LFM set for each ASIL level

<Self-diagnosis circuit (basic configuration)>
FIG. 1 is a diagram showing the basic configuration of a self-diagnostic circuit. A self-diagnostic circuit 10 and a circuit under test (CUT [circuit under test]) 20 are mounted (integrated) on the semiconductor device 1 of this configuration example.

The self-diagnostic circuit 10 is a subject that performs a scan test of the test target circuit 20 when the semiconductor device 1 is activated or in operation (or during a mass production test of the semiconductor device 1). It has a unit 12 , a test response compactor 13 (so-called TRC [test response compactor]), a comparator 14 , and a controller 15 .

A scan chain 11 consists of a plurality of scan flip-flops 21 . The scan flip-flop 21 is a sequential circuit that replaces all (or part of) the flip-flops incorporated in the circuit under test 20, and is serially connected during the scan test (particularly during scan-in and scan-out operations). to form a shift register. As the number of scan chains 11 increases, the number of flip-flops per chain (=bit length of the shift register) decreases, so the time required for the scan test (and thus the failure detection time) can be shortened.

The test pattern generator 12 includes a pseudo random number pattern generator 12 a (so-called PRPG [pseudo random pattern generator]) and a phase shifter 12 b , sequentially generates test patterns S 1 and inputs them to the scan chain 11 .

The pseudorandom number pattern generation unit 12a generates at least one system (a plurality of systems in this configuration example) of the pseudorandom number pattern S0. A linear feedback shift register (so-called LFSR [linear feedback shift register]), for example, is suitable for the pseudo-random number pattern generator 12a.

The phase shifter 12b generates a test pattern S1 in which the correlation between adjacent systems is reduced by performing a predetermined logical operation (for example, an exclusive OR operation) on the pseudorandom number patterns S0 of multiple systems. If the pseudo-random number pattern S0 (and the test pattern S1) is one system, the phase shifter 12b can be omitted and the pseudo-random number pattern S0 can be directly output as the test pattern S1.

The test response compression unit 13 compresses the test response pattern S2 output from the scan chain 11 to generate a signature S3. As the test response compression unit 13, for example, a multiple input shift register (so-called MISR [multiple input shift register]) is suitable.

The comparison unit 14 determines whether or not the circuit under test 20 is faulty by comparing the signature S3 with an expected value (=corresponding to a signature that should be obtained when there is no fault in the circuit under test 20).

The control unit 15 controls the units 11 to 14 as a whole.

<Pseudo-random number pattern generator>
FIG. 2 is a diagram showing a configuration example of the pseudo-random number pattern generator 12a. The pseudo-random number pattern generator 12a of this configuration example includes D flip-flops a1 to a5 and an XOR gate a6.

The data input terminal (D) of the D flip-flop a1 is connected to the output terminal of the XOR gate a6. The output terminal (Q) of the D flip-flop a1 is connected to the data input terminal (D) of the D flip-flop a2 as the output terminal of the logic signal X1. The output terminal (Q) of the D flip-flop a2 is connected to the data input terminal (D) of the D flip-flop a3 as the output terminal of the logic signal X2. The output terminal (Q) of the D flip-flop a3 is connected to the data input terminal (D) of the D flip-flop a4 and the first input terminal of the XOR gate a6 as the output terminal of the logic signal X3. The output terminal (Q) of the D flip-flop a4 is connected to the data input terminal (D) of the D flip-flop a5 as the output terminal of the logic signal X4. The output terminal (Q) of the D flip-flop a5 is connected to the second input terminal of the XOR gate a6 as the output terminal of the logic signal X5.

The D flip-flops a1 to a5 and the XOR gate a6 connected in this manner function as a 5-bit LFSR, and generate a pseudo-random number pattern S0 (=X1X2X3X4X5) represented by the feedback polynomial X ⁵ +X ³ +1 (31 periods). It is generated sequentially in synchronization with the clock input.

The initial value of the pseudorandom number pattern S0 is determined by the seed data SEED[4:0] (=initial output values of the D flip-flops a1 to a5).

In this figure, a 5-bit LFSR is used as an example to simplify the explanation, but the actual pseudo-random number pattern generator 12a is configured with an LFSR with a much larger number of bits than in the example. Therefore, many pseudo-random number patterns S0 can be generated with a small amount of data (only seed data SEED).

<Scan test>
FIG. 3 is a diagram showing an outline of a scan test. As shown in the figure, a test target circuit 20 for which the presence or absence of a failure is determined by a scan test includes a scan flip-flop 21 and a combinational logic circuit 22 (so-called CLC [combinational logic circuit]).

The scan flip-flops 21 each include a D flip-flop 211 and a multiplexer 212 (see callout box).

A data input terminal (D) of the D flip-flop 211 receives the output signal of the multiplexer 212 . A clock signal CK is input to the clock input terminal (>) of the D flip-flop 211 . The latch signal output from the output terminal (Q) of the D flip-flop 211 is output to the combinational logic circuit 22 or the outside of the circuit as the data output signal DO, or as the scan output signal SO (and the test response pattern S2). It is output to the subsequent scan flip-flop 21 or test response compression section 13 .

For example, the multiplexer 212 selects the data input signal DI when the scan enable signal SE is at low level (=logical level in normal mode), and selects the data input signal DI when the scan enable signal SE is at high level (=logical level in scan mode). The scan input signal SI is selected when . The data input signal DI is a signal input from the outside of the circuit or from the combinational logic circuit 22 . On the other hand, the scan input signal SI is the test pattern S1 generated by the test pattern generator 12 or the scan output signal SO output from the scan flip-flop 21 in the previous stage.

In the scan test of the test target circuit 20, three operation states of (1) scan-in operation, (2) capture operation, and (3) scan-out operation are sequentially repeated. Each operating state will be described below.

First, in the scan-in operation, the test target circuit 20 is in scan mode (SE=H). At this time, a plurality of scan flip-flops 21 are serially connected to form a series of scan chains 11 (=shift registers). A test pattern S1 is serially input to the scan chain 11 in synchronization with the clock signal CK.

Next, in the capture operation, the circuit under test 20 is put into the normal mode (SE=L), and the normal operation of the combinational logic circuit 22 is performed. At this time, each of the plurality of scan flip-flops 21 captures the output result of the combinational logic circuit 22 corresponding to the test pattern S1 in synchronization with the clock signal CK.

Finally, in the scan-out operation, the circuit under test 20 is put into the scan mode (SE=H) again, and the scan chain 11 described above is re-formed. From the scan chain 11, the test response pattern S2 (=the output result of the combinational logic circuit 22 corresponding to the test pattern S1) is serially output in synchronization with the clock signal CK.

By comparing the test response pattern S2 (or signature S3) thus generated with the expected value, it is possible to determine whether or not the circuit under test 20 is faulty.

In the following, a novel embodiment is proposed in which the fault detection rate and fault detection time of the self-diagnostic circuit 10 can be arbitrarily adjusted even after the self-diagnostic circuit 10 is mounted on the semiconductor device 1. FIG.

<Self-diagnostic circuit (first embodiment)>
FIG. 4 is a diagram showing a first embodiment of the self-diagnostic circuit 10. As shown in FIG. The self-diagnostic circuit 10 of the present embodiment is based on FIG. 1 and has a new functional block added to the control section 15 .

More specifically, the control unit 15 includes a pattern number register 151, a pattern number counter 152, and an expected value register 153 as means for variably setting the pattern number of the test pattern S1.

The pattern number register 151 stores the pattern number of the test pattern S1 (=pseudorandom number pattern S0) used in the scan test. Note that the set value of the pattern number register 151 can be arbitrarily rewritten even after the self-diagnostic circuit 10 is mounted on the semiconductor device 1 .

The pattern number counter 152 counts the number of test patterns S1 (=pseudo-random number pattern S0) actually generated in the scan test.

The expected value register 153 stores the expected value to be compared with the signature S3 at the end of the scan test. Note that the set value of the expected value register 153 can be arbitrarily rewritten even after the self-diagnostic circuit 10 is mounted on the semiconductor device 1 .

As described above, when the pattern number register 151 is used to change the pattern number of the test pattern S1, the test response pattern S2 changes, so the signature S3 also changes. Therefore, it is preferable that the control unit 15 includes an expected value register 153 in addition to the pattern number register 151 so that both the number of test patterns and the expected value can be variably set.

In addition, in this figure, in order to simplify the explanation, the case where the scan chain 11 is one system is exemplified. In this case, the test pattern generator 12 outputs the pseudorandom number pattern S0 generated by the pseudorandom number pattern generator 12a as it is as the test pattern S1. However, the scan chain 11 may have multiple systems. In that case, the test pattern S1 is generated from the pseudo-random number pattern S0 through the phase shifter 12b, as in FIG.

FIG. 5 is a diagram showing an example of the self-diagnosis operation in the first embodiment, in which the self-diagnosis start signal BIST_START, the failure detection signal BIST_FAIL, and the count value CNT of the pattern number counter 152 are depicted in order from the top. .

In this figure, the set value of the pattern number register 151 (=the number of test patterns S1 generated by the LFSR) is m.

When a pulse is generated in the self-diagnosis start signal BIST_START, the count value CNT is initialized to 0 and the scan test using the first test pattern S1 (=PTN1) is started. When this scan test is completed, the count value CNT is incremented by one (0→1), and the scan test using the second test pattern S1 (=PTN2) is started.

After the operation similar to the above is repeated m times, when the scan test using the mth test pattern S1 (=PTNm) is completed, the count value CNT reaches the set value m. At this point, the series of scan tests is completed, and the logic level of the failure detection signal BIST_FAIL is determined (for example, normal=L, failure=H).

In this manner, the control unit 15 controls the test pattern generation unit 12 so as to sequentially generate the test patterns S1 until the number of test patterns S1 reaches the set value m. That is, the control unit 15 has a function of variably setting the pattern number of the test pattern S1 in accordance with the set value m of the pattern number register 151 .

As the number of test patterns S1 is increased, the fault detection time becomes longer, but the fault detection rate can be increased. Conversely, as the number of patterns in the test pattern S1 is reduced, the fault coverage decreases, but the fault detection time can be shortened.

That is, according to the self-diagnostic circuit 10 of the present embodiment, not only before mounting on the semiconductor device 1 but also after mounting on the semiconductor device 1, the fault detection rate and Any failure detection time can be set. Therefore, it is possible to greatly expand the applications of the semiconductor device 1 .

For example, when a high ASIL level (for example, ASIL D) needs to be handled, it is preferable to increase the number of test patterns S1 so as to give priority to improving the fault detection rate over shortening the fault detection time. Conversely, if it is sufficient to deal with a low ASIL level (for example, ASIL B), the number of patterns in the test pattern S1 may be reduced to give priority to shortening the fault detection time even if the fault coverage is somewhat sacrificed. can.

<Problems with pseudo-random number patterns>
As described above, the self-diagnostic circuit 10 that performs the scan test using the pseudo-random number pattern S0 does not need to store the test pattern S1, so the area overhead is small. However, there are some failures that are difficult to detect with the pseudo-random number pattern S0, and it is not always easy to detect them in a practical time.

FIG. 6 is a diagram showing an example of a failure that is difficult to detect with the pseudorandom number pattern S0. For example, consider a case where the combinational logic circuit 22 is a multi-input (five-input in this figure) AND gate and a stuck-at-1 fault occurring in one of its input terminals is detected.

In order to detect such a stuck-at-1 fault, it is necessary to input a specific test pattern S1 (=“11110”) and check the output signal of the combinational logic circuit 22 (=AND gate). . That is, when the specific test pattern S1 is input, the output signal of the combinational logic circuit 22 becomes "0" when normal and becomes "1" when abnormal, so that the stuck-at-1 fault can be detected. . On the other hand, when a test pattern S1 other than the above is input, the logic level of the output signal is "1" even when it is normal, and conversely, it is "0" even when it is abnormal. cannot be detected.

Of course, if all the test patterns S1 are input, it is possible to detect stuck-at-1 faults as described above. isn't it.

In the following, a second embodiment and a third embodiment are proposed, which are capable of quickly detecting failures that are difficult to detect with the pseudo-random number pattern S0.

<Self-diagnostic circuit (second embodiment)>
FIG. 7 is a diagram showing a second embodiment of the self-diagnostic circuit 10. As shown in FIG. The self-diagnostic circuit 10 of the present embodiment is based on the first embodiment (FIG. 4) described above, and new functional blocks are added to the test pattern generation section 12 and the control section 15, respectively.

More specifically, the test pattern generator 12 includes a weighting processor 12c in addition to the pseudo-random number pattern generator 12a.

The weighting processing unit 12c generates a test pattern S1 by weighting the pseudo-random number pattern S0 according to the additional weight WT. Note that the additional weight WT is set so that a predetermined bit value in the test pattern S1 is likely to be "0" or "1", in other words, so that a specific test pattern S1 (see FIG. 6) is likely to appear. This is a set value for weighting the occurrence probability of the random number pattern S0. As the additional weight WT, a weight of zero (=set value for not weighting the pseudo-random number pattern S0) can also be supplied.

In addition to the pattern number register 151 , the pattern number counter 152 , and the expected value register 153 , the control section 15 includes a pattern number register 154 and a weight switching function section 155 .

The pattern number register 154 stores the pattern number of the test pattern S1 (=pseudo-random number pattern S0) corresponding to the switching timing of the additional weight WT. The set value of the pattern number register 154 can be arbitrarily rewritten even after the self-diagnostic circuit 10 is mounted on the semiconductor device 1, like the set value of the pattern number register 151 and the set value of the expected value register 152. be.

The weight switching function unit 155 controls the weighting processing unit 12c to switch the additional weight WT during the scan test using the pseudorandom number pattern S0 according to the set value of the pattern number register 154. FIG.

FIG. 8 is a diagram showing an example of the self-diagnosis operation in the second embodiment, in which the self-diagnosis start signal BIST_START, the failure detection signal BIST_FAIL, and the count value CNT of the pattern number counter 152 are depicted in order from the top. .

In this figure, the set value of the pattern number register 151 (=the number of patterns of the test pattern S1 generated by the LFSR) is set to m, and the set value of the pattern number register 154 (=the pattern corresponding to the switching timing of the additional weight WT). number) are i, j, ... (where i < j < ... ≤ m).

In the case of this figure, first, from the start of the scan test using the first test pattern S1 (=PTN1) to the completion of the scan test using the i-th test pattern S1 (=PTNi) During this period, that is, until the count value CNT reaches the set value i, the weighting process with the additional weight WT1 is performed.

After that, when the count value CNT reaches the set value i, the additional weight WT is switched (WT1→WT2) until the scan test using the j-th test pattern S1 (=PTNj) is completed. That is, the weighting process with the additional weight WT2 is performed until the count value CNT reaches the set value j.

After that, while repeating the switching process of the additional weight WT, when the count value CNT reaches the set value m, the above series of scan tests are all completed.

In this way, if the pseudo-random number pattern S0 is weighted arbitrarily to generate the test pattern S1, the number of patterns in the test pattern S1 is not increased unnecessarily, and faults that are difficult to detect with the pseudo-random number pattern S0 can be detected. can be detected quickly.

In the above, an example of sequentially switching a plurality of additional weights WT1, WT2, .

<Self-diagnostic circuit (third embodiment)>
FIG. 9 is a diagram showing a third embodiment of the self-diagnostic circuit 10. As shown in FIG. The self-diagnostic circuit 10 of the present embodiment is based on the first embodiment (FIG. 4) described above, and new functional blocks are added to the test pattern generation section 12 and the control section 15, respectively.

More specifically, the test pattern generation unit 12 includes a pattern expansion unit 12d and a selector 12e in addition to the pseudorandom number pattern generation unit 12a.

The pattern expansion unit 12d sequentially expands the encoded additional patterns TP and sequentially outputs them to the selector 12e. The additional pattern TP may be automatically generated using ATPG [automatic test pattern generator].

The selector 12e outputs one of the pseudo-random number pattern S0 and the additional pattern TP (expanded) as a selection pattern (test pattern S1 in this figure). When the scan chain 11 has a plurality of systems, the test pattern S1 is generated from the selection pattern of the selector 12e via the phase shifter 12b, as in FIG.

In addition to the pattern number register 151 , the pattern number counter 152 , and the expected value register 153 , the control section 15 includes a pattern number register 156 and a mode switching function section 157 .

The pattern number register 156 stores the number of test patterns S1 (=additional pattern pattern TP) generated using ATPG. The set value of the pattern number register 156 can be arbitrarily rewritten even after the self-diagnostic circuit 10 is mounted on the semiconductor device 1, like the set value of the pattern number register 151 and the set value of the expected value register 152. be.

The mode switching function unit 157 controls the pseudorandom number pattern generation unit 12a and the selector 12e so that the scan test using the pseudorandom number pattern S0 is performed and then the scan test using the additional pattern TP is performed.

FIG. 10 is a diagram showing an example of the self-diagnosis operation in the third embodiment, in which the self-diagnosis start signal BIST_START, the failure detection signal BIST_FAIL, and the count value CNT of the pattern number counter 152 are depicted in order from the top. .

In this figure, the set value of the pattern number register 151 (=the number of test patterns S1 generated by LFSR) is m, and the set value of the pattern number register 156 (=the number of test patterns S1 generated by ATPG) is m. number) is n.

In the case of this figure, first, the selector 12e enters the first mode (MODE 1) in which the pseudorandom number pattern S0 is output as the test pattern S1 until the count value CNT reaches the set value m. Therefore, in the first mode (MODE1), scan tests using test patterns S1 (=PTN1 to PTNm) generated by the LFSR are sequentially performed.

When the count value CNT reaches the set value m, the selector 12e switches to the second mode (MODE2) in which the additional pattern TP is output as the test pattern S1. Therefore, in the second mode (MODE2), scan tests using test patterns S1 (=PTN1 to PTNn) generated by ATPG are sequentially performed.

After that, when the count value CNT reaches the set value (m+n), the above series of scan tests are all terminated. Incidentally, as indicated by parentheses attached to the count value CNT in the figure, the count value CNT may be once reset to a zero value when it reaches the set value m. In that case, when the count value CNT reaches the set value n due to the increment after the reset, the above series of scan tests are all terminated.

As described above, the self-diagnostic circuit 10 of the third embodiment first performs a scan test using the pseudo-random number pattern S0, and then performs a scan test using the additional pattern TP for failures that are difficult to detect with the pseudo-random number pattern S0. It is configured to be detected by By adopting such a configuration, it is possible to quickly detect failures that are difficult to detect with the pseudo-random number pattern S0 without unnecessarily increasing the number of test patterns S1.

In the above description, the configuration in which both the pattern number m of the test pattern S1 generated by the LFSR and the pattern number n of the test pattern S1 generated by the ATPG are variably set was taken as an example. One of the numbers m and n may be a fixed value.

Also, by combining with the second embodiment (FIG. 7) described above, it is possible to apply any weighting process to the pseudo-random number pattern S0 in the first mode (MODE 1).

<Introduction of external interface>
In the above-described first embodiment (FIG. 4), the test pattern S1 is automatically generated using the pseudo-random number pattern generator 12a (for example, LFSR). No additional pattern needs to be supplied from outside the device 1 .

On the other hand, in the second embodiment (FIG. 7) in which the pseudo-random number pattern S0 is weighted, and in the third embodiment (FIG. 9) using ATPG, the additional weight WT and the additional pattern TP are supplied from outside the semiconductor device 1, respectively. must be supplied.

For example, the additional pattern TP can be stored inside the semiconductor device 1 . However, in that case, all of the additional patterns TP that can be set must be stored in advance, assuming the maximum number of patterns for the scan test by ATPG. Therefore, when the number of additional patterns TP actually set is small, the area overhead increases. To avoid this, it is effective to introduce an external interface.

FIG. 11 is a diagram showing an introduction example of an external interface. The semiconductor device 1 of this configuration example has, in addition to the self-diagnostic circuit 10 described so far, an external interface 30 that receives an external input of the additional weight WT or the additional pattern TP.

Note that when the scan test is repeatedly performed while switching a plurality of additional weights WT or additional patterns PT, the external interface 30 does not necessarily need to receive all the additional weights WT or additional patterns PT at once, and the scan test is performed. The additional weights WT or the additional patterns PT may be received sequentially as many times as necessary.

In this case, the specifications of the external interface 30 are not particularly limited except that the additional weight WT or the additional pattern PT used in the scan test can be supplied before the scan test is started.

In this way, by implementing a mechanism for sequentially supplying additional weights WT or additional patterns TP from the outside of the semiconductor device 1, the area overhead can be eliminated, and an optimum system can be constructed.

<Application to vehicles>
FIG. 12 is an external view showing one configuration example of the vehicle X. As shown in FIG. The vehicle X of this configuration example is equipped with various electronic devices X11 to X18 that operate with power supplied from a battery (not shown). Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual ones for convenience of illustration.

The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

The electronic device X12 is a lamp control unit that controls lighting and extinguishing of HID [high intensity discharged lamps] and DRL [daytime running lamps].

The electronic device X13 is a transmission control unit that performs control related to the transmission.

The electronic device X14 is a braking unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that drives and controls door locks, security alarms, and the like.

Electronic device X16 includes wipers, electric door mirrors, power windows, dampers (shock absorbers), electric sunroofs, electric seats, and other electronic devices built into vehicle X at the factory shipment stage as standard equipment or manufacturer options. is.

The electronic device X17 is an electronic device arbitrarily mounted on the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device having a high withstand voltage motor, such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

The semiconductor device 1 described above can be incorporated in any of the electronic devices X11 to X18 as an in-vehicle LSI.

<Other Modifications>
In addition to the above embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is not limited to the above-described embodiments. It is to be understood that a range and equivalents are meant to include all changes that fall within the range.

INDUSTRIAL APPLICABILITY The invention disclosed in this specification can be used, for example, in a self-diagnostic circuit mounted on a vehicle-mounted semiconductor device.

1 Semiconductor device (in-vehicle LSI)
10 self-diagnostic circuit 11 scan chain 12 test pattern generator 12a pseudorandom number pattern generator 12b phase shifter 12c weighting processor 12d pattern expansion unit 12e selector 13 test response compression unit 14 comparison unit 15 control unit 151 pattern number register (for LFSR test )
152 Pattern number counter 153 Expected value register 154 Pattern number register (for weight switching)
155 weight switching function unit 156 pattern number register (for ATPG test)
157 Mode switching function part 20 Test target circuit 21 Scan flop flop 211 D flip flop 212 Multiplexer 22 Combinational logic circuit 30 External interface a1 to s5 D flip flop a6 XOR gate X Vehicle X11 to X18 Electronic equipment

Claims (8)

a scan chain embedded in the circuit under test;
a test pattern generator that sequentially generates test patterns and inputs them to the scan chain;
a control unit that variably sets the number of test patterns;
has
The test pattern generation unit includes a pseudorandom number pattern generation unit that sequentially generates pseudorandom number patterns, a pattern expansion unit that sequentially expands encoded additional patterns, and one of the pseudorandom number pattern and the additional pattern as a selection pattern. and a selector for outputting, which outputs the selected pattern as the test pattern, or generates the test pattern from the selected pattern,
The self-diagnostic circuit, wherein the control unit controls the pseudorandom number pattern generation unit and the selector so as to perform a scan test using the pseudorandom number pattern and then perform a scan test using the additional pattern. The control unit includes a register that stores rewritable set values and a counter that counts the number of test patterns, and sequentially generates the test patterns until the number of test patterns reaches the set value. 2. The self-diagnostic circuit according to claim 1 , wherein said test pattern generator is controlled so as to 3. The self-diagnostic circuit according to claim 1, wherein said test pattern generator further includes a weighting processor for weighting said pseudo-random number pattern according to an additional weight. 4. The self-diagnosis circuit according to claim 3, wherein said control section controls said weighting processing section so as to switch said additional weight during a scan test using said pseudo-random number pattern. a test response compression unit that compresses the test response pattern output from the scan chain to generate a signature;
a comparison unit that compares the signature with an expected value;
further having
5. The self-diagnosis circuit according to claim 1, wherein said control unit variably sets both the number of patterns of said test patterns and said expected value. a self-diagnostic circuit according to any one of claims 1 to 5 ;
the circuit under test;
A semiconductor device having 7. The semiconductor device according to claim 6, further comprising an external interface for receiving an external input of said additional pattern. A self-diagnostic circuit according to claim 3 or 4 ;
the circuit under test;
an external interface that receives an external input of the additional weight or the additional pattern;
A semiconductor device having

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