JP2022151587A5 - - Google Patents
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- Publication number
- JP2022151587A5 JP2022151587A5 JP2022004048A JP2022004048A JP2022151587A5 JP 2022151587 A5 JP2022151587 A5 JP 2022151587A5 JP 2022004048 A JP2022004048 A JP 2022004048A JP 2022004048 A JP2022004048 A JP 2022004048A JP 2022151587 A5 JP2022151587 A5 JP 2022151587A5
- Authority
- JP
- Japan
- Prior art keywords
- fin
- wall
- integrated circuit
- circuit structure
- gate endcap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002070 nanowire Substances 0.000 claims 11
- 239000004020 conductor Substances 0.000 claims 8
- 238000002955 isolation Methods 0.000 claims 3
- 230000008878 coupling Effects 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 2
- 238000005859 coupling reaction Methods 0.000 claims 2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2024228683A JP2025069125A (ja) | 2021-03-24 | 2024-12-25 | キャップが低減された自己整合ゲートエンドキャップ（ｓａｇｅ）アーキテクチャ |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/211,751 | 2021-03-24 | ||
| US17/211,751 US20220310818A1 (en) | 2021-03-24 | 2021-03-24 | Self-aligned gate endcap (sage) architectures with reduced cap |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024228683A Division JP2025069125A (ja) | 2021-03-24 | 2024-12-25 | キャップが低減された自己整合ゲートエンドキャップ（ｓａｇｅ）アーキテクチャ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2022151587A JP2022151587A (ja) | 2022-10-07 |
| JP2022151587A5 true JP2022151587A5 (enExample) | 2024-10-30 |
Family
ID=83365082
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2022004048A Pending JP2022151587A (ja) | 2021-03-24 | 2022-01-14 | キャップが低減された自己整合ゲートエンドキャップ（ｓａｇｅ）アーキテクチャ |
| JP2024228683A Pending JP2025069125A (ja) | 2021-03-24 | 2024-12-25 | キャップが低減された自己整合ゲートエンドキャップ（ｓａｇｅ）アーキテクチャ |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024228683A Pending JP2025069125A (ja) | 2021-03-24 | 2024-12-25 | キャップが低減された自己整合ゲートエンドキャップ（ｓａｇｅ）アーキテクチャ |
Country Status (2)
| Country | Link |
|---|---|
| US (3) | US20220310818A1 (enExample) |
| JP (2) | JP2022151587A (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12170203B2 (en) * | 2021-07-23 | 2024-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit with conductive via formation on self-aligned gate metal cut |
| US20230180451A1 (en) * | 2021-12-03 | 2023-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Structure With Source/Drain Contact Plugs And Method For Forming The Same |
| US20230197826A1 (en) * | 2021-12-21 | 2023-06-22 | Christine RADLINGER | Self-aligned gate endcap (sage) architectures with improved cap |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11296079B2 (en) * | 2017-12-28 | 2022-04-05 | Intel Corporation | PMOS and NMOS contacts in common trench |
| US11329138B2 (en) * | 2018-04-02 | 2022-05-10 | Intel Corporation | Self-aligned gate endcap (SAGE) architecture having endcap plugs |
-
2021
- 2021-03-24 US US17/211,751 patent/US20220310818A1/en active Pending
-
2022
- 2022-01-14 JP JP2022004048A patent/JP2022151587A/ja active Pending
-
2024
- 2024-09-27 US US18/900,116 patent/US20250022936A1/en active Pending
- 2024-12-25 JP JP2024228683A patent/JP2025069125A/ja active Pending
- 2024-12-27 US US19/004,021 patent/US20250142935A1/en active Pending
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