JP2022143995A - Signal processing device, image formation apparatus and program - Google Patents

Abstract

To provide a technique which can reduce waste of a bandwidth when transmitting data to an engine side in high-speed serial communication.SOLUTION: Synchronous signals and image signals of a plurality of channels of YMCK are received and the synchronous signals and the image signals of any two or more channels of the plurality of channels are time-division multiplexed by an integration unit 15YM and output. Also, a reference signal prescribing the initiation time of communication is superimposed on the synchronous signal and output. A serial converter 16YM performs serial conversion on the reference signal and the time-division multiplexed synchronous signals and image signals and transfers them to an image output unit (engine) in the high-speed serial communication via a transmission path 18.SELECTED DRAWING: Figure 3A

Description

The present invention relates to a signal processing device, an image forming device, and a program.

Japanese Unexamined Patent Application Publication No. 2002-100000 describes an image processing apparatus that extracts different data from common data using a plurality of apparatuses having a common structure. The notification unit notifies the external device of the second identification information in the next order when the first identification information among the plurality of identification information is notified. The notification unit supplies the first identification information notified to itself to the storage unit, and the storage unit stores the supplied first identification information. The receiver and the selector extract the first data from the second data when the second data including the first data identified by the identification information stored in the storage are received. The transmitter transmits the second data received by the extractor to the external device.

JP 2016-182742 A

By the way, when an image processing unit, a video output unit, and a serial conversion unit are provided for each of a plurality of channels, data is transmitted to the engine of the image forming apparatus, and the engine receives the data to form an image. When data is sent to the engine by serial communication, the transfer is completed in a short time because the bandwidth of high-speed serial communication is relatively large, resulting in wasted bandwidth.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a technique capable of reducing wasted bandwidth when data is transmitted to an engine by high-speed serial communication.

According to the first aspect of the invention, receiving means for receiving synchronization signals and image signals of each of a plurality of channels; integration means for time-division multiplexing and integration; reference timing generation means for superimposing a reference signal defining the start time of communication on the synchronization signal and outputting it; the reference signal, the time-division multiplexed synchronization signal and and serial conversion means for serially converting an image signal and outputting the signal.

According to a second aspect of the present invention, the integrating means time-division-multiplexes a reference clock signal serving as a reference for generating the synchronizing signals of each of the plurality of channels and the image signal. 2. The signal processing apparatus according to claim 1, which operates with a transmission reference clock signal multiplied by (n is an integer equal to or greater than 2).

According to a third aspect of the present invention, the integrating means includes sampling means for sampling the synchronization signal and the image signal received by the receiving means based on the transmission reference clock signal, and a channel to be transmitted based on the reference signal. selection control means for outputting a selection signal to be selected; synchronization signal selection means for selecting a synchronization signal of a channel to be time-division multiplexed based on the selection signal from the synchronization signals of each channel sampled by the sampling means; sampling means 3. The signal processing apparatus according to claim 2, further comprising: image signal selection means for selecting an image signal of a channel to be time-division multiplexed based on said selection signal from the image signals of each channel sampled in .

According to a fourth aspect of the invention, the synchronization signal includes a line synchronization signal, a page synchronization signal, and a data enable signal, and the reference signal is superimposed on either the line synchronization signal or the page synchronization signal. , a signal processing apparatus according to any one of claims 1 to 3.

According to a fifth aspect of the invention, the integrating means time-division multiplexes and integrates the synchronizing signals and the image signals of any two or more of the plurality of channels for each line. 1. The signal processing device according to 1.

According to a sixth aspect of the present invention, the synchronizing signal includes a line synchronizing signal, and the integrating means uses different delay times for the reference line synchronizing signal as the reference signal to determine which one of the plurality of channels is selected. 6. The signal processing apparatus according to claim 5, wherein the line synchronization signals of two or more channels are time division multiplexed.

According to a seventh aspect of the present invention, the synchronization signal includes a data enable signal, and the integrating means uses different delay times from the reference line synchronization signal to select any two or more of the plurality of channels. 7. The signal processing apparatus according to claim 6, wherein the data enable signals of .

According to an eighth aspect of the present invention, there is provided separation means for receiving the serial signal output from the serial conversion means and separating it into the time-division multiplexed synchronization signal and the image signal, and time-division based on the reference signal. 8. The signal processing apparatus according to claim 1, further comprising extracting means for extracting the synchronizing signal and image signal of each channel from the multiplexed synchronizing signal and image signal.

According to a ninth aspect of the invention, there is provided the signal processing apparatus according to the eighth aspect, and forming means for forming an image on a medium based on the synchronizing signals and image signals of each channel output from the extracting means of the signal processing apparatus. and an image forming apparatus.

According to a tenth aspect of the present invention, a computer comprises receiving means for receiving synchronizing signals and image signals for each of a plurality of channels, and synchronizing signals and image signals for any two or more of the plurality of channels. Integrating means for time-division multiplexing and integrating each of the above, reference timing generation means for superimposing a reference signal defining the start time of communication on the synchronization signal and outputting it, the reference signal and the time-division multiplexed This is a program that functions as serial conversion means for serially converting and outputting the synchronizing signal and the image signal.

According to the inventions described in claims 1 to 10, it is possible to reduce wasted bandwidth when data is transmitted to the engine side by high-speed serial communication.

According to the fourth aspect of the invention, there is no need to transfer the reference signal through a separate signal line.

1 is a configuration diagram of an image forming apparatus of a comparative example; FIG. 4 is a timing chart of line synchronization signals and data enable signals in a comparative example; 2 is a configuration diagram of an image processing section (controller) in the image forming apparatus according to the embodiment; FIG. 2 is a configuration diagram of an image output unit (engine) in the image forming apparatus of the embodiment; FIG. 4 is a detailed configuration diagram of an integration unit of the embodiment; FIG. 4 is a timing chart of the embodiment; 4 is a timing chart of reference signals of the embodiment; 4 is a detailed configuration diagram of an extraction unit of the embodiment; FIG. 4 is a processing flowchart of an image processing unit (controller) according to the embodiment; 4 is a processing flowchart of an image output unit (engine) of the embodiment; It is a timing chart of a modification.

An embodiment of the present invention will be described below with reference to the drawings.

First, before describing the present embodiment, an image forming apparatus of a comparative example will be described as a premise. The configuration of the image forming apparatus is described in, for example, Japanese Patent Application Laid-Open No. 2002-200010. An image forming apparatus forms a color image on a medium such as paper by, for example, electrophotography using toners of Y (yellow), M (magenta), C (cyan), and K (black). An image forming apparatus includes an exposure control section, an LPH (LED Print Head), a photosensitive drum, and a forming section as main components.

The LPH has an LED (Light Emitting Diode) array, which is a plurality of light sources arranged in the main scanning direction, and illuminates each LED to irradiate the photosensitive drum with exposure light. The exposure control section controls the lighting timing of each LPH. The photosensitive drum is an image carrier that has a photosensitive layer and holds a latent image and a toner image formed by developing the latent image on the surface of the photosensitive layer. For example, one LPH exposes a photoreceptor drum to form a latent image that is developed with yellow (Y) toner. The photoreceptor drums are provided corresponding to the respective light sources (LPH of each color). The forming unit develops the latent image formed on the photosensitive drum exposed by the LPH of each color to form an image on the medium.

The exposure control section includes an image processing section, an image output section, and a transmission section that connects these to transmit data. The image processing unit generates image data of each color of YMCK from the image data transmitted from the external device. The image data for each color generated by the image processing section is transmitted to the image output section via the transmission section. The image output unit outputs to a medium an image in which toner images of respective colors represented by the transmitted image data of respective colors are superimposed. The transmission unit forms, for example, a data transmission path in serial communication (high-speed serial communication) conforming to the V-by-one (registered trademark) standard, and includes up to two signal lines for transmitting synchronization signals and serial data transmission lines. and a signal line for transmitting a signal.

The image processing section includes a data control section, a signal line, and a conversion section. The data control unit generates a data signal including image data of each color, a synchronization signal, and a signal including a data enable signal, and supplies these signals to the conversion unit via signal lines. The conversion section is connected to the transmission section, converts the supplied signal into a serial data signal in which a plurality of signal sequences are arranged in time series, and transfers the serial data signal to the image output section via the transmission section.

FIG. 1 shows configurations of an image processing unit and an image output unit of a comparative example. The image processing section functions as a controller, and the image output section functions as an engine.

The image processing unit includes an image processor, a video interface (IF), and a serial converter for each color to generate image data for each color of YMCK. Specifically, for Y color, an image processor 12Y, a video interface (IF) 14Y, and a serial converter 16Y are provided. Here, the suffix "Y" of the code indicates that the configuration is for Y color. For M color, it has an image processor 12M, a video interface (IF) 14M, and a serial converter 16M. For C color, an image processor 12C, a video interface (IF) 14C, and a serial converter 16C are provided. For K color, it has an image processor 12K, a video interface (IF) 14K, and a serial converter 16K. If each color of YMCK is called a channel, it can be said that channel Y is composed of image processor 12Y, video interface (IF) 14Y, and serial converter 16Y. The same is true for other channels.

The image processing section also includes a timing generator 10 . The timing generator 10 generates a page synchronizing signal PS as a vertical synchronizing signal and a line synchronizing signal LS as a horizontal synchronizing signal for each channel and outputs them to the video IFs 14Y, 14M, 14C and 14K of each channel. Specifically, the timing generator 10 generates a page synchronizing signal PS(Y) and a line synchronizing signal LS(Y) for channel Y, and outputs them to the channel Y video IF 14Y. The timing generator 10 also generates a page synchronizing signal PS(M) and a line synchronizing signal LS(M) for the channel M and outputs them to the channel M video IF 14M. The timing generator 10 also generates a page synchronizing signal PS(C) and a line synchronizing signal LS(C) for the channel C and outputs them to the channel C video IF 14C. Further, the timing generator 10 generates a page synchronizing signal PS(K) and a line synchronizing signal LS(K) for channel K, and outputs them to the channel K video IF 14K.

The video IFs 14Y, 14M, 14C, and 14K of each channel are based on the page synchronization signal PS and the line synchronization signal LS from the timing generator 10, respectively, the data signal Data indicating the image data for each channel, the page synchronization signal PS, and the line synchronization signal. A signal LS and a data enable signal DE are generated and output to the serial converter.

The serial converters 16Y, 16M, 16C, 16K of each channel convert the data signal Data, page synchronization signal PS, line synchronization signal LS, and data enable signal DE from the video IFs 14Y, 14M, 14C, 14K of each channel into serial signals. , and transferred to the image output unit via the transmission unit 18 .

The transmission unit 18 is shown as a harness in the drawing, and transmits a data signal Data, a page synchronization signal PS, and a line synchronization signal LS in serial communication (high-speed serial communication) conforming to the V-by-one (registered trademark) standard, for example. , and the data enable signal DE to the image output unit. If the page synchronization signal PS, the line synchronization signal LS, and the data enable signal DE are collectively referred to as synchronization signals, the image signal (data signal Data) and the synchronization signal are transferred to the image output section by high-speed serial communication.

The image output unit (engine) includes a deserial converter and an output unit for each color (channel) to output image data of each color of YMCK. Specifically, channel Y includes a deserial converter 20Y and an output section 22Y. Channel M includes a deserial converter 20M and an output section 22M. Channel C includes a deserial converter 20C and an output section 22C. Channel K includes a deserial converter 20K and an output section 22K.

The deserial converters 20Y, 20M, 20C, and 20K of each channel inversely convert the received serial signal into a data signal Data before serial conversion, a page synchronization signal PS, a line synchronization signal LS, and a data enable signal DE. Output to the output units 20Y, 20M, 22C, and 22K.

The output units 20Y, 22M, 22C, and 22K of each channel include an LPH lighting control unit, LPH, photosensitive drum, and forming unit. The LPH lighting control section controls the lighting timing of the LPH using the supplied data signal Data, etc., and develops the latent image formed on the photosensitive drum exposed by the LPH of each channel in the forming section and onto the medium. form an image.

In FIG. 2, a data signal Data, a page synchronization signal PS, a line synchronization signal LS, and a data enable signal DE are sent to an image output unit through serial communication (high-speed serial communication) conforming to the V-by-one (registered trademark) standard. A timing chart for transfer is shown. For convenience of explanation, the figure shows a timing chart of any one of channel Y, channel M, channel C, and channel K. FIG.

In one cycle of the line synchronizing signal LS, that is, in the section (LS section) from the rise timing of a certain pulse to the rise timing of the next pulse, the image data for one line is transferred from the image processing section (controller) to the image output section (engine). However, the transmission of one line of image data is completed in the interval in which the pulse of the data enable signal DE indicating the interval in which the data signal Data is transmitted rises, and the rest of the interval is wasted. Show what is going on.

Specifically, assuming that the image data for one line is 1200 x 2400 dpi and 30 ppm, a bandwidth of about 270 Mbps per channel is enough, but V-by-one (registered trademark) (4-byte mode lower limit) transfer The bandwidth is 600 Mbps, and the transfer bandwidth for high-speed serial communication is more than twice as large as the required bandwidth, resulting in excessive waste of the bandwidth.

Therefore, in the present embodiment, instead of transferring data signals and the like from the image processing section to the image output section independently for each channel, at least two or more of the four YMCK channels are integrated (merged). This is to reduce wasted bandwidth. For example, in the present embodiment, the data signals of channel Y and channel M are integrated, and serial communication (high-speed serial communication) conforming to the V-by-one (registered trademark) standard is sent to the image output unit as a signal of one channel. ). As a result, the bandwidth is expanded compared to the case of independently transferring signals of one channel, and the transfer bandwidth of V-by-one (registered trademark) (lower limit of 4-byte mode) can be effectively utilized.

However, in the V-by-one (registered trademark) standard, there are one signal line each for the page synchronization signal PS, the line synchronization signal LS, and the data enable signal DE. The line synchronization signal LS and data enable signal DE cannot be output at the same time.

Therefore, in this embodiment, the number of channels to be integrated is n ( n is an integer equal to or greater than 2), a new transmission reference clock signal (TCLK) is multiplied by a factor n, and this transmission reference clock signal is used to time-division multiplex and integrate n channels. For example, two channels, channel Y and channel M, are time-division multiplexed and integrated, and then transferred from the image processing section (controller) to the image output section (engine). By time-division multiplexing, the page synchronization signal PS, the line synchronization signal LS, and the data enable signal DE of a plurality of channels can be transferred through a single signal line without being output at the same time.

Next, the image forming apparatus of this embodiment will be described on the premise of the comparative example described above.
FIG. 3A shows the configuration of an image processing section as a signal processing device in the image forming apparatus of this embodiment. For convenience of explanation, a case where two channels, channel Y and channel M, of the four YMCK channels are integrated will be exemplified. The difference from FIG. 1 is that a merge section 15YM is provided between the video IFs 14Y and 14M of channel Y and channel M and the serial converters 16Y and 16M, and the serial converters 16Y and 16M are integrated into one serial converter. The point is that it is 16YM. The code suffix "YM" indicates that channel Y and channel M are combined. The image processors 12Y, 12M and the video IFs 14Y, 14M function as receiving means, the merging section 15YM functions as integrating means, and the serial converter 16YM functions as serial conversion means. In the following description, the merge unit 15YM will be referred to as an "integration unit" as appropriate.

The integration unit 15YM doubles the data signal Data, the page synchronization signal PS, the line synchronization signal LS, and the data enable signal DE from the video IFs 14Y and 14M with respect to the reference clock signal (VCLK) to generate a transmission reference clock signal. (TCLK), and the signals of channel Y and channel M are sequentially transmitted to the serial converter 16YM in chronological order. That is, in synchronization with the transmission reference clock signal (TCLK), the data signal Data etc. of channel Y is first transmitted, then the data signal Data etc. of channel M is transmitted, and then the data signal Data etc. of channel Y is transmitted. Then, the data signal of channel M, etc. is transmitted. That is, time division multiplexing is performed by alternately transmitting the data signals of the two channels Y and M to be integrated. The integration unit 15YM outputs the data signal or the like integrated by time-division multiplexing to the serial converter 16YM. The transmit reference clock signal (TCLK) may be generated by the timing generator 10 from the reference clock signal (VCLK).

The integration unit 15YM integrates the data signals of the two channels, channel Y and channel M, and also integrates the timing of the transmission reference clock signal (TCLK) obtained by multiplying the reference clock signal (VCLK) by two. A reference signal indicating whether the signals of each channel correspond to each other is generated and output to the serial converter 16YM. Specifically, as will be described later, the integrated line synchronization signal is added with the reference signal and output to the serial converter 16YM.

The serial converter 16YM serially converts the integrated data signals of channel Y and channel M, etc., and transfers them to the image output section (engine) via the transmission section 18 .

Similarly, the data signals of channel C and channel K can be time-division multiplexed and integrated by using the integration unit.

FIG. 3B shows the configuration of an image output unit as a signal processing device in this embodiment. For the convenience of explanation, a case where two channels, channel Y and channel M, of the four YMCK channels are integrated in accordance with the configuration of FIG. 3A will be exemplified. A different point from FIG. 1 is that extraction units 21Y and 21M are provided between deserial converters 20Y and 20M of channel Y and channel M and output units 22Y and 22M.

Extraction units 21Y and 21M are provided for each channel. For example, the channel Y is provided with an extractor 21Y, which is supplied with the data signal Data, the page synchronization signal PS, the line synchronization signal LS, and the data enable signal from the deserial converter 20Y. The extraction unit 21Y detects which timing of the transmission reference clock signal is the reference for the signals of the channels Y and M according to the reference signal generated by the integration unit 15YM (see FIG. 3A) and transferred, It controls the timing of selecting the data signal Data and the like in each channel. For example, the extraction unit 21Y for channel Y extracts data signal Data (Y), page synchronization signal PS (Y), line synchronization signal LS (Y), and data enable signal DE for channel Y, which have been time-division multiplexed and transferred. (Y), and from the data signal Data(M) of channel M, the page synchronization signal PS(M), the line synchronization signal LS(M), and the data enable signal DE(M), the data signal Data(Y) of channel Y, The page sync signal PS(Y), the line sync signal LS(Y), and the data enable signal DE(Y) are selected and read. On the other hand, the data signal Data(M), page synchronization signal PS(M), line synchronization signal LS(M), and data enable signal DE(M) of channel M are skipped without being selected. Then, the extracted data signal of channel Y and the like are output to the output section 22Y.

In addition, the extraction unit 21M for channel M extracts the data signal Data (Y), page synchronization signal PS (Y), line synchronization signal LS (Y), and data enable signal DE for channel Y, which have been time-division multiplexed and transferred. (Y), data signal Data(M) of channel M, page sync signal PS(M), line sync signal LS(M), data enable signal DE(M), data signal Data(M) of channel M, page The sync signal PS(M), the line sync signal LS(M), and the data enable signal DE(M) are selected and read. On the other hand, the data signal Data(Y), page synchronization signal PS(Y), line synchronization signal LS(Y), and data enable signal DE(Y) of channel Y are skipped without being selected. Then, it outputs the extracted data signal and the like to the output section 22M. It can be said that the extraction units 21Y and 21M perform the inverse transformation of the integration unit 15YM to extract data signals and the like of each channel (separate time-division multiplexed signals from each other).

The extraction units 21Y and 21M of each channel extract the data signal and the like of their own channel. , 22M, it is converted to the original reference clock signal (VCLK) and then output.

FIG. 4 shows a detailed configuration of the integration unit 15YM in FIG. 3A. For convenience of explanation, a case where two channels, channel Y and channel M, of the four YMCK channels are integrated will be exemplified in accordance with the configuration of FIG. 3A.

The integration unit 15YM includes sampling units 30Y and 30M, a control signal selector unit (LS) 32, a control signal selector unit (PS) 34, a control signal selector unit (DE) 36, an image data selector unit 38, a reference timing generation unit 40, A selector control section 42 , a reference signal generation section 44 and a reference signal selector section 46 are provided.

The sampling units 30Y and 30M sample the data signal Data, page synchronization signal, line synchronization signal, and data enable signal of each channel with the transmission reference clock signal (TCLK), and the control signal selector (LS) 32 and the control signal selector It outputs to a section (PS) 34, a control signal selector section (DE) 36, and an image data selector section 38, respectively. For example, the channel Y sampling unit 30Y converts the channel Y data signal Data (Y), page synchronization signal PS (Y), line synchronization signal LS (Y), and data enable signal DE (Y) into the transmission reference clock signal ( TCLK) and output to a control signal selector (LS) 32, a control signal selector (PS) 34, a control signal selector (DE) 36, and an image data selector 38, respectively. Also, the sampling unit 30M for channel M converts data signal Data (M), page synchronization signal PS (M), line synchronization signal LS (M), and data enable signal DE (M) for channel M into transmission reference clock signal ( TCLK) and output to a control signal selector (LS) 32, a control signal selector (PS) 34, a control signal selector (DE) 36, and an image data selector 38, respectively.

The reference timing generator 40 receives a transmission reference clock signal (TCLK) and determines which timing (edge) of the transmission reference clock signal (TCLK) is the transmission timing of each channel. For example, the reference timing generation unit 40 determines the transmission timing of the signal of channel Y based on the rising edge of a certain pulse of the transmission reference clock signal (TCLK), and determines the rising edge of the next pulse following that pulse of channel M. It is determined as the transmission timing of the signal.

The selector control section 42 controls selection of a channel to be transmitted with the transmission reference clock signal (TCLK) according to the timing determined by the reference timing generation section 40 . The selector control unit 42 uses the transmission reference clock signal (TCLK) to select a channel to be currently transmitted through a control signal selector unit (LS) 32, a control signal selector unit (PS) 34, a control signal selector unit (DE) 36, and a control signal selector unit (DE) 36. and output to the image data selector unit 38 .

The control signal selector (LS) 32 responds to the selection signal from the selector control unit 42 by selecting the line synchronization signal LS (Y) of the channel Y from the sampling unit 30Y and the line synchronization signal LS (Y) of the channel M from the sampling unit 30M. M) are alternately selected in time series to time-division multiplex these two signals.

The control signal selector (PS) 34 responds to the selection signal from the selector control unit 42 by selecting the page synchronization signal PS(Y) of channel Y from the sampling unit 20Y and the page synchronization signal PS(Y) of channel M from the sampling unit 20M. M) are alternately selected in time series to time-division multiplex these two signals.

The control signal selector section (DE) 36 responds to the selection signal from the selector control section 42 by selecting the data enable signal DE(Y) for the channel Y from the sampling section 20Y and the data enable signal DE(Y) for the channel M from the sampling section 20M. M) are alternately selected in time series to time-division multiplex these two signals.

In response to a selection signal from the selector control unit 42, the image data selector unit 38 converts the data signal Data(Y) of the channel Y from the sampling unit 20Y and the data signal Data(M) of the channel M from the sampling unit 20M into time series. These two signals are time division multiplexed by alternately selecting above.

The reference signal generation unit 44 generates a reference signal that serves as a reference for extracting the signal time-division multiplexed by the image output unit (engine) for each channel according to the timing determined by the reference timing generation unit 40. and output to the reference signal selector unit 46 .

The reference signal selector section 46 superimposes (adds) the reference signal from the reference signal generation section 44 on the integrated line synchronization signal from the control signal selector section (LS) 32, and outputs it to the serial converter 16YM. The reference timing generator 40, the reference signal generator 44, and the reference signal selector 46 function as reference timing generator.

At least one or all of the functional blocks of the integration unit 15YM and the serial converter 16YM shown in FIG. This can be achieved by reading and executing A processor refers to a processor in a broad sense, and includes general-purpose processors (e.g. CPU Central Processing Unit, etc.) and dedicated processors (e.g. GPU Graphics Processing Unit, ASIC Application Specific Integrated Circuit, FPGA Field Programmable Gate Array, programmable logic devices, etc.). ). In addition, the operation of the processor may be performed not only by one processor but also by the cooperation of a plurality of physically separated processors. Also, the order of operations of the processor may be changed as appropriate.

FIG. 5 shows a timing chart of each signal in the integrating section 15YM. In the figure, from top to bottom, reference clock signal (VLCK), line synchronization signal LS (Y), data enable signal DE (Y), data signal Data (Y), line synchronization signal LS (M), data enable signal DE ( M) shows a timing chart of the data signal Data(M). Here, in the figure, the line synchronization signal LS(Y) is LS_Y, the data enable signal DE(Y) is DE_Y, the data signal Data(Y) is DATA_Y, the line synchronization signal LS(M) is LS_M, the data enable signal DE( Y) is shown as DE_M, and the data signal Data(Y) as DATA_M. Further below these signals, the transmission reference clock signal (TCLK), the integrated line synchronization signal LS_0, the integrated data enable signal DE_0, and the integrated data signal DATA_0 are shown in order.

As for channel Y, the line synchronization signal LS_Y rises from L (Low) to H (Hi) at a certain rise timing with respect to the reference clock signal VCLK. In addition, the data enable signal DE_Y rises from L (Low) to H (Hi) at the subsequent rising timing with respect to the reference clock signal VCLK. The data signal DATA_Y is, in the section where the data enable signal DE_Y is H,
D_Y0, D_Y1, D_Y2, . . .
are sent sequentially.

As for the channel M, the line synchronization signal LS_M rises from L to H at a different rise timing than the reference clock signal VCLK. In addition, the data enable signal DE_M rises from L to H at the subsequent rising timing with respect to the reference clock signal VCLK. The data signal DATA_M, in the section where the data enable signal DE_M is H,
D_M0, D_M1, D_M2,...
are sent sequentially.

On the other hand, the transmission reference clock signal TCLK is multiplied by two times the reference clock signal VCLK according to the number of integrated channels n=2. The reference timing generator determines the timing of transmitting the data signal of channel Y and the timing of transmitting the data signal of channel M, etc., using this transmission reference clock signal TCLK. In the figure, the timing of the circled number 1 (hereinafter referred to as "1" timing) is the transmission timing of channel Y, and the circled number 2 timing (hereinafter referred to as "2" timing). ) is the transmission timing of channel M, the line synchronization signal LS_Y of channel Y is selected at timing "1", LS_0 rises from L to H, and at the timing of the next pulse channel M at timing "2". However, since the line synchronizing signal LS_M is L at this timing, the line synchronizing signal LS_0 after integration becomes L. Similarly, the line synchronization signal LS_Y of channel Y and the line synchronization signal LS_M of channel M are time-divisionally integrated at timings "1" and "2" synchronized with the transmission reference clock signal. At the timing when the line synchronization signal LS_M of the channel M changes from L to H, the line synchronization signal LS_M of the channel M also rises to H at timing "2". remains.

At the timing of "1", the data enable signal DE_Y of the channel Y is selected, DE_0 rises from L to H, and at the timing of the next pulse, the data enable signal DE_M of the channel M is selected at the timing of "2". However, since the data enable signal DE_M is L at this timing, the data enable signal DE_0 after integration becomes L. Similarly, the data enable signal DE_Y of channel Y and the data enable signal DE_M of channel M are integrated in a time division manner at timings "1" and "2" synchronized with the transmission reference clock signal. At the timing when the data enable signal DE_M of the channel M changes from L to H, the data enable signal DE_M of the channel M also rises to H at the timing "2". remains.

At the timing of "1" and the data enable signal DE_0 is H, the data signal DATA_Y of the channel Y is selected, and at the timing of "2" and the data enable signal DE_0 is H, By selecting the data signal DATA_M of channel M, the image data of the two channels are merged. As a result, the data signals of the two channels Y and M are
D_Y0, D_Y1, D_Y2, . . . D_Y(N), D_M0, D_Y(N+1), D_M1, .
and integrated in a time-sharing manner.

In FIG. 5, the integrated data signal at the timing when the data enable signal DE_M of the channel M is L is expressed as D_MX. It shows that

Also, although the timing chart of the page synchronization signal after integration is omitted in FIG. and the timing "2", the page synchronization signal PS_Y of the channel Y and the page synchronization signal PS_M of the channel M are integrated in a time division manner.

As described above, the control signal selector (LS) 32, the control signal selector (PS) 34, the control signal selector (DE) 36, and the image data selector 38 are synchronized with the transmission reference clock signal, By alternately selecting the signal of channel Y and the signal of channel M in time series using the timing determined by the timing generator 40, the data signal etc. of channel Y and the data signal etc. of channel M are integrated. Output to serial converter 16YM.

Although the timing chart of FIG. 5 does not show the reference signal generated by the reference signal generator 44, the reference signal is added to the start timing of the integrated line synchronization signal LS_0.

FIG. 6 shows a timing chart of the reference signal generated by the reference signal generator 44 and added to the line synchronization signal LS_0 integrated by the reference signal selector 46. As shown in FIG.

FIG. 6 is a timing chart of the reference clock signal VCLK, the transmission reference clock signal TCLK, the line synchronization signal LS_0 after integration, the data enable signal DE_0 after integration, and the data signal DATA_0 after integration in order from the top in FIG.

For example, using the reference clock signal VCLK, the reference signal is a pulse-shaped signal that rises from L to H in one cycle of VCLK and then falls from H to L, and is superimposed (added) on the start timing of the line synchronization signal LS_0. be done. The reference signal can be said to be a signal that toggles at 1VCLK. It should be noted that the reference signal must have a signal waveform that can be clearly distinguished from the line synchronization signal LS of each channel. A pulsed reference signal that toggles at 1 VCLK is valid.

As described above, the image output unit (engine) extracts the data signal for each channel from the integrated and transferred signals. At this time, the reference signal is detected from the line synchronization signal LS_0 shown in FIG. The timing of the channel Y data signal and the timing of the channel M data signal are determined by detecting this reference signal. That is, the reference signal serves as the signal that determines the initiation of communication of the integrated signal.

In FIG. 6, the reference signal is a signal that toggles at 1VCLK, but the signal waveform is not limited to this. Also, in this embodiment, the reference signal is added to the integrated line synchronization signal LS_0, but it may be added to the integrated page synchronization signal PS_0. Additionally, a reference signal may be added to the integrated data signal DATA_0. However, in the last example, the integrated data enable signal DE_0 should be changed to H at the timing when the reference signal is added.

FIG. 7 shows the detailed configuration of the extraction unit 21Y in FIG. 3B. The extraction unit 21M has the same configuration.

The channel Y extractor 21Y includes a control signal selector (LS) 50, a control signal selector (PS) 52, a control signal selector (DE) 54, an image data selector 56, a reference timing detector 58, and a selector controller. 60 and a clock converter 62 .

The reference timing detector 58 detects a reference signal from the integrated line synchronization signal LS_0 output from the deserial converter 20Y. That is, as shown in FIG. 6, if the reference signal is appended to the integrated line sync signal LS_0, the reference timing detector 58 detects the reference toggling at 1 VCLK appended to the consolidated line sync signal LS_0. A signal is detected and output to the selector control unit 60 .

The selector control unit 60 determines the timing of the channel Y among the integrated two channels Y and M according to the reference signal detected by the reference timing detection unit 58, and outputs the selection signal to the control signal selector unit (LS ) 50 , a control signal selector (PS) 52 , a control signal selector (DE) 54 and an image data selector 56 . Specifically, when the reference signal is detected, one cycle of the transmission reference clock signal advanced by a predetermined cycle with reference to the rise timing of the reference signal is set as the channel Y interval, and the next one cycle of the transmission reference clock signal is set as the channel Y interval. A selection signal is generated and output as the channel M section.

A control signal selector unit (LS) 50 selects a signal in a section defined by the selection signal from the integrated line synchronization signal LS_0 output from the deserial converter 20Y, and selects signals in other sections. By skipping first, the line synchronization signal LS_Y of channel Y is extracted.

A control signal selector (PS) 52 selects a signal in a section defined by the selection signal from the integrated line synchronization signal PS_0 output from the deserial converter 20Y, and selects signals in other sections. The page synchronization signal PS_Y of the channel Y is extracted by skipping without skipping.

A control signal selector unit (DE) 54 selects a signal in a section defined by the selection signal from the integrated data enable signal DE_0 output from the deserial converter 20Y, and selects signals in other sections. The data enable signal DE_Y of channel Y is extracted by skipping first.

The image data selector unit 56 selects signals in the section specified by the selection signal from the integrated data signal DATA_0 output from the deserial converter 20Y, and skips signals in other sections without selecting them. to extract the channel Y data signal DATA_Y.

The clock converter 62 converts the channel Y line synchronization signal output from the control signal selector (LS) 50, the control signal selector (PS) 52, the control signal selector (DE) 54, and the image data selector 56. By re-sampling LS_Y, page synchronization signal PS_Y, data enable signal DE_Y, and data signal DATA_Y with reference clock signal VCLK, the clock signal is converted from transmission reference clock signal TCLK to reference clock signal VCLK and output.

At least some of the functional blocks of the extracting unit 21Y shown in FIG. 7 can be realized by reading and executing the processing program from a memory storing the processing program by a computer having one or more processors. A processor refers to a processor in a broad sense, and includes general-purpose processors (e.g. CPU Central Processing Unit, etc.) and dedicated processors (e.g. GPU Graphics Processing Unit, ASIC Application Specific Integrated Circuit, FPGA Field Programmable Gate Array, programmable logic devices, etc.). ). In addition, the operation of the processor may be performed not only by one processor but also by the cooperation of a plurality of physically separated processors. Also, the order of operations of the processor may be changed as appropriate.

FIG. 8 shows a main processing flowchart of the image processing unit (controller).

The reference timing generator 40 determines the timings of the two channels Y and M to be combined and outputs them to the reference signal generator 44 . The reference signal generator 44 generates a reference signal corresponding to this timing and transmits it to the reference signal selector 46 (S101). The selector control unit 42 also outputs a selection signal according to the timing determined by the reference timing generation unit 40 to a control signal selector unit (LS) 32, a control signal selector unit (PS) 34, and a control signal selector unit (DE) 36. , and the image data selector 38 .

A control signal selector (LS) 32, a control signal selector (PS) 34, a control signal selector (DE) 36, and an image data selector 38 generate a line synchronization signal LS, page synchronization signal, By selecting the data enable signal DE and the data signal, the data signals of channels Y and M are time-division multiplexed and integrated (S102). Also, the reference signal selector unit 46 adds a reference signal to the integrated line synchronization signal.

The serial converter 16YM converts integrated data, that is, integrated line sync signal, integrated page sync signal, integrated data enable signal, and integrated data signal into standards such as V-by-one (registered trademark). The data is transferred to the image output unit (engine) by high-speed serial communication conforming to the standard (S103).

FIG. 9 shows a main processing flowchart of the image output unit (engine).

The reference timing detection unit 58 receives the reference signal included in the integrated line synchronization signal (S201) and outputs the detection signal to the selector control unit 60. The selector control unit 60 sends a selection signal to a control signal selector unit (LS) 50, a control signal selector unit (PS) 52, a control signal selector unit (DE) 54, and an image data selector unit 56 according to the detection timing of the reference signal. output to

A control signal selector unit (LS) 50, a control signal selector unit (PS) 52, a control signal selector unit (DE) 54, and an image data selector unit 56 receive integrated data (S202), and select It is determined whether or not it is the clock timing of its own channel (ch) (S203). For example, as described above, if the timing of "1" is the timing of the data signal of channel Y, and the timing of "2" is the timing of the data signal of channel Y, the control signal selector unit (LS ), the control signal selector unit (PS), the control signal selector unit (DE), and the image data selector unit determine that the timing of "1" is the clock timing of their own channel (YES in S203), and integrate the received data. A signal is read from the data (S204). Also, at timing "2", it is determined that it is not the clock timing of its own channel (NO in S203), and the signal is skipped without being read from the received integrated data (S205).

As described above, in this embodiment, in synchronization with the transmission reference clock signal obtained by multiplying the reference clock signal VCLK, image signals and synchronization signals of a plurality of channels are time-divisionally integrated to form a V-by-one (registered trademark). By transferring to the image output unit by serial communication (high-speed serial communication) conforming to standards such as the above, it is possible to reduce wasted bandwidth compared to the case of independent transfer for each channel.

In this embodiment, the image signals and synchronization signals of two channels, channel Y and channel M, are time-division multiplexed, but the image signals and synchronization signals of two channels, channel C and channel K, are also time-division multiplexed. can do. Moreover, the image signals and synchronization signals of two or more of channels Y, M, C, and K may be time-division multiplexed if necessary. For example, when the image signals and synchronization signals of channel Y, channel M, and channel C are integrated, the image signals and synchronization signals are sampled by the transmission reference clock signal TCLK which is three times the reference clock signal VCLK, and time-division multiplexing is performed. do it.

In this embodiment, the image signals and synchronization signals of a plurality of channels are time-division multiplexed at the clock cycle of the transmission reference clock signal. Then, image signals and synchronization signals of a plurality of channels may be time-division multiplexed using different delay times from the reference timing.

For example, when integrating the image signal and synchronization signal of two channels, channel Y and channel C, the image signal and synchronization signal of channel Y are selected by the first delay time from the reference timing for channel Y, and then the channel Y is selected. The image signal and synchronizing signal of channel C are selected and integrated at a second delay time from the C reference timing.

FIG. 10 shows a timing chart of the modification.

In FIG. 10, the timing charts of the line synchronization signal LS_0 after integration, the data enable signal DE_0 after integration, and the data signal DATA_0 after integration are shown in order from the top.

A reference timing signal for channel Y (reference LS(Y)) is inserted into the line synchronization signal, and the line synchronization signal LS_Y for channel Y is selected from this reference timing signal with a first delay time. Next, a reference timing signal for channel M (reference LS(M)) is inserted, and the line synchronization signal LS_M for channel M is selected from this reference timing signal with a second delay time.
Also, the data enable signal DE_Y for channel Y is selected from the reference timing signal for channel Y by the first delay time, and then the data enable signal for channel M is selected by the second delay time from the reference timing signal for channel M. Select DE_M.

Further, the data signal DATA_Y of channel Y is selected from the reference timing signal for channel Y with the first delay time, and then the data signal DATA_M of channel M is selected from the reference timing signal for channel M with the second delay time. select.

In this manner, the image signals and synchronization signals of a plurality of channels are time-division multiplexed and integrated in the section of the line synchronization signal LS for each color, and the signals of the plurality of channels are switched for each line. It can reduce the number of image processors and video IFs used.

10 timing generator, 12Y to 12K image processor, 14Y to 14K video IF, 15YM integration (merge) section (channel Y and channel M) 16Y to 16K serial converter, 18 transmission line, 20Y to 20K deserial converter, 21Y, 21M extraction section, 22Y to 22K output sections.

Claims (10)

receiving means for receiving synchronization signals and image signals for each of a plurality of channels;
integration means for time-division multiplexing and integrating synchronization signals and image signals of any two or more of the plurality of channels;
reference timing generation means for superimposing a reference signal defining the start of communication on the synchronization signal and outputting the synchronization signal;
serial conversion means for serially converting the reference signal, the time-division multiplexed synchronization signal and the image signal, and outputting the serial conversion means;
A signal processing device comprising: The integrating means multiplies the synchronization signal of each of the plurality of channels and the reference clock signal serving as the reference for generating the image signal by the number of channels n (n is an integer equal to or greater than 2) to be time-division multiplexed. 2. The signal processing device according to claim 1, which operates with a transmitted reference clock signal. The integration means is
sampling means for sampling the synchronization signal and the image signal received by the receiving means based on the transmission reference clock signal;
selection control means for outputting a selection signal for selecting a channel to be transmitted based on the reference signal;
Synchronization signal selection means for selecting a synchronization signal of a channel to be time-division multiplexed based on the selection signal from the synchronization signals of each channel sampled by the sampling means;
image signal selection means for selecting an image signal of a channel to be time-division multiplexed based on the selection signal from the image signals of each channel sampled by the sampling means;
The signal processing device according to claim 2, comprising: the synchronization signals include line synchronization signals, page synchronization signals, and data enable signals;
the reference signal is superimposed on either the line synchronization signal or the page synchronization signal;
The signal processing device according to any one of claims 1 to 3. The integrating means time-division-multiplexes and integrates the synchronization signals and image signals of any two or more channels out of the plurality of channels, line by line.
The signal processing device according to claim 1. the synchronization signal includes a line synchronization signal;
The integrating means time-division multiplexes the line synchronization signals of any two or more of the plurality of channels using different delay times with respect to the reference line synchronization signal as the reference signal.
The signal processing device according to claim 5. the synchronization signal includes a data enable signal;
The integrating means time-division multiplexes the data enable signals of any two or more of the plurality of channels using different delay times from the reference line synchronization signal.
The signal processing device according to claim 6. a separation means for receiving the serial signal output from the serial conversion means and separating it into the time division multiplexed synchronization signal and the image signal;
extracting means for extracting the synchronizing signal and the image signal of each channel from the synchronizing signal and the image signal time-division multiplexed based on the reference signal;
The signal processing device according to any one of claims 1 to 7, further comprising: A signal processing device according to claim 8;
forming means for forming an image on a medium based on the synchronizing signal and the image signal of each channel output from the extracting means of the signal processing device;
An image forming apparatus comprising: the computer,
receiving means for receiving synchronization signals and image signals for each of a plurality of channels;
integration means for time-division multiplexing and integrating synchronization signals and image signals of any two or more of the plurality of channels;
reference timing generation means for superimposing a reference signal defining a communication start time on the synchronization signal and outputting the same;
serial conversion means for serially converting the reference signal and the time-division multiplexed synchronization signal and image signal;
A program that acts as a

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