JP4433951B2 - Image data transfer method and image data transfer apparatus - Google Patents

Description

  The present invention uses a transfer circuit of two or more channels, distributes image data to each channel in units of main scanning lines, corresponds to each channel transfer circuit, and generates a main scanning synchronization signal and a sub-scanning synchronization signal. The present invention relates to an image data transfer method for transferring data based on the image data, and an image formation control apparatus to which the image data transfer method is applied.

  Multi-beam image forming apparatuses (print engines) that can form images at high speed by scanning a plurality of beams have become widespread.

  As an apparatus for transferring image data to an image forming apparatus (dual beam print engine) that forms an image by scanning two beams, a plurality of lines of image data are divided into two memory groups and written. There is known a data processing apparatus that outputs a delay to the image forming apparatus at the same time from the memory or between a plurality of lines in the main scanning (see, for example, Patent Document 1 and Patent Document 2).

  On the other hand, in a print engine such as a color print or a color copying machine, there is a color print engine that outputs four CMYK colors simultaneously or with a delay between colors. As a print controller corresponding to this, an ASIC having built-in image data transfer circuits for four colors is used.

  The image data transfer circuit designed for the color print engine as described above may be applied as a monochrome multi-beam print engine.

  By the way, in an image data transfer circuit designed for a color print engine, it is assumed that a sub-scanning synchronization signal (hereinafter referred to as “VSYNC”) and a main scanning synchronization signal (hereinafter referred to as “HSYNC”) are synchronized. In other words, when VSYNC and HSYNC are asynchronous, the position of the writing start line of each channel in the sub-scanning direction does not match, and color misregistration may occur.

On the other hand, in black and white image data, since there is no need to consider color misregistration from the beginning, VSYNC and HSYNC are often asynchronous. In this case, in printing with a single beam, there was no problem at all because the start of writing was only delayed by one line.
Japanese Patent Laid-Open No. 10-257242 JP-A-10-257243

  However, when a transfer circuit designed for a color print engine or the like is applied as a transfer circuit of an engine that forms a black and white image with multi-beams using, for example, two channels among the plurality of channel transfer circuits, VSYNC and Asynchrony with HSYNC can be a major obstacle.

  That is, when HSYNC is input immediately after VSYNC is input in one channel, the image for the first line of the channel is transferred based on the input of HSYNC. At this time, if HSYNC is input immediately before the input of VSYNC on the other side, the standby state is entered until the next input of HSYNC, and then the image for the first line of the channel is transferred.

  For this reason, there is a possibility that the transfer time of the first one line is shifted by the time range of ± 1 HSYNC in the image transfer time of two channels.

  FIG. 8 shows a conventional transfer circuit in which the above problem occurs, and here, a C channel transfer circuit 102C and a K channel transfer circuit 102K are applied from the transfer processing unit 100 for the color print engine. .

  When VSYNC and HSYNC are input to the respective channels, the transfer circuits 102C and 102K of each channel independently control the transfer of image data for one line. Note that clock signals (VCLK-C, VCLK-K) are input to the channel transfer circuits 102C, 102K, respectively.

  FIG. 9 shows a transfer timing chart of each of the C channel transfer circuit 102C and the K channel transfer circuit 102K.

  In the C channel transfer circuit 102C, VSYNC is input first, and immediately after that, HSYNC is input. Therefore, after a predetermined time has elapsed from the input of HSYNC, image data for the first line is transferred. ing.

  On the other hand, in the K channel transfer circuit 102K, HSYNC is inputted before VSYNC is inputted, and this HSYNC becomes invalid, and the transfer of the image data of the first one line is not executed. Thereafter, the transfer of the first one line of image data is executed based on the input of the next HSYNC.

  In the timing chart of FIG. 9, the transfer of image data in the K channel transfer circuit 102K is delayed by one line, which corresponds to “Problem 1” in Table 1. The timing chart of FIG. 9 is an example, and there may be a case of “normal” in Table 1, or a case where transfer of image data in the C channel transfer circuit 102C is delayed by one line as in “Defect 2” in Table 1. In other words, VSYNC and HSYNC are not asynchronously defined.

  In consideration of the above facts, the present invention considers the main scanning synchronization signal and the sub-scanning synchronization signal input to each channel when transferring a plurality of black and white images simultaneously using a plurality of channels of transfer circuits of two or more channels. An object of the present invention is to obtain an image data transfer method and an image formation control device capable of specifying the transfer order of each channel even if they are asynchronous.

The present invention is an image data transfer method that uses two or more channels of transfer circuits and distributes and transfers image data to a predetermined channel in units of main scanning lines, and includes a main scanning synchronization signal and a sub-scanning synchronization signal. Are not synchronized with each other, the main scanning synchronization signal is sent to each of the two or more channel transfer circuits, and the sub scanning synchronization signal is transferred to one channel of the two or more channel transfer circuits. In the transfer circuit of the channel that is sent to only the circuit and to which the sub-scanning synchronization signal is input, the main-scanning synchronization signal and the predetermined scanning signal are determined based on the input sub-scanning synchronization signal and the input main-scanning synchronization signal. Generates a correlated sub-scanning synchronization signal that is synchronized with the main-scanning synchronization signal at a time-shifted timing, and from the transfer circuit of the channel to which the sub-scanning synchronization signal is input In the transfer circuit of the channel to which the correlated sub-scanning synchronization signal is input, the correlated sub-scanning synchronization signal is sent to the input terminal of the sub-scanning synchronization signal in the transfer circuit of the other channel to which the main scanning synchronization signal is input. Based on the inputted main scanning synchronization signal and the inputted correlated sub-scanning synchronizing signal, the distributed image data in units of main scanning lines is transferred.

  According to the present invention, when image data for a plurality of main scanning lines is simultaneously transferred using a transfer circuit of two or more channels, that is, a plurality of channels, this is a predetermined channel (that is, a channel for transferring image data). The number of channels is 1 channel or more.) When the main scanning synchronization signal and the sub scanning synchronization signal to be sent to the transfer circuit are asynchronous, the main scanning synchronization signal is sent to the transfer circuit of each channel, and the sub scanning is performed. A synchronization signal is sent only to the transfer circuit of one channel.

In the transfer circuit of the channel to which the sub-scanning synchronization signal is input, a correlated sub-scanning synchronization signal having a correlation with the main scanning synchronization signal is generated.

The generated correlated sub-scanning synchronization signal is simultaneously transmitted from the transfer circuit of the channel to which the sub-scanning synchronization signal is input to the transfer circuit of the channel that has transmitted the main scanning synchronization signal.

  In the distributed channel, the transfer timing of each main scanning line is determined based on the correlated sub-scanning synchronization signal and the main scanning synchronization signal. That is, the correlated sub-scanning synchronization signal and the main scanning synchronization signal are synchronized with each other without the input timings randomly changing from each other. Accordingly, the same correlation is obtained between the channels, and the transfer time is not shifted.

Further, the image data transfer method of the present invention forms, for example, an electrostatic latent image by making the surface of the photosensitive drum uniform and scanning with a light beam, and supplying and developing the toner, and recording paper. The present invention can be applied to a print controller (image formation control device) of an image forming apparatus that transfers the toner image, fixes it, and discharges it.
The present invention is an image data transfer device that uses a transfer circuit of two or more channels and distributes and transfers image data to a predetermined channel in units of main scanning lines, and includes a main scanning synchronization signal and a sub-scanning synchronization signal. Are synchronized with each other, the main scanning synchronization signal is sent to each of the transfer circuits of the two or more channels, and the sub-scanning synchronization signal is sent only to the transfer circuit of one channel of the transfer circuits of the two or more channels. Correlation that synchronizes with the main scanning synchronization signal at a timing shifted from the main scanning synchronization signal by a predetermined time based on the sending means for sending, and the inputted sub-scanning synchronization signal and the inputted main scanning synchronization signal A sub-scan synchronization signal is generated, and the correlated sub-scan synchronization is applied to an input terminal of a sub-scan synchronization signal in a transfer circuit of another channel to which the main scan synchronization signal is input. No. Based and first transfer means for sending, to said correlation sub-scanning synchronization signal sent from the main scanning synchronizing signal transmitted from said transmitting means and said first transfer means, distributed main scanning And second transfer means for transferring image data in units of lines .

Further, the present invention distributes and transfers black and white dual beam image data in units of main scanning lines to two channels of a four-channel image data transfer circuit corresponding to each of four color images for color printing. When the main scanning synchronization signal and the sub-scanning synchronization signal are asynchronous with each other, the main scanning synchronization signal is sent to each of the two-channel transfer circuit and the other than the two-channel transfer circuit. Sending to the one-channel transfer circuit and sending the sub-scanning synchronization signal only to the one-channel transfer circuit, the inputted sub-scanning synchronization signal and the inputted main-scanning synchronization signal And generating a correlated sub-scanning synchronization signal that is synchronized with the main scanning synchronization signal at a timing shifted from the main scanning synchronization signal by a predetermined time, A first transfer means for sending the correlated sub-scanning synchronization signal to the input end of the serial two-channel transfer circuit each sub-scan synchronizing signal, transfer the main scanning synchronization signal transmitted from said transmitting means and said first And second transfer means for transferring distributed image data in units of main scanning lines based on the correlated sub-scanning synchronization signal sent from the means .

  As described above, in the present invention, when a plurality of black-and-white images are simultaneously transferred using a plurality of channels of transfer circuits of two or more channels, a main scanning synchronization signal and a sub-scanning synchronization signal input to each channel Even if they are asynchronous, there is an excellent effect that the transfer order of each channel can be specified.

[First Embodiment]
FIG. 1 is a block diagram illustrating a configuration of a print controller 10 according to the first embodiment.

  As shown in the figure, the print controller 10 includes a CPU 12, a RAM 14, and an image data transfer processing unit 16, which are connected by a bus 18.

  The CPU 12 forms and accumulates image data in the RAM 14 by data input from a host computer (not shown) by a program stored in a ROM (not shown). Also, various settings necessary for the transfer processing of the image data transfer processing unit 16 are performed, and a transfer start command is output.

  The image data transfer processing unit 16 is configured for color printing, and is an image data transfer circuit (hereinafter, referred to as four-color image data of Y (yellow), M (magenta), C (cyan), K (black)). In general, the image data transfer circuit 20 is referred to, and when distinguishing, “Y”, “M”, “C”, and “K” are added to the end of the code) and the main scanning synchronization signal HSYNC. And a timing generation circuit 60 for outputting the sub-scanning synchronization signal VSYNC.

  Since the image data transfer circuit 20 has the same configuration, only the configuration of the image data transfer circuit 20Y for Y color will be described here, and the description of other components will be omitted by changing the end of the code. .

  The image data transfer circuit 20Y includes a DMAC (direct memory access controller) 22Y, an expander 24Y, an image shift circuit 26Y, and an image cropping circuit 28Y.

  The DMAC 22Y directly accesses the RAM 14 without using the CPU 12 by the DMA method, inputs image data, and outputs it to the decompressor 24Y.

  If the input image data is compressed data, the decompressor 24Y decompresses it and outputs it to the image shift circuit 26Y. If it is uncompressed data, it outputs it to the image shift circuit 26Y as it is.

  The image shift circuit 26Y outputs the image data of the image obtained by shifting the image of the input image data by the shift amount set by the CPU 12 to the image cropping circuit 28Y.

  The image cropping circuit 28Y outputs only the image data of the pixels extracted according to the setting of the CPU 12 among the pixels constituting the image of the input image data to the print engine 70.

  In the first embodiment, an example has been described in which the CPU 12 sets the values of the registers so that the decompressor, the image shift circuit, and the image cropping circuit transfer (through) the input image data as they are. However, for example, the image data transfer processing unit 16 may have a configuration in which an expander, an image shift circuit, and an image cropping circuit are not provided.

  As described above, the image data transfer circuit 20 having the above configuration is for color printing. In the print controller 10 of the first embodiment, the image data transfer circuit 20 for color printing is used to make a monochrome dual beam. (2 beam) printing is performed.

  That is, the print engine 70 is configured as a black and white dual beam print engine 70A (see FIG. 2) that forms an image by scanning two beams. An image data transfer process executed by the print controller 10 in order to realize monochrome printing will be described.

  As shown in FIG. 2, in order to realize black and white dual beam printing, in the first embodiment, two image data transfers out of the four image data transfer circuits 20 constituting the image data transfer processing unit 16 are performed. A circuit (for example, image data transfer circuits 20C and 20K) is used, and the monochrome image data stored in the RAM 14 is transferred line by line to the monochrome dual beam print engine 70A. More specifically, based on the setting value set by the CPU 12, the odd-numbered line image data among the image data to be transferred is transferred to the monochrome dual beam print engine 70A for each line via the image data transfer circuit 20C. The image data of even lines is transferred for each line via the image data transfer circuit 20K.

  Note that the image data stored in the RAM 14 is the data stored in the RAM 14 by the CPU 12 by data input from a host computer (not shown), but the image data obtained by copying is input. In this case, image data from an image input device (not shown) may be stored in the RAM 14 by an image data storage device (not shown).

  FIG. 3 shows a wiring diagram of signal lines for controlling the image data processing timing (transfer timing) of the image data transfer circuits 20C and 20K of the image data transfer processing unit 16.

  In order to transfer image data at a predetermined timing, a main scanning synchronization signal (HSYNC) and a sub-scanning synchronization signal (VSYNC) are necessary.

  The main scanning synchronization signal HSYNC is a signal for instructing the writing start timing of each line. The input of the main scanning synchronization signal HSYNC is used as a trigger to write out one line after a predetermined time (based on a clock signal CLK (not shown)). The execution is to start.

  On the other hand, the sub-scanning synchronization signal VSYNC is a signal for instructing the writing timing of one page unit, and transfer of one line unit by the main scanning synchronization signal HSYNC is started only when the sub-scanning synchronization signal VSYNC is inputted. become.

  That is, the timing for recognizing the signal is VSYNC → HSYNC → HSYNC →... → HSYNC → VSYNC.

  Incidentally, in general, for each color of color image data, the main scanning synchronization signal HSYNC and the sub-scanning synchronization signal VSYNC in each color are synchronized with each other in order to prevent color misregistration. The correlation between the main scanning synchronization signal HSYNC and the sub-scanning synchronization signal VSYNC is not necessary. This is because, if each has a predetermined timing, the start of writing is shifted by one cycle of the sub-scanning synchronization signal VSYNC, and the formed image is not affected at all.

  However, when scanning this black and white image data with dual beams as described above, if the distributed main scanning synchronization signal HSYNC and the sub-scanning synchronization signal VSYNC are uncorrelated (not synchronized), The main scanning synchronization signal HSYNC may be input immediately before the scanning synchronization signal VSYNC, and the main scanning synchronization signal HSYNC may be input immediately after the sub-scanning synchronization signal VSYNC. As a result, one of them is shifted by one line. It becomes writing in the state.

  In order to solve this problem, in the first embodiment, an image data transfer circuit (here, the image data transfer circuit 20Y) other than the image data transfer circuits 20C and 20K applied for transferring the monochrome dual beam image data is provided. The main scanning synchronization signal HSYNC and the sub-scanning synchronization signal VSYNC are input to the image data transfer circuit 20Y.

  The image data transfer circuit 20Y generates a correlated sub-scanning synchronization signal PDATA to be sent to the image data transfer circuits 20C and 20K based on the input sub-scanning synchronization signal VSYNC. The correlated sub-scanning synchronization signal PDATA is generated based on the period of the main scanning synchronization signal HSYNC input together (here, the timing not coincident with the period (rising) of the main scanning synchronization signal HSYNC. The generated correlated sub-scanning synchronization signal PDATA is transmitted to the input terminal of the sub-scanning synchronization signal VSYNC of the image data transfer circuits 20C and 20K.

  As a result, the image data transfer circuits 20C and 20K recognize the same signal (correlated sub-scanning synchronization signal PDATA) as the sub-scanning synchronization signal VSYNC and execute the transfer process.

  In this way, by sending the same correlated sub-scanning synchronization signal PDATA (pseudo sub-scanning synchronization signal VSYNC) to the two image data transfer circuits 20C and 20K, the main scanning synchronization signal HSYNC input to each of them is transmitted. As a result, the transfer timing becomes unambiguous.

  The operation of the first embodiment will be described below.

(Overall flow of transfer processing)
FIG. 4 is a flowchart showing the setting process by the CPU 12.

  In step 100, the CPU 12 determines the data length d of one line in the main scanning direction of the image data to be transferred. Since the data length d for one line has a predetermined number of pixels per line, for example, the image size of the image data (for example, A4 size, B4 size, etc.) and the print direction (longitudinal or short). The data width d of one line in the main scanning direction (hereinafter simply referred to as “data length d of one line”) is determined according to the hand direction.

  In step 102, the CPU 12 causes the transfer circuit (each DMAC) used for transfer to image one page of image data every other line in accordance with the data length d of one line determined in step 100. A transfer start address, a data transfer amount, and an address shift amount are set in a register (not shown) for each DMAC so that data is input and transferred.

  The transfer start address is set by shifting by one line between the DMACs. Specifically, for the DMAC 20C of the image data transfer circuit 20C that transfers image data of odd lines, the start address (address of the first line) of the image data is set as the transfer start address. For the DMAC 20K of the transfer circuit 20K that transfers even-line image data, an address obtained by adding the data length d of one line to the start address of the image data (address of the second line) is set as the transfer start address.

  The data transfer amount is set to a data length d of one line for all DMACs so that image data is transferred line by line by each DMAC.

  As the address shift amount, the data length width d of one line is set for all the DMACs used so that the transfer start address is shifted every other line. As a result, the next transfer is started from the address added by one line to the current address (transfer end address) at the end of one transfer.

  Further, the CPU 12 sets the value of each register so that the decompressor, the image shift circuit, and the image cropping circuit output (through) the input image data as they are.

  In step 104, the CPU 12 outputs a transfer start command to the DMACs 20 </ b> C and 20 </ b> K of each image data transfer circuit of the image data transfer processing unit 16.

  Here, the DMAC as the output destination of the transfer start instruction, that is, the DMAC of the image data transfer circuit used for transfer is DMAC 20C, 20K, but the transfer circuit used for transfer can be freely selected by the CPU 12. There is no particular limitation.

  In step 106, the CPU 12 waits for a transfer end notification from the DMACs 20C and 20K.

  Next, image data transfer processing performed by each DMAC will be described.

  When a transfer start command is input from the CPU 12, each DMAC transfers image data based on register settings. Specifically, among the image data formed in the RAM 14, image data is input by the amount of data transfer (data length d of one line) from the transfer start address set for each transfer circuit (each DMAC). And transfer. The image data output from each DMAC is transferred to the monochrome dual beam print 70A through the decompressor, the image shift circuit, and the image cropping circuit according to the above setting.

  When the transfer of the image data for one line is completed, each DMAC performs the next transfer using an address obtained by adding the data length d of one line to the current address according to the set address shift amount.

  In this way, each DMAC transfers one page of image data by repeating the process of transferring image data for one line every other line while shifting the transfer start address.

  When the transfer of one page of image data is completed, each DMAC outputs a transfer end notification to the CPU 12.

  Through the processing described above, the DMAC (C) 42 performs image data transfer of odd lines (1, 3, 5,...), And the DMAC (K) 52 transfers even lines (2, 4, 6,.・ ・ Transfer image data of line).

  As described above, when transferring image data to the black and white dual beam print engine 70A, the process of inputting and transferring image data from one page of image data to the two transfer circuits every other line is repeated. Thus, one page of image data is transferred.

(Establishment of distribution method for monochrome image data)
In the transfer process as described above, the first embodiment has a problem that is peculiar to the transfer of image data when monochrome image data is formed with a dual beam.

  That is, in the case of black and white image data, the normal (single beam) does not require a correlation between the main scanning synchronization signal HSYNC and the sub-scanning synchronization signal VSYNC that trigger the data transfer timing.

  However, when scanning this black and white image data with dual beams as described above, if the distributed main scanning synchronization signal HSYNC and the sub-scanning synchronization signal VSYNC are uncorrelated (not synchronized), The main scanning synchronization signal HSYNC may be input immediately before the scanning synchronization signal VSYNC, and the main scanning synchronization signal HSYNC may be input immediately after the sub-scanning synchronization signal VSYNC. As a result, one of them is shifted by one line. It becomes writing in the state.

  Therefore, in the first embodiment, the image data transfer circuit 20Y other than the image data transfer circuits 20C and 20K applied for transferring the monochrome dual beam image data is used, and the main scanning synchronization signal HSYNC and the sub-scanning synchronization signal are used. VSYNC is input to the image data transfer circuit 20Y, and a correlated sub-scanning synchronization signal PDATA to be transmitted to the image data transfer circuits 20C and 20K is generated based on the input sub-scanning synchronization signal VSYNC.

  The correlated sub-scanning synchronization signal PDATA is generated based on the period of the main scanning synchronization signal HSYNC input to the image data transfer circuit 20Y together with the sub-scanning synchronization signal VSYNC at a timing that does not coincide with the period (rise) of the main scanning synchronization signal HSYNC. To do.

  The generated correlated sub-scanning synchronization signal PDATA is sent to the input terminal of the sub-scanning synchronization signal VSYNC of the image data transfer circuits 20C and 20K.

  As a result, the image data transfer circuits 20C and 20K recognize the same signal (correlated sub-scanning synchronization signal PDATA) as the sub-scanning synchronization signal VSYNC and execute the transfer process.

  FIG. 5 shows a timing chart showing the output timing of the image data from the image data transfer circuits 20C and 20K by the main scanning synchronization signal HSYNC, the sub scanning synchronization signal VSYNC and the correlated sub scanning synchronization signal PDATA. Yes.

  In the example of the timing chart of FIG. 5, the sub-scanning synchronization signal VSYNC and the main-scanning synchronization signal HSYNC are input almost simultaneously (matching the falling timing), and the time difference due to physical factors such as the length of the signal line. It is a delicate state which is first, including.

  At this time, the sub-scanning synchronization signal VSYNC is actually input to the image data transfer circuit 20Y, and a correlated sub-scanning synchronization signal PDATA having a timing shifted from the main scanning synchronization signal HSYNC by a predetermined time is generated, and the image data transfer circuit Send to 20C, 20K.

  As a result, the image data transfer circuits 20C and 20K recognize the correlated sub-scanning synchronization signal PDATA as the sub-scanning synchronization signal VSYNC. Therefore, the main scanning is triggered by the input (falling) timing of the correlated sub-scanning synchronization signal PDATA. It waits for the input of the synchronization signal HSYNC.

  Therefore, between the two image data transfer circuits 20C and 20K, the main scanning synchronization signal HSYNC and the pseudo sub scanning synchronization signal (correlated sub scanning synchronization signal PDATA) are synchronized. Data transfer is always performed in the “normal” state shown in Table 1.

  In this way, by sending the same correlated sub-scanning synchronization signal PDATA (pseudo sub-scanning synchronization signal VSYNC) to the two image data transfer circuits 20C and 20K, the main scanning synchronization signal HSYNC input to each of them is transmitted. As a result, the transfer timing becomes unambiguous.

[Second Embodiment]
The second embodiment of the present invention will be described below. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description of the configuration is omitted.

  In the first embodiment, an image data transfer circuit (in the first embodiment, the image data transfer circuit 20Y) that is not applied to monochrome dual beam printing is used, and the sub-scanning synchronization signal VSYNC is used as the image. The data is transferred to the data transfer circuit 20Y, and the image data transfer circuit 20Y generates the correlated sub-scanning synchronization signal PDATA and sends it to the respective image data transfer circuits 20C, so that the image data transfer circuits 20C and 20K have the correlation. The sub-scanning synchronization signal PDATA is recognized as the sub-scanning synchronization signal VSYNC.

  On the other hand, in the second embodiment, the correlated sub-scanning synchronization signal PDATA is generated using only the two image data transfer circuits 20C and 20K applied to monochrome dual beam printing.

  As shown in FIG. 6, the main scanning synchronization signal HSYNC is input to both the image data transfer circuits 20K and 20C, but the sub-scanning synchronization signal VSYNC is input only to the image data transfer circuit 20K.

  The image data transfer circuit 20K generates a correlated sub-scanning synchronization signal PDATA sufficiently delayed with respect to the main scanning synchronization signal HSYNC based on the input sub-scanning synchronization signal VSYNC, and sends it to the other image data transfer circuit 20C. To do.

  With such a configuration, the two image data transfer circuits 20K and 20C recognize the correlated sub-scanning synchronization signal PDATA as the sub-scanning synchronization signal VSYNC, and as shown in FIG. Be unique.

  In the second embodiment, since the sub-scanning synchronization signal VSYNC is input to the image data transfer circuit 20K, image data transfer may be performed based on the first sub-scanning synchronization signal VSYNC. . In order to avoid such a case, the “normal” image data transfer state shown in Table 1 can be obtained by sending blank data as shown in FIG.

  In the first and second embodiments, the case where the transfer destination print engine is a monochrome dual beam print engine has been described. However, in the first embodiment, a maximum of three beams are used. The present invention can be applied to a print engine that scans, and in the case of the second embodiment, it can be applied to a print engine that scans four beams.

  In this way, for a multi-beam print engine that scans two beams to form an image, image data for one page is placed every other line using two of the four transfer circuits. Since the data is transferred line by line, the image data can be transferred to the monochrome multi-beam print engine without changing the image data generation method corresponding to the multi-beam.

  In the first embodiment and the second embodiment, the configuration of the print controller 10 as shown in FIG. 1 is used. However, the configuration is not limited to the above-described circuit configuration. Hereinafter, modified examples (modified example 1 and modified example 2) of the configuration of the print controller 10 will be described. In addition, about the same component of FIG. 1, the same code | symbol is attached | subjected and description of the structure is abbreviate | omitted.

(Modification 1)
As shown in FIG. 10, in the first modification, image data is input only to the K channel, and a line dividing circuit 30 is connected to the K channel expander 24K. The line dividing circuit 30 divides the image data into odd lines (1, 3, 5... Lines) and even lines (2, 4, 6... Lines) and sends them to the selection circuit 32. It has become.

  The selection circuit 32 is connected to a C channel expander 24C. The selection circuit 32 selects whether the data to be input to the C-channel image shift circuit 26C is an output from the decompressor 24C or an even line from the line dividing circuit 30.

  Thereby, the image data input only to the K channel can be sent to the print engine 70 as a dual beam.

  In the first modification, the image data input destination is not limited to the K channel. Also, the number of divisions is not limited to dual (two divisions) and may be three or more divisions.

  In the first modification, the first embodiment can be applied if there are extra channels, and the second embodiment can be applied if there are no extra channels.

(Modification 2)
As shown in FIG. 11, in the second modification, image data is input only to the Y channel, and a line dividing circuit 34 is connected to the Y channel expander 24Y. In this line dividing circuit 34, the image data is divided into n (here, n = 4) (1, 5, 9... Line, 2, 6, 10,... Line, 3, 7, 11... Line. 4, 8, 12... Line), and is sent to the selection circuit 36.

  The selection circuit 36 is connected to decompressors 24M, 24C, and 24K for the M, C, and K channels. Thereby, the image data input only to the Y channel can be sent to the print engine 70 as four beams.

  In the second modification, since all the channels are applied as image formation, the configuration of the second embodiment can be applied.

FIG. 2 is a block diagram illustrating a configuration of a print controller according to the first embodiment. It is the figure which showed the outline | summary of the transfer process of 1st Embodiment. FIG. 3 is a block diagram for establishing proper black and white image data transfer timing in the image data transfer circuit according to the first embodiment. It is the flowchart which showed the setting process by CPU of 1st Embodiment. 3 is an image data transfer timing chart according to the first embodiment. FIG. 10 is a block diagram for establishing proper black and white image data transfer timing in an image data transfer circuit according to a second embodiment. 6 is an image data transfer timing chart according to the second embodiment. It is a block diagram of a conventional monochrome image data transfer circuit. It is a conventional monochrome image data transfer timing chart. FIG. 10 is a block diagram illustrating a configuration of a print controller according to a first modification. FIG. 10 is a block diagram illustrating a configuration of a print controller according to a second modification.

Explanation of symbols

10 Print controller 12 CPU
14 RAM
16 Image data transfer processing unit 18 Bus 20 (Y, M, C, K) Image data transfer circuit 22 (Y, M, C, K) DMAC
24 (Y, M, C, K) Expander 26 (Y, M, C, K) Image shift circuit 28 (Y, M, C, K) Image cropping circuit 60 Timing generation circuit 70 Print engine 70A Black and white dual beam printing Engine HSYNC main scan sync signal VSYNC sub scan sync signal PDATA correlation sub scan sync signal

Claims (3)

An image data transfer method in which image data is distributed and transferred in units of main scanning lines to a predetermined channel using transfer circuits of two or more channels,
When the main scanning synchronization signal and the sub-scanning synchronization signal are asynchronous with each other,
Sending the main scanning synchronization signal to each of the transfer circuits of two or more channels;
Sending the sub-scanning synchronization signal only to one channel transfer circuit of the two or more channel transfer circuits,
In the transfer circuit of the channel to which the sub-scanning synchronization signal is input, based on the input sub-scanning synchronization signal and the input main-scanning synchronization signal, the timing is shifted from the main-scanning synchronization signal by a predetermined time. Generating a correlated sub-scan sync signal that is synchronized with the main scan sync signal;
Sending the correlated sub-scanning synchronization signal from the transfer circuit of the channel to which the sub-scanning synchronization signal is input to the input terminal of the sub-scanning synchronization signal in the transfer circuit of the other channel to which the main-scanning synchronization signal is input,
In the transfer circuit of the channel to which the correlated sub-scanning synchronization signal is input, the distributed image data of the main scanning line unit is obtained based on the input main-scanning synchronization signal and the input correlated sub-scanning synchronization signal. An image data transfer method comprising transferring the image data. An image data transfer device that uses two or more transfer circuits and distributes and transfers image data to a predetermined channel in units of main scanning lines.
When the main scanning synchronization signal and the sub scanning synchronization signal are asynchronous with each other, the main scanning synchronization signal is sent to each of the two or more channel transfer circuits, and the sub scanning synchronization signal is sent to the two or more channel transfer circuits. Sending means for sending only to one channel of the transfer circuit,
Based on the input sub-scanning synchronization signal and the input main-scanning synchronization signal, a correlated sub-scanning synchronization signal is generated that is synchronized with the main-scanning synchronization signal at a timing shifted from the main-scanning synchronization signal by a predetermined time. And a first transfer means for sending the correlated sub-scanning synchronization signal to the input terminal of the sub-scanning synchronization signal in the transfer circuit of another channel to which the main scanning synchronization signal is input,
A second image data transfer unit for transferring the distributed main scan line unit image data based on the main scanning synchronization signal sent from the sending unit and the correlated sub-scanning synchronizing signal sent from the first transfer unit ; Transfer means;
An image data transfer device comprising: An image data transfer device that distributes black and white dual-beam image data in units of main scanning lines to two channels of the four-channel image data transfer circuit corresponding to each of four color images for color printing. There,
When the main scanning synchronization signal and the sub-scanning synchronization signal are asynchronous with each other, the main scanning synchronization signal is sent to each of the two-channel transfer circuits and to one channel transfer circuit other than the two-channel transfer circuit. And a sending means for sending the sub-scanning synchronization signal only to the transfer circuit of the one channel;
Based on the input sub-scanning synchronization signal and the input main-scanning synchronization signal, a correlated sub-scanning synchronization signal is generated that is synchronized with the main-scanning synchronization signal at a timing shifted from the main-scanning synchronization signal by a predetermined time. And a first transfer means for sending the correlated sub-scanning synchronization signal to the input end of the sub-scanning synchronization signal of each of the two-channel transfer circuits;
A second image data transfer unit for transferring the distributed main scan line unit image data based on the main scanning synchronization signal sent from the sending unit and the correlated sub-scanning synchronizing signal sent from the first transfer unit ; Transfer means;
An image data transfer device comprising:

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