JP2019164559A - Image processor and image processing method - Google Patents

Abstract

To perform debug output with one operation.SOLUTION: An image processor includes: an image path selection part which selects an input path inputting image data to an image processing module during an actual operation and an output path outputting image data processed from the path after the image processing module; and a control signal selection part which synchronizes different control signals of the image processing module corresponding to the selected input path and output path.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an image processing apparatus and an image processing method.

  Conventionally, there is a technique for confirming the operation of an image processing function in an internal circuit of an ASIC for image processing. For example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2007-43571) discloses a technique for inputting image data and acquiring the output of the corresponding image processing module when processing by the image processing module to be debugged is completed. Has been.

  However, the conventional technique has a problem that it is difficult to compare with a series of processing results of image processing in the image processing apparatus. For example, since the prior art acquires the output of the image processing module to be debugged, it cannot obtain a series of processing results of image processing in the image processing apparatus.

  The present invention has been made in view of the above, and an object of the present invention is to perform debug output with a single operation.

  In order to solve the above-described problems and achieve the object, an image processing apparatus according to the present invention is processed from an input path for inputting image data to an image processing module in actual operation and a path after the image processing module. An image path selection unit that selects an output path for outputting the image data; and a control signal selection unit that synchronizes different control signals of the image processing modules corresponding to the selected input path and the output path.

  According to the present invention, it is possible to perform debug output with a single operation.

FIG. 1 is a diagram illustrating an internal configuration example of the image processing apparatus according to the first embodiment. FIG. 2 is a diagram illustrating a configuration example of a control system of the image processing apparatus according to the first embodiment. FIG. 3 is a diagram illustrating an example of a clock system in the engine image processing unit according to the first embodiment. FIG. 4 is a block diagram illustrating a configuration example of the read image processing unit according to the first embodiment. FIG. 5 is a block diagram illustrating a configuration example of the image debug interface unit according to the first embodiment. FIG. 6 is a diagram for explaining an example of delay adjustment in the image processing module according to the first embodiment. FIG. 7 is a diagram for explaining an example of image transfer via a line FIFO when no delay adjustment is performed. FIG. 8 is a diagram for explaining an example of image transfer via a line FIFO when no delay adjustment is performed. FIG. 9 is a diagram for explaining an example of image transfer via a line FIFO when delay adjustment according to the first embodiment is performed. FIG. 10 is a diagram for explaining an example of image transfer via a line FIFO when delay adjustment according to the first embodiment is performed. FIG. 11 is a diagram illustrating an example when the line cycle of the internal image path is short. FIG. 12 is a diagram for explaining an example of an image data output method when the line cycle of the internal image path is short according to the first embodiment. FIG. 13 is a diagram for explaining an example of an image data output method when the line cycle of the internal image path is short according to the first embodiment. FIG. 14 is a diagram for explaining an example of an image data output method when the line cycle of the internal image path is short according to the first embodiment.

  Embodiments of an image processing apparatus and an image processing method according to the present invention will be described below with reference to the accompanying drawings. In addition, this invention is not limited by the following embodiment.

(Embodiment 1)
The internal configuration of the image processing apparatus 1 according to the first embodiment will be described with reference to FIG. FIG. 1 is a diagram illustrating an internal configuration example of an image processing apparatus 1 according to the first embodiment.

  As shown in FIG. 1, the image processing apparatus 1 includes an image processing unit 10, a contact glass 11, an image forming station 12a, an image forming station 12b, an image forming station 12c, and an image forming station 12d. The image processing apparatus 1 also includes an intermediate transfer belt 13, a transfer roller 14, a fixing roller 15, a first paper feed tray 16, a second paper feed tray 17, an automatic document feeder 20, and a document feed. It has a table 21, a paper discharge tray 22, a transport roller 23, and a 3-bin sorter 30.

  An automatic document feeder (ADF) 20 guides a document placed on a document feeder 21 onto the contact glass 11. Then, the automatic document feeder 20 reads each document once. At that time, the conveyance roller 23 is driven or driven to convey the document. Then, the automatic document feeder 20 discharges the document to the discharge tray 22 after the CCD (Charge Coupled Device) 120 (see FIG. 2) or the CIS (Contact Image Sensor) 130 (see FIG. 2) reads the document. Let

  The image processing unit 10 generates an RGB image by causing the CCD 120 and the CIS 130 to read the document placed on the contact glass 11 or the document conveyed by the automatic document feeder 20 once. Then, the image processing unit 10 generates a CMYK image or a monoK image converted from the RGB image. Here, the RGB image is color image information having each color of R (red), G (green), and B (blue). The CMYK image is color image information having each color of C (cyan), M (magenta), Y (yellow), and K (black). That is, the CMYK image has four versions of image information of a C image, an M image, a Y image, and a K image. The monoK image is monochrome image information having a K (black) color. Then, the image processing unit 10 prints a CMYK image or a monoK image on a sheet depending on whether the document is a color document or a monochrome document.

  The image forming stations 12a to 12d create toner images of respective colors of C (cyan), M (magenta), Y (yellow), and K (black). The image forming stations 12a to 12d are arranged along the intermediate transfer belt 13 at a predetermined interval. The image forming stations 12a to 12d have the same configuration except that the toner colors are different. In the following description, when the image forming stations 12a to 12d are not distinguished, they are referred to as image forming stations 12.

  The image forming station 12 includes a photosensitive drum 121, a developing unit (not shown), and an LD (Laser Diode) 140 (see FIG. 2). When the LD 140 emits laser light, the photosensitive drum 121 forms an electrostatic latent image on the surface. The developing unit applies toner to the photosensitive drum 121 on which the electrostatic latent image is formed. The toner remains in the portion irradiated with the laser beam and does not remain in the portion not irradiated with the laser beam. Each image forming station 12 is implemented in each color of C (cyan), M (magenta), Y (yellow), and K (black). As a result, toner images of C, M, Y, and K colors corresponding to the image information are formed on the photosensitive drum 121, respectively.

  The toner image formed on the photosensitive drum 121 is transferred to the intermediate transfer belt 13. In the case of a color original, the image forming station 12 serving as an image forming unit forms a color image by sequentially superimposing and transferring toner images of C, M, Y, and K colors. On the other hand, in the case of monochrome, the image forming station 12 forms a monochrome image by transferring only the K color.

  The transfer roller 14 transfers the image formed on the intermediate transfer belt 13 to a sheet. The fixing roller 15 fixes the image transferred on the paper. Then, the sheet is discharged from the image processing apparatus 1. The first paper feed tray 16 and the second paper feed tray 17 are loaded with paper before an image is formed.

  The 3-bin sorter 30 has a stapler and a shift tray. Then, the 3-bin sorter 30 can bind the paper on which the image is fixed in a predetermined number according to an instruction based on the print job.

  Next, the configuration of the control system of the image processing apparatus 1 according to the first embodiment will be described with reference to FIG. FIG. 2 is a diagram illustrating a configuration example of a control system of the image processing apparatus 1 according to the first embodiment.

  As illustrated in FIG. 2, the image processing apparatus 1 includes an engine control unit 100 and a controller unit 200. The engine control unit 100 controls document reading processing, paper writing processing, and various image processing. The controller unit 200 receives print data input from an external interface, distributes a scanner image, and stores image data.

  The engine control unit 100 includes an engine CPU (Central Processing Unit) 110, a CCD 120, a CIS 130, an LD 140, an engine image memory 150, and an engine image processing unit 160.

  The engine CPU 110 comprehensively controls the engine control unit 100. The CCD 120 reads an original on the contact glass 11 and generates an RGB image. The CIS 130 reads a document conveyed by the automatic document feeder 20 and generates an RGB image. Then, the CCD 120 and the CIS 130 read each original once. The image processing apparatus 1 has two of the CCD 120 and the CIS 130, so that both sides of the document can be read simultaneously. The engine image memory 150 stores image data read by the CCD 120 and the CIS 130. The LD 140 irradiates the photosensitive drum 121 with a laser beam modulated based on image data to be printed to form an image.

  The engine image processing unit 160 includes a reading control unit 161, a reading control unit 162, a memory control unit 163, a reading image processing unit 164, and a serial communication control unit 165. The engine image processing unit 160 includes a write control unit 166, a write image processing unit 167, a register IF 168, and an image debug interface unit 169. The engine image processing unit 160 executes various image processes.

  The register IF 168 controls reading and writing of data between the engine CPU 110 and a setting register in the engine control unit 100. The reading control unit 161 and the reading control unit 162 control reading of a document by the CCD 120 and the CIS 130 and transfer image data for the read document to the memory control unit 163. The memory control unit 163 stores image data for the document read by the CCD 120 or the CIS 130 in the engine image memory 150. Further, the memory control unit 163 acquires image data stored in the engine image memory 150 and transfers it to the read image processing unit 164. When image data is simultaneously input from the CCD 120 and the CIS 130 (during simultaneous reading on both sides), the memory control unit 163 stores each image data in the engine image memory 150 and engine image data on the front side or back side for each side. Read from the image memory 150.

  The read image processing unit 164 performs MTF (Modulation Transfer Function) correction, smooth filter correction, generation of a CMYK image from an RGB image, generation of a monoK image from an RGB image, color correction, and image processing of the image data read by the CCD 120 and the CIS 130. , Scaling, encoding (compression processing), etc. are executed. The serial communication control unit 165 connects the engine control unit 100 and the controller unit 200. For example, the connection between the engine control unit 100 and the controller unit 200 uses a high-speed serial IF such as PCI (Peripheral Component Interconnect) -Express.

  The writing control unit 166 controls the laser beam irradiation to the photosensitive drum 121 by the LD 140. The writing image processing unit 167 outputs the image information output from the controller unit 200 to the LD 140 at a timing depending on the interval between the photosensitive drums 121. In the image processing by the writing image processing unit 167, normal color (CMYK) image data composition (decompression processing), normal color image data gradation processing, image shift processing for each plate, total amount control processing of image data, and the like are executed. Is done. The image debug interface unit 169 inputs and outputs image data with respect to the image path between the image processing modules.

  The controller unit 200 includes a controller memory 210, an HDD (Hard Disk Drive) 220, a controller CPU 230, an external IF control unit 240, and a controller image processing unit 250. The controller unit 200 receives print data from the outside, distributes a scanner image, stores image data, and the like.

  The controller CPU 230 controls the controller unit 200, translates print data, draws a print image, draws a stamp image, draws a copy-forgery-inhibited pattern image, compresses JPEG (Joint Photographic Experts Group) data, and decompresses JPEG data to an image. Execute the process. The controller CPU 230 stores the input image data in the controller memory 210. The controller memory 210 stores various programs and rewritable various data. For example, the controller memory 210 is a work memory used for temporarily storing received print data, a print image, a stamp image, a copy-forgery-inhibited pattern image, a normal color image, a read image, and the like. The HDD 220 stores various programs and images. The external IF control unit 240 controls connection with an external communication device connected via a network. For example, the external IF control unit 240 controls image transfer to the outside and input of print data from the outside.

  The controller image processing unit 250 includes a serial communication control unit 251, an input controller 252, an output controller 253, a controller internal bus control unit 254, and a serial communication control unit 255. The controller image processing unit 250 includes a rotator 256, an editor 257, a compressor 258, a decompressor 259, and an HDD controller 260. The controller image processing unit 250 executes various image processes.

  The serial communication control unit 251 connects the controller unit 200 and the engine control unit 100. The input controller 252 receives input of image data from the engine control unit 100 and transfers it to the controller memory 210. The output controller 253 transfers the image data stored in the controller memory 210 to the engine control unit 100. In the controller image processing unit 250, the controller internal bus control unit 254 arbitrates bus switching between blocks and image data transfer. The serial communication control unit 255 connects the controller image processing unit 250 and the controller CPU 230.

  A rotator 256 and an editor 257 execute image processing of a printer image and a read image. The compressor 258 performs data compression when storing a printer image or a read image. The decompressor 259 executes processing for returning the compressed saved data to the original image data. The HDD controller 260 executes data write control and data read control on the HDD 220.

  Next, a clock system in the engine image processing unit 160 according to the first embodiment will be described with reference to FIG. FIG. 3 is a diagram illustrating an example of a clock system in engine image processing unit 160 according to the first embodiment.

  As shown in FIG. 3, the reading control unit 161 controls reading of a document by the CCD 120 and transfers image data for the read document to the memory control unit 163. For example, the clock system of the reading control unit 161 is clk_ccd. In addition, the reading control unit 162 controls reading of a document by the CIS 130 and transfers image data for the read document to the memory control unit 163. For example, the clock system of the reading control unit 162 is clk_cis. At this time, the reading control unit 161 and the reading control unit 162 convert the image data transferred as the LVDS (Low Voltage Differential Signaling) signal from the LVDS signal to the video signal. After the reading control unit 161 and the reading control unit 162, image transfer using video signals (fgate, lsync, lgate, data) is performed.

  The memory control unit 163 stores the image data for the document read by the CCD 120 or the CIS 130 in the engine image memory 150, acquires the image data stored in the engine image memory 150, and transfers it to the read image processing unit 164. For example, the clock system of the memory control unit 163 is lsync_wait.

  FIG. 4 is a block diagram illustrating a configuration example of the read image processing unit 164 according to the first embodiment. As shown in FIG. 4, the read image processing unit 164 includes an image path selection unit 164a, a filter processing unit 164b, a color correction unit 164c, a read image processing unit 164d, and a compression unit 164e. The filter processing unit 164b performs smoothing processing, edge enhancement processing, and the like to improve image quality. The color correction unit 164c creates a CMYK image for full color output from the RGB image. The read image processing unit 164d performs specified resolution, scaling, enlargement / reduction, and adjustment of the image position. The compression unit 164e compresses the CMYK raw image in order to reduce the burden on the subsequent serial communication control unit 165. For example, the compression method includes fixed value compression and JPEG compression. For example, the clock system of the read image processing unit 164 is clk_scan.

  For example, in FIG. 4, the image path selection unit 164a can input and output image data before and after each module for debugging. Depending on the selected image path, the image data may be input from a block before the read image processing unit 164, or may be output to a block after the read image processing unit 164. . Note that the image data may be test image data. Image data suitable for each image processing module can be prepared by using the test image data. Further, by using the test image data, it is possible to confirm a suitable setting value (mode or the like) of the image processing apparatus 1 for any input image data.

  The writing image processing unit 167 includes, for example, an expansion unit, a writing image processing unit, a total amount regulating unit, and a gradation processing unit. The decompression unit develops the compressed data stored in the HDD 220 or the controller memory 210 by the controller unit 200 into a CMYK raw image. The writing image processing unit adjusts and trims the printing position. The total amount regulating unit reduces the density of each color so that the added value of the input CMYK image data falls within the upper limit value in order to prevent fixing errors due to toner overlap. The gradation processing unit converts the number of gradations of the input image data into a number of gradations suitable for printing. For example, the clock system of the write image processing unit 167 is clk_prt. The writing control unit 166 converts the video signal into a control signal output to the LD 140. For example, the clock system of the write control unit 166 is clk_ld.

  The image debug interface unit 169 selects an image path to be input / output from image paths selected in each unit grouped for each clock system, and performs an interface with the outside. The image debug interface unit 169 can accurately input / output image data with different clock systems by moving the internal circuit according to the clock system corresponding to the selected image path. That is, the image debug interface unit 169 selects a clock system corresponding to each unit from different clock systems, and transfers image data in units of lines. For example, the clock system of the image debug interface unit 169 is clk_dbg.

  In other words, the image debug interface unit 169 synchronizes different clock systems in each unit when inputting image data to the selected path or acquiring image data from the selected path, and inputs the image data. Make the output accurate. In each of the above-described units, an image path selection unit (an image path selection unit 161a, an image path selection unit 162a, an image path selection unit 164a, an image path selection unit, in order to input / output image data to / from the selected image path. 166a, an image path selection unit 167a, and an image path selection unit 169a) are arranged.

  Next, the configuration of the image debug interface unit 169 according to the first embodiment will be described with reference to FIG. FIG. 5 is a block diagram illustrating a configuration example of the image debug interface unit 169 according to the first embodiment.

  As shown in FIG. 5, the image debug interface unit 169 includes an image path selection unit 169a, an image clock selection unit 169b, an output write control unit 169c, an output FIFO 169d, an output FIFO 169e, and an output read control unit 169f. And have. The image debug interface unit 169 includes a debug interface external control unit 169g, an input write control unit 169h, an input FIFO 169i, an input FIFO 169j, and an input read control unit 169k.

  The image path selection unit 169a selects an image path to be input / output to each unit having a different clock system. The image clock selection unit 169b selects a clock system according to the image path selected by the image path selection unit 169a. As a result, different clock systems can be synchronized in each unit, and processing in each unit can be executed, thereby preventing the occurrence of an asynchronous path. For example, the interface with the outside is transferred on the board, and since it is difficult to transfer the image with a high-speed clock inside the image processing, it is performed with a low-frequency clock (clk_dbg). For this reason, the line FIFO is toggled for speed conversion between the internal clock and the debug clock. The line FIFO is prepared for output and input. As a result, simultaneous input / output operations are possible.

  The output light control unit 169c inputs image data for output of the image path selected by the image path selection unit 169a to the output FIFO 169d and the output FIFO 169e. As described above, the output FIFO 169d and the output FIFO 169e are alternately switched by toggle, and image data is input. The output read control unit 169f acquires image data from the output FIFO 169d and the output FIFO 169e, and transfers the image data to the debug interface external control unit 169g. The debug interface external control unit 169g transfers the image data to the selected image path and inputs the image data acquired from the selected image path.

  The input write control unit 169h inputs the image data input from the debug interface external control unit 169g to the input FIFO 169i and the input FIFO 169j. As described above, the input FIFO 169i and the input FIFO 169j are alternately switched by toggle to input image data. The input read control unit 169k acquires image data from the input FIFO 169i and the input FIFO 169j and transfers the image data to the image path selection unit 169a.

  Next, delay adjustment in the image processing module according to the first embodiment will be described with reference to FIG. FIG. 6 is a diagram for explaining an example of delay adjustment in the image processing module according to the first embodiment. The image processing module refers to an image processing module included in each unit such as the filter processing unit 164b and the color correction unit 164c (see FIG. 4).

  As illustrated in FIG. 6, the image processing module 170 includes a delay adjustment unit 171, an image selection unit 172, and an internal processing unit 173. Each image processing module 170 in each unit performs image processing using a video signal of the same control method. Normal control signals (lsync, fgate, lgate) are prepared. These signals are used in the image debug interface unit 169 to eliminate line delay and pixel delay when the line FIFO is toggled. That is, when the line FIFO is toggled, line delay and pixel delay are generated by switching the FIFO and inputting or outputting image data. Therefore, delay adjustment processing is performed to eliminate the generated delay. . In the image processing module 170, dbg_fgate and dbg_lgate are also synchronized with the delay of the normal control signal.

  That is, the image selection unit 172 inputs the input image data to the internal processing unit 173. The internal processing unit 173 performs some image processing on the image data and outputs it. At this time, the delay adjustment unit 171 performs synchronization in accordance with the line delay or pixel delay when the line FIFO is toggled.

  FIG. 7 is a diagram for explaining an example of image transfer via a line FIFO when no delay adjustment is performed. FIG. 7 shows an example of outputting an image.

  As shown in FIG. 7, when fgate and dbg_fgate are the same line and pass through the toggle line FIFO, when outputting an image, invalid data is generated in the first line of the output image data, and the final line is output. May not be.

  FIG. 8 is a diagram for explaining an example of image transfer via a line FIFO when no delay adjustment is performed. FIG. 8 shows an example of inputting an image.

  As shown in FIG. 8, when inputting an image, invalid data may be generated in the first line of the image data input to the image path and may not be input until the last line. At this time, a failure occurs in the debug result (for example, an edge portion of the debug result is not normal).

  FIG. 9 is a diagram for explaining an example of image transfer via a line FIFO when delay adjustment according to the first embodiment is performed. FIG. 9 shows an example of outputting an image.

  As shown in FIG. 9, in the case of outputting an image, dbg_fgate is delayed by one line with respect to the normal fgate of the image path, so that all the flowing lines can be output. For an image in a line, the circuit delay can be corrected and all the pixels in the line can be output by setting the pixel delay pixdly in dbg_lgate with respect to the normal lgate of the image path.

  FIG. 10 is a diagram for explaining an example of image transfer via a line FIFO when delay adjustment according to the first embodiment is performed. Note that FIG. 10 shows an example of inputting an image.

  As shown in FIG. 10, when inputting an image, by generating dbg_fgate one line before the normal fgate of the image path, all the lines of image data from the outside are input to the internal image path. be able to. Also, for the image in the line, the pixel delay pixdly is set in the negative direction in dbg_lgate with respect to the normal lgate of the image path, so that the pixel delay to the internal circuit is corrected and all the lines in the line from the outside are corrected. Pixels can be input.

  FIG. 11 is a diagram illustrating an example when the line cycle of the internal image path is short.

  In the image processing apparatus 1, when processing is performed at a high speed such as a double-sided simultaneous reading operation, the clock frequency is also increased, so that the line cycle for performing line transfer is also shortened. As shown in FIG. 11, since the interface with the outside cannot output with a high-frequency clock, reading from the FIFO of the image debug interface unit 169 may not end during the line cycle. Note that FIG. 11 shows that output is possible only halfway through the internal image path. Hereinafter, a method for outputting image data when the line cycle is short will be described.

  FIG. 12 is a diagram for explaining an example of an image data output method when the line cycle of the internal image path is short according to the first embodiment.

  As shown in FIG. 12, the image data on the internal image path is cut out with the xoffset and xwidth setting values and output to the outside. The cut-out size is a size that can be output to the outside during the line cycle. In FIG. 12, a case where the cutout size is from a to a + w is taken as an example. By switching xoffset, it is possible to adjust to the position of the image data to be confirmed (arbitrary position can be confirmed). For example, it is possible to confirm only a portion having a feature in the image data.

  FIG. 13 is a diagram for explaining an example of an image data output method when the line cycle of the internal image path is short according to the first embodiment.

  As illustrated in FIG. 13, the internal lsync is stopped using the lsync_wait signal until image output to the outside is completed. Thereby, all the line image data of the internal image path can be output. For example, when the logic of the lsync_wait signal is 1, lsync generation is prohibited, and when it is 0, lsync generation is permitted.

  FIG. 14 is a diagram for explaining an example of an image data output method when the line cycle of the internal image path is short according to the first embodiment.

  As shown in FIG. 14, when dbg_data is 8 bits, when image data is stored in the FIFO, it is expanded to a 16-bit width and saved. In other words, it is a method that copes by expanding the bus width. When reading image data from the FIFO, 16 bits can be output in one clock, so even if the transfer rate is doubled and the internal line cycle is short, it is output to the outside using the slow clk_dbg. Can do. The same applies to image input, and image data may be expanded from 16 bits to 8 bits.

  As described above, the image processing apparatus 1 selects an image data input / output path for the image processing module in actual operation, and synchronizes with the control signal corresponding to the selected path. Can be output.

  Information including processing procedures, control procedures, specific names, various data, parameters, and the like shown in the above documents and drawings can be arbitrarily changed unless otherwise specified. Each component of the illustrated apparatus is functionally conceptual and does not necessarily need to be physically configured as illustrated. That is, the specific form of the distribution or integration of the devices is not limited to the illustrated one, and all or a part of the distribution or integration is functionally or physically distributed or arbitrarily in any unit according to various burdens or usage conditions. Can be integrated.

DESCRIPTION OF SYMBOLS 1 Image processing apparatus 160 Engine image processing part 161 Reading control part 161a Image path selection part 162 Reading control part 162a Image path selection part 163 Memory control part 164 Read image processing part 164a Image path selection part 165 Serial communication control part 166 Write control part 166a Image path selection unit 167 Write image processing unit 167a Image path selection unit 169 Image debug interface unit 169a Image path selection unit 169b Image clock selection unit

JP 2007-43571 A

Claims (6)

An image path selection unit for selecting an input path for inputting image data to an image processing module in actual operation, and an output path for outputting the image data processed from the path after the image processing module;
An image processing apparatus comprising: a control signal selection unit that synchronizes different control signals of image processing modules corresponding to the selected input path and output path. A delay adjustment unit that eliminates line delay and pixel delay of the image data when image data input to the image processing module and image data output from the image processing module are alternately stored and retrieved; The image processing apparatus according to claim 1. The image processing apparatus according to claim 2, wherein the image data is cut out according to a predetermined size including a set position. The image processing apparatus according to claim 2, wherein the image data is stored with an expanded image data width. The delay adjusting unit inputs the image data one line before the control signal of the selected input path, and delays the image by one line with respect to the control signal of the selected output path. The image processing apparatus according to claim 2, wherein data is output. An image processing method executed in an image processing apparatus,
Selecting an input path for inputting image data to an image processing module in actual operation, and an output path for outputting the image data processed from the path after the image processing module;
Synchronizing the different control signals of the image processing module corresponding to the selected input path and output path.

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