JP2010056649A - Data transmission circuit, image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transmission circuit which reduces skew between data as much as possible. <P>SOLUTION: The apparatus includes: clock delay circuits 210 to 212 with a series circuit of output buffers 361 to 368 and a selector 369; detection circuits 310 to 312 with output buffers 371 to 378, a PLL circuit 379, flip-flops FF1 to FF8, and a register 380; a first detection unit 414 which detects clock signals output from the clock delay circuits 210 to 212 to parallel conversion circuits 201 to 203 in a case that a combination of output signals output from the respective output buffers 371 to 378 agree with one determined beforehand when a pattern signal predetermined beforehand is transmitted on a transmission route; and a clock signal setting unit 415 which establishes the clock signal as a clock signal to be output from the delay circuit 210 in a normal mode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a data transmission circuit for transmitting data and an image forming apparatus using the same.

  In an apparatus that handles a large amount of data, such as an image forming apparatus such as a copying machine, a printer, a facsimile apparatus, and a multifunction machine of these, for example, between a scanner that acquires a document image and an image processing circuit, or between an image processing circuit and an image It is necessary to transmit a large amount of data at high speed inside the apparatus, such as with a forming circuit. Conventionally, a parallel bus has been generally used for data transmission inside such devices. As a method of improving the data transmission speed in the parallel bus, there are a method of increasing the bus width and a method of increasing the clock frequency of data transmission.

  However, image data handled by the image forming apparatus is represented by data corresponding to, for example, three colors of R, G, and B, and is represented by 8 to 10 bits for each color. In order to transmit such image data via a parallel bus, a bus width of 24 bits to 30 bits is required. Furthermore, in order to transmit such a signal at high speed, it is desirable to use a differential signal. However, if a differential signal is used, twice as many signal lines are required, and the number of parallel bus signal lines is 48 to 60. Become a book. If it does so, it will cause the increase in the cost of a signal cable or a connector. Further, an increase in the number of signals and an increase in the clock frequency increase the unnecessary radiation of electromagnetic waves, which is also a problem from the viewpoint of EMC (Electro Magnetic Compatibility).

  Therefore, in recent years, a serial bus that can reduce the number of signal lines is used for such data transmission in the apparatus.

  The following patent documents 1 and 2 are related to the data transmission technology in the image forming apparatus. In the following Patent Document 1, a clock whose frequency changes according to the writing density is used as a writing clock for image data, and writing is performed using image data sent from the image memory in synchronization with the writing clock. A technique in which an optical writing device of an image forming apparatus is provided with a latch circuit that latches image data by two write clocks whose phases are reversed, and a selection unit that selects image data latched by one write clock as write data Is disclosed.

In Patent Document 2 below, in an image processing apparatus that receives video data from the outside and transmits the video data to an image forming unit, a first clock generating unit that generates a first clock; Second clock generating means for generating a second clock having the same period as the clock of the second clock, N latch means for latching N video data for N periods in synchronization with the first clock, In synchronism with the second clock, there is provided selection means for sequentially selecting the N latch means, and video data latched in the latch means sequentially selected by the selection means is stored in the image forming means. There is a description to send.
JP-A-5-110822 JP 2002-44319 A

  By the way, the parasitic capacitance of the transmission path between the transmission side circuit and the reception side circuit that transmits the data varies among the transmission paths that transmit the data of each color, the transmission distance of the wiring in the apparatus, and the data transmission. A skew occurs between data due to variations in output buffer characteristics of wiring. In some cases, for example, a cable is dropped. When such a situation occurs, appropriate image data is not transmitted to the image forming unit, and an image having a color faithful to the original cannot be formed on the recording paper.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a data transmission circuit and an image forming apparatus that can reduce the skew between data as much as possible.

  According to the first aspect of the present invention, there is provided a transmission side including first and second serial signal generation units that respectively output first and second serial signals in synchronization with a clock signal output at a predetermined cycle. A circuit, a first parallel signal generator that converts the first serial signal output from the first serial signal generator into a parallel signal, and outputs the converted parallel signal as a first parallel signal; and A receiving side circuit including a second parallel signal generation unit that converts the second serial signal output from the second serial signal generation unit into a parallel signal and outputs the converted parallel signal as a second parallel signal; A data transmission circuit having first and second serial signals transmitted from the transmission-side circuit that are converted into the first and second parallel signals by the reception-side circuit, respectively. A mode setting unit that performs mode switching setting between the first mode and the second mode different from the first mode, and the mode setting unit sets the second mode in advance. An instruction unit for transmitting a predetermined pattern signal as a first pattern signal from the transmission side circuit, and a plurality of output buffers having a predetermined time shorter than the period of the clock signal as a delay time are connected in series, A first delay circuit unit for generating a delayed clock signal having a different delay time by each output buffer, and a first serial signal generation from among the delayed clock signals respectively output by each output buffer of the first delay circuit unit A first selection unit that alternatively selects a delayed clock signal to be output to the unit; and a plurality of output buffers having the predetermined time as a delay time Are connected in series, and each of the output buffers generates a delayed clock signal having a different delay time, and a delay clock signal output from each of the output buffers of the second delay circuit unit. A second selection unit that alternatively selects a delayed clock signal to be output to the second serial signal generation unit; and the first pattern signal is received from the first serial signal generation unit and the predetermined A first detection circuit unit comprising a series circuit of a plurality of output buffers having time as a delay time, and a signal acquisition unit that simultaneously acquires an output signal from each output buffer of the series circuit in synchronization with the clock signal; A series circuit of a plurality of output buffers that receive the first pattern signal from the second serial signal generation unit and have the predetermined time as a delay time; and The second detection circuit unit including a signal acquisition unit that simultaneously acquires an output signal from each output buffer of the series circuit in synchronization with the clock signal, and each signal acquisition unit of the first detection circuit unit acquires the output signal. The combination of the delayed clock signal output to the first serial signal generation unit and the output signal acquired by each signal acquisition unit of the second detection circuit unit when the combination of output signals is a predetermined combination Are detected in the mode, the first detection unit for detecting the delayed clock signal output to the second serial signal generation unit, and the delayed clock signal detected by the first detection unit as the mode. A clock signal setting that is set as a clock signal to be selected by the first and second selection units when the first mode is set by the setting unit. Those having a part.

  According to this invention, when the second mode is set by the mode setting unit, a predetermined pattern signal is set as a first pattern signal from the first and second serial signal generation units from the instruction unit. An instruction to send is output. Accordingly, the first pattern signal is output from the first and second serial signal generation units to the first and second detection circuit units.

  Here, since each output buffer of the first and second delay circuit units has a predetermined time shorter than the period of the clock signal as a delay time, the first and second delay circuit units are connected in series. Each output buffer generates a delayed clock signal that is different from each other by the delay time.

  Accordingly, when the target delayed clock signal to be output to the first and second serial signal generators is switched among these delayed clock signals, the first pattern signal is output from the first and second serial signal generators. Timing changes. As a result, the timing at which the first pattern signal is received by the first and second detection circuit units changes.

  Further, since each output buffer of the first and second detection circuit units has the predetermined time as a delay time, each output buffer connected in series of the first and second detection circuit units, First pattern signals received in the past by the first and second detection circuit units are generated at a plurality of timings having a time difference corresponding to the delay time.

  Therefore, when the target delay clock signal to be output to the first and second serial signal generation units is switched among the output buffers of the first and second delay circuit units, the first and second detection circuit units The first pattern signal output from each output buffer also changes.

  Using this, the delayed clock signal to be output to the first serial signal generation unit is switched by the first detection unit among the delayed clock signals generated in the output buffers of the first delay circuit unit, A delayed clock signal is searched when the combination of output signals of the output buffers acquired by the signal acquisition unit is a predetermined combination.

  Similarly, the clock signal to be output to the second serial signal generation unit is switched by the first detection unit among the delayed clock signals generated by the output buffers of the second delay circuit unit, and the signal acquisition is performed. The delay clock signal when the combination of output signals of each output buffer acquired by the unit becomes the predetermined combination is searched.

  Then, each delayed clock signal detected by the first detector is selected by the first and second selectors when the clock signal setting unit is set to the first mode by the mode setting unit. Each is set as a clock signal to be transmitted.

  Thus, the first and second serial signal generators detect the delays detected by the first detector during data transmission / reception between the transmitter circuit and the receiver circuit when the first mode is set. The first and second serial signals are transmitted to the receiving side circuit according to the clock signal and the clock signal.

  As described above, in the present invention, the timing at which the first and second parallel signal generators receive the first and second serial signals from the first and second serial signal generators is based on the period of the clock signal. It is adjusted on the order of the short predetermined time. Thereby, it is possible to prevent or suppress the occurrence of skew between data transmitted through each transmission path.

  According to a second aspect of the present invention, in the data transmission circuit according to the first aspect, the first and second parallel signals generated by the first and second parallel signal generation units are received, and the received A receiver configured to perform a predetermined process on the first and second parallel signals, and a first serial signal generator and a first parallel signal generator configured after the setting by the clock signal setting unit. A plurality of types of pattern signals whose phases are different from each other for each of the predetermined periods are transmitted to one transmission path and a second transmission path configured by the second serial signal generation unit and the second parallel signal generation unit. The second pattern signal is transmitted as a second pattern signal, and among the second pattern signals, the second pattern signal having the same reception timing received by the first and second parallel signal generators. A second detection unit that detects a combination of the second pattern signal and a phase before transmission of second pattern signals belonging to the combination detected by the second detection unit, and based on a phase difference obtained by the comparison, A reception timing setting unit that sets a timing at which the reception unit receives the first and second parallel signals output from the first and second parallel signal generation units.

  According to the present invention, when the setting by the clock signal setting unit is performed, the plurality of types of second pattern signals are transmitted to the first and second transmission paths according to an instruction from the second detection unit, and the second patterns thereof are transmitted. Among the signals, a combination of second pattern signals having the same timing received by the first and second parallel signal generators is detected.

  Then, the reception timing setting unit compares the phases before transmission of the second pattern signals belonging to the combination detected by the second detection unit, and based on the phase difference obtained by the comparison, the reception unit A reception timing for receiving the first and second parallel signals output from the first and second parallel signal generators is set.

  Specifically, for example, as in the third aspect of the invention, the reception timing setting unit has the earlier phase before transmission among the second pattern signals belonging to the combination detected by the second detection unit. It is detected whether the parallel signal having the same transmission path as the second pattern signal is the first parallel signal or the second parallel signal, and the reception timing of the detected parallel signal by the receiving unit is the phase difference. Only delayed.

  As described above, the first and second parallel signal generation units are connected to the first and second serial signal generation units from the first and second serial signal generation units in units of the clock signal period (in units of the predetermined period). The timing for receiving two serial signals is adjusted. As a result, it is possible to prevent or suppress the occurrence of skew between data transmitted through each transmission path.

  The invention according to claim 4 includes an image acquisition unit that acquires image data, and an image forming unit that forms an image on a recording sheet based on the image data acquired by the image acquisition unit, and the image acquisition unit 4. An image forming apparatus in which the data transmission circuit according to claim 1 is used in at least a part of a data transmission path for transmitting the image data to the image forming unit.

  According to the present invention, in an image forming apparatus comprising: an image acquisition unit that acquires image data; and an image formation unit that forms an image on recording paper based on the image data acquired by the image acquisition unit. In the data transmission circuit used in at least a part of the data transmission path for transmitting the image data from the image forming unit to the image forming unit, it is possible to prevent or suppress the occurrence of skew between the data.

  According to the present invention, since it is possible to prevent or suppress the occurrence of skew between data, it is possible to prevent a color image faithful to an original from being formed on a recording sheet. Can do.

  Embodiments of an image forming apparatus including a data transmission circuit according to the present invention will be described below with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted. FIG. 1 is a block diagram illustrating a configuration example of a multifunction peripheral as an example of an image forming apparatus. A multifunction peripheral is an apparatus having two or more functions relating to image formation, such as a copying function, a printer function, a facsimile function, and a scanner function.

  The multifunction device 1 includes a scanner unit 11, an image processing unit 21, a printer unit 31, a control unit 41, an operation panel unit 51, a facsimile communication unit 61, a network I / F unit 71, a parallel I / F unit 72, and a serial I / F. A unit 73, an HDD (hard disk drive) 74, and data transmission circuits 2 and 3 are provided.

  The scanner unit 11, the image processing unit 21, the printer unit 31, the data memory 36, the control unit 41, the operation panel unit 51, and the facsimile communication unit 61 realize a facsimile function. The image processing unit 21, the printer unit 31, the control unit 41, the operation panel unit 51, the network I / F unit 71, and the parallel I / F unit 72 realize a printer function. The scanner unit 11, the image processing unit 21, the printer unit 31, the control unit 41, and the operation panel unit 51 implement a copying function.

  The operation panel unit 51 is used for a user to perform operations related to a copy function, a printer function, a facsimile function, and the like. An operation instruction by the user, for example, a copy instruction for instructing copying of a document image is given to the control unit 41. To give. The operation panel unit 51 includes a display unit 52 having a touch panel and the like, and an operation key unit 53 having a start key, a numeric keypad, and the like.

  The display unit 52 includes, for example, a touch panel unit capable of color display combining a touch panel and an LCD (Liquid Crystal Display), displays various operation screens, and allows a user to perform an input operation. For example, when executing the facsimile function, the display unit 52 displays information on user selection, transmission destination selection, transmission setting, and the like, and an operation for the user to input various operation instructions by touching the part. Displays buttons, etc. The operation key unit 53 is used for inputting various instructions such as a copy execution start instruction or a facsimile transmission start instruction by the user.

  The scanner unit 11 optically acquires a document image and generates image data. The scanner unit 11 includes an exposure lamp 12 and a CCD (charge coupled device) 13. The scanner unit 11 irradiates the document with the exposure lamp 12 and receives the reflected light with the CCD 13 to read the document image. Then, the scanner unit 11 converts the image data corresponding to the read image into, for example, 8-bit red data RD [7: 0] indicating a red component and 8-bit green data GD [7: 0] indicating a green component. , And 8-bit blue data BD [7: 0] indicating a blue component.

  Then, for example, the scanner unit 11 includes red data RD [7: 0], green data GD [7: 0], blue data BD [7: 0], red data RD [7: 0], and green data GD [ 7: 0] and blue data BD [7: 0] are synchronized with the basic clock signal TxCLK, red data RD [7: 0], green data GD [7: 0], and blue data BD [ 7: 0], the control signal S1 indicating the effective vertical and horizontal synchronization timing is transmitted to the image processing unit 21 by the data transmission circuit 2.

  The image processing unit 21 performs various image processing on the image data. For example, the image processing unit 21 performs predetermined correction processing such as level correction and γ correction, image data compression or expansion processing, enlargement or reduction processing on image data obtained by being read by the scanner unit 11. Various image processing (processing processing) is performed. The image processing unit 21 includes an image memory 22 and stores processed image data or the like in the image memory 22 or outputs the image data to the printer unit 31, the facsimile communication unit 61, the network I / F unit 71, or the like. The image processing unit 21 transmits image data stored in the image memory 22, for example, to the printer unit 31 by the data transmission circuit 3, and causes the printer unit 31 to form an image.

  The printer unit 31 receives image data transmitted from the image processing unit 21 by the data transmission circuit 3, image data received from an external personal computer or the like via the network I / F unit 71, and an external facsimile apparatus by the facsimile communication unit 61. An image based on image data such as fax data received from the printer is printed on a predetermined recording sheet. The printer unit 31 includes a paper transport unit 32 having a paper feed cassette and paper feed rollers, an intermediate transfer body roller, a photosensitive drum, an image forming unit 33 having an exposure device and a developing device, and a transfer unit 34 having a transfer roller. In addition, a fixing unit 35 having a fixing roller and the like is included. Specifically, the paper transport unit 32 transports the recording paper to the image forming unit 33, the image forming unit 33 forms a toner image corresponding to the image data, and the transfer unit 34 transfers the toner image to the recording paper. The fixing unit 35 fixes the toner image on the recording paper to form an image.

  The facsimile communication unit 61 includes an encoding / decoding unit (not shown), a modulation / demodulation unit (not shown), and an NCU (Network Control Unit) (not shown), and an image of a document read by the scanner unit 11. Data is transmitted to another facsimile apparatus via a communication line 611 such as a telephone line, and image data transmitted from another facsimile apparatus is received. The encoding / decoding unit compresses and encodes image data to be transmitted, and decompresses and decodes received image data. The modem unit modulates the compressed and encoded image data into an audio signal. Or the received signal (audio signal) is demodulated into image data. The NCU controls connection with a facsimile machine as a transmission destination via a telephone line.

  The network I / F unit 71 uses a network interface (for example, 10 / 100base-TX) or the like, and performs various operations with a user side server connected via a communication line 711 such as a LAN (Local Area Network) or the Internet. It controls the transmission and reception of data. When one or more communication terminal devices (not shown) such as a personal computer are connected to the communication line 711, the network I / F unit 71 transmits and receives various data to and from these communication terminal devices. Control. For example, the network I / F unit 71 transmits the document image data read by the scanner unit 11 as an e-mail to the communication terminal device or the image data transmitted from the communication terminal device for printing by the printer unit 31. Or receive.

  The parallel I / F unit 72 uses a high-speed bidirectional parallel interface (for example, IEEE1284 compliant) or the like to transmit print data from an external device or the like by parallel transmission in which data is transmitted in units of a plurality of bits using a plurality of signal lines. It is something to receive. The serial I / F unit 73 uses a serial interface (for example, RS-232C) or the like, and receives various data from an external device by serial transmission that sequentially transmits data bit by bit using a single signal line. To do.

  The HDD 74 stores image data read by the scanner unit 11, image data transmitted via a network, an output format set for the image data, and the like. The image data stored in the HDD 74 is not only used in the multifunction machine 1 but also confirmed by the communication terminal device via the network I / F unit 71 or transferred to a predetermined folder of the communication terminal device. As a result, it may be used in the communication terminal device.

  The control unit 41 includes a CPU (Central Processing Unit) (not shown), a RAM (Random Access Memory) or ROM (Read Only Memory) that stores a program that defines the operation of the CPU, and data temporarily. A RAM for storing data, peripheral devices thereof, and the like. As a result, the control unit 41 controls the entire multifunction device 1 in accordance with the instruction information received by the operation panel unit 51 and the like and the detection signals from the sensors provided in various parts of the multifunction device 1. More specifically, the control unit 41 functions as a scanner controller 42, a facsimile controller 43, a printer controller 44, and a copy controller 45.

  A program for realizing the above-described functions by being read by a computer as the control unit 41 is stored in a non-volatile and large-capacity external storage device such as the HDD 74 and is appropriately transferred to the main storage device such as the RAM. By doing so, it is also possible to provide execution by the CPU. The program can be supplied through a recording medium such as a ROM or a CD-ROM, or can be supplied through a transmission medium such as a network connected to the network I / F unit 71. The transmission medium is not limited to a wired transmission medium, and may be a wireless transmission medium. The transmission medium includes not only a communication line but also a relay device that relays the communication line, for example, a communication link such as a router.

  When the program is supplied through the ROM, the ROM in which the program is recorded is mounted on the control unit 41 so that the program can be executed by the CPU. When the program is supplied through a CD-ROM, the CD-ROM reader can be connected to, for example, the parallel I / F unit 72 and transferred to the RAM or HDD 74 for execution by the CPU. it can. When the program is supplied through a transmission medium, the program received through the network I / F unit 71 can be transferred to the RAM or the HDD 74 for execution by the CPU.

  The scanner controller 42 controls the operation of each unit used to realize the scanner function. Here, when the PC transmission function is realized, the scanner controller 42 uses the IP address stored in the data memory 36 for the image data of the document read by the scanner unit 11 by the network I / F unit 71. Direct transmission is performed via a communication line 711 to a designated communication terminal device.

  The facsimile controller 43 controls the operation of each unit used to implement the facsimile function. When the facsimile controller 43 performs facsimile transmission, the facsimile communication unit 61 designates the image data of the original read by the scanner unit 11 by designating a telephone number stored in the data memory 36, a facsimile machine or the like. Directly through the communication line 611.

  The printer controller 44 controls the operation of each unit used for realizing the printer function. The copy controller 45 controls the operation of each unit used for realizing the copy function.

  The data transmission circuit 2 transmits the image data output from the scanner unit 11 to the image processing unit 21 at high speed. The data transmission circuit 3 transmits the image data output from the image processing unit 21 to the image forming unit 33 at high speed. FIG. 2 is a block diagram showing an example of the configuration of the data transmission circuits 2 and 3. Since the data transmission circuit 2 and the data transmission circuit 3 are configured in the same manner, both are shown in FIG.

  Hereinafter, the configuration of the data transmission circuit 2 will be described. The data transmission circuit 2 illustrated in FIG. 2 includes a transmission side circuit 20 and a reception side circuit 30. The transmission side circuit 20 in the data transmission circuit 2 is disposed in the vicinity of the scanner unit 11, and signals indicating image data output from the scanner unit 11, that is, red data RD [7: 0], green data GD [7: 0], blue data BD [7: 0], the basic clock signal TxCLK, and the control signal S1 are transmitted to the reception side circuit 30 disposed in the vicinity of the image processing unit 21.

  The transmission side circuit 20 includes parallel-serial conversion units 201 to 203 (parallel serial conversion unit), a PLL (Phase Locked Loop) circuit 204, differential driver units 205, 206, and 207, and differential drivers 208 and 209.

  The reception side circuit 30 includes differential receivers 301, 302, 303, 304, and 305, termination resistors R1, R2, R3, R4, and R5, a PLL circuit 313, and serial-parallel conversion units 307, 308, and 309.

  The differential driver unit 205 and the differential receiver 301 are connected by a pair of cables 231, the differential driver unit 206 and the differential receiver 302 are connected by a pair of cables 232, and the differential driver unit 207 and the differential receiver 303 are connected. Are connected by a pair of cables 233, the differential driver 208 and the differential receiver 304 are connected by a pair of cables 234, and the differential driver 209 and the differential receiver 305 are connected by a pair of cables 235. As the cables 231, 232, 233, 234, and 235, for example, twisted pair cables are used.

  The PLL circuit 204 multiplies the basic clock signal TxCLK to generate a synchronous clock signal CLK1, and outputs it to clock delay circuits 210 to 212 described later. Since the parallel-serial converters 201 to 203 convert an 8-bit parallel signal into a serial signal, the multiplication factor is increased by 8 to generate a synchronous clock signal CLK1 indicating the period of the serial signal from the basic clock signal TxCLK synchronized with the parallel signal. Has been.

  For example, the scanner unit 11 is operating at a clock frequency of 50 MHz, and red data RD [7: 0], green data GD [7: 0], and blue data BD [7: 0] are 50 MHz basic clock signals TxCLK. Is changed in synchronization with the basic clock signal TxCLK by the PLL circuit 204, the synchronous clock signal CLK1 is set to 400 MHz.

  The clock delay circuits 210 to 212 generate the delayed clock signal TxCLK by delaying the basic clock signal TxCLK by the clock delay time, and output the delayed clock signal TxCLK to the parallel-serial converters 201 to 203. FIG. 3 is a circuit diagram showing an example of the configuration of the clock delay circuits 210-212.

  The clock delay circuits 210 to 212 have substantially the same configuration, and are configured using a series circuit of output buffers 361 to 368 and a selector 369 as shown in FIG. The basic clock signal TxCLK is delayed by a series circuit of output buffers 361 to 368 and is output to the selector 369 as a delayed clock signal TxCLK8.

  The selector 369 is input with delayed clock signals TxCLK1 to TxCLK7 which are output signals of the output buffers 361 to 367. Each of the output buffers 361 to 368 has a delay time ΔT shorter than the cycle of the synchronous clock signal CLK1.

  Then, the delayed clock signal TxCLK1 becomes a signal delayed by ΔT from the synchronous clock signal CLK, the delayed clock signal TxCLK2 becomes a signal delayed by 2 × ΔT from the synchronous clock signal CLK, and the delayed clock signal TxCLK3 is delayed by 3 × ΔT from the synchronous clock signal CLK. The delayed clock signal TxCLK4 is a signal delayed by 4 × ΔT from the synchronous clock signal CLK, the delayed clock signal TxCLK5 is a signal delayed by 5 × ΔT from the synchronous clock signal CLK, and the delayed clock signal TxCLK6 is compared with the synchronous clock signal CLK. The delayed clock signal TxCLK7 is a signal delayed by 7 × ΔT from the synchronous clock signal CLK, and the delayed clock signal TxCLK8 is a signal delayed by 8 × ΔT from the synchronous clock signal CLK. .

  The selector 369 selects any one of the basic clock signal TxCLK and the delayed clock signals TxCLK1 to TxCLK8 according to the control signal CLKSEL output from the control unit 41, and outputs the selected one to the parallel-serial conversion units 201 to 203. Accordingly, the clock delay circuits 210 to 212 can change the delay time according to the control signal CLKSEL output from the control unit 41.

  Returning to FIG. 2, the parallel-serial conversion units 201 to 203 are configured using, for example, shift registers. Then, the parallel-serial conversion unit 201 shifts the red data RD [7: 0], which is an 8-bit parallel signal, bit by bit in synchronization with, for example, the synchronous clock signal CLK1, so that the differential driver unit as the serial signal TxOUT2 Output to 205.

  The parallel-serial conversion unit 202 generates the serial signal TxOUT1 by shifting the green data GD [7: 0], which is an 8-bit parallel signal, bit by bit in synchronization with the synchronous clock signal CLK1, for example, and generates the serial signal TxOUT1. Is output to the differential driver unit 206.

  The parallel-serial conversion unit 203 shifts the blue data BD [7: 0], which is an 8-bit parallel signal, one bit at a time in synchronization with the synchronous clock signal CLK1, for example, to the differential driver unit 207 as the serial signal TxOUT0. Output.

  The differential driver unit 205 converts the serial signal TxOUT2 output from the parallel-serial conversion unit 201 into a differential signal, and transmits the differential signal to the differential receiver 301 via the cable 231. The differential driver unit 206 converts the serial signal TxOUT1 output from the parallel-serial conversion unit 202 into a differential signal, and transmits the differential signal to the differential receiver 302 via the cable 232. The differential driver unit 207 converts the serial signal TxOUT0 output from the parallel-serial conversion unit 203 into a differential signal, and transmits the differential signal to the differential receiver 303 via the cable 233.

  The differential driver 208 converts the control signal S1 output from the scanner unit 11 into a differential signal, and transmits the differential signal to the differential receiver 304 via the cable 234. The differential driver 209 converts the basic clock signal TxCLK output from the scanner unit 11 into a differential signal, and transmits the differential signal to the differential receiver 305 via the cable 235.

  Termination resistors R1, R2, R3, R4, and R5 are provided between the signal input terminals of the differential receivers 301, 302, 303, 304, and 305, respectively, and the impedances of the transmission lines are matched. Then, the differential receiver 301 receives the serial signal TxOUT2 and outputs it to the serial-parallel conversion unit 307 as the serial signal RxIN2. The differential receiver 302 receives the serial signal TxOUT1 and outputs it to the serial-parallel converter 308 as the serial signal RxIN1. The differential receiver 303 receives the serial signal TxOUT0 and outputs it as the serial signal RxIN0 to the serial-parallel converter 309. The differential receiver 304 receives the control signal S1 and outputs it to the reception control circuit 300. The differential receiver 305 receives the basic clock signal TxCLK and outputs it to the clock delay circuit 306 as the clock signal RxCLK. The reception control circuit 300 corresponds to the reception unit, and performs predetermined processing on the parallel signals received from the serial-parallel conversion units 307 to 309.

  The PLL circuit 313 multiplies the clock signal RxCLK, further inverts it to generate a synchronous clock signal CLKB, and outputs the synchronous clock signal CLKB to the serial-parallel converters 307, 308, and 309. The multiplication factor of the PLL circuit 313 is the same as the multiplication factor of the PLL circuit 204, for example, eight times.

  The clock delay circuit 306 delays the basic clock signal TxCLK by the clock delay time to generate a delayed clock signal RxCLK, and outputs the delayed clock signal RxCLK to the PLL circuit 313 and the reception control circuit 300. Since the configuration of the clock delay circuit 306 is substantially the same as the configuration of the clock delay circuits 210 to 212, the description thereof is omitted.

  The serial-parallel conversion units 307, 308, and 309 are configured using, for example, shift registers. Then, the serial-parallel conversion unit 307 converts the serial signal RxIN2 into red data RD [7: 0], which is an 8-bit parallel signal, by acquiring the serial signal RxIN2, for example, by shifting one bit at a time in synchronization with the synchronous clock signal CLKB. And output to the reception control circuit 300.

  The serial-parallel converter 308 converts the serial signal RxIN1 into green data GD [7: 0], which is an 8-bit parallel signal, by acquiring the serial signal RxIN1 while shifting it by one bit in synchronization with the synchronous clock signal CLKB, for example. Output to the reception control circuit 300.

  The serial-parallel conversion unit 309 converts the serial signal RxIN0 into blue data BD [7: 0], which is an 8-bit parallel signal, by acquiring the serial signal RxIN0 while shifting it bit by bit in synchronization with the synchronous clock signal CLKB, for example. Output to the reception control circuit 300.

  As shown in FIG. 4, the detection circuits 310 to 312 are configured using a series circuit of output buffers 371 to 378, a PLL circuit 379, flip-flops FF <b> 1 to FF <b> 8, and a register 380. The output buffers 371 to 378 and the FF1 to FF8 are associated with each other on a one-to-one basis, and the output terminals of the output buffers 371 to 378 are connected to the D terminals of the corresponding FF1 to FF8. Further, the CK terminals of FF1 to FF8 are connected to the output terminal of the PLL circuit 379, and the Q terminals of the FF1 to FF8 are connected to the register 380.

  The PLL circuit 379 has the same configuration as that of the PLL circuit 313, generates a synchronous clock signal CLKB obtained by multiplying the basic clock signal TxCLK, and outputs the synchronous clock signal CLKB to the CK terminals of the FF1 to FF8. The multiplication factor of the PLL circuit 379 is the same as the multiplication factor of the PLL circuit 313, for example, eight times.

  Each of the output buffers 371 to 378 has a delay time (same as the delay time ΔT) obtained by dividing the period of the synchronous clock signal CLKB by the number of these output buffers. Therefore, the series circuit of the output buffers 371 to 378 has a delay time corresponding to one cycle of the synchronous clock signal CLKB as a whole.

  The flip-flops FF1 to FF8 output the output signals of the corresponding output buffers to the register 380 in synchronization with the synchronous clock signal CLKB output from the PLL circuit 379.

The delay time of each output buffer 371 to 378 is a value T _CLKB / 8 obtained by dividing the cycle T _CLKB of the synchronous clock signal CLKB input to the CK terminals of FF1 to FF8 by the number (eight) of output buffers 371 to 378. Therefore, when the synchronous clock signal CLKB is output from the PLL circuit 379 at a certain timing, output signals obtained from the FF1 to FF8 (output buffers 371 to 378) are as follows.

That is, the output signal of FF1 is an output signal generated by the output buffer 371 at a timing T _CLKB / 8 past the timing at which the FF1 received the synchronous clock signal CLKB, and the output signal of FF2 is the FF2 Is an output signal generated by the output buffer 372 at a timing 2 × T _CLKB / 8 past the timing at which the synchronous clock signal CLKB is received, and the output signal of the FF3 is received by the FF3. The output signal generated by the output buffer 373 at a timing past by 3 × T _CLKB / 8 from the timing at which the FF 4 is output. The output signal of the FF 4 is 4 × T _CLKB / from the timing at which the FF 4 receives the synchronous clock signal CLKB. Output buffer 374 at a past timing of 8 Are more generated output signal, the output signal of FF5, said FF5 is located in the output signal generated by the output buffer 375 with 5 × T _{CLKB / 8} only historical timing than the timing of receiving the synchronization clock signal CLKB , The output signal of FF6 is an output signal generated by the output buffer 376 at a timing 6 × T _CLKB / 8 past the timing at which the _FF6 received the synchronous clock signal CLKB, and the output signal of FF7 is This is an output signal generated by the output buffer 377 at a timing past 7 × T _CLKB / 8 from the timing at which the FF 7 receives the synchronous clock signal CLKB. The output signal of the FF 8 is the output signal of the synchronous clock signal CLKB. 8 than the received timing × _{T CLKB} / 8 just past the timing An output signal generated by the output buffer 378 in grayed.

Accordingly, the detection circuit 310 to 312, separate the only past timing point _{T CLKB} from the timing of receiving the synchronization clock signal CLKB, a period until the timing of receiving the synchronization clock signal CLKB from the timing by _{T CLKB} / 8 Timing In this case, the signals acquired from the serial-parallel conversion units 307 to 309 are output from the FF1 to FF8.

  The register 380 stores the output signals of the FF1 to FF8. When the synchronous clock signal CLKB is simultaneously input to the CK terminals of the FF1 to FF8, it is simultaneously output from the Q terminals of the FF1 to FF8. The signal to be stored is stored.

  Since the data transmission circuit 3 is configured in the same manner as the data transmission circuit 2 except that the image data output from the image processing unit 21 is transmitted to the image forming unit 33, the description thereof is omitted.

  Next, operations of the multi-function device 1 and the data transmission circuit 2 configured as described above will be described.

  FIG. 5 is a signal waveform diagram for explaining image data transmission processing in the data transmission circuit 2. For example, when an operation instruction for instructing copying from the user is received by the operation panel unit 51, an image is read from an original by the scanner unit 11 in accordance with a control signal from the copy controller 45, and an image is read from the scanner unit 11. The signals shown, namely, red data RD [7: 0], green data GD [7: 0], blue data BD [7: 0], basic clock signal TxCLK and control signal S1 are transmitted to the data transmission circuit 2.

  In FIG. 5, red data RD [7: 0], red data RD [7: 0], green data GD [7: 0], and blue data BD [7: 0] are shown in order of data flow in bit units. : 0], bits 23 to 16, green data GD [7: 0], bits 15 to 08, and blue data BD [7: 0], bits 07 to 00.

  The control signal S1 is transmitted to the image processing unit 21 by the differential driver 208 via the cable 234 and the differential receiver 304.

  The basic clock signal TxCLK is supplied to the PLL circuit 204 and is output to the PLL circuit 313 and the image processing unit 21 as the clock signal RxCLK by the differential driver 209 via the cable 235 and the differential receiver 305.

  Then, the PLL circuit 204 generates a synchronous clock signal CLK1 from the basic clock signal TxCLK and outputs it to the parallel-serial converters 201-203. Next, the parallel data conversion units 201 to 203 cause the red data RD [7: 0], the green data GD [7: 0], and the blue data BD [7: 0] to synchronize with the synchronous clock signal CLK1 and serial signals TxOUT2 and TxOUT1. , TxOUT0.

  Further, the serial signals TxOUT2, TxOUT1, and TxOUT0 are serialized as serial signals RxIN2, RxIN1, and RxIN0 through the cables 231, 232, 233 and the differential receivers 301, 302, and 303 by the differential driver units 205, 206, and 207, respectively. The data is transmitted to the conversion units 307, 308, and 309.

  Next, serial signals RxIN2, RxIN1, and RxIN0 are acquired bit by bit by the serial-parallel converters 307, 308, and 309 in synchronization with the rising timing of the synchronous clock signal CLKB, converted into parallel signals, and red data RD [ 7: 0], green data GD [7: 0], and blue data BD [7: 0] are obtained, and each data is output to the image processing unit 21 via the reception control circuit 300.

  Next, the red data RD [7: 0], green data GD [7: 0], blue data BD [7: 0], control signal S1, and clock output from the data transmission circuit 2 by the image processing unit 21. After various image processing is performed on the signal RxCLK, the image data subjected to the image processing is transmitted to the image forming unit 33 by the data transmission circuit 3. Since the operation of the data transmission circuit 3 is the same as that of the data transmission circuit 2, the description thereof is omitted.

  Then, the image forming unit 33 forms an image on the recording paper based on the image data output from the data transmission circuit 3.

  By the way, in the multi-function device 1, as described above, the parasitic capacitance of the transmission path between the transmission side circuit 20 and the reception side circuit 30 that transmits the data varies between the transmission paths that transmit the data of each color. As shown by the arrow A in FIG. 6, there is a skew between the data due to the transmission distance of the in-device wiring and the variation in the output buffer characteristics of the data transmission wiring. When such a situation occurs, appropriate image data is not transmitted to the image forming unit, and an image having a color faithful to the original cannot be formed on the recording paper.

  Therefore, the multi-function device 1 of the present embodiment eliminates the skew between data in addition to the mode (corresponding to the first mode) in which data is transmitted and received between the transmission side circuit 20 and the reception side circuit 30. A calibration mode (corresponding to the second mode) for performing processing for reduction is provided. Hereinafter, a process performed when setting the calibration mode will be described. In FIG. 6, as an example of the occurrence of the skew, the green data GD [7: 0] is synchronized with the red data RD [7: 0] and the blue data BD [7: 0]. In this case, it is assumed that the skew is longer than the period of the synchronous clock signal CLKB.

  In the present embodiment, the skew is divided into fractions less than one cycle of the synchronous clock signal CLKB (in the above example, a time lag of 0.5 cycles) and other portions (of the cycle of the synchronous clock signal CLKB). Time that is an integral multiple; in the above example, a time shift of one cycle), and after performing the first processing for eliminating or reducing the shift of fractions less than one cycle, A second process for eliminating or reducing the time that is an integral multiple of the cycle of the clock signal CLKB is performed.

  The control unit 41 includes a mode setting unit 411 and functionally includes an instruction unit 412, a selection unit 413, a first detection unit 414, and a clock signal setting unit 415 so as to perform the first processing. And functionally includes a storage unit 416, a second detection unit 417, and a reception timing setting unit 418 in order to perform the second processing.

  The mode setting unit 411 is configured to switch the mode between a normal mode (corresponding to the first mode) in which data is transmitted and received between the transmission side circuit 20 and the reception side circuit 30 and the calibration mode. Is to do.

  When the mode setting unit 411 sets the calibration mode, the instruction unit 412 first transmits a predetermined pattern signal (hereinafter referred to as a first pattern signal) to perform the first processing. Send in order for each road. Accordingly, output signals Q1 to Q8 are simultaneously output from the output buffers 371 to 378 of the detection circuits 310 to 312 to the register 380 in synchronization with the synchronous clock signal CLKB.

  The selection unit 413 corresponds to the first selection unit and the second selection unit, and is alternatively selected from the basic clock signals TxCLK1 to TxCLK8 generated by the output buffers 361 to 368 of the clock delay circuits 210 to 212. The delay clock signal is selected and the selector 369 acquires the selected delayed clock signal.

  The first detection unit 414 detects when the combination (Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8) of the output signals Q1 to Q8 held in the register 380 matches the predetermined combination. The clock signal output to the parallel conversion units 201 to 203 is detected.

  That is, when the output signals Q1 to Q8 are held in the register 380, the first detection unit 414 determines whether or not the combination of the output signals matches a predetermined combination. Then, after changing the delay clock signal to be selected by the selection unit 413, the first pattern signal is transmitted on the transmission path, and the register 380 is again simultaneously sent from the output buffers 371 to 378 of the detection circuits 310 to 312. Output signals Q1-Q8 are acquired. The first detection unit 414, the selection unit 413, and the detection circuits 310 to 312 have a combination (Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8) of the output signals Q1 to Q8 held in the register 380. This process is repeatedly executed until it matches the predetermined combination, and the first detection unit 414 performs the process when the combination of the output signals Q1 to Q8 held in the register 380 matches the predetermined combination. The delay clock signal output from the parallel conversion units 201 to 203 is detected.

  7A to 7I show the output buffers 371 of the detection circuits 310 to 312 when the delayed clock signals to be selected by the selection unit 413 are set to the clock signals TxCLK and TxCLK1 to TxCLK8 in order. It is a figure which shows the output signal obtained from -378 (FF1-FF8).

  7A shows output signals obtained from the output buffers 371 to 378 when the clock signal to be selected by the selection unit 413 is set to the basic clock signal TxCLK. ) Shows output signals obtained from the output buffers 371 to 378 when the clock signal to be selected by the selection unit 413 is set to the delayed clock signal TxCLK1, and FIG. 7C shows the selection unit. FIG. 7 (d) shows the clock signal to be selected by the selection unit 413 when the clock signal to be selected by 413 is set to the delayed clock signal TxCLK2 and the output signals obtained from the output buffers 371 to 378 are shown. Indicates the output signal obtained from each of the output buffers 371 to 378 when the delay clock signal TxCLK3 is set. (E) shows output signals obtained from the output buffers 371 to 378 when the clock signal to be selected by the selection unit 413 is set to the delayed clock signal TxCLK4. FIG. FIG. 7G shows the output signals obtained from the output buffers 371 to 378 when the clock signal to be selected by the selection unit 413 is set to the delayed clock signal TxCLK5. FIG. FIG. 7H shows the output signals obtained from the output buffers 371 to 378 when the clock signal is set to the delayed clock signal TxCLK6, and FIG. FIG. 7 (i) shows output signals obtained from the output buffers 371 to 378 when the clock signal TxCLK7 is set. A clock signal to be selected on the selection section 413, when set to the delayed clock signal TxCLK8, shows the output signals obtained from the output buffer 371 to 378.

  When the first detection unit 414 detects a combination of output signals that matches the predetermined combination, the clock signal setting unit 415 detects the first detection unit 414 out of the clock signals TxCLK and TxCLK1 to 8. The clock signal when the combination of the output signals detected by the above is obtained is set as a clock signal to be output from the delay circuits 210 to 212.

  For example, it is assumed that the predetermined combination is (0, 0, 0, 0, 1, 1, 1, 1). Further, when the clock signal to be selected by the selection unit 413 is sequentially switched to the clock signals TxCLK and TxCLK1 to 8, the output signals shown in FIGS. 7A to 7I are output from the FF1 to FF8 of the detection circuit 310. Assume that a combination is obtained. At this time, as can be seen from FIG. 7, the combinations (Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8) of the output signals of the output buffers 371 to 378 are the predetermined combinations (0, 0, 0, 0, 1, 1, 1, 1) is the delayed clock signal TxCLK3, and the clock signal setting unit 415 should output the delayed clock signal TxCLK3 from the delay circuit 210 in the normal mode. Set as clock signal.

  The multifunction device 1 performs the above-described processing on each transmission line, so that if the first pattern signal is simultaneously transmitted to each transmission line, each output buffer 371-1 in the detection circuits 310 to 312. The combination of the output signals of 378 coincides with the detection circuits 310 to 312 (to the predetermined combination).

At this time, in the present embodiment, the output buffers 371 to 378 having a delay time of 1/8 of the period T _CLKB of the synchronous clock signal CLKB are connected in series, and combinations of output signals of the output buffers 371 to 378 are set in advance. Therefore, the target combination can be set in the order of the delay times of the output buffers 371 to 378. That is, it is possible to correct a shift of time less than one period of the synchronous clock signal CLKB in the order of the delay time of the output buffers 371 to 378.

  When data is transmitted and received between the transmission side circuit 20 and the reception side circuit 30 by the first processing as described above, among the skews of signal reception timings by the serial-parallel conversion units 307 to 309, Deviations less than one period can be eliminated or reduced.

  Next, the second process will be described.

  In the stage after the first processing, when predetermined signals as shown in FIGS. 8A-1 to 8A-3 are simultaneously transmitted to the respective transmission lines, for example, FIGS. As shown in (b-3), the timing at which the predetermined signal is received by the serial-parallel converter 308 on the green data GD transmission path is the serial-parallel converter 307 on the red data RD and blue data BD transmission paths. , 309 is delayed by a time corresponding to one cycle of the synchronous clock signal CLKB from the timing at which the predetermined signal is received. The second process is a process for eliminating or reducing this time lag.

  The storage unit 416 stores a plurality of types of pattern signals (hereinafter referred to as second pattern signals) whose phases are different from each other by a time corresponding to one cycle of the synchronous clock signal TxCLKB as shown in FIGS. 8 (c-1) to (c-3). Are stored in advance.

  The second detection unit 417 transmits the second pattern signal stored in the storage unit 416 to each transmission path. For example, when the second pattern signal shown in FIG. 8C-1 is transmitted to each transmission path, the waveform of the signal received by the reception control circuit 300 via the transmission path of the red data RD is as shown in FIG. The waveform of the signal received by the reception control circuit 300 via the green data GD transmission path is the waveform shown in FIG. 8E-1 and the blue data BD transmission path. It is assumed that the waveform of the signal received by the reception control circuit 300 via the waveform shown in FIG.

  For example, when the second pattern signal shown in FIG. 8C-2 is transmitted to each transmission path, the waveform of the signal received by the reception control circuit 300 via the transmission path of the red data RD is as shown in FIG. The waveform of the signal received by the reception control circuit 300 via the green data GD transmission path is the waveform shown in FIG. 8E-2, and the blue data BD transmission path is the waveform shown in (d-2). It is assumed that the waveform of the signal received by the reception control circuit 300 via the waveform shown in FIG.

  For example, when the second pattern signal shown in FIG. 8C-3 is transmitted to each transmission path, the waveform of the signal received by the reception control circuit 300 via the transmission path of the red data RD is as shown in FIG. The waveform of the signal received by the reception control circuit 300 via the green data GD transmission path becomes the waveform shown in FIG. 8E-3, and the blue data BD transmission path. It is assumed that the waveform of the signal received by the reception control circuit 300 via the waveform shown in FIG.

  The second detection unit 417 compares each second pattern signal acquired from each transmission path among the second pattern signals received by the reception control circuit 300 in this way, and the reception timing is between the transmission paths. The combination of the second pattern signals that coincide with each other is detected.

  That is, in the example shown in FIG. 8, the waveform shown in FIG. 8 (d-3), the waveform shown in FIG. 8 (e-2), and the waveform shown in FIG. The reception timings of the two pattern signals are the same between the transmission paths. Therefore, in this case, the second detection unit 417 detects combinations of signals shown in FIG. 8 (d-3), FIG. 8 (e-2), and FIG. 8 (f-3).

  The reception timing setting unit 418 compares the phases before transmission of the second pattern signals belonging to the combination detected by the second detection unit 417 (phases of the second pattern signals stored in the storage unit 416) with each other. Based on the phase difference obtained by the comparison, the reception timing at which the reception control circuit 300 receives data output from the parallel-serial converters 201 to 203 in the normal mode is set.

  In the example shown in FIG. 8, the reception control circuit 300 receives the second pattern signal from the serial-parallel converter 307, and the reception control circuit 300 receives the second pattern signal from the serial-parallel converters 308 and 309. It is delayed from the timing by a time corresponding to one cycle of the synchronous clock signal CLKB. In this case, the reception timing setting unit 418 delays the timing at which the reception control circuit 300 receives the signals output from the serial-parallel conversion units 308 and 309 by the time corresponding to the period of the synchronous clock signal CLKB.

  As a result, when data is transmitted and received between the transmission side circuit 20 and the reception side circuit 30, the synchronous clock signal CLKB is received at the timing when the reception control circuit 300 receives the data via each transmission path. The time lag for one cycle is not generated, and the time lag can be eliminated. As described above, when data is transmitted and received between the transmission-side circuit 20 and the reception-side circuit 30 by the second processing, the skew between the reception timings of the signals by the serial-parallel conversion units 307 to 309 is synchronized. Correction can be made in the order of the period of the clock signal CLKB.

  As described above, even when a signal indicating image data is transmitted to each transmission path by performing the first and second processes, the serial-parallel converters 307 to 309 simultaneously transmit the image data. Or it can receive substantially simultaneously. As a result, it is possible to prevent or suppress the occurrence of skew between data transmitted through each transmission path.

  In this case, the following modifications may be employed instead of or in addition to the embodiment.

  [1] In the above-described embodiment, both the first processing and the second processing are performed. However, even if any one of the first processing and the second processing is performed, the skew can be reduced.

  [2] Although the example in which the data transmission circuit 2 is applied to transmission of color image data has been described, monochrome image data may be distributed and transmitted to serial signals TxOUT2, TxOUT1, and TxOUT0.

  [3] The location where data transmission by the data transmission circuit is performed is not limited to between the scanner unit 11 and the image processing unit 21 and between the image processing unit 21 and the image forming unit 33. For example, the facsimile communication unit 61, It may be between the communication I / F unit such as the network I / F unit 71, the parallel I / F unit 72, and the serial I / F unit 73 and the image processing unit 21, or any other place. Good.

  [4] As an example of the image forming apparatus, an example of a multifunction peripheral is shown. However, for example, the data transmission circuit 2 may be used for data transmission in an image forming apparatus such as a copying machine, a facsimile machine, or a printer.

  [5] The data transmitted by the data transmission circuit 2 is not limited to image data, and may be any data. The data transmission circuit 2 may be used for data transmission in various apparatuses other than the image forming apparatus. .

1 is a block diagram illustrating an example of a configuration of a digital multi-function peripheral that is an embodiment of an image forming apparatus including a data transmission circuit according to an embodiment of the present invention. It is a block diagram which shows an example of a structure of the data transmission circuit which concerns on one Embodiment of this invention. It is a figure which shows the circuit structural example of a delay circuit. It is a figure which shows the circuit structural example of a detection circuit. FIG. 3 is a signal waveform diagram for describing image data transmission processing in the data transmission circuit shown in FIG. 2. It is explanatory drawing of a skew. It is explanatory drawing of the output signal of each flip-flop in a detection circuit. It is explanatory drawing of a 2nd process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Multifunction device 2, 3 Data transmission circuit 11 Scanner part 20 Transmission side circuit 21 Image processing part 30 Reception side circuit 31 Printer part 33 Image formation part 210-212 Clock delay circuit 310-312 Detection circuit 41 Control part 411 Mode setting part 412 Instruction unit 413 Selection unit 414 First detection unit 415 Clock signal setting unit 416 Storage unit 417 Second detection unit 418 Reception timing setting unit 361-368 Output buffer 369 Selector 371-378 Output buffer 379 PLL circuit 380 Register

Claims (4)

A transmission-side circuit including first and second serial signal generation units for outputting the first and second serial signals in synchronization with a clock signal output at a predetermined period;
A first parallel signal generating section that converts the first serial signal output from the first serial signal generating section into a parallel signal and outputs the converted parallel signal as a first parallel signal; and the second serial signal. A data transmission comprising: a receiving side circuit including a second parallel signal generation unit that converts the second serial signal output from the signal generation unit into a parallel signal and outputs the converted parallel signal as a second parallel signal A circuit,
A first mode in which the first and second serial signals transmitted from the transmission side circuit are converted into the first and second parallel signals in the reception side circuit, respectively, and a second mode different from the first mode A mode setting unit for setting mode switching between
When the mode setting unit sets the second mode, an instruction unit that transmits a predetermined pattern signal as the first pattern signal from the transmission side circuit;
A plurality of output buffers having a predetermined time as a delay time shorter than the cycle of the clock signal are connected in series, and each output buffer generates a delayed clock signal having a different delay time;
A first selection unit that alternatively selects a delay clock signal to be output to the first serial signal generation unit from among the delay clock signals output by the respective output buffers of the first delay circuit unit;
A plurality of output buffers having the predetermined time as a delay time are connected in series, and each output buffer generates a delayed clock signal having a different delay time;
A second selection unit that alternatively selects a delay clock signal to be output to the second serial signal generation unit from among the delay clock signals output by the respective output buffers of the second delay circuit unit;
The first pattern signal is received from the first serial signal generation unit, and a plurality of output buffer serial circuits having the predetermined time as a delay time, and output signals from the output buffers of the serial circuit simultaneously. A first detection circuit unit including a signal acquisition unit that acquires in synchronization with the clock signal;
The first pattern signal is received from the second serial signal generation unit, and a plurality of output buffer serial circuits having the predetermined time as a delay time, and an output signal from each output buffer of the serial circuit simultaneously. A second detection circuit unit including a signal acquisition unit that acquires in synchronization with the clock signal;
The delayed clock signal output to the first serial signal generator when the combination of the output signals acquired by each signal acquisition unit of the first detection circuit unit is a predetermined combination, and the second detection A first detection unit that detects each of the delayed clock signals output to the second serial signal generation unit when a combination of output signals acquired by each signal acquisition unit of the circuit unit is a predetermined combination;
A clock signal that sets the delayed clock signal detected by the first detection unit as a clock signal to be selected by the first and second selection units when the mode setting unit sets the first mode. A data transmission circuit having a setting unit. A receiver that receives the first and second parallel signals generated by the first and second parallel signal generators and performs a predetermined process on the received first and second parallel signals; ,
After the setting by the clock signal setting unit, a first transmission path constituted by the first serial signal generation unit and the first parallel signal generation unit, and the second serial signal generation unit and the second parallel signal generation unit A plurality of types of pattern signals having different phases from each other in the predetermined period as the second pattern signal, and among the second pattern signals, the first and second patterns A second detection unit for detecting a combination of second pattern signals having the same reception timing received by the second parallel signal generation unit;
The second pattern signals belonging to the combination detected by the second detector are compared with each other in phase before transmission, and output from the first and second parallel signal generators based on the phase difference obtained by the comparison. The data transmission circuit according to claim 1, further comprising: a reception timing setting unit that sets a timing at which the reception unit receives the first and second parallel signals.   The reception timing setting unit is configured such that, among the second pattern signals belonging to the combination detected by the second detection unit, a parallel signal having a common transmission line with a second pattern signal having a earlier phase before transmission is the first parallel signal. The data transmission circuit according to claim 2, wherein the data transmission circuit detects whether the signal is a signal or a second parallel signal, and delays the reception timing of the detected parallel signal by the receiving unit by the phase difference. An image acquisition unit for acquiring image data;
An image forming unit that forms an image on recording paper based on the image data acquired by the image acquisition unit,
4. An image forming apparatus in which the data transmission circuit according to claim 1 is used in at least part of a data transmission path for transmitting the image data from the image acquisition unit to the image forming unit.

Images