JP2022135860A - ループ依存電圧ランプ目標及びタイミング制御を通じたピーク電流及びプログラム時間最適化 - Google Patents
ループ依存電圧ランプ目標及びタイミング制御を通じたピーク電流及びプログラム時間最適化 Download PDFInfo
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- 230000001419 dependent effect Effects 0.000 title claims abstract description 27
- 238000005457 optimization Methods 0.000 title 1
- 230000015654 memory Effects 0.000 claims abstract description 492
- 238000000034 method Methods 0.000 claims abstract description 100
- 238000004891 communication Methods 0.000 claims abstract description 10
- 238000001514 detection method Methods 0.000 claims description 17
- 230000002829 reductive effect Effects 0.000 claims description 12
- 244000045947 parasite Species 0.000 abstract 1
- 230000008569 process Effects 0.000 description 56
- 238000007600 charging Methods 0.000 description 44
- 239000000758 substrate Substances 0.000 description 36
- 238000003860 storage Methods 0.000 description 27
- 238000007667 floating Methods 0.000 description 26
- 238000010586 diagram Methods 0.000 description 25
- 238000013459 approach Methods 0.000 description 24
- 238000012795 verification Methods 0.000 description 24
- 230000003071 parasitic effect Effects 0.000 description 17
- WVRNUXJQQFPNMN-VAWYXSNFSA-N 3-[(e)-dodec-1-enyl]oxolane-2,5-dione Chemical compound CCCCCCCCCC\C=C\C1CC(=O)OC1=O WVRNUXJQQFPNMN-VAWYXSNFSA-N 0.000 description 15
- 230000000875 corresponding effect Effects 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 230000000670 limiting effect Effects 0.000 description 13
- 230000006870 function Effects 0.000 description 12
- 230000002401 inhibitory effect Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 12
- 230000007704 transition Effects 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 11
- 230000001276 controlling effect Effects 0.000 description 10
- 238000009826 distribution Methods 0.000 description 10
- 230000001105 regulatory effect Effects 0.000 description 10
- 239000007787 solid Substances 0.000 description 9
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 238000003491 array Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000013500 data storage Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000007257 malfunction Effects 0.000 description 4
- 238000007726 management method Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000002411 adverse Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 101000578349 Homo sapiens Nucleolar MIF4G domain-containing protein 1 Proteins 0.000 description 2
- 102100027969 Nucleolar MIF4G domain-containing protein 1 Human genes 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 101710190981 50S ribosomal protein L6 Proteins 0.000 description 1
- 101710190962 50S ribosomal protein L9 Proteins 0.000 description 1
- 101100481702 Arabidopsis thaliana TMK1 gene Proteins 0.000 description 1
- 101100481703 Arabidopsis thaliana TMK2 gene Proteins 0.000 description 1
- 101100481704 Arabidopsis thaliana TMK3 gene Proteins 0.000 description 1
- 108700019909 BL 19 Proteins 0.000 description 1
- 101000751000 Bacillus subtilis (strain 168) 50S ribosomal protein L1 Proteins 0.000 description 1
- 101000574917 Bacillus subtilis (strain 168) 50S ribosomal protein L10 Proteins 0.000 description 1
- 101000575029 Bacillus subtilis (strain 168) 50S ribosomal protein L11 Proteins 0.000 description 1
- 101001105315 Bacillus subtilis (strain 168) 50S ribosomal protein L17 Proteins 0.000 description 1
- 101000682328 Bacillus subtilis (strain 168) 50S ribosomal protein L18 Proteins 0.000 description 1
- 101001101476 Bacillus subtilis (strain 168) 50S ribosomal protein L21 Proteins 0.000 description 1
- 101000592939 Bacillus subtilis (strain 168) 50S ribosomal protein L24 Proteins 0.000 description 1
- 101000712130 Bacillus subtilis (strain 168) 50S ribosomal protein L7/L12 Proteins 0.000 description 1
- 101000935024 Bungarus multicinctus Beta-bungarotoxin B chain-like Proteins 0.000 description 1
- 102100035793 CD83 antigen Human genes 0.000 description 1
- 208000032368 Device malfunction Diseases 0.000 description 1
- 101001070329 Geobacillus stearothermophilus 50S ribosomal protein L18 Proteins 0.000 description 1
- 101001110617 Geobacillus stearothermophilus 50S ribosomal protein L5 Proteins 0.000 description 1
- 101001093025 Geobacillus stearothermophilus 50S ribosomal protein L7/L12 Proteins 0.000 description 1
- 101000946856 Homo sapiens CD83 antigen Proteins 0.000 description 1
- 208000024875 Infantile dystonia-parkinsonism Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011370 conductive nanoparticle Substances 0.000 description 1
- 238000010277 constant-current charging Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 208000001543 infantile parkinsonism-dystonia Diseases 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000012782 phase change material Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000007619 statistical method Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- G11C16/24—Bit-line control circuits
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
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- G11C16/26—Sensing or reading circuits; Data output circuits
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
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- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
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Abstract
Description
ループ依存性プログラミング調節パラメータによって修正される際に、複数のメモリセルに対するプログラミング及び検証動作を実行するステップと、を実行するように構成されている、制御回路と、を有し、ループ依存性プログラミング調節パラメータの判定が、複数のメモリセルのとそれぞれ電気通信する複数のビット線の相対容量に基づく、不揮発性メモリデバイスが提供される。制御回路は、複数のメモリセルに対するプログラミング動作を完了するために実行されるプログラムループのシーケンス内のプログラムループの位置を判定するステップを実行するように更に構成されることを含み、かつループ依存性プログラミング調節パラメータの判定が、プログラムループのシーケンス内のループの位置に更に基づく、任意の所望の機能を提供し得る。更に、不揮発性メモリデバイスでは、プログラム制御回路のシーケンス内のループの位置が、開始セクション、中間セクション、又は終了セクションのうちの1つにあると判定され得、ループ位置が開始セクション内にある場合、調節パラメータを第1のより低い値に設定し、ループ位置が中間セクション内にある場合、調節パラメータをより高い値に設定し、ループ位置が終了セクション内にある場合、調節パラメータを第2のより低い値に設定する。複数のビット線の相対容量は、複数のビット線にそれぞれ割り当てられた禁止電圧又はプログラム電圧の構成に基づいて静電容量を判定することなど、任意の所望の方式で判定され得る。更に、複数のビット線の相対容量はまた、複数のメモリセルのそれぞれのプログラミング状態に基づいて判定され得る。
Claims (20)
- 不揮発性メモリデバイスであって、
複数のビット線に電気的にそれぞれ電気的に結合された複数のメモリセルと、
制御回路であって、前記複数のメモリセルに結合されており、かつ、
前記複数のメモリセルのプログラミングサイクルに基づいて、ループ依存性プログラミング調節パラメータを判定するステップと、
前記ループ依存性プログラミング調節パラメータによって修正される際に、前記複数のメモリセルに対するプログラミング及び検証動作を実行するステップと、を実行するように構成されている、制御回路と、を備え、
前記ループ依存性プログラミング調節パラメータの前記判定が、前記複数のメモリセルの前記とそれぞれ電気通信している複数のビット線の相対容量に基づく、不揮発性メモリデバイス。 - 前記制御回路が、
前記複数のメモリセルに対するプログラミング動作を完了するために実行されるプログラムループのシーケンス内のプログラムループの位置を判定するステップを実行するように更に構成されており、
前記ループ依存性プログラミング調節パラメータの前記判定が、前記プログラムループのシーケンス内の前記ループの前記位置に更に基づく、請求項1に記載の不揮発性メモリデバイス。 - プログラム制御回路のシーケンス内の前記ループの前記位置が、開始セクション、中間セクション、又は終了セクションのうちの1つにあると判定され、
前記ループ位置が前記開始セクション内にある場合、前記調節パラメータを第1のより低い値に設定し、
前記ループ位置が前記中間セクション内にある場合、前記調節パラメータをより高い値に設定し、
前記ループ位置が前記終了セクション内にある場合、前記調節パラメータを第2のより低い値に設定する、請求項2に記載の不揮発性メモリデバイス。 - 前記複数のビット線の前記相対容量が、前記複数のビット線にそれぞれ割り当てられた禁止電圧又はプログラム電圧の構成に基づいて判定される、請求項1に記載の不揮発性メモリデバイス。
- 前記複数のビット線の前記相対容量が、前記複数のメモリセルのそれぞれのプログラミング状態に基づいて判定される、請求項4に記載の不揮発性メモリデバイス。
- 前記複数のメモリセルに対する前記プログラミング及び検証動作の修正が、前記メモリデバイスによるピーク電流利用の低減をもたらす、請求項1に記載の不揮発性メモリデバイス。
- 前記プログラミング調節パラメータが、前記それぞれのビット線の禁止電圧チャージアップの電圧検出閾値を含む、請求項1に記載の不揮発性メモリデバイス。
- 前記プログラミング調節パラメータが、前記プログラミングサイクルのプログラム回復フェーズのビット線等化時間値を含む、請求項1に記載の不揮発性メモリデバイス。
- 前記プログラミング調節パラメータが、前記プログラミングサイクルのプログラム検証/読み出しフェーズの電圧時間値を読み出すためのビット線設定を含む、請求項1に記載の不揮発性メモリデバイス。
- 前記ループ依存性プログラミング調節パラメータの前記判定が、前記メモリデバイスの前記メモリセルのうちの少なくとも1つの電圧閾値状態に基づく、請求項1に記載の不揮発性メモリデバイス。
- 複数のビット線にそれぞれ電気的に結合された複数のメモリセルと、前記複数のメモリセルに結合された制御回路と、を備える、不揮発性メモリデバイスを制御するための方法であって、
前記複数のメモリセルのプログラミングサイクルに基づいて、ループ依存性プログラミング調節パラメータを判定することと、
前記ループ依存性プログラミング調節パラメータによって修正される際に、前記複数のメモリセルに対するプログラミング及び検証動作を実行することと、を含み、
前記ループ依存性プログラミング調節パラメータの前記判定が、前記複数のメモリセルの前記とそれぞれ電気通信している複数のビット線の相対容量に基づく、方法。 - 前記制御回路が、
前記複数のメモリセルに対するプログラミング動作を完了するために実行されるプログラムループのシーケンス内のプログラムループの位置を判定するステップを実行するように更に構成されており、
前記ループ依存性プログラミング調節パラメータの前記判定が、前記プログラムループのシーケンス内の前記ループの前記位置に更に基づく、請求項11に記載の方法。 - プログラム制御回路のシーケンス内の前記ループの前記位置が、開始セクション、中間セクション、又は終了セクションのうちの1つにあると判定され、
前記ループ位置が前記開始セクション内にある場合、前記調節パラメータを第1のより低い値に設定し、
前記ループ位置が前記中間セクション内にある場合、前記調節パラメータをより高い値に設定し、
前記ループ位置が前記終了セクション内にある場合、前記調節パラメータを第2のより低い値に設定する、請求項12に記載の方法。 - 前記複数のビット線の前記相対容量が、前記複数のビット線にそれぞれ割り当てられた禁止電圧又はプログラム電圧の構成に基づいて判定される、請求項11に記載の方法。
- 前記複数のビット線の前記相対容量が、前記複数のメモリセルのそれぞれのプログラミング状態に基づいて判定される、請求項14に記載の方法。
- 前記複数のメモリセルに対する前記プログラミング及び検証動作の修正が、前記メモリデバイスによるピーク電流利用の低減をもたらす、請求項11に記載の方法。
- 前記プログラミング調節パラメータが、前記それぞれのビット線の禁止電圧チャージアップの電圧検出閾値を含む、請求項11に記載の方法。
- 前記プログラミング調節パラメータが、前記プログラミングサイクルのプログラム回復フェーズのビット線等化時間値を含む、請求項11に記載の方法。
- 前記プログラミング調節パラメータが、前記プログラミングサイクルのプログラム検証/読み出しフェーズの電圧時間値を読み出すためのビット線設定を含む、請求項11に記載の方法。
- 前記ループ依存性プログラミング調節パラメータの前記判定が、前記メモリデバイスの前記メモリセルのうちの少なくとも1つの電圧閾値状態に基づく、請求項11に記載の方法。
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