JP2022038486A - 試験装置、試験方法および製造方法 - Google Patents
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- 238000012360 testing method Methods 0.000 title claims abstract description 107
- 238000004519 manufacturing process Methods 0.000 title claims description 12
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- 238000012216 screening Methods 0.000 claims abstract description 17
- 230000007547 defect Effects 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 15
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- 238000005259 measurement Methods 0.000 description 2
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
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- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- 230000006378 damage Effects 0.000 description 1
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- 239000007769 metal material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
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- 239000011574 phosphorus Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H01L29/70—Bipolar devices
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
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- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
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Abstract
Description
特許文献1 国際公開第2018/092457号
Claims (11)
- 第1電源電圧が印加される第1主端子と、前記第1電源電圧よりも低い第2電源電圧が印加される第2主端子とを有する半導体装置を試験する試験装置であって、
前記半導体装置のターンオフ時における、前記第1主端子の端子電圧の変化速度を設定する条件設定部と、
前記条件設定部が設定した条件で、前記半導体装置をターンオフさせる動作制御部と、
前記半導体装置の動作結果に基づいて、前記半導体装置をスクリーニングする判定部と
を備え、
前記半導体装置のターンオフ時における前記端子電圧の時間波形は、変化速度が最大となる最大変化点を有し、
前記条件設定部は、前記最大変化点の電圧よりも高い第1設定電圧における前記変化速度を、予め定められた値に設定する
試験装置。 - 前記第1設定電圧は、前記第1電源電圧の80%以上の電圧である
請求項1に記載の試験装置。 - 前記第1設定電圧は、前記第1電源電圧以上の電圧である
請求項2に記載の試験装置。 - 前記第1設定電圧は、前記第1電源電圧と同一の電圧である
請求項3に記載の試験装置。 - 前記試験装置は、前記半導体装置がチップ状態の場合と、モジュール状態の場合の2つの状態のそれぞれにおいて、前記半導体装置を試験し、
前記条件設定部は、前記モジュール状態の前記半導体装置を試験する場合の前記第1設定電圧における前記変化速度よりも、前記チップ状態の前記半導体装置を試験する場合の前記第1設定電圧における前記変化速度を大きくする
請求項1から4のいずれか一項に記載の試験装置。 - 前記条件設定部は、前記モジュール状態の前記半導体装置に対するスクリーニング結果に応じて、前記チップ状態の前記半導体装置に対する前記第1設定電圧における前記変化速度を調整する
請求項5に記載の試験装置。 - 前記条件設定部は、前記モジュール状態の前記半導体装置における不良率が増大した場合に、前記チップ状態の前記半導体装置に対する前記第1設定電圧における前記変化速度を増大させる
請求項6に記載の試験装置。 - 前記条件設定部は、前記第1設定電圧とは異なる第2設定電圧における前記変化速度を、予め定められた値にさらに設定する
請求項1から7のいずれか一項に記載の試験装置。 - 前記第2設定電圧は前記第1設定電圧よりも低い
請求項8に記載の試験装置。 - 第1電源電圧が印加される第1主端子と、前記第1電源電圧よりも低い第2電源電圧が印加される第2主端子とを有する半導体装置を試験する試験方法であって、
前記半導体装置のターンオフ時における、前記第1主端子の端子電圧の変化速度を設定する条件設定段階と、
前記条件設定段階で設定した条件で、前記半導体装置をターンオフさせる動作制御段階と、
前記半導体装置の動作結果に基づいて、前記半導体装置をスクリーニングする判定段階と
を備え、
前記半導体装置のターンオフ時における前記端子電圧の時間波形は、変化速度が最大となる最大変化点を有し、
前記条件設定段階において、前記最大変化点の電圧よりも高い第1設定電圧における前記変化速度を、予め定められた値に設定する
試験方法。 - 第1電源電圧が印加される第1主端子と、前記第1電源電圧よりも低い第2電源電圧が印加される第2主端子を有する半導体装置を含む半導体モジュールの製造方法であって、
チップ状態の前記半導体装置を試験する試験段階と、
前記試験段階において選別された前記半導体装置をモジュールに組み込むことで、前記半導体モジュールを形成する組込段階と
を備え、
前記試験段階は、
前記半導体装置のターンオフ時における、前記第1主端子の端子電圧の変化速度を設定する条件設定段階と、
前記条件設定段階で設定した条件で、前記半導体装置をターンオフさせる動作制御段階と、
前記半導体装置の動作結果に基づいて、前記半導体装置をスクリーニングする判定段階と
を有し、
前記半導体装置のターンオフ時における前記端子電圧の時間波形は、変化速度が最大となる最大変化点を有し、
前記条件設定段階において、前記最大変化点の電圧よりも高い第1設定電圧における前記変化速度を、予め定められた値に設定する
製造方法。
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