JP2021190607A - 半導体装置の製造方法、および、半導体装置 - Google Patents
半導体装置の製造方法、および、半導体装置 Download PDFInfo
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- JP2021190607A JP2021190607A JP2020095910A JP2020095910A JP2021190607A JP 2021190607 A JP2021190607 A JP 2021190607A JP 2020095910 A JP2020095910 A JP 2020095910A JP 2020095910 A JP2020095910 A JP 2020095910A JP 2021190607 A JP2021190607 A JP 2021190607A
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Abstract
Description
以下、本実施の形態に関する半導体装置の製造方法、および、半導体装置について説明する。
以下の実施の形態で示される例として示される(電力)半導体装置は、リードフレーム上にパワーチップ(たとえば、スイッチング素子)、ダイオード素子および集積回路(IC)を備え、トランスファーモールドによって封止された大電力用途の半導体装置であり、4辺のうち対向する2辺に端子を配置し、それぞれの辺において制御側端子とパワー側端子とが分かれているものとする。なおパワーチップは、Siを用いる半導体チップだけでなく、SiCなどのワイドバンドギャップ半導体を用いる半導体チップであってもよい。
図5は、本実施の形態に関する半導体装置の製造工程、特にリードフォーミングに関する製造工程の例を示すフローチャートである。図5に例が示されるように、本実施の形態に関する半導体装置の製造工程においては、まず、パワーチップダイボンド工程においては、パワーチップ22と、パワーチップ24と、パワーチップ26と、パワーチップ28と、パワーチップ30と、パワーチップ32とを、リードフレームの対応する箇所にそれぞれ接着する(図5におけるステップST01)。
本実施の形態に関する半導体装置の製造方法、および、半導体装置について説明する。なお、以下の説明においては、以上に記載された実施の形態で説明された構成要素と同様の構成要素については同じ符号を付して図示し、その詳細な説明については適宜省略するものとする。
図12は、本実施の形態に関する、パワーチップダイボンド工程からトランスファーモールド工程までが完了した時点での半導体装置の構造の例を示す平面図である。
本実施の形態に関する半導体装置の製造方法、および、半導体装置について説明する。なお、以下の説明においては、以上に記載された実施の形態で説明された構成要素と同様の構成要素については同じ符号を付して図示し、その詳細な説明については適宜省略するものとする。
図14は、本実施の形態に関する、パワーチップダイボンド工程からトランスファーモールド工程までが完了した時点での半導体装置の構造の例を示す平面図である。
本実施の形態に関する半導体装置の製造方法、および、半導体装置について説明する。なお、以下の説明においては、以上に記載された実施の形態で説明された構成要素と同様の構成要素については同じ符号を付して図示し、その詳細な説明については適宜省略するものとする。
図15は、本実施の形態に関する、パワーチップダイボンド工程からトランスファーモールド工程までが完了した時点での半導体装置の構造の例を示す平面図である。
本実施の形態に関する半導体装置の製造方法、および、半導体装置について説明する。なお、以下の説明においては、以上に記載された実施の形態で説明された構成要素と同様の構成要素については同じ符号を付して図示し、その詳細な説明については適宜省略するものとする。
図17は、本実施の形態に関する、パワーチップダイボンド工程からトランスファーモールド工程までが完了した時点での半導体装置の構造の例を示す平面図である。また、図18は、図17に示されるカット部品400の形状の例を示す平面図である。
次に、以上に記載された実施の形態によって生じる効果の例を示す。なお、以下の説明においては、以上に記載された実施の形態に例が示された具体的な構成に基づいて当該効果が記載されるが、同様の効果が生じる範囲で、本願明細書に例が示される他の具体的な構成と置き換えられてもよい。
以上に記載された実施の形態では、それぞれの構成要素の材質、材料、寸法、形状、相対的配置関係または実施の条件などについても記載する場合があるが、これらはすべての局面においてひとつの例であって、限定的なものではないものとする。
Claims (9)
- 少なくとも1つの半導体素子を設け、
前記半導体素子に、複数の第1の端子と、前記第1の端子よりも低い電圧が印加される制御用端子である少なくとも1つの第2の端子とを接続し、
前記第1の端子に第1の曲げ部を形成し、
隣り合う前記複数の第1の端子は、互いに対向する面において前記第1の曲げ部が突出しない、
半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法であり、
前記第2の端子は、前記半導体素子に対して複数接続され、
それぞれの前記第2の端子に第2の曲げ部を形成し、
隣り合う複数の前記第2の端子は、互いに対向する面において前記第2の曲げ部が突出する、
半導体装置の製造方法。 - 請求項1または2に記載の半導体装置の製造方法であり、
前記半導体素子に、前記複数の第1の端子と前記第2の端子とを接続することは、前記半導体素子にリードを接続し、前記リードにおける前記第1の端子または前記第2の端子となる箇所間の領域であるタイバー部を切断することであり、
隣り合う前記複数の第1の端子間の領域に対応する前記タイバー部には、スリットが形成される、
半導体装置の製造方法。 - 請求項3に記載の半導体装置の製造方法であり、
前記スリットは、隣り合う前記複数の第1の端子に向かう面が凸形状である、
半導体装置の製造方法。 - 請求項3または4に記載の半導体装置の製造方法であり、
前記スリットは、隣り合う前記複数の第1の端子の近傍にのみ形成される、
半導体装置の製造方法。 - 請求項1から5のうちのいずれか1つに記載の半導体装置の製造方法であり、
前記半導体素子に、前記複数の第1の端子と前記第2の端子とを接続することは、前記半導体素子にリードを接続し、前記リードにおける前記第1の端子または前記第2の端子となる箇所間の領域であるタイバー部を切断することであり、
前記タイバー部を切断するためのカット部品は、隣り合う前記複数の第1の端子間の領域に対応して凸形状の端面を有する、
半導体装置の製造方法。 - 少なくとも1つの半導体素子と、
前記半導体素子に接続される複数の端子とを備え、
前記複数の端子は、
第1の曲げ部を有する複数の第1の端子と、
前記第1の端子よりも低い電圧が印加される制御用端子である少なくとも1つの第2の端子とを備え、
隣り合う前記複数の第1の端子は、互いに対向する面において前記第1の曲げ部が突出しない、
半導体装置。 - 請求項7に記載の半導体装置であり、
前記第2の端子を複数備え、
それぞれの前記第2の端子は第2の曲げ部を有し、
隣り合う複数の前記第2の端子は、互いに対向する面において前記第2の曲げ部が突出する、
半導体装置。 - 請求項7または8に記載の半導体装置であり、
前記半導体素子には、ワイドバンドギャップ半導体が用いられる、
半導体装置。
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JPH01100456U (ja) * | 1987-12-23 | 1989-07-05 | ||
JP2004063688A (ja) * | 2002-07-26 | 2004-02-26 | Mitsubishi Electric Corp | 半導体装置及び半導体アセンブリモジュール |
JP2015090960A (ja) * | 2013-11-07 | 2015-05-11 | 株式会社デンソー | 半導体パッケージ |
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