JP2021180564A - Drive circuit for switch - Google Patents

Abstract

To provide a drive circuit for switch capable of eliminating a short circuit detection exclusive element and a short circuit detection terminal as far as possible.SOLUTION: A drive circuit Dr of a switch SW determines whether or not a shift to a mirror period is performed based on gate voltage of the switch SW in a period when an ON command is performed to the switch SW. When the shift to the mirror period is not determined in a period when the gate voltage reaches determination voltage lower than output voltage Vcc of a constant voltage power supply 40 and higher than mirror voltage of the switch SW after the ON command is performed, the drive circuit Dr switches the switch SW into an OFF state.SELECTED DRAWING: Figure 2

Description

The present invention relates to a switch drive circuit.

As a drive circuit of this type, as seen in Patent Documents 1 and 2, for example, a circuit that protects a switch (for example, an IGBT) from a short-circuit current by a Desat method is known. This drive circuit has a diode with a cathode connected to the high potential side terminal of the switch, a capacitor connecting the anode of the diode and the low potential side terminal of the switch, and a short circuit detection terminal to which the anode of the diode is connected. I have.

Japanese Unexamined Patent Publication No. 2017-17870 International Publication No. 2017/104077

In the Desat type drive circuit, a dedicated element for short-circuit detection such as the above-mentioned diode or capacitor is required, or a short-circuit detection terminal is required. Since the dedicated element and the short-circuit detection terminal are not used to drive the switch when a short circuit does not occur, it is desired to reduce the number of the dedicated element and the short-circuit detection terminal as much as possible.

An object of the present invention is to provide a dedicated element for short-circuit detection and a switch drive circuit capable of reducing short-circuit detection terminals as much as possible.

The present invention relates to a switch drive circuit that drives a switch.
A determination unit that determines whether or not the switch has entered the mirror period based on the gate voltage of the switch or the charging current of the gate of the switch during the period in which the ON command is given to the switch.
The mirror period by the determination unit during the period from when the ON command is given until the gate voltage of the switch reaches a determination voltage that is lower than the upper limit of the gate voltage and higher than the mirror voltage of the switch. When it is not determined that the switch has been shifted to, the switch is provided with an off switching unit for switching the switch to the off state.

When an on command is given to the switch, a charging current is supplied to the gate of the switch. In this case, when no short circuit current is flowing through the switch, a mirror period appears in which the gate voltage of the switch is maintained at the mirror voltage. On the other hand, when the short-circuit current is starting to flow in the switch, the short-circuit current affects the gate through the feedback capacitance of the switch, so the mirror period does not appear and the gate voltage continues to rise toward its upper limit. ..

In view of this point, in the present invention, it is determined whether or not the mirror period of the switch has been entered based on the gate voltage of the switch or the charging current of the gate of the switch during the period when the ON command is given to the switch. Then, in the period from when the on command is given until the gate voltage reaches the determination voltage, if it is not determined that the mirror period has been entered, the switch is switched to the off state. The determination voltage is a value lower than the upper limit of the gate voltage of the switch and higher than the mirror voltage.

According to the present invention, a dedicated element such as a diode and a capacitor used in the Desert method and a short circuit detection terminal are not required. Therefore, the number of dedicated elements for short-circuit detection and short-circuit detection terminals can be reduced as much as possible.

The figure which shows the whole structure of the control system which concerns on 1st Embodiment. The figure which shows the drive circuit. A flowchart showing a short circuit protection process. A time chart showing the short circuit protection process. The figure which shows the drive circuit which concerns on 2nd Embodiment. The figure which shows the differentiating circuit. A time chart showing the operation of the drive circuit. The figure which shows the drive circuit which concerns on 3rd Embodiment. The figure which shows the voltage buffer part. A time chart showing the operation of the drive circuit. The figure which shows the voltage buffer part which concerns on the modification of 3rd Embodiment. The figure which shows the drive circuit which concerns on 4th Embodiment. A time chart showing the operation of the drive circuit. The figure which shows the drive circuit which concerns on 5th Embodiment. A flowchart showing the procedure of the short circuit protection process. A time chart showing the operation of the drive circuit.

<First Embodiment>
Hereinafter, the first embodiment in which the drive circuit according to the present invention is embodied will be described with reference to the drawings.

As shown in FIG. 1, the control system includes a rotary electric machine 10 and an inverter. The inverter includes a switching device unit 20 and a control unit 30 for controlling the rotary electric machine 10. In this embodiment, the rotary electric machine 10 includes a three-phase winding 11 connected in a star shape. The control system of this embodiment is mounted on a vehicle. The rotor of the rotary electric machine 10 is connected to the drive wheels of the vehicle so as to be able to transmit power. The rotary electric machine 10 is, for example, a synchronous machine.

The rotary electric machine 10 is connected to the DC power supply 21 via the switching device unit 20. In the present embodiment, the DC power supply 21 is a secondary battery. The switching device unit 20 includes a smoothing capacitor 22.

The switching device unit 20 includes a series connection body of the upper and lower arm switches SW for each of the U, V, and W phases. In this embodiment, each switch SW is an IGBT. A freewheel diode is connected in antiparallel to each switch SW. In each switch SW of the present embodiment, the high potential side terminal is a collector and the low potential side terminal is an emitter.

In each phase, the first end of the winding 11 is connected to the connection point between the emitter of the upper arm switch SW and the collector of the lower arm switch SW. The second end of the winding 11 of each phase is connected at the neutral point.

The control unit 30 drives each switch SW of the switching device unit 20 in order to control the control amount of the rotary electric machine 10 to a command value. The control amount is, for example, torque. The control unit 30 individually sets the drive signal IN corresponding to the upper and lower arm switch SW to the upper and lower arm switch SW in order to alternately turn on the upper and lower arm switch SW while sandwiching the dead time. It is output to the provided drive circuit Dr. The drive signal IN takes either an on command instructing the switch to be switched to the on state or an off command instructing the switch to be switched to the off state.

Subsequently, the drive circuit Dr will be described with reference to FIG. Each drive circuit Dr of the upper and lower arms of the present embodiment has basically the same configuration.

The drive circuit Dr includes a constant voltage power supply 40, a charging switch 41, and a charging resistor 42. The charging switch 41 of this embodiment is a P-channel MOSFET. The gate terminal Tg of the drive circuit Dr is connected to the constant voltage power supply 40 via the charging switch 41 and the charging resistor 42. The gate of the switch SW is connected to the gate terminal Tg. The output voltage Vcc (for example, 15V) of the constant voltage power supply 40 is the power supply voltage supplied to the gate of the switch SW, and corresponds to the upper limit of the gate voltage of the switch SW.

The drive circuit Dr includes a discharge resistor 43 and a discharge switch 44. The discharge switch 44 of this embodiment is an N-channel MOSFET. The emitter of the switch SW as a ground portion is connected to the gate terminal Tg via the discharge resistor 43 and the discharge switch 44.

The drive circuit Dr includes a drive unit 50. The drive unit 50 acquires the drive signal IN output from the control unit 30. When the acquired drive signal IN is an ON command, the drive unit 50 performs a charging process. The charging process is a process of turning on the charging switch 41 and turning off the discharge switch 44. According to the charging process, the gate voltage of the switch SW becomes equal to or higher than the threshold voltage Vth, and the switch SW is switched to the ON state.

When the acquired drive signal IN is an off command, the drive unit 50 performs a discharge process. The discharge process is a process in which the charge switch 41 is turned off and the discharge switch 44 is turned on. According to the discharge process, the gate voltage of the switch SW becomes less than the threshold voltage Vth, and the switch SW is switched to the off state.

The function provided by the drive unit 50 can be provided by, for example, software recorded in a substantive memory device, a computer for executing the software, hardware, or a combination thereof.

The drive circuit Dr includes a mirror transition determination unit 49, a voltage detection unit 51, and a determination device 52. The mirror transition determination unit 49 detects the gate voltage of the switch SW, and determines whether or not the mirror period has been entered based on the detected gate voltage. If, for example, the mirror transition determination unit 49 determines that the mirror period has been entered when it is determined that a period in which the detected gate voltage is maintained at a constant voltage has appeared after the drive signal IN is switched to the ON command. good. The mirror shift determination unit 49 outputs the determination result to the determination device 52.

The voltage detection unit 51 detects the gate voltage of the switch SW and outputs the detected gate voltage Vgr to the determination device 52.

After the drive signal IN was switched to the ON command and the gate voltage Vgr started to rise, the determination device 52 shifted from the mirror transition determination unit 49 to the mirror period by the time the gate voltage Vgr reached the determination voltage Vsc. If the determination result is not input, the drive unit 50 is instructed to switch the switch SW to the off state. The determination voltage Vsc is set to a value higher than the mirror voltage VM of the switch SW and lower than the output voltage Vcc of the constant voltage power supply 40 (for example, 12V). When the determination device 52 inputs an instruction to switch to the off state, the drive unit 50 switches the switch SW to the off state by the discharge process even if the drive signal IN is an on command.

On the other hand, when the determination device 52 inputs a determination result that the mirror transition determination unit 49 has shifted to the mirror period after the gate voltage Vgr starts to rise and before the gate voltage Vgr reaches the determination voltage Vsc. , Do not instruct the drive unit 50 to switch the switch SW to the off state.

In the present embodiment, the mirror shift determination unit 49 corresponds to the “determination unit”, and the drive unit 50 and the determination device 52 correspond to the “off switching unit”.

In the short-circuit protection process of the switch SW described above, the mirror period appears when the short-circuit current does not flow in the switch SW, whereas the mirror period does not appear when the short-circuit current starts to flow in the switch SW. This is a process in consideration of this. By this process, the short circuit of TYPE1 can be appropriately dealt with. A short circuit of TYPE1 is a short circuit of the upper and lower arms in which both the upper and lower arm switches are turned on by switching the other from the off state to the on state in a situation where one of the upper and lower arm switches is short-circuited. That is.

FIG. 3 shows a procedure of the short-circuit protection process executed by the determination device 52.

In step S10, it is determined whether or not the gate voltage Vgr detected by the voltage detection unit 51 has started to rise.

If an affirmative determination is made in step S10, the process proceeds to step S11, and it is determined whether or not the mirror transition determination unit 49 has notified the determination result that the mirror period has been entered.

If it is determined in step S11 that the notification has been made, the process proceeds to step S12 to invalidate the short circuit determination. In this case, the drive unit 50 is not instructed to switch the switch SW to the off state.

If a negative determination is made in step S11, the process proceeds to step S13, and it is determined whether or not the detected gate voltage Vgr has reached the determination voltage Vsc. If it is determined that the gate voltage Vgr has not reached the determination voltage Vsc, the process proceeds to step S11.

On the other hand, when it is determined that the gate voltage Vgr has reached the determination voltage Vsc, the process proceeds to step S14, and it is determined that a short circuit of TYPE1 has occurred. Then, in step S15, the drive unit 50 is instructed to switch the switch SW to the off state.

The phenomenon that a short-circuit current flows through the switch SW is not limited to the upper and lower arm short-circuits, but may also occur, for example, due to a phase-to-phase short circuit or a ground fault.

The short circuit protection process will be described with reference to FIG. FIG. 4A shows the transition of the drive signal IN, FIG. 4B shows the transition of the gate voltage Vge of the switch SW in the normal state when the upper and lower arm short circuit does not occur, and FIG. 4C shows the transition of TYPE1. The transition of the gate voltage Vge of the switch SW when a short circuit occurs is shown. FIG. 4D shows the transition of the determination result of the determination device 52.

First, the processing in the normal state will be described with reference to FIGS. 4A, 4B, and 4D.

At time t1, the drive signal IN is switched to the on command. Therefore, the charging process is started, and the gate voltage Vge starts to rise from 0.

Then, at time t2, the gate voltage Vge reaches the mirror voltage VM. After that, the mirror period ends at time t3, and the gate voltage Vge begins to rise again. After the time t3, the gate voltage Vgr detected by the voltage detection unit 51 reaches the determination voltage Vsc, but it is not determined by the determination device 52 that a short circuit has occurred. The switch SW is not instructed to switch to the off state. After that, at time t6, the gate voltage Vge reaches the output voltage Vcc of the constant voltage power supply 40.

Subsequently, processing when a short circuit of TYPE1 occurs will be described with reference to FIGS. 4A, 4C, and 4D. In the following description, among the upper and lower arm switches, the switch in which the short failure has occurred may be referred to as an opposed arm switch, and the switch in which the short failure has not occurred may be referred to as the own arm switch.

At time t1, the drive signal IN corresponding to the own arm switch is switched to the on command, so that the gate voltage Vge of the own arm switch starts to rise from 0. When the own arm switch is switched to the ON state, a short circuit of TYPE1 occurs. In this case, the mirror period of the own arm switch does not appear, and the gate voltage Vge of the own arm switch continues to increase monotonically. As a result, the gate voltage Vgr detected by the voltage detection unit 51 reaches the determination voltage Vsc at time t4 without being determined by the determination device 52 to have shifted to the mirror period, and the determination device 52 causes a short circuit. Is determined. As a result, the determination device 52 is instructed to switch to the off state of the switch SW to the drive unit 50, and the own arm switch is switched to the off state. After that, at time t5, the gate voltage Vge reaches the output voltage Vcc of the constant voltage power supply 40.

According to the present embodiment described above, the following effects can be obtained.

During the period when the drive signal IN is set to ON, it is determined whether or not the mirror period has been entered based on the detected value of the gate voltage. Then, if it is not determined that the mirror period has been entered in the period from the switching to the on command until the gate voltage Vgr reaches the determination voltage Vsc, the switch SW is turned off even when the on command is given. Switch to the state. This eliminates the need for dedicated elements such as diodes and capacitors used in the Desat method and sense resistors used in the sense current method. Further, the short-circuit detection terminal of the drive circuit Dr becomes unnecessary, and the gate terminal Tg used for turning on / off the switch SW in the normal drive for controlling the control amount of the rotary electric machine to the command value can be diverted to the short-circuit detection. Therefore, it is possible to reduce the number of dedicated elements for short-circuit detection and short-circuit detection terminals.

<Second Embodiment>
Hereinafter, the second embodiment will be described with reference to the drawings, focusing on the differences from the first embodiment. In the present embodiment, the method of determining whether or not the mirror period has been entered is changed.

FIG. 5 shows the drive circuit Dr according to the present embodiment. In FIG. 5, the same configurations as those shown in FIG. 2 above are designated by the same reference numerals for convenience.

The drive circuit Dr includes a differentiating circuit 53 in place of the mirror transition determination unit 49. The differentiating circuit 53 detects the gate voltage of the switch SW as the input voltage Vin, and outputs the time derivative value of the detected input voltage Vin as the output voltage Vout to the determination device 52. As the differentiating circuit 53, for example, as shown in FIG. 6, a differentiating circuit 53 including an operational amplifier 53a, a capacitor 53b, a resistor 53c, and a reference voltage source 53d can be used. Vb in FIG. 6 indicates the output voltage (hereinafter referred to as the specified voltage) of the reference voltage source 53d.

After the drive signal IN is switched to the ON command, the input voltage Vin changes positively until the gate voltage of the switch SW becomes the mirror voltage VM, so that the output voltage Vout of the differentiating circuit 53 becomes L. On the other hand, during the mirror period, the input voltage Vin is maintained at the mirror voltage VM, so that “Vout = Vb”. That is, the output voltage Vout of the differentiating circuit 53 becomes H. From the above, by detecting that the output voltage Vout of the differentiating circuit 53 becomes H, it is possible to detect that the mirror period has started.

In the determination device 52, after the drive signal IN is switched to the ON command and the detected gate voltage Vgr starts to rise, the output voltage Vout of the differentiating circuit 53 becomes H by the time the gate voltage Vgr reaches the determination voltage Vsc. If it is not determined, the drive unit 50 is instructed to switch the switch SW to the off state.

In the present embodiment, the differentiating circuit 53 corresponds to the "differentiated value calculation unit", the determination unit 52 corresponds to the "determination unit", and the drive unit 50 and the determination unit 52 correspond to the "off switching unit".

The operation of the drive circuit Dr in the normal state will be described with reference to FIG. 7. 7 (c) shows the transition of the output voltage Vout of the differentiating circuit 53, and FIGS. 7 (a) and 7 (b) correspond to FIGS. 4 (a) and 4 (b) above.

Since the drive signal IN is switched to the ON command at time t1, the gate voltage Vge begins to rise. During the period from time t1 to time t2 when the gate voltage Vge reaches the mirror voltage VM, the output voltage Vout of the differentiating circuit 53 is maintained at L.

The output voltage Vout of the differentiating circuit 53 is maintained at H until the time t2 to t3, which is the mirror period. After that, the output voltage Vout of the differentiating circuit 53 is maintained at L from the time t3 when the gate voltage Vge starts to rise again until the gate voltage Vge reaches the output voltage Vcc of the constant voltage power supply 40. After the time t3, the gate voltage Vgr detected by the voltage detection unit 51 reaches the determination voltage Vsc, but the output voltage Vout of the differentiating circuit 53 is H, so that the short-circuit determination is invalidated in the determination device 52. .. As a result, switching from the determination device 52 to the drive unit 50 to the off state of the switch SW is not instructed.

According to the present embodiment described above, the same effect as that of the first embodiment can be obtained.

<Third Embodiment>
Hereinafter, the third embodiment will be described with reference to the drawings, focusing on the differences from the first embodiment. In this embodiment, the drive circuit Dr shown in FIG. 8 is used. In FIG. 8, the same configurations as those shown in FIG. 2 above are designated by the same reference numerals for convenience.

The drive circuit Dr includes a reference voltage generation unit 60. The reference voltage generation unit 60 includes a constant voltage power supply 61, a charging switch 62, a charging resistor 63, and a capacitor 66. The charging switch 62 of this embodiment is a P-channel MOSFET. In FIG. 8, Vcc indicates the output voltage of the constant voltage power supply 61, and Cref indicates the capacitance of the capacitor 66. The first end of the capacitor 66 is connected to the constant voltage power supply 61 via the charging switch 62. The emitter of the switch SW is connected to the second end of the capacitor 66.

The reference voltage generation unit 60 includes a discharge resistor 64 and a discharge switch 65. The discharge switch 65 of this embodiment is an N-channel MOSFET. The emitter of the switch SW is connected to the first end of the capacitor 66 via the discharge resistor 64 and the discharge switch 65. The reference voltage generation unit 60 outputs the voltage between the terminals of the capacitor 66 as the reference voltage Vref.

The drive circuit Dr includes a voltage buffer unit 70. The voltage buffer unit 70 voltage buffers the reference voltage Vref from the reference voltage generation unit 60. The voltage buffer unit 70 of the present embodiment is a circuit including an operational amplifier as shown in FIG.

The drive circuit Dr includes a detection resistor 71. A gate terminal Tg is connected to the output terminal of the voltage buffer unit 70 via a detection resistor 71.

In the present embodiment, the charging process performed by the drive unit 50 is a process in which the charging switch 62 is turned on and the discharge switch 65 is turned off. During the period when the charging switch 62 is turned on, the reference voltage Vref is a time constant determined by the resistance value of the charging resistor 63 and the capacitance Clef of the capacitor 66 from 0 toward the output voltage Vcc of the constant voltage power supply 61. It increases monotonically with τ.

Further, the discharge process of the present embodiment is a process in which the charge switch 62 is turned off and the discharge switch 65 is turned on. During the period when the discharge switch 65 is turned on, the reference voltage Vref is a time constant determined by the resistance value of the discharge resistor 64 and the capacitance Clef of the capacitor 66 from the output voltage Vcc of the constant voltage power supply 61 toward 0. Decreases monotonously.

The drive circuit Dr includes a differential voltage detection unit 74, a voltage detection unit 51, and a determination device 52. The differential voltage detection unit 74 detects the inter-terminal voltage ΔVd of the detection resistor 71, and outputs the detected inter-terminal voltage ΔVd to the determination device 52. The terminal voltage ΔVd is the difference between the reference voltage Vref and the gate voltage Vge.

After the charging switch 62 is switched to the ON state, the gate voltage Vge is controlled by the voltage buffer unit 70 to the reference voltage Vref until the gate voltage Vge rises to the mirror voltage VM. Therefore, the voltage between terminals ΔVd detected by the difference voltage detection unit 74 is maintained at 0. After that, during the period in which the gate voltage Vge is maintained at the mirror voltage VM, the deviation of the reference voltage Vref with respect to the gate voltage Vge becomes large with the passage of time. As a result, the voltage between terminals ΔVd detected by the difference voltage detection unit 74 increases with the passage of time.

After the drive signal IN is switched to the ON command, the determination device 52 determines the timing at which the inter-terminal voltage ΔVd detected by the difference voltage detection unit 74 becomes the determination threshold value Vα as the transition timing of the mirror period.

In the determination device 52, after the drive signal IN is switched to the ON command and the detected gate voltage Vgr starts to rise, the gate voltage Vgr reaches the determination voltage Vsc between the terminals detected by the difference voltage detection unit 74. When the voltage ΔVd does not rise to the determination threshold value Vα, the drive unit 50 is instructed to switch the switch SW to the off state by the discharge process.

On the other hand, in the determination device 52, after the gate voltage Vgr starts to rise, the terminal voltage ΔVd detected by the differential voltage detection unit 74 reaches the determination threshold value Vα by the time the gate voltage Vgr reaches the determination voltage Vsc. In this case, the drive unit 50 is not instructed to switch the switch SW to the off state.

In the present embodiment, the determination device 52 corresponds to the "determination unit", and the drive unit 50 and the determination unit 52 correspond to the "off switching unit".

The operation of the drive circuit Dr in the normal state will be described with reference to FIG. FIG. 10A shows the transition of the drive signal IN, FIG. 10B shows the transition of the gate voltage Vge and the reference voltage Vref, and FIG. 10C shows the transition of the terminal voltage detected by the differential voltage detection unit 74. The transition of ΔVd is shown, and FIG. 10D shows the transition of the determination result of the determination device 52. 10 (e) shows the transition of the charging current Ig of the gate of the switch SW, FIG. 10 (f) shows the transition of the driving state of the charging switch 62, and FIG. 10 (g) shows the transition of the driving state of the discharge switch 65. Is shown.

Before the time t1, the drive signal IN is turned off, the charge switch 62 is turned on, and the discharge switch 65 is turned on, so that the stored charge of the capacitor 66 becomes 0. There is. Therefore, "Vref = Vge = 0" is set.

Since the drive signal IN is switched to the on command at time t1, the charging switch 62 is switched to the on state and the discharge switch 65 is switched to the off state. As a result, the reference voltage Vref starts to rise at the time constant τ. The rate of increase of the reference voltage Vref after time t1 is not always constant. However, FIG. 10B shows the transition of the reference voltage Vref at which the rising speed becomes a constant speed for convenience.

The reference voltage Vref is input to the voltage buffer unit 70, and the output voltage Vout of the voltage buffer unit 70 becomes a voltage equivalent to the reference voltage Vref. Therefore, the gate voltage Vge rises as the reference voltage Vref rises. Here, in the period from the time t1 when the gate voltage Vge starts to rise to the time t2 when the gate voltage Vge becomes the mirror voltage VM, the charging current Ig1 of the gate of the switch SW is expressed by the following equation (eq1). In the following equation (eq1), Cge indicates the feedback capacity of the switch SW.

その後、時刻ｔ２〜ｔ４がミラー期間となる。ミラー期間に移行した後は、帰還容量Ｃｇｅへの充電によりゲート電圧Ｖｇｅが一定に維持されるのに対し、基準電圧Ｖｒｅｆは上昇し続ける。その結果、差電圧検出部７４により検出される端子間電圧ΔＶｄが時間経過とともに大きくなる。ここで、この場合における充電電流Ｉｇ２は、下式（ｅｑ２）で表される。下式（ｅｑ２）において、Ｒｄは検出用抵抗体７１の抵抗値を示す。

After that, the time t2 to t4 becomes the mirror period. After the transition to the mirror period, the gate voltage Vge is kept constant by charging the feedback capacitance Cge, while the reference voltage Vref continues to rise. As a result, the voltage between terminals ΔVd detected by the difference voltage detection unit 74 increases with the passage of time. Here, the charging current Ig2 in this case is expressed by the following equation (eq2). In the following equation (eq2), Rd indicates the resistance value of the detection resistor 71.

上式（ｅｑ２）は、時間経過とともに充電電流Ｉｇ２が増加することを示している。以上から、ゲートの充電電流が大きくなったことを検出する、つまり、端子間電圧ΔＶｄが判定閾値Ｖαに到達したことを検出することにより、ミラー期間が開始されたことを判定できる。ここで、ミラー期間に移行したことを検出するためには、「Ｉｇ２＞Ｉｇ１」に設定される必要がある。なお、時間経過とともに充電電流Ｉｇ２を増加させることにより、スイッチング速度を高めてスイッチング損失を低減させることができる。

The above equation (eq2) shows that the charging current Ig2 increases with the passage of time. From the above, it can be determined that the mirror period has started by detecting that the charging current of the gate has increased, that is, detecting that the voltage between terminals ΔVd has reached the determination threshold value Vα. Here, in order to detect the transition to the mirror period, it is necessary to set "Ig2>Ig1". By increasing the charging current Ig2 with the passage of time, the switching speed can be increased and the switching loss can be reduced.

At time t3 during the mirror period, the determination device 52 determines that the inter-terminal voltage ΔVd detected by the difference voltage detection unit 74 has reached the determination threshold value Vα, and determines that the mirror period has started. Therefore, after the time t4, the gate voltage Vgr detected by the voltage detection unit 51 reaches the determination voltage Vsc, but the short-circuit determination is invalidated in the determination device 52. As a result, switching from the determination device 52 to the drive unit 50 to the off state of the switch SW is not instructed.

After that, the reference voltage Vref reaches the output voltage Vcc of the constant voltage power supply 61 at time t5, and the gate voltage Vge reaches the output voltage Vcc of the constant voltage power supply 61 at time t6.

According to the present embodiment described above, a short circuit can be detected by diverting a configuration that reduces switching loss. Therefore, the number of parts of the drive circuit Dr can be reduced.

<Modified example of the third embodiment>
The voltage buffer unit may be the one shown in FIG. The voltage buffer unit 75 shown in FIG. 11 includes a constant voltage power supply 75a, a first switch 75b of the NPN type bipolar transistor, and a second switch 75c of the PNP type bipolar transistor. A reference voltage Vref is applied to the bases of the first and second switches 75b and 75c connected to the input terminals of the voltage buffer unit 75. The first end of the detection resistor 71 is connected to the output terminals connected to the emitters of the first and second switches 75b and 75c, respectively.

During the period when the charging process is performed and the reference voltage Vref increases monotonically, the output voltage Vout of the voltage buffer unit 75 is "Vout = Vref-Vf1" when the voltage between the base and the emitter of the first switch 75b is Vf1. It becomes. That is, in the period in which the reference voltage Vref increases monotonically, the output voltage Vout increases with a slight delay with respect to the reference voltage Vref.

On the other hand, during the period when the discharge process is performed and the reference voltage Vref decreases monotonically, the output voltage Vout of the voltage buffer unit 75 is "Vout = Vref + Vf2" when the voltage between the base and the emitter of the second switch 75c is Vf2. It becomes. That is, in the period in which the reference voltage Vref decreases monotonically, the output voltage Vout decreases with a slight delay with respect to the reference voltage Vref.

<Fourth Embodiment>
Hereinafter, the fourth embodiment will be described with reference to the drawings, focusing on the differences from the third embodiment. In this embodiment, as shown in FIG. 12, the configuration of the drive circuit Dr is changed. In FIG. 12, the same components as those shown in FIG. 8 are designated by the same reference numerals for convenience.

The drive circuit Dr includes a reference voltage generation unit 80. The reference voltage generation unit 80 includes a constant voltage power supply 81, a first constant current power supply 82, a charge switch 83, a discharge switch 84, a second constant current power supply 85, and a capacitor 86. The charge switch 83 and the discharge switch 84 are driven by the drive unit 50. The first constant current power supply 82 is supplied with power from the constant voltage power supply 81 and outputs the first reference current Iref1. The first end of the capacitor 86 is connected to the first constant current power supply 82 via the charging switch 83. The emitter of the switch SW is connected to the second end of the capacitor 86. The reference voltage generation unit 80 outputs the voltage between the terminals of the capacitor 86 as the reference voltage Vref.

The emitter of the switch SW is connected to the second end of the capacitor 86 via the discharge switch 84 and the second constant current power supply 85. The second constant current power supply 85 is configured to set the discharge current from the capacitor 86 as the second reference current Iref2 when the first discharge switch 84 is turned on.

The drive circuit Dr includes a voltage buffer unit 91. The voltage buffer unit 91 of the present embodiment is a circuit including an operational amplifier, and voltage buffers the reference voltage Vref from the reference voltage generation unit 80. The drive circuit Dr further includes a limiting resistor 92, a comparator 93, a reference power supply 94, a first control switch 95, and a second control switch 96. Each of the control switches 95 and 96 of this embodiment is an NPN type bipolar transistor. According to the configuration including the voltage buffer unit 91, the limiting resistor 92, the comparator 93, and the reference power supply 94, the reference voltage Vref is voltage buffered while limiting the maximum value of the output current of the voltage buffer unit 91 by the current limit value Illim. Can realize the function to do.

The first end of the capacitor 86 is connected to the non-inverting input terminal of the voltage buffer unit 91. The first end of the limiting resistor 92 and the negative electrode terminal of the reference power supply 94 are connected to the output terminal of the voltage buffer unit 91. An inverting input terminal of the voltage buffer unit 91, a non-inverting input terminal of the comparator 93, and a gate terminal Tg are connected to the second end of the limiting resistor 92. An inverting input terminal of the comparator 93 is connected to the positive electrode terminal of the reference power supply 94. The limiting resistor 92, the comparator 93, the reference power supply 94, and the first control switch 95 set the reference voltage Vref during the mirror period to the value obtained by adding the output voltage of the reference power supply 94 (hereinafter, offset value Vh) to the mirror voltage VM. It is a configuration to maintain.

The bases of the first control switch 95 and the second control switch 96 are connected to the output terminals of the comparator 93. The second end of the limiting resistor 92 is connected to the collector of the first control switch 95, and the first end of the capacitor 86 is connected to the emitter of the first control switch 95.

The drive circuit Dr includes a resistor 97 and a constant voltage power supply 98. A constant voltage power supply 98 is connected to the collector of the second control switch 96 via the resistor 97. The first end of the capacitor 86 is connected to the emitter of the second control switch 96. A current proportional to the current flowing through the first control switch 95 flows through the second control switch 96.

In the present embodiment, the charging process is a process in which the charging switch 83 is turned on and the discharge switch 84 is turned off. Further, the discharge process of the present embodiment is a process in which the charge switch 83 is turned off and the discharge switch 84 is turned on. During the period in which the charging switch 83 is turned on, the reference voltage Vref rises from 0 toward the output voltage Vcc of the constant voltage power supply 81 at a constant speed (hereinafter, charging side slew rate SRC). The slew rate SRC on the charging side is determined by the first reference current Static electricity Ref1 of the first constant current power supply 82 and the capacitance Clef of the capacitor 86.

The drive circuit Dr includes a voltage detection unit 51 and a determination device 52. The determination device 52 detects the voltage between the terminals of the resistor 97 as the correlation value of the current flowing through the second control switch 96. When the charging switch 83 is switched to the ON state, the gate voltage Vge of the switch SW starts to rise from 0 at the slew rate SRC on the charging side. After that, the gate voltage Vge is controlled by the voltage buffer unit 91 to the reference voltage Vref until the gate voltage Vge becomes the mirror voltage VM. In this case, the first control switch 95 and the second control switch 96 are turned off, and no current flows through the second control switch 96. Therefore, the current (voltage between terminals) detected by the determination device 52 is maintained at 0.

After that, during the period in which the gate voltage Vge is maintained at the mirror voltage VM, the reference voltage Vref adds an offset value Vh to the mirror voltage VM by the limiting resistor 92, the comparator 93, the reference power supply 94, and the first control switch 95. A current flows through the capacitor 86 via the first control switch 95 so that the value is maintained at the same value. At this time, a current proportional to the current flowing through the first control switch 95 flows through the second control switch 96. As a result, the voltage between terminals detected by the determination device 52 becomes larger than 0. Therefore, it is possible to determine whether or not the mirror period has been entered based on the voltage between the terminals. Specifically, the determination device 52 determines the timing at which the detected voltage between terminals rises from 0 to a predetermined voltage (> 0) as the timing at which the mirror period shifts.

In the determination device 52, after the drive signal IN is switched to the ON command and the detected gate voltage Vgr starts to rise, the detected voltage between terminals 97 of the resistor 97 is predetermined by the time the gate voltage Vgr reaches the determination voltage Vsc. If the voltage does not rise to the voltage, the drive unit 50 is instructed to switch the switch SW to the off state by the discharge process.

On the other hand, the determination device 52 switches to the drive unit 50 when the detected voltage between terminals reaches a predetermined voltage after the gate voltage Vgr starts to rise and before the gate voltage Vgr reaches the determination voltage Vsc. Does not instruct to switch the SW to the off state.

In the present embodiment, the determination device 52 corresponds to the "determination unit", the determination unit 52 and the drive unit 50 correspond to the "off switching unit", and the limiting resistor 92, the comparator 93, the reference power supply 94, and the first unit. The control switch 95 corresponds to the "offset portion".

The operation of the drive circuit Dr in the normal state will be described with reference to FIG. 13 (a) to 13 (d) correspond to FIGS. 10 (a), (b), (d), and (e) above. 13 (e) shows the transition of the drive state of the charge switch 83, and FIG. 13 (f) shows the transition of the drive state of the discharge switch 84.

Before the time t1, the charge switch 83 is turned off and the discharge switch 84 is turned on, and the stored charge of the capacitor 86 is zero. Therefore, "Vref = Vge = 0" is set.

Since the drive signal IN is switched to the on command at time t1, the charge switch 83 is switched to the on state and the discharge switch 84 is switched to the off state. As a result, the reference voltage Vref starts to rise at a constant slew rate SRC on the charging side.

The reference voltage Vref is input to the voltage buffer unit 91, and the output voltage Vout of the voltage buffer unit 91 becomes a voltage equivalent to the reference voltage Vref. Therefore, as the reference voltage Vref increases, the gate voltage Vge also increases at the slew rate SRC on the charging side. Here, in the period from the time t1 when the gate voltage Vge starts to rise to the time t2 when the gate voltage Vge becomes the mirror voltage VM, the charging current Ig1 of the gate of the switch SW is expressed by the following equation (eq3). Since the feedback capacitance Cge, the capacitance Clef, and the first reference current Iref1 are constant values, the charging current Ig1 becomes a constant current.

その後、時刻ｔ２〜ｔ３がミラー期間となる。ミラー期間に移行した後は、帰還容量Ｃｇｅへの充電によりゲート電圧Ｖｇｅが一定に維持されるのに対し、基準電圧Ｖｒｅｆは「ＶＭ＋Ｖｈ」に維持される。この場合、第２制御スイッチ９６を介して電流が流れるため、判定器５２は、検出した端子間電圧が所定電圧になったと判定し、ミラー期間に移行したと判定する。ミラー期間における充電電流Ｉｌｉｍは、下式（ｅｑ４）で表される。下式（ｅｑ４）において、Ｒｌｉｍは制限抵抗体９２の抵抗値を示す。抵抗値Ｒｌｉｍ及びオフセット値Ｖｈが一定値であるため、充電電流Ｉｌｉｍは定電流となる。ミラー期間に渡って大きな定電流を供給できるため、スイッチング損失を好適に低減できる。ここで、ミラー期間に移行したことを検出するためには、「Ｉｌｉｍ＞Ｉｇ１」に設定される必要がある。

After that, the time t2 to t3 becomes the mirror period. After the transition to the mirror period, the gate voltage Vge is maintained constant by charging the feedback capacity Cge, while the reference voltage Vref is maintained at "VM + Vh". In this case, since the current flows through the second control switch 96, the determination device 52 determines that the detected voltage between the terminals has reached a predetermined voltage, and determines that the mirror period has started. The charging current Illim in the mirror period is expressed by the following equation (eq4). In the following equation (eq4), Rlim indicates the resistance value of the limiting resistor 92. Since the resistance value Rlim and the offset value Vh are constant values, the charging current Ilim becomes a constant current. Since a large constant current can be supplied over the mirror period, switching loss can be suitably reduced. Here, in order to detect the transition to the mirror period, it is necessary to set "Ilim>Ig1".

また、本実施形態では、ミラー期間中において基準電圧Ｖｒｅｆを「ＶＭ＋Ｖｈ」に維持するために第１制御スイッチ９５を介してコンデンサ８６に供給される電流の相関値（つまり、抵抗体９７の端子間電圧）が判定器５２により検出される。そして、その検出値に基づいてミラー期間に移行したことが判定される。

Further, in the present embodiment, the correlation value of the current supplied to the capacitor 86 via the first control switch 95 in order to maintain the reference voltage Vref at “VM + Vh” during the mirror period (that is, between the terminals of the resistor 97). Voltage) is detected by the determination device 52. Then, it is determined that the mirror period has started based on the detected value.

According to the present embodiment described above, it can be determined that the mirror period has been entered by using the current supplied to maintain the reference voltage Vref at “VM + Vh”. Therefore, the number of parts of the drive circuit Dr can be reduced.

<Modified example of the fourth embodiment>
The drive circuit Dr shown in FIG. 12 may not be provided with the second control switch 96, the resistor 97, and the constant voltage power supply 98. In this case, the determination device 52 may detect, for example, the voltage between the collector and the emitter of the second control switch 96 as a charging current, and determine whether or not the mirror period has been entered based on the detected value.

In the drive circuit Dr shown in FIG. 12, instead of the configuration including the voltage buffer unit 91, the limiting resistor 92, the comparator 93, the reference power supply 94, and the first control switch 95, another configuration having the same function as this configuration is provided. May be provided.

<Fifth Embodiment>
Hereinafter, the fifth embodiment will be described with reference to the drawings, focusing on the differences from the fourth embodiment. In this embodiment, as shown in FIG. 14, the configuration of the drive circuit Dr is changed. In FIG. 14, the same configurations as those shown in FIG. 12 above are designated by the same reference numerals for convenience. Further, in the present embodiment, the voltage buffer unit 91, the limiting resistor 92, the comparator 93 and the reference power supply 94 of FIG. 12 above are used in the first voltage buffer unit 91, the first limiting resistor 92, the first comparator 93 and the first comparator. It shall be referred to as 1 reference power supply 94. Further, the discharge switch 84 will be referred to as a first discharge switch 84.

The drive circuit Dr has, in addition to the configuration shown in FIG. 12, a configuration for dealing with a short circuit of the TYPE 2. The short circuit of TYPE2 is a short circuit of the upper and lower arms in which one of the upper and lower arm switches is turned on and the other is short-circuited.

The drive circuit Dr has a second voltage buffer unit 100, a second limiting resistor 101, a second comparator 102, a second reference power supply 103, a third control switch 104, and a fourth control as a configuration for dealing with a short circuit of the TYPE 2. It includes a switch 105 and a detection resistor 108. The second voltage buffer unit 100 is a circuit including an operational amplifier, and voltage buffers the reference voltage Vref from the reference voltage generation unit 80. Each of the control switches 104 and 105 of this embodiment is a PNP type bipolar transistor.

The first end of the second limiting resistor 101 and the inverting input terminal of the second comparator 102 are connected to the output terminal of the second voltage buffer unit 100. An inverting input terminal of the second voltage buffer unit 100, a negative electrode terminal of the second reference power supply 103, and a gate terminal Tg are connected to the second end of the second limiting resistor 101. The non-inverting input terminal of the second comparator 102 is connected to the positive electrode terminal of the second reference power supply 103. By the way, even if the configuration shown in FIG. 14 and the configuration shown in FIG. 12 can be shared as appropriate, such as using the second reference power supply 103 and the first reference power supply 94 as a common reference power supply, the configuration shown in FIG. 14 and the configuration shown in FIG. good.

The drive circuit Dr includes a discharge resistor 106 and a second discharge switch 107. The second discharge switch 107 of this embodiment is an N-channel MOSFET. The emitter of the switch SW is connected to the gate terminal Tg via the discharge resistor 106 and the second discharge switch 107.

Emitters of the third control switch 104 and the fourth control switch 105 are connected to the second end of the second limiting resistor 101. The first end of the capacitor 86 is connected to the collector of the third control switch 104. The emitter of the switch SW is connected to the collector of the fourth control switch 105 via the detection resistor 108. The output terminal of the second comparator 102 is connected to the base of each of the third control switch 104 and the fourth control switch 105. A current proportional to the current flowing through the third control switch 104 flows through the fourth control switch 105.

After the drive signal IN is switched to the ON command, the gate voltage Vge of the own arm switch reaches the output voltage Vcc of the constant voltage power supply 81. After that, a short circuit occurs in the facing arm switch during the period when the ON command is given, so that the TYPE 2 is short-circuited. In this case, assuming that the output voltage of the DC power supply 21 is VH, the charge of "VH x Cge" is rapidly supplied to the gate of the own arm switch. In this case, the gate voltage of the own arm switch tends to rise sharply beyond the output voltage Vcc of the constant voltage power supply 81. However, in the present embodiment, the gate charge is sucked into the second voltage buffer unit 100, so that a rapid increase in the gate voltage is suppressed. Specifically, the gate voltage is limited to a value (Vref + Vh) obtained by adding the output voltage Vh of the second reference power supply 103 to the reference voltage Vref.

At this time, since the discharge current of the gate flows through the third control switch 104, a current proportional to this discharge current also flows through the fourth control switch 105. The determination device 52 detects the current flowing through the fourth control switch 105 as the inter-terminal voltage ΔVk of the detection resistor 108. In the present embodiment, the voltage between terminals ΔVk is positive when the potential on the collector side of the fourth control switch 105 is higher than that on the emitter side of the switch SW. When the determination device 52 determines that the detected voltage between terminals ΔVk exceeds the threshold value Vβ (> 0), it determines that a short circuit of TYPE 2 has occurred, and stops the operation of the second voltage buffer unit 100. The enable signal to be instructed is output, and the second discharge switch 107 is switched to the on state. The discharge rate of the gate charge via the discharge resistor 106 and the second discharge switch 107 is set to be lower than the discharge rate of the gate charge when the first discharge switch 84 is turned on.

FIG. 15 shows a procedure of processing executed by the determination device 52.

In step S20, it is determined whether or not the detected voltage between terminals ΔVk exceeds the threshold value Vβ.

If an affirmative determination is made in step S20, the process proceeds to step S21, and it is determined that a short circuit in TYPE2 has occurred. Then, in step S22, an enable signal is output to the second voltage buffer unit 100, and the second discharge switch 107 is switched to the on state.

The operation of the drive circuit Dr when a short circuit of TYPE2 occurs will be described with reference to FIG. FIG. 16A shows the transition of the gate voltage Vge of the own arm switch, FIG. 16B shows the transition of the gate current Ig of the own arm switch, and FIG. 16C shows the transition of the determination result of the determination device 52. 16 (d) shows the transition of the driving state of the second discharge switch 107. In FIG. 16B, the positive gate current Ig indicates the charging current, and the negative gate current Ig indicates the discharging current.

At time t1, the drive signal IN is switched to the ON command, and the gate voltage Vge begins to rise. Then, after the mirror period of time t2 to t3, the gate voltage Vge reaches the output voltage Vcc of the constant voltage power supply 81 at time t4. In this case, "VCC = Vref = Vge".

After that, at time t5, a short-circuit failure occurs in the facing arm switch, and a short-circuit of TYPE2 occurs. In this case, the voltage Vce between the collector and the emitter of the own arm switch changes from the on-voltage Von to VH, and the gate charge of "VH x Vge" suddenly flows into the gate of the own arm switch. However, the gate voltage Vge is limited by "Vref + Vh" by the second voltage buffer unit 100, the second limiting resistor 101, the second comparator 102, the second reference power supply 103, and the third control switch 104, and the gate voltage Vge suddenly increases. The rise is suppressed. After that, at time t6, the operation of the second voltage buffer unit 100 is stopped, and the second discharge switch 107 is switched to the ON state.

According to the present embodiment described above, the own arm switch can be appropriately protected even when a short circuit of the TYPE 2 occurs.

<Other embodiments>
In addition, each of the above-mentioned embodiments may be changed and carried out as follows.

A second voltage buffer unit 100, a second limiting resistor 101, a second comparator 102, a second reference power supply 103, a third control switch 104, a fourth control switch 105, and a detection device shown in FIG. 14 of the fifth embodiment. The resistor 108 may be provided in the drive circuit Dr shown in FIG. 8 above.

The drive circuit Dr shown in FIG. 14 of the fifth embodiment may not be provided with the fourth control switch 105 and the detection resistor 108. In this case, the determination device 52 may detect, for example, the voltage between the collector and the emitter of the third control switch 104 as a discharge current, and determine whether or not a short circuit of the TYPE 2 has occurred based on the detected value.

-For detecting the overcurrent of the switch SW, which is smaller than the short-circuit current, not for short-circuit detection, for detecting the sense voltage, which is the potential difference between the dedicated element such as the sense resistor used in the sense current method and the sense resistor. The terminal may be provided in the drive circuit Dr.

-The switch constituting the switching device unit is not limited to the IGBT, and may be, for example, an N-channel MOSFET having a built-in body diode.

The power converter provided with the switch is not limited to the inverter, and may be, for example, a DCDC converter that transforms and outputs an input voltage. Specifically, the DCDC converter has at least one of a step-down function of stepping down the input voltage and outputting the step and a function of stepping up the input voltage and outputting the step-down function.

The controls and methods thereof described in the present disclosure are provided by a dedicated computer provided by configuring a processor and memory programmed to perform one or more functions embodied by a computer program. It may be realized. Alternatively, the controls and methods thereof described in the present disclosure may be implemented by a dedicated computer provided by configuring the processor with one or more dedicated hardware logic circuits. Alternatively, the controls and techniques described herein are by a combination of a processor and memory programmed to perform one or more functions and a processor configured by one or more hardware logic circuits. It may be realized by one or more dedicated computers configured. Further, the computer program may be stored in a computer-readable non-transitional tangible recording medium as an instruction executed by the computer.

49 ... Mirror transition determination unit, 50 ... Drive unit, 52 ... Judgment device, Dr ... Drive circuit, SW ... Switch.

Claims (7)

In the drive circuit (Dr) of the switch that drives the switch (SW),
A determination unit (49, 52) that determines whether or not the switch has entered the mirror period based on the gate voltage of the switch or the charging current of the gate of the switch during the period in which the ON command is given to the switch. When,
From the time when the ON command is given until the gate voltage of the switch reaches a determination voltage (Vsc) that is lower than the upper limit value (Vcc) of the gate voltage and higher than the mirror voltage (VM) of the switch. A switch drive circuit including an off switching unit (50, 52) for switching the switch to an off state when the determination unit does not determine that the mirror period has been entered during the period. The switch drive circuit according to claim 1, wherein the determination unit (49, 52) determines whether or not the mirror period has been entered based on the detected value of the gate voltage. A differential value calculation unit (53) for calculating the time differential value of the gate voltage based on the detected value of the gate voltage is provided.
The switch drive circuit according to claim 2, wherein the determination unit (52) determines whether or not the mirror period has been entered based on the calculated time differential value. A reference voltage generation unit (60) that outputs a reference voltage (Vref) that monotonically increases after the ON command is given, and
A voltage buffer unit (70, 75) for controlling the gate voltage of the switch to the reference voltage is provided.
The switch drive circuit according to claim 1, wherein the determination unit (52) determines whether or not the mirror period has been entered, based on the detected value of the potential difference between the gate voltage of the switch and the reference voltage. A reference voltage generator (80) that outputs a reference voltage (Vref),
A voltage buffer unit (91) that controls the gate voltage of the switch to the reference voltage, and
After the start of the mirror period, by supplying the charging current of the gate when the gate voltage is controlled to the reference voltage by the voltage buffer unit to the reference voltage generation unit, the said after the start of the mirror period. It is provided with an offset portion (92 to 95) that maintains the reference voltage at a value higher by a predetermined offset value (Vh) with respect to the gate voltage.
The determination unit (52) detects the charging current supplied to the reference voltage generation unit by the offset unit or its correlation value, and determines whether or not the mirror period has been entered based on the detected value. The switch drive circuit according to claim 1. The reference voltage generation unit (80) monotonically increases the reference voltage to the upper limit value during the period when the on command is given, and then maintains the reference voltage at the upper limit value.
The voltage buffer unit is a first voltage buffer unit.
A second voltage buffer unit (100) for controlling the gate voltage of the switch to the reference voltage is provided.
The off switching unit is a case where the gate voltage is controlled to the reference voltage by the second voltage buffer unit after the timing when the gate voltage reaches the upper limit value during the period when the on command is given. The drive circuit for a switch according to claim 4 or 5, wherein the discharge current of the gate or a correlation value thereof is detected, and the switch is switched to an off state when the detected value exceeds a threshold value (Vβ). In the drive circuit (Dr) of the switch that drives the switch (SW),
A reference voltage generator that monotonically increases the reference voltage (Vref) to the upper limit (Vcc) of the gate voltage of the switch and then maintains the reference voltage at the upper limit during the period when the on command is given to the switch. (80) and
A voltage buffer unit (100) that controls the gate voltage to the reference voltage,
The discharge current of the gate or its correlation when the gate voltage is controlled to the reference voltage by the voltage buffer unit after the timing when the gate voltage reaches the upper limit value during the period in which the on command is given. A switch drive circuit including an off switching unit (50, 52) that detects a value and switches the switch to an off state when the detected value exceeds a threshold value (Vβ).

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