JP7183375B1 - Protection circuit and power converter - Google Patents

Abstract

Kind Code: A1 A protection circuit and a power conversion device are provided for early detection of an overcurrent when a short circuit occurs in another circuit and an overcurrent occurs during a turn-on period of a semiconductor switching element. A first comparator (20) for outputting an output signal in a first state representing the occurrence of overcurrent when a voltage Vces at a high potential side terminal exceeds a first reference voltage, and a voltage Vges at a control terminal is a first comparator (20). 2 a second comparator 40 that outputs an output signal in the third state when the reference voltage exceeds the reference voltage and outputs an output signal in the fourth state when the voltage falls below the reference voltage; and when the output signal of the second comparator is in the fourth state. , a first comparator locking circuit 50 for reducing the voltage Vces at the high potential side terminal to less than the first reference voltage; and a second comparator locking circuit 50 for reducing the first reference voltage when the output signal of the second comparator is in the third state. 1 reference modification circuit 60 . [Selection drawing] Fig. 1

Description

TECHNICAL FIELD The present application relates to protection circuits and power converters.

Conventionally, when an upper arm or lower arm of a semiconductor switching element of a power conversion device has a short-circuit failure and an overcurrent flows through the normal upper arm or lower arm, an overcurrent detection circuit provided in a drive circuit detects an overcurrent ( short-circuit current) is detected.

A semiconductor switching element has an output characteristic in which a collector current changes according to a gate voltage and a collector voltage. There is a characteristic that as the gate voltage increases, the amount of increase in the collector current relative to the amount of increase in the collector voltage increases.

In a power conversion device, when a normal semiconductor switching element is turned on in a state in which an arm short circuit or a load short circuit occurs, the power supply voltage of the power conversion device is directly applied to the normal semiconductor switching device, causing the above-mentioned problems. Overcurrent flows due to output characteristics.

Patent Document 1 discloses an overcurrent detection circuit that detects the occurrence of overcurrent (short-circuit current). In the technique of Patent Document 1, a first comparator that determines the gate voltage of the semiconductor switching element and a second comparator that determines the collector voltage are provided, and the logical product of the determination results of the two comparators is 1. case, it is determined that an overcurrent has occurred.

In addition, in the technique of Patent Document 1, since the voltage obtained by dividing the gate voltage with a dividing resistor is input to the comparator, the terrace voltage of various semiconductor switching elements (minimum gate voltage for rated current flow) voltage), each resistance value of the dividing resistor is set.

Japanese Patent Laid-Open No. 2002-200002 describes a soft cut-off means for suppressing a collector voltage jump due to wiring inductance of a circuit when an overcurrent is cut off at high speed.

Patent No. 4223331 JP-A-2000-295838

If a short circuit occurs in another circuit during the turn-on period in which a normal semiconductor switching element is turned on and an overcurrent flows, the conductivity of the semiconductor is in a completely modulated state. The collector current will increase more rapidly than if there is a short circuit in . In this case, a displacement current flows through the gate-collector mirror capacitance due to the high current change speed, and the gate voltage rises to increase the peak of the overcurrent, which may cause the semiconductor switching element to malfunction.

As the collector current increases after the occurrence of a short circuit, the collector voltage increases, but there is a delay in the collector voltage increase. may malfunction.

Therefore, the present application aims to provide a protection circuit and a power conversion device that can detect the occurrence of overcurrent at an early stage when a short circuit occurs in another circuit during the turn-on period of a semiconductor switching element and an overcurrent occurs. aim.

The protection circuit according to the present application is
A semiconductor switching device comprising a high potential side terminal, a low potential side terminal, and a control terminal, and turning on and off conduction between the high potential side terminal and the low potential side terminal according to an increase or decrease in voltage applied to the control terminal. A protection circuit for detecting the occurrence of overcurrent between the high potential side terminal and the low potential side terminal in the element,
a first reference voltage generation circuit that generates a first reference voltage;
When the input voltage of the high potential side terminal exceeds the first reference voltage, outputting an output signal in the first state indicating the occurrence of overcurrent, and outputting the input voltage of the high potential side terminal when the input voltage of the high potential side terminal exceeds the first reference voltage. a first comparator that, when falling below one reference voltage, outputs an output signal in a second state indicating that no overcurrent has occurred;
a second reference voltage generation circuit that generates a second reference voltage;
outputting an output signal in a third state when the input voltage of the control terminal exceeds the second reference voltage; and outputting a fourth state output signal when the input voltage of the control terminal is lower than the second reference voltage. a second comparator that outputs a state output signal;
A first comparator lock circuit for lowering the voltage of the high potential side terminal input to the first comparator below the first reference voltage when the output signal of the second comparator is in the fourth state. When,
a first reference changing circuit that reduces the first reference voltage when the output signal of the second comparator is in the third state;
is provided.

The power conversion device according to the present application is
the protection circuit;
and the semiconductor switching element.

According to the protection circuit and the power conversion device of the present application, the first comparator outputs the first state output signal representing the occurrence of overcurrent when the input voltage of the high potential side terminal exceeds the first reference voltage. to detect the occurrence of overcurrent. On the other hand, when it is not turned on, immediately after the turn-on is started, and immediately after the turn-on is finished, the voltage of the high potential side terminal is high and exceeds the first reference voltage, and the occurrence of overcurrent is erroneously detected. Therefore, when the voltage at the control terminal is below the second reference voltage and the output signal of the second comparator is in the fourth state, the first comparator lock circuit is set to the high potential side input to the first comparator. Since the voltage of the terminal is lowered below the first reference voltage, the above erroneous detection can be prevented.

The first reference changing circuit reduces the first reference voltage when the voltage of the control terminal exceeds the second reference voltage and the output signal of the second comparator is in the third state. Therefore, the period until the voltage of the high potential side terminal exceeds the first reference voltage after a short circuit occurs during the turn-on period can be shortened, and the occurrence of overcurrent can be detected early. Therefore, even if a short circuit occurs during the turn-on period, the rapidly increasing current flowing through the high-potential side terminal can be stopped early, thereby suppressing failure of the element. On the other hand, when the voltage at the control terminal is below the second reference voltage and the output signal of the second comparator is in the fourth state, the first reference changing circuit does not lower the first reference voltage, so no short circuit occurs. Immediately after the start of turn-on of the state, the voltage of the high-potential side terminal exceeds the first reference voltage in a state where the voltage of the high-potential side terminal has not completely decreased, and erroneous determination that an overcurrent has occurred can be suppressed. It is possible to suppress erroneous determination due to noise components generated at turn-on. That is, by providing the first reference changing circuit, the first reference voltage for suppressing an erroneous determination when a short circuit occurs before turn-on and the first reference voltage for early overcurrent detection when a short circuit occurs during the turn-on period. The first reference voltage can be set appropriately.

1 is a circuit diagram of a protection circuit according to Embodiment 1; FIG. 4 is a time chart at normal current according to Embodiment 1. FIG. 5 is a time chart at the time of overcurrent when a short circuit occurs before turn-on according to the first embodiment; 5 is a time chart at the time of overcurrent when a short circuit occurs during the turn-on period according to Embodiment 1; 8 is a circuit diagram of an active clamp circuit according to a second embodiment; FIG. 8 is a time chart for explaining the operation of the active clamp circuit according to the second embodiment; FIG.

1. Embodiment 1
A protection circuit 1 and a power converter according to Embodiment 1 will be described with reference to the drawings. FIG. 1 is a circuit diagram of a protection circuit 1 according to this embodiment. A protection circuit 1 is a protection circuit for a semiconductor switching element 200 .

1-1. Semiconductor switching element 200
The semiconductor switching element 200 includes a high potential side terminal 200A, a low potential side terminal 200B, and a control terminal 200C. turn on and off the continuity between A high potential voltage such as the high potential side of the DC power supply is applied to the high potential side terminal 200A, and a low potential voltage such as the low potential side of the DC power supply is applied to the low potential side terminal 200B. The low potential side terminal 200B is also connected to the reference potential of the protection circuit 1 and the reference potential of the drive circuit 210 . One or both of the high potential side terminal 200A and the low potential side terminal 200B are connected to one or both of an electrical load and other semiconductor switching elements. For example, the semiconductor switching element 200 constitutes a power converter such as an inverter or a converter.

In this embodiment, an IGBT (Insulated Gate Bipolar Transistor) in which diodes are connected in anti-parallel is used as the semiconductor switching element 200 . The high potential side terminal 200A is the collector terminal 200A, the low potential side terminal 200B is the emitter terminal 200B, and the control terminal 200C is the gate terminal 200C. Various semiconductor switching elements such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) may be used as the semiconductor switching element 200 .

1-2. drive circuit 210
The drive circuit 210 generates a gate voltage Vge according to the input ON/OFF command signal Vin, and applies the gate voltage Vge to the gate terminal 200C. The gate voltage Vge becomes the voltage Vge of the control terminal. An on/off command signal Vin is input to the drive circuit 210 from the control device 220 or the like. The drive circuit 210 has a pre-drive circuit 210A and two semiconductor switching elements. An IC (Integrated Circuit) is used for the pre-drive circuit 210A.

The drive circuit 210 basically generates a high voltage gate voltage Vge when the on/off command signal Vin is an on signal (high voltage), and generates a high voltage gate voltage Vge when the on/off command signal Vin is an off signal (low voltage). , to generate a low voltage gate voltage Vge.

An output signal Vout1 of the protection circuit 1 (the output signal of the logic circuit 20A in this example) is input to the drive circuit 210 . When the output signal Vout1 of the protection circuit 1 (the output signal Vout1 of the first comparator 20) becomes a high voltage indicating the occurrence of overcurrent, the driving circuit 210 forcibly generates a high voltage gate voltage Vge. to stop. Note that the output signal Vout1 of the protection circuit 1 may be input to the control device 220 . Then, the control device 220 may forcibly switch the on/off command signal Vin to an off signal (low voltage) when the output signal Vout1 of the protection circuit 1 becomes high voltage.

1-3. Protection Circuit First, the ON/OFF behavior during normal current and the ON/OFF behavior during overcurrent, which are the premises for designing the protection circuit 1, will be described.

<ON/OFF behavior at normal current>
The on/off behavior during normal current will be described with reference to FIG. The determination behavior of the protection circuit 1 is also superimposed on FIG. Each voltage such as the gate voltage Vge and the collector voltage Vce is a potential based on the potential of the emitter terminal 200B, which is the reference potential.

At time t01, the ON/OFF command signal Vin changes from the low voltage to the high voltage, and the driving circuit 210 starts generating the high voltage gate voltage Vge. After that, the gate voltage Vge gradually increases, and at time t02, when the gate voltage Vge reaches the ON voltage Von, conduction between the collector and the emitter starts, the collector current Ic starts to increase, and the collector voltage Vce decreases. do.

At time t03, charging of the Miller capacitance between collector terminal 200A and gate terminal 200C begins. When the charging of the mirror capacitance on the collector terminal side starts, the rising speed of the gate voltage Vge slows down. The collector voltage Vce also decreases while the mirror capacitance on the collector terminal side is being charged. After the charging of the mirror capacitance on the collector terminal side is completed (after time t04), the gate voltage Vge increases to the circuit power supply voltage Vcc. From time t03 to time t04, the gate voltage Vge while the mirror capacitance between the collector terminal 200A and the gate terminal 200C is being charged is referred to as a mirror voltage Vmr.

On the other hand, at time t05, the ON/OFF command signal Vin changes from the high voltage to the low voltage, and the driving circuit 210 starts generating the low voltage gate voltage Vge. After that, the gate voltage Vge decreases. When the gate voltage Vge reaches the mirror voltage Vmr at time t06, the gate voltage Vge is maintained at the mirror voltage Vmr until the discharge of the mirror capacitance on the collector terminal side ends. At time t07, when the discharge of the Miller capacitance ends, the gate voltage Vge begins to drop from the Miller voltage Vmr. At time t08, when the gate voltage Vge falls below the on-voltage Von, the collector-emitter becomes non-conductive, and the collector current Ic drops to zero.

<On/off behavior during overcurrent>
Next, the on/off behavior during overcurrent will be described with reference to FIG. The determination behavior of the protection circuit 1 is also superimposed on FIG. A short circuit occurs before turning on, and an overcurrent flows when turning on. The principle of turning on and off is the same as in the case of normal current, but the waveform is deformed because the collector current Ic becomes excessive. At time t11, the ON/OFF command signal Vin changes from the low voltage to the high voltage, and the driving circuit 210 starts generating the high voltage gate voltage Vge. After that, the gate voltage Vge gradually increases, and when the gate voltage Vge reaches the ON voltage Von, conduction between the collector and the emitter starts, the collector current Ic starts to increase, and the collector voltage Vce starts to decrease.

In the case of overcurrent, there is no charging or discharging of the Miller capacitance, so there is no Miller time (a period during which the gate voltage Vge is constant) and the increase (charging) of the gate voltage Vge becomes faster. At this time, the amount of collector-emitter voltage drop due to the wiring inductance of the power supply circuit becomes large, and thereafter the collector voltage Vce rises.

On the other hand, at time t13, the output signal Vout1 of the first comparator 20 changes from the low voltage to the high voltage, and the drive circuit 210 starts generating the low voltage gate voltage Vge, and the gate voltage Vge is declining. After that, when the gate voltage Vge falls below the ON voltage Von, the collector-emitter becomes non-conductive, and the collector current Ic drops to zero.

<Basic configuration of protection circuit>
The protection circuit 1 includes a first reference voltage generation circuit 10, a first comparator 20, a second reference voltage generation circuit 30, a second comparator 40, a first comparator lock circuit 50, a first reference change circuit 60, and a judgment circuit. A result latch circuit 70 is provided.

The first reference voltage generation circuit 10 generates a first reference voltage Vref<b>1 and outputs the generated first reference voltage Vref<b>1 to the first comparator 20 . The first comparator 20 is connected to the collector terminal 200A. When the input collector voltage Vces (hereinafter referred to as input collector voltage Vces) exceeds the first reference voltage Vref1, the first comparator 20 outputs a first-state output signal Vout1 representing the occurrence of overcurrent. , when the input collector voltage Vces falls below the first reference voltage Vref1, it outputs the output signal Vout1 in the second state indicating that no overcurrent has occurred. In the present embodiment, the first comparator 20 outputs a high voltage output signal Vout1 as the first state output signal Vout1, and outputs a low voltage output signal Vout1 as the second state output signal Vout1. Note that the first state may be the low voltage and the second state may be the high voltage.

The second reference voltage generation circuit 30 generates a second reference voltage Vref2 and outputs the generated second reference voltage Vref2 to the second comparator 40 . The second comparator 40 outputs the output signal Vout2 in the third state when the input gate voltage Vges (hereinafter referred to as the input gate voltage Vges) exceeds the second reference voltage Vref2, and the input gate voltage Vges is When it falls below the second reference voltage Vref2, it outputs the output signal Vout2 in the fourth state.

The first comparator lock circuit 50 reduces the input collector voltage Vces input to the first comparator 20 to less than the first reference voltage Vref1 when the output signal Vout2 of the second comparator 40 is in the fourth state. Let On the other hand, when the output signal Vout2 of the second comparator 40 is in the third state, the first comparator lock circuit 50 prevents the input collector voltage Vces from dropping below the first reference voltage Vref1 and prevents the collector voltage Vce from falling below the first reference voltage Vref1. , to the first comparator 20 as the input collector voltage Vces.

As shown in FIG. 2, the collector voltage Vce is higher than the first reference voltage Vref1 until generation of the high voltage gate voltage Vge is started (until time t01). If it is input to the first comparator 20 as the collector voltage Vces, it is erroneously determined that an overcurrent has occurred. However, according to the above configuration, the first comparator lock circuit 50 controls the input collector voltage Vces until the generation of the high voltage gate voltage Vge starts and the input gate voltage Vges exceeds the second reference voltage Vref2. It is forcibly lowered below the first reference voltage Vref1. Therefore, it is possible to prevent the input collector voltage Vces from becoming lower than the first reference voltage Vref1 and erroneously determining that an overcurrent has occurred until generation of the high voltage gate voltage Vge is started.

In this embodiment, the second reference voltage Vref2 is set to a voltage corresponding to a voltage higher than the mirror voltage Vmr and lower than the circuit power supply voltage Vcc.

As described with reference to FIG. 2, after the start of generation of the high voltage gate voltage Vge, while the mirror capacitance between the collector terminal and the gate terminal is being charged (time t03 to time t04), the collector voltage Since Vce has decreased, the collector voltage Vce exceeds the first reference voltage Vref1, and there is a risk of erroneous determination that an overcurrent has occurred. When the gate voltage Vge becomes higher than the mirror voltage Vmr, the charging of the mirror capacitance is completed, and the decrease of the collector voltage Vce is almost finished. Therefore, by setting the second reference voltage Vref2 as described above, after the charging of the mirror capacitance is completed and the forcible reduction of the input collector voltage Vces is completed, the input collector voltage Vces is controlled by the first comparator 20. Based on this, it is possible to accurately determine the occurrence of overcurrent. As described with reference to FIG. 3, when an overcurrent occurs, the collector voltage Vce becomes higher than the first reference voltage Vref1 even after the drop in the collector voltage Vce is almost finished. can be determined to have occurred.

<Decrease in first reference voltage Vref1>
If a short circuit occurs during the turn-on period and an overcurrent flows, the collector current Ic increases more rapidly than if a short circuit occurs before turn-on because the conductivity of the semiconductor is fully modulated. On the other hand, the collector voltage Vce increases as the collector current Ic increases, but with a delay. Therefore, after the short circuit occurs, a delay occurs until the input collector voltage Vces exceeds the first reference voltage Vref1, and the occurrence of overcurrent cannot be detected early. Therefore, there is a possibility that the device will fail due to the rapidly increasing collector current Ic.

Therefore, the first reference changing circuit 60 reduces the first reference voltage Vref1 when the output signal Vout2 of the second comparator 40 is in the third state.

According to this configuration, after the generation of the high voltage gate voltage Vge is started, the input gate voltage Vges exceeds the second reference voltage Vref2, and the output signal Vout2 of the second comparator 40 becomes the third state, The first reference voltage Vref1 is lowered. Therefore, the period until the input collector voltage Vces exceeds the first reference voltage Vref1 after a short circuit occurs during the turn-on period can be shortened, and the occurrence of overcurrent can be detected early. Therefore, even if a short circuit occurs during the turn-on period, the rapidly increasing collector current Ic can be stopped early to suppress failure of the device.

On the other hand, when the input gate voltage Vges is lower than the second reference voltage Vref2 and the output signal Vout2 of the second comparator 40 is in the fourth state, the first reference changing circuit 60 does not lower the first reference voltage Vref1. Immediately after the start of turn-on in a state where no short circuit occurs, the input collector voltage Vces exceeds the first reference voltage Vref1 in a state where the input collector voltage Vces has not completely decreased, preventing an erroneous determination that an overcurrent has occurred. can. In addition, erroneous determination due to noise components generated at turn-on can be suppressed.

That is, by providing the first reference changing circuit 60, the first reference voltage Vref1 for suppressing an erroneous determination when a short circuit occurs before turn-on and early overcurrent detection when a short circuit occurs during the turn-on period. Therefore, the first reference voltage Vref1 can be set appropriately.

<Circuit Configuration Related to First Reference Changing Circuit 60>
In the present embodiment, the first reference voltage generation circuit 10 divides the circuit power supply voltage Vcc by dividing resistors to generate the first reference voltage Vref1. In this example, a dividing resistor is composed of a high potential side resistor 10A and a low potential side resistor 10B connected in series between the circuit power supply voltage Vcc and the reference potential. The potential at the intermediate point of the dividing resistors (in this example, the connection point between the high potential side resistor 10A and the low potential side resistor 10B) is input to the first comparator 20 as the first reference voltage Vref1. A capacitor 10C is connected in parallel with the low potential side resistor 10B. Therefore, the first reference voltage Vref1 drops due to the response delay of the CR time constant. That is, the first reference changing circuit 60 gradually lowers the first reference voltage Vref1 after the output signal Vout2 of the second comparator 40 becomes the third state.

A circuit power supply (not shown) that generates a circuit power supply voltage Vcc is provided, and the circuit power supply generates the circuit power supply voltage Vcc that is higher than the reference potential by a predetermined voltage.

The second comparator 40 outputs a high voltage output signal Vout2 as the third state output signal Vout2, and outputs a low voltage output signal Vout2 as the fourth state output signal Vout2. The first reference changing circuit 60 includes an inverting circuit 60A that inverts the high/low level of the output signal Vout2 of the second comparator 40, and an intermediate point between the output terminal of the inverting circuit 60A and the dividing resistor (in this example, a high potential side resistor). 10A and the connection point of the low potential side resistor 10B).

According to this configuration, the generation of the high voltage gate voltage Vge is started, the input gate voltage Vges exceeds the second reference voltage Vref2, and the second comparator 40 outputs the high voltage output signal Vout2 in the third state. When output, high/low is inverted by the inverting circuit 60A, and the output voltage of the inverting circuit 60A becomes a low voltage (eg, reference potential). The reference changing resistor 60B is connected in parallel to the dividing resistor (in this example, the low potential side resistor 10B) between the reference potential and the connection point, thereby lowering the first reference voltage Vref1.

On the other hand, when the input gate voltage Vges falls below the second reference voltage Vref2 and the second comparator 40 outputs the low voltage output signal Vout2 in the fourth state, the inverter circuit 60A inverts the high/low state. The output voltage of 60A becomes a high voltage (eg, circuit power supply voltage Vcc). The reference changing resistor 60B is connected in parallel to the dividing resistor (the high potential side resistor 10A in this example) between the circuit power supply voltage Vcc and the connection point, thereby increasing the first reference voltage Vref1.

The resistance values of the high potential side resistor 10A, the low potential side resistor 10B, and the reference changing resistor 60B are set so that the first reference voltage Vref1 before and after the increase/decrease becomes an appropriate voltage.

<Circuit Configuration of First Comparator Lock Circuit 50>
The first comparator lock circuit 50 is connected between the input terminal of the input collector voltage Vces in the first comparator 20 and the output terminal of the second comparator 40, and the anode faces the first comparator 20 side. It has a reverse blocking diode 50A which is a diode.

According to this configuration, when the input gate voltage Vges is lower than the second reference voltage Vref2 and the second comparator 40 outputs the low voltage output signal Vout2 in the fourth state, the reverse operation blocking diode 50A , the input terminal side of the first comparator 20 and the output terminal side of the second comparator 40 are electrically connected, and the potential of the input terminal of the first comparator 20 (input collector voltage Vces) drops to near the reference potential. do. On the other hand, when the input gate voltage Vges exceeds the second reference voltage Vref2 and the second comparator 40 outputs the high voltage output signal Vout2 in the fourth state, the input terminal side of the first comparator 20 and the output terminal side of the second comparator 40 become non-conductive, and the potential of the input terminal of the first comparator 20 (input collector voltage Vces) becomes a voltage corresponding to the collector voltage Vce. Therefore, the generation of the high voltage gate voltage Vge is started, and the input collector voltage Vces is forcibly lowered to the reference potential until the input gate voltage Vges exceeds the second reference voltage Vref2. Current determination can be put in a non-operating state (locked state).

In this embodiment, a limiting resistor 50B is connected in series with a reverse blocking diode 50A (on the anode side in this example). Limiting resistor 50B limits the rush current when capacitor 106 is discharged.

The first comparator lock circuit 50 is connected between the input terminal of the input collector voltage Vces in the first comparator 20 and the input terminal of the drive circuit 210 to which the ON/OFF command signal Vin is input, and the anode is connected to the first comparator. It has a second reverse blocking diode 50C facing the 20 side. The anode of the second reverse action blocking diode 50C is connected to the connection point between the limiting resistor 50B and the reverse action blocking diode 50A. When the on/off command signal Vin is at a low voltage (off state), the input terminal side of the first comparator 20 and the input terminal of the drive circuit 210 are electrically connected, and the potential of the input terminal of the first comparator 20 (input collector voltage Vces) drops to near the reference potential. On the other hand, when the on/off command signal Vin is at a high voltage (on state), the input terminal side of the first comparator 20 and the input terminal of the drive circuit 210 are disconnected.

<Connection of Input Terminal of First Comparator 20>
The input terminal of the first comparator 20 is connected to a high potential side main connection line 201 (hereinafter referred to as a high potential side main connection line) to which the collector terminal 200A is connected via a diode 103 whose anode faces the first comparator 20 side. 201). A connection line 101 connecting between the input terminal of the first comparator 20 and the high potential side main connection line 201 is called a first input connection line 101 . A resistor 104 is provided between the input terminal of the first comparator 20 and the diode 103 on the first input connection line 101 . A voltage limiter 105 (two diodes) is connected between the diode 103 and the resistor 104 in the first input connection line 101 to limit the potential of the first input connection line 101 between the circuit power supply voltage Vcc and the reference potential. It is One end of the limiting resistor 50B and one end of the constant current source 107 are connected to the first comparator 20 side of the resistor 104 in the first input connection line 101 . A circuit power supply voltage Vcc is supplied to the constant current source 107 , and the constant current source 107 supplies a constant current to the first input connection line 101 . One end of a capacitor 106 is connected between the resistor 104 and the first comparator 20 on the first input connection line 101 . The other end of capacitor 106 is connected to a reference potential.

<Circuit Configuration of First Comparator 20>
The first comparator 20 outputs the high voltage output signal Vout1 as the first state output signal Vout1, and outputs the low voltage output signal Vout1 as the second state output signal Vout1. The first comparator 20 is a comparator. The first input connection line 101 is connected to the inverting input terminal (-) of the first comparator 20, and the input collector voltage Vces is input. The first reference voltage generating circuit 10 is connected to the non-inverting input terminal (+) of the first comparator 20, and the first reference voltage Vref1 is input. The output terminal of the first comparator 20 is connected to the logic circuit 20A. The logic circuit 20A outputs a high voltage when the output signal Vout1 of the first comparator 20 is higher than the threshold, and outputs a low voltage when the output signal Vout1 of the first comparator 20 is lower than the threshold. . The output terminal of logic circuit 20A is connected to drive circuit 210 .

<Circuit Configuration of Second Reference Voltage Generation Circuit 30>
In the present embodiment, the second reference voltage generation circuit 30 divides the circuit power supply voltage Vcc by dividing resistors to generate the second reference voltage Vref2. In this example, a dividing resistor is composed of a high potential side resistor 30A and a low potential side resistor 30B connected in series between the circuit power supply voltage Vcc and the reference potential. The potential at the intermediate point of the dividing resistors (in this example, the connection point between the high potential side resistor 30A and the low potential side resistor 30B) is input to the second comparator 40 as the second reference voltage Vref2. A capacitor 30C is connected in parallel with the low potential side resistor 30B.

<Circuit Configuration of Second Comparator 40>
A resistor 111 is connected to a connection line 110 (referred to as a second input connection line 110) between the input terminal of the second comparator 40 and a gate terminal main connection line 202 (hereinafter referred to as a gate main connection line 202). is provided. The gate main connection line 202 connects between the output terminal of the drive circuit 210 and the gate terminal 200C. One end of a resistor 112 and one end of a capacitor 113 are connected to the second comparator 40 side of the resistor 111 in the second input connection line 110 . The other end of the resistor 112 and the other end of the capacitor 113 are connected to the reference potential. Therefore, in this embodiment, the input gate voltage Vges is a voltage obtained by dividing the gate voltage Vge by the resistors 111 and 112 . For simplification of explanation, it is assumed that the input gate voltage Vges is not divided, and each time chart shows the input gate voltage Vges converted to the gate voltage Vge.

The second comparator 40 outputs a high voltage output signal Vout2 as the third state output signal Vout2, and outputs a low voltage output signal Vout2 as the fourth state output signal Vout2. The second comparator 40 is a comparator. The second input connection line 110 is connected to the inverting input terminal (-) of the second comparator 40, and the input gate voltage Vges is input. The second reference voltage generating circuit 30 is connected to the non-inverting input terminal (+) of the second comparator 40, and the second reference voltage Vref2 is input. The output terminal of the second comparator 40 is connected to the first reference changing circuit 60 (inverting circuit 60A).

<Determination result latch circuit 70>
After the generation of the high voltage gate voltage Vge is started, if an overcurrent flows due to a short circuit, the wiring inductance may cause the gate voltage Vge to oscillate. Oscillations in the gate voltage Vge may cause the input gate voltage Vges to fall below the second reference voltage Vref2 after the input gate voltage Vges exceeds the second reference voltage Vref2. When the output signal Vout2 of the second comparator 40 fluctuates due to the oscillation of the gate voltage Vge due to the occurrence of overcurrent, the operations of the first comparator lock circuit 50 and the first reference change circuit 60 fluctuate, and the overcurrent judgment accuracy decreases. decreases.

Therefore, the determination result latch circuit 70 increases the input gate voltage Vges input to the second comparator 40 when the output signal of the second comparator is in the third state (high voltage in this example), The determination result of the second comparator 40 is given hysteresis.

When the generation of the high voltage gate voltage Vge is started, the input gate voltage Vges exceeds the second reference voltage Vref2, and the second comparator 40 outputs the high voltage output signal Vout2 in the third state, the determination result is latched. Circuit 70 raises the input gate voltage Vges. Therefore, even if the gate voltage Vge oscillates due to the occurrence of overcurrent, the input gate voltage Vges is higher than the gate voltage Vge. Hysteresis can be given to the determination result of the comparator 40 . Therefore, even if the gate voltage Vge oscillates due to overcurrent, the output signal Vout2 of the second comparator 40 is suppressed from fluctuating, and the operations of the first comparator lock circuit 50 and the first reference change circuit 60 are suppressed. Fluctuation can be suppressed, and a decrease in overcurrent determination accuracy can be suppressed.

In this embodiment, the determination result latch circuit 70 is a resistor connected between the output terminal of the second comparator 40 and the input terminal (inverting input terminal) of the input gate voltage Vges of the second comparator 40. It has a feedback resistor 70A.

According to this configuration, when the second comparator 40 outputs the high voltage output signal Vout2 in the third state, the voltage of the input terminal of the second comparator 40 is pulled up via the feedback resistor 70A. The resistance value of each resistor such as the feedback resistor 70A is set so that appropriate determination can be made. Strictly speaking, since the input gate voltage Vges before being raised is voltage-divided, it is lower than the circuit power supply voltage Vcc and can be raised up to the circuit power supply voltage Vcc.

Incidentally, when the rise width of the input gate voltage Vges by the determination result latch circuit 70 is increased, the role of latching the output signal Vout2 of the second comparator 40 to the third state (high voltage) becomes higher. Therefore, when the gate voltage Vge drops during turn-off, the timing at which the output signal Vout2 of the second comparator 40 changes to the fourth state (low voltage) is delayed. The timing at which the overcurrent determination of 20 is set to a non-operating state (locked state) is delayed. Therefore, in this case, when the ON/OFF command signal Vin becomes a low voltage (OFF state), the second reverse blocking diode 50C becomes conductive, and the overcurrent judgment of the first comparator 20 is disabled (locked). state).

<Behavior during short circuit before turn-on>
As shown in FIG. 3, at time t12, the input gate voltage Vges exceeds the second reference voltage Vref2, and the output signal Vout2 of the second comparator 40 becomes the third state (high voltage). As a result, the reduction of the input collector voltage Vces caused by the first comparator lock circuit 50 is released, and the input collector voltage Vces increases toward the collector voltage Vce, which is higher than that during normal current. At this time, a response delay occurs due to the capacitor. Further, when the output signal Vout2 of the second comparator 40 becomes the third state (high voltage), the first reference voltage Vref1 is lowered by the first reference changing circuit 60. FIG. At this time, a response delay occurs due to the capacitor.

After time t12, overshoot and undershoot occur in the gate voltage Vge due to the influence of the overcurrent. Therefore, the gate voltage Vge may fall below the second reference voltage Vref2, resulting in an erroneous determination. However, in the present embodiment, when the output signal Vout2 of the second comparator 40 becomes the third state (high voltage), the input gate voltage Vges input to the second comparator 40 is raised by the determination result latch circuit 70. It is Therefore, even if the gate voltage Vge oscillates, the input gate voltage Vges can be prevented from falling below the second reference voltage Vref2, and erroneous determination can be prevented.

At time t13, the input collector voltage Vces, which has increased due to the overcurrent, exceeds the decreased first reference voltage Vref1, and the output signal Vout1 of the first comparator 20 becomes the first state (high voltage), causing overcurrent. is detected. Then, the driving circuit 210 forcibly stops generating the gate voltage Vge. After that, the gate voltage Vge decreases, and at time t14, the input gate voltage Vges falls below the second reference voltage Vref2, and the output signal Vout2 of the second comparator 40 is in the fourth state (low voltage).

<Behavior at short circuit during turn-on period>
FIG. 4 shows the behavior when a short circuit occurs in another circuit during the turn-on period. At time t31, the ON/OFF command signal Vin is changed from the OFF state to the ON state. After that, when the gate voltage Vge exceeds the on-voltage Von, the collector current Ic increases normally. After that, while the gate voltage Vge is maintained at the mirror voltage Vmr, the collector voltage Vce gradually decreases to near the reference potential.

After that, at time 32, the input gate voltage Vges exceeds the second reference voltage Vref2, and the output signal Vout2 of the second comparator 40 becomes the third state (high voltage). As a result, the decrease in the input collector voltage Vces caused by the first comparator lock circuit 50 is released, but since the collector voltage Vce has decreased to near the reference voltage, the input collector voltage Vces remains near the reference voltage. It is At this time, even if the collector voltage Vce has not completely decreased to the vicinity of the reference voltage, the first reference voltage Vref1 is high, so an erroneous determination is not made. Moreover, even if a noise component occurs in the input collector voltage Vces at turn-on, erroneous determination can be suppressed.

Further, when the output signal Vout2 of the second comparator 40 becomes the third state (high voltage), the first reference voltage Vref1 is lowered by the first reference changing circuit 60. FIG. At this time, a response delay occurs due to the capacitor. Further, when the output signal Vout2 of the second comparator 40 becomes the third state (high voltage), the input gate voltage Vges input to the second comparator 40 is raised by the determination result latch circuit 70 .

At time t33, another circuit is short-circuited. Due to the fully modulated conductivity of the semiconductor, the collector current Ic increases more rapidly than if there was a short circuit prior to turn-on. When the collector current Ic increases, the collector voltage Vce increases due to the effect of the voltage drop. However, the increase in collector voltage Vce lags behind the increase in collector current Ic. Also, the increase in the input collector voltage Vces is delayed due to the response delay caused by the capacitor. However, the first reference voltage Vref1 has already been lowered by the first reference changing circuit 60 . Therefore, at time t34, the input collector voltage Vces quickly exceeds the first reference voltage Vref1, the output signal Vout1 of the first comparator 20 becomes the first state (high voltage), and the occurrence of overcurrent is detected early. be.

On the other hand, after time t33, the gate voltage Vge fluctuates due to the influence of the overcurrent. It does not fall below Vref2, and erroneous determination can be prevented.

At time t34, the driving circuit 210 forcibly stops generating the gate voltage Vge. After that, the gate voltage Vge decreases, and at time t35, the input gate voltage Vges falls below the second reference voltage Vref2, and the output signal Vout2 of the second comparator 40 is in the fourth state (low voltage).

2. Embodiment 2
A protection circuit 1 according to a second embodiment will be described with reference to the drawings. Descriptions of the same components as in the first embodiment are omitted. The basic configuration of the protection circuit 1 according to the present embodiment is similar to that of the first embodiment, but differs from the first embodiment in that an active clamp circuit 80 is provided. FIG. 5 shows a schematic configuration diagram of the active clamp circuit 80. As shown in FIG. The same parts as those in the first embodiment are omitted from the illustration.

If the switch is turned off while an overcurrent is flowing, a surge voltage may occur in the collector voltage Vce due to the inductance of the circuit wiring, and the semiconductor switching element 200 may fail.

Therefore, the active clamp circuit 80 increases the gate voltage Vge when the collector voltage Vce rises sharply after the gate voltage Vge starts to decrease.

According to this configuration, after the turn-off is started in a state in which an overcurrent is flowing, when a surge voltage is generated due to a surge of the collector voltage Vce, the gate voltage Vge is raised at the timing of switching, thereby reducing the collector current Ic. current, which clamps the surge voltage peaks. Therefore, it is possible to suppress the failure of the element due to the surge voltage.

The active clamp circuit 80 has a semiconductor switching element 81 for clamping that increases the gate voltage Vge when turned on. As a semiconductor switching element 81 for clamping, an NPN transistor 81A and a PNP transistor 81B are connected in series between the circuit power supply voltage Vcc and the reference potential. A connection point between the two transistors 81A and 81B is connected to a gate terminal 200C of the semiconductor switching element 200. FIG.

The active clamp circuit 80 is connected in series between the collector terminal 200A and the control terminal 81C (base terminal 81C) of the semiconductor switching element 81 for clamping. It has a turn-on blocking diode 83, which is a side-facing diode, and a base resistor 84, which is a resistor. The feedback capacitor 82 has two capacitors 82A and 82B connected in series. Leak suppression resistors 82C and 82D are connected in parallel to the capacitors 82A and 82B, respectively.

As shown in the time chart of FIG. 6, after starting turn-off at time t41, the gate voltage Vge decreases, and when the collector voltage Vce rises sharply (time t42), the jump of the collector voltage Vce becomes the feedback voltage. Feedback to the base terminal 81C of the semiconductor switching element 81 for clamping through the capacitor 82, the turn-on operation blocking diode 83, and the base resistor 84 causes a base current to flow between the base terminal and the emitter terminal. The gate terminal 200C of the switching element 200 is turned on, the collector current Ic flows, and the collector voltage Vce is clamped (from time t42 to time t43). As a result, the generation of surge voltage can be suppressed more than the collector voltage Vce indicated by the dotted line when clamping is not performed. After time t43, the collector voltage Vce is released from clamping, and the gate voltage Vge and collector current Ic decrease.

The active clamp circuit 80 also has a discharge resistor 85 connected between the connection point between the feedback capacitor 82 and the turn-on blocking diode 83 and the reference potential. A discharge resistor 85 allows the feedback capacitor 82 to be discharged. The connection destination of the discharge resistor 85 may be set to the high potential side bus potential, and only the increment of the surge voltage higher than the bus voltage may be clamped.

A soft cut-off resistor, which is several times larger than the gate-off side resistor used for off-surge reduction, can be eliminated from the circuit.

<Example of diversion>
In each embodiment, a switching element made of a wide bandgap semiconductor may be used as semiconductor switching element 200 . A switching element made of a wide bandgap semiconductor has a high breakdown voltage, good heat dissipation, and is capable of high-speed switching. Specifically, they are semiconductor switching elements such as IGBTs using SiC (silicon carbide, silicon carbide)-based materials, GaN (gallium nitride)-based materials, and diamond-based materials. SiC-IGBTs are capable of high-speed switching compared to conventional switching elements made of Si (silicon) semiconductors. Therefore, the protection circuit 1 of the present application is suitable when a switching element made of a wide bandgap semiconductor is used.

Further, in each of the above embodiments, the case where the collector voltage Vce is input to the first comparator 20 as the input collector voltage Vces has been described as an example. However, a voltage obtained by dividing the collector voltage Vce by dividing resistors may be input to the first comparator 20 as the input collector voltage Vces. In each of the embodiments described above, the case where the voltage obtained by dividing the gate voltage Vge by the dividing resistor is input to the first comparator 20 as the input gate voltage Vges has been described as an example. However, the gate voltage Vge may be input to the first comparator 20 as the input gate voltage Vges without being divided.

While this application describes various exemplary embodiments and examples, various features, aspects, and functions described in one or more embodiments may not apply to particular embodiments. can be applied to the embodiments singly or in various combinations. Accordingly, numerous variations not illustrated are envisioned within the scope of the technology disclosed herein. For example, modification, addition or omission of at least one component, extraction of at least one component, and combination with components of other embodiments shall be included.

1 protection circuit 10 first reference voltage generation circuit 20 first comparator 30 second reference voltage generation circuit 40 second comparator 50 first comparator lock circuit 50A reverse blocking diode 50B limiting resistor 60 first reference change circuit, 60A inverting circuit, 60B reference change resistor, 70 determination result latch circuit, 80 active clamp circuit, 81 semiconductor switching element for clamping, 82 feedback capacitor, 83 turn-on operation blocking diode, 84 base resistor, 85 discharge resistor, 200 semiconductor switching element, 200A collector terminal (high potential side terminal), 200B emitter terminal (low potential side terminal), 200C gate terminal (control terminal), Vcc circuit power supply voltage, Vce collector voltage (high potential side terminal voltage), Vces Input collector voltage (input voltage of high potential side terminal), Vge Gate voltage (voltage of control terminal), Vges Input gate voltage (input voltage of control terminal), Vmr Mirror voltage, Vout1 of first comparator Output signal, Vout2 Second comparator output signal, Vref1 First reference voltage, Vref2 Second reference voltage

Claims (10)

A semiconductor switching device comprising a high potential side terminal, a low potential side terminal, and a control terminal, and turning on and off conduction between the high potential side terminal and the low potential side terminal according to an increase or decrease in voltage applied to the control terminal. A protection circuit for detecting the occurrence of overcurrent between the high potential side terminal and the low potential side terminal in the element,
a first reference voltage generation circuit that generates a first reference voltage;
When the input voltage of the high potential side terminal exceeds the first reference voltage, outputting an output signal in the first state indicating the occurrence of overcurrent, and outputting the input voltage of the high potential side terminal when the input voltage of the high potential side terminal exceeds the first reference voltage. a first comparator that, when falling below one reference voltage, outputs an output signal in a second state indicating that no overcurrent has occurred;
a second reference voltage generation circuit that generates a second reference voltage;
outputting an output signal in a third state when the input voltage of the control terminal exceeds the second reference voltage; and outputting a fourth state output signal when the input voltage of the control terminal is lower than the second reference voltage. a second comparator that outputs a state output signal;
A first comparator lock circuit for lowering the voltage of the high potential side terminal input to the first comparator below the first reference voltage when the output signal of the second comparator is in the fourth state. When,
a first reference changing circuit that reduces the first reference voltage when the output signal of the second comparator is in the third state;
protection circuit with The first reference voltage generation circuit divides a circuit power supply voltage with a dividing resistor to generate the first reference voltage,
the second comparator outputs a high voltage output signal as the output signal in the third state and outputs a low voltage output signal as the fourth state output signal;
The first reference changing circuit is an inverting circuit that inverts high/low of the output signal of the second comparator, and a resistor connected between the output terminal of the inverting circuit and an intermediate point of the dividing resistor. 2. The protection circuit of claim 1, comprising a reference changing resistor. the second comparator outputs a high voltage output signal as the output signal in the third state and outputs a low voltage output signal as the fourth state output signal;
The first comparator lock circuit is connected between the voltage input terminal of the high potential side terminal of the first comparator and the output terminal of the second comparator, and the anode is connected to the first comparator side. 3. A protection circuit as claimed in claim 1 or 2, comprising a reverse blocking diode which is a connected diode. The second reference voltage is set to a voltage corresponding to a voltage greater than the mirror voltage and less than the circuit power supply voltage, and the mirror voltage increases the voltage of the control terminal when no overcurrent occurs. 4. The protection circuit according to any one of claims 1 to 3, wherein the voltage of the control terminal is the voltage of the control terminal while the Miller capacitance between the high potential side terminal and the control terminal is being charged. When the output signal of the second comparator is in the third state, the voltage of the control terminal input to the second comparator is increased to provide hysteresis to the determination result of the second comparator. 5. A protection circuit as claimed in any one of claims 1 to 4, comprising a result latch circuit. the second comparator outputs a high voltage output signal as the output signal in the third state and outputs a low voltage output signal as the fourth state output signal;
6. The determination result latch circuit has a feedback resistor connected between the output terminal of the second comparator and the input terminal for the voltage of the control terminal of the second comparator. Protection circuit described in . 7. An active clamp circuit for increasing the voltage of the control terminal when the voltage of the high potential side terminal rises sharply after the voltage of the control terminal starts to decrease. Protection circuit described in . The active clamp circuit is
a clamping semiconductor switching element that increases the voltage of the control terminal when turned on;
a feedback capacitor connected in series between the high-potential side terminal and the control terminal of the semiconductor switching element for clamping, and a turn-on operation blocking block whose anode is a diode connected to the high-potential side terminal side; a diode, a base resistor that is a resistor, and a discharge resistor that is a resistor connected between a connection point between the feedback capacitor and the turn-on operation blocking diode and a reference potential;
8. The protection circuit of claim 7, comprising: 9. The protection circuit according to claim 1, wherein the semiconductor switching element is a switching element made of a wide bandgap semiconductor. The protection circuit according to any one of claims 1 to 9;
the semiconductor switching element;
A power converter with

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