JP2009225506A - Power converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power converter which can be protected from a short circuit and can suppress an overvoltage before a switching element is failed, and is high in responsiveness. <P>SOLUTION: A short-circuit determination means 5 determines the short circuit of the switching element 1 by using a second comparison means 7b when a voltage corresponding to a gate current Ig detected by a gate current detection means 4 becomes not higher than a negative reference voltage of a second reference voltage generation means 6a within a prescribed time after the voltage corresponding to the gate current Ig detected by the gate current detection means 4 becomes not lower than a positive reference voltage of a first reference voltage generation means 6a by a first comparison means 7a. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power converter using a power switching element.

  Power converters using power switching elements are steadily expanding their application range as the capacity and speed of switching elements increase. Among such power switching elements, in particular, IGBTs and MOSFETs, which are MOS gate type switching elements, have recently been expanded in application fields.

  IGBTs and MOSFETs are non-latching switching elements that do not self-continue in an on / off state, and have a great advantage in that high controllability by gate driving is possible as compared with latching switching elements such as thyristors. Even when a short circuit occurs, the short circuit current can be reduced by reducing the gate voltage. Therefore, a power converter using a short circuit protection method by reducing the gate voltage of the IGBT has been put into practical use.

  Protecting the switching element in the event of a short-circuit accident, detecting the collector voltage when the switching element is on, and detecting that the collector voltage is higher than the reference value indicates an overcurrent or short-circuit condition (For example, refer to Patent Document 1).

In addition, there is one that detects a short-circuit fault by comparing an on-gate current flowing from the gate drive circuit of the semiconductor element into the gate or an off-gate current flowing from the gate of the semiconductor element into the gate drive circuit with a current in a healthy state (for example, Patent Document 2).
JP 2001-197724 A JP 2007-202238 A

  However, in Patent Document 1, the short circuit is detected and shut off by detecting the collector voltage of the switching element, but the time until the short circuit is detected is long, and the switching element may be destroyed. .

  Patent Document 2 detects that the switching element is broken and cannot operate in a short circuit state (failure) so that the switching element can be short-circuited in a normal operation state. It was n’t.

  Normally, when the switching element is turned on, the voltage between the main electrodes of the switching element becomes a very low voltage determined by the switching element, but when the switching element is short-circuited, a voltage determined by the DC voltage, the inductance of the main circuit and the short-circuit current is generated. To do. Although the short-circuit current is determined by the characteristics of the switching element, it is a very large current several times to a dozen times the rated current. When a large current flows, a large loss occurs and the switching element is destroyed. Therefore, it is necessary to detect a short circuit at an early stage and perform a protection operation.

  However, the higher the withstand voltage switching element during the turn-on transition, the longer it takes for the collector voltage to decrease. Therefore, in the case of detecting the collector voltage and detecting a short circuit, it is necessary to mask for a certain period until the switching element is turned on. is there. As a result, it takes a relatively long time to detect a short circuit or an overcurrent, and the switching element may be destroyed. Furthermore, in order to cut off an excessive current, a surge voltage may be generated and the switching element may be destroyed.

  During normal operation, a voltage of about +15 V is applied to the gate terminal of the switching element via a gate resistor in order to turn on the switching element. Then, a gate current limited by the gate resistance flows to the gate terminal, and the switching element is turned on. In order to turn it off, a voltage of about −15 V is applied to the gate terminal of the switching element via a gate resistor. Then, the gate charge of the switching element flows out from the gate terminal, and the switching element is turned off. At this time, the gate current is not detected and is not controlled.

  Therefore, the gate current at the on / off time is determined by the gate resistance, and an inrush current at the on time and an overvoltage at the off time may occur, which may destroy the switching element. The response speed of the switching element is also determined by the gate resistance. Decreasing the gate resistance also affects overvoltage and loss, so it is difficult to increase the response speed using a gate resistance with a small resistance value.

  An object of the present invention is to provide a power converter with high response performance capable of short-circuit protection and overvoltage suppression before a switching element fails.

  The power converter according to the present invention includes a gate current detecting means for detecting the gate current of the switching element, a first reference voltage generating means for generating a positive reference voltage, and a second reference voltage for generating a negative reference voltage. Reference voltage generation means, first comparison means for comparing a voltage corresponding to the gate current detected by the gate current detection means and a positive reference voltage of the first reference voltage generation means, and the gate current A second comparing means for comparing a voltage corresponding to the gate current detected by the detecting means and a negative reference voltage of the second reference voltage generating means; and the gate current detecting means by the first comparing means. The gate current detected by the gate current detection means by the second comparison means within a predetermined time after the voltage corresponding to the detected gate current becomes equal to or higher than the positive reference voltage of the first reference voltage generation means. When voltage corresponding to becomes less negative reference voltage of said second reference voltage generating means is characterized by comprising a short-circuit and determining short circuit determining means of the switching element.

  ADVANTAGE OF THE INVENTION According to this invention, before a switching element reaches failure, a short circuit protection and overvoltage suppression are possible, and the power converter with high response performance can be provided.

(First embodiment)
FIG. 1 is a configuration diagram of a power converter according to the first embodiment of the present invention. A flywheel diode 2 is connected in parallel to the switching element 1, and the switching element 1 is driven by a gate circuit 3. Thereby, the device current Ic of the switching device 1 is controlled. The gate current Ig applied from the gate circuit 3 to the gate of the switching element 1 is detected by the gate current detection means 4 and input to the first comparison means 7a and the second comparison means 7b.

  The first comparing means 7a compares the voltage corresponding to the gate current Ig detected by the gate current detecting means 4 with the positive reference voltage of the first reference voltage generating means 6a. The second comparison means 7b compares the voltage corresponding to the gate current Ig detected by the gate current detection means 4 with the negative reference voltage of the second reference voltage generation means 6b.

  The short-circuit determining means 5 includes the second short circuit within a predetermined time after the gate current detected by the gate current detecting means 4 by the first comparing means 7a becomes equal to or higher than the positive reference voltage of the first reference voltage generating means 6a. When the gate current detected by the gate current detection means 4 by the comparison means 7b becomes equal to or lower than the negative reference voltage of the second reference voltage generation means 6b, it is determined that the switching element 2 is short-circuited.

  Next, the operation will be described. FIG. 2 is a waveform diagram of the gate current Ig and the device current Ic during normal operation of the power converter according to the embodiment of the present invention. The power converter drives the switching element 1 by the gate circuit 3 to turn on / off the current. As shown in FIG. 2, when the gate current Ig flows in the positive direction at time t1, the switching element 1 is turned on and the element current Ic flows with a steep slope. The steep current at this time is such that the flywheel diode (FWD) 2 of the arm paired with the switching element 1 is in a reverse recovery state, and the DC circuit is short-circuited with the FWD2 of the arm paired with the switching element 1. Because there is.

  On the other hand, FIG. 3 is a waveform diagram of the gate current Ig and the device current Ic when the power converter is short-circuited in the embodiment of the present invention.

  When the switching element 1 short-circuits the DC voltage, if the gate current Ig flows in the positive direction at the time t1, a current many times the rated current flows to the switching element. Here, there is a deep relationship between the element current Ic of the switching element 1 and the gate voltage of the switching element 1, and generally a larger element current Ic can flow as the gate voltage increases.

  Conversely, when a large current such as a short-circuit current flows through the switching element 1, the gate voltage rises. On the other hand, the voltage of the gate circuit 3 is about 15 V when the switching element 1 is on. For this reason, when an excessive current flows when the switching element 1 is short-circuited, the gate voltage of the switching element 1 becomes higher than the voltage of the gate circuit 3, and the current flows from the switching element 1 to the gate circuit 3.

  As a result, as shown in FIG. 3, when a short circuit occurs, a gate current for turning on the switching element 1 flows at time t <b> 1, and then flows at a gate current time t <b> 2 in the opposite direction to the current that is turned on because of the short circuit. Become. That is, by determining whether the gate current Ig at the time of turning on is positive or negative, it is possible to determine whether the gate current Ig is normal on or short-circuited.

  In order to realize this determination, in the first embodiment, the output of the gate current detection means 4 is input to the two comparison means 7a and 7b. The outputs of the reference voltage generating means 6a and 6b are also inputted to the comparing means 7a and 7b, respectively, and compared with the signal of the gate current detecting means 4. The reference voltage generating means 6a and 6b generate positive and negative reference voltages, respectively, compare whether the output of the gate current detecting means 4 is larger than the level, and output the result to the short circuit determining means 5. First, the short circuit determination means 5 detects whether the output of the gate current detection means 4 is larger than the positive reference voltage. If detected, if there is a signal whose output of the gate current detection means 4 is smaller than the negative reference voltage during a predetermined time specified from there, it is regarded as a short circuit, and the gate circuit 3 narrows down the gate voltage. Protection can be performed.

  In the above description, the gate current Ig is detected by the gate current detector 4 and compared with the positive reference voltage of the first reference voltage generator 6a and the negative reference voltage of the second reference voltage generator 6b. However, the gate current Ig may be detected by the gate current detection means 4 and compared with a positive reference current and a negative reference current.

  According to the first embodiment, by detecting the time change of the output of the gate current detection means, it is possible to detect a short circuit early and protect the switching element before the switching element fails. .

(Second Embodiment)
FIG. 4 is a configuration diagram of a power converter according to the second embodiment of the present invention. This second embodiment is different from the first embodiment in that a gate voltage detection means 8 is provided in addition to the gate current detection means 4, the gate current flows in by the mirror period determination means 9, and the gate When the voltage is constant, the mirror period is determined, and the voltage when the switching element 1 is turned off is suppressed.

  A flywheel diode 2 is connected in parallel to the switching element 1, and the switching element 1 is driven by a gate circuit 3. Thereby, the device current Ic of the switching device 1 is controlled. The gate current Ig applied from the gate circuit 3 to the gate of the switching element 1 is detected by the gate current detection means 4 and input to the comparison means 7. The reference voltage generator 6 generates a reference voltage when the switching element 1 is off. The comparing means 7 compares the voltage corresponding to the gate current Ig detected by the gate current detecting means 4 with the off-time reference voltage (negative reference voltage) from the reference voltage generating means 6.

  The mirror period determination means 9 is detected by the gate voltage detection means 8 in a state where the gate current detected by the comparison means 7 by the gate current detection means 4 is equal to or lower than the reference voltage generation means 6 off-time reference voltage. When a mirror period in which the gate voltage is substantially constant is detected, a command is output to the gate circuit 3 so as to suppress the voltage when the switching element 1 is turned off.

  Next, the operation will be described. When the switching element 1 is turned off, the gate circuit 3 applies about −15 V and causes the gate current to flow in the negative direction. As a result, the charge stored in the gate-emitter capacitance of the switching element 1 is discharged, and the gate voltage of the switching element 1 decreases. Next, a gate current flows from the feedback capacitance between the gate and the collector. At this time, since the gate-emitter capacitance is hardly discharged, the gate voltage becomes substantially constant. Finally, the gate-emitter capacitance is discharged, the collector voltage begins to increase, the gate voltage drops to -15 V, and the turn-off is completed.

  Here, a period in which the gate voltage is substantially constant is referred to as a mirror period. In FIG. 4, the gate current detecting means 4 detects that the gate current Ig at the time of OFF flows. Further, the gate voltage detection means 8 detects the gate voltage Vg and inputs it to the mirror period determination means 9. When the gate current Ig flows and the gate voltage Vg is constant, the mirror period determination means 9 determines that the mirror period is present.

  When it is determined as the mirror period, it is possible to suppress the surge voltage at the OFF time by increasing the gate resistance of the gate circuit 3 or decreasing the gate current Ig drawn from the switching element 1. In particular, since a larger current than usual is cut off at the time of overcurrent, the switching element 1 can be turned off without being destroyed by changing the off condition when the mirror period is detected in the interruption after the short circuit is detected. Become.

  According to the second embodiment, it is possible to determine the mirror period by detecting the gate current and the gate voltage, and to suppress the voltage when the switching element 1 is turned off.

(Third embodiment)
FIG. 5 is a configuration diagram of a power converter according to the third embodiment of the present invention. In the third embodiment, a differentiating means 10 for differentiating the gate voltage detected by the gate voltage detecting means 8 is provided, and the mirror period determining means 9 has a differential value of the gate voltage obtained by the differentiating means 10 being zero. This period is detected as a mirror period. The same elements as those in FIG. 4 are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 5, differentiating means 10 for differentiating the gate voltage detected by the gate voltage detecting means 8 is added, and the output of the differentiating means 10 is input to the mirror period determining means 9.

  In the second embodiment, the mirror period is determined when the gate current is flowing in the negative direction and the gate voltage becomes constant. However, since this constant voltage varies depending on element characteristics, element current Ic, and the like, reliability may not be maintained if it is determined that the mirror period is simply compared with a certain set voltage value. In order to provide the reliability, the circuit configuration of the gate voltage detection means 8 becomes complicated.

  Therefore, in the third embodiment, the output of the gate voltage detection means 8 is input to the differentiation means 10, and the differentiation means 10 differentiates the gate voltage Vg and inputs it to the mirror period determination means 9. The mirror period determination means 9 determines that it is the mirror period when the gate current Ig flows and the differential output becomes zero. Although the gate voltage Vg that becomes constant varies depending on the switching element 1 and the element current Ic, the differential output becomes zero. Therefore, the mirror period can be determined regardless of the switching element 1 and the element current Ic.

  According to the third embodiment, the mirror period can be determined without complicating the circuit configuration of the gate voltage detection means 8.

(Fourth embodiment)
FIG. 6 is a configuration diagram of a power converter according to the fourth embodiment of the present invention. In the fourth embodiment, the gate current detected by the gate current detection means 4 is integrated by the integration means 11, and the mirror period determination means 9 is a charge that is an integration of the gate current Ig obtained by the integration means 11. The mirror period is detected based on the correlation between the amount and the gate voltage detected by the gate voltage detecting means 8.

  In the third embodiment, when the gate current Ig flows in the negative direction and the differential value of the gate voltage Vg becomes zero, the mirror period is determined. However, the detection of the gate voltage Vg is performed. There is a possibility that noise is added to the value and it cannot be judged correctly. Therefore, in the fourth embodiment, the output of the gate current detecting means Ig is input to the integrating means 11 and the result is input to the mirror period determining means 9.

  Here, when the switching element 1 is turned off, first, the charge stored in the gate-emitter capacitance is discharged. At this time, the charge amount Q remaining in the gate-emitter capacitance and the voltage V have a relationship of Q = CV (C is a constant). Since C is a constant, the charge amount Q and the voltage V are in a proportional relationship. For example, when a certain amount of charge Q is discharged, the gate voltage Vg decreases by the voltage V = Q / C determined by the above equation. Since the charge amount is an integral value of the current, the amount of charge discharged from the gate can be obtained by integrating the gate current Ig. The increase in the integral value (charge amount) and the decrease in the gate voltage Vg change in a proportional relationship.

  In the mirror period, the gate-emitter capacitance is not discharged, and the gate current flows from the gate-collector feedback capacitance. For this reason, the integrated value of the gate current Ig continues to increase, but the gate voltage Vg does not change. Therefore, the gate voltage drop expected from the integrated value of the gate current Ig does not coincide with the actual gate voltage Vg drop. At this time, it can be determined that it is the mirror period.

  According to the fourth embodiment, it is possible to correctly determine the mirror period even when noise is added to the detection value of the gate voltage Vg.

(Fifth embodiment)
FIG. 7 is a configuration diagram of a power converter according to the fifth embodiment of the present invention. In the fifth embodiment, the gate voltage detecting means 8 is removed from the fourth embodiment shown in FIG.

  In the fourth embodiment, the gate voltage Vg in the mirror period in which the mirror period is determined by comparing the integrated value of the gate current Ig and the gate voltage Vg varies with the element current Ic. In addition, the gate voltage Vg is often not constant but fluctuates. For this reason, there is a possibility that the mirror period cannot be determined by comparison with the gate voltage Vg.

  Therefore, in the fifth embodiment, the output of the gate current detection unit 4 is integrated by the integration unit 11 and only the output is input to the mirror period determination unit 9. The relationship between the gate capacitance charge of the switching element 1 and the gate voltage Vg is determined by the switching element 1. For example, when the switching element 1 is turned on, current is injected into the gate of the switching element 1. If the current value at this time is integrated, the charge of the gate can be obtained. Since the relationship between the gate charge and the gate voltage is obtained from the data sheet, the range of the gate charge during the period in which the gate voltage Vg is constant can be easily known. For this reason, when the charge amount obtained by integrating the gate current Ig is within a certain range, it can be determined that it is the mirror period.

  According to the fifth embodiment, even when the gate voltage Vg varies, the mirror period can be determined by detecting the integrated output of the gate current.

(Sixth embodiment)
FIG. 8 is a configuration diagram of the mirror period determining means and the gate circuit portion of the power converter according to the sixth embodiment of the present invention. The sixth embodiment is different from the second to fifth embodiments in that the gate current adjusting means 12 for adjusting the gate current Ig during the mirror period detected by the mirror period determining means 9 is provided. It is provided.

  When the switching element 1 is turned on, the paired flywheel diodes 2 perform reverse recovery, and an overvoltage is generated. This overvoltage occurs because the flywheel diode 2 is turned off from the conductive state, and the overvoltage increases as the speed of turning on becomes faster. Therefore, this overvoltage can be suppressed by increasing the gate resistance of the gate circuit 3 to reduce the gate current and turning it on slowly, but in this case, the loss of the switching element 1 increases.

  Therefore, in the fifth embodiment, the gate current adjusting means 12 can adjust the gate current when the mirror period determining means 9 determines that it is the mirror period. As a result, the voltage is first turned on slowly to suppress overvoltage, and when the mirror period is reached, the gate current is increased to increase the ON speed and suppress loss.

  According to the sixth embodiment, since the gate current is adjusted when it is determined that the period is the mirror period, the loss of the switching element 1 can be reduced.

(Seventh embodiment)
FIG. 9 is a configuration diagram of the mirror period determining means and the gate circuit portion of the power converter according to the seventh embodiment of the present invention. This seventh embodiment is different from the sixth embodiment shown in FIG. 8 in that current detection means 13 for detecting the element current Ic of the switching element 1 is provided, and the gate current adjustment means 13 is current detection means. The gate current Ig is adjusted based on the magnitude of the element current Ic of the switching element 1 detected at 13.

  In the sixth embodiment, the gate current is adjusted during the mirror period, but the overvoltage applied to the switching element 1 varies depending on the element current Ic. For example, when the switching element 1 is turned off, the overvoltage increases when a large current is cut off. For this reason, if the gate current is adjusted uniformly during the mirror period, the loss of the switching element 1 increases.

  Therefore, in the seventh embodiment, the output of the current detection unit 13 is input to the gate current adjustment unit 12, and when the current value of the element current Ic is large, the overvoltage is large, so that the injection of the gate current Ig is suppressed. On the other hand, when the current value of the element current Ic is small, the overvoltage is small, so that a large amount of the gate current Ig can be injected and promptly cut off to suppress the loss.

  According to the seventh embodiment, the loss of the switching element 1 can be appropriately suppressed by controlling the adjustment amount of the gate current according to the element current Ic of the switching element 1.

(Eighth embodiment)
FIG. 10 is a configuration diagram of the mirror period determining means and the gate circuit portion of the power converter according to the eighth embodiment of the present invention. The eighth embodiment is different from the sixth embodiment shown in FIG. 8 in that voltage detecting means 14 for detecting the element voltage of the switching element 1 is provided, and the gate current adjusting means 12 is the voltage detecting means 14. The gate current Ig is adjusted based on the magnitude of the element voltage of the switching element 1 detected in (1).

  In the sixth embodiment, the gate current is adjusted during the mirror period, but a DC voltage higher than usual may be applied to a power converter such as an inverter. When the DC voltage is high, the margin with respect to the withstand capability of the switching element 1 becomes small. Therefore, there is a possibility that the switching element 1 is destroyed by the same gate injection as usual.

  Therefore, in the eighth embodiment, since the output of the voltage detection means 14 is input to the gate current adjusting means 12 and it is necessary to suppress the overvoltage more than usual when the DC voltage is high, the gate current injection is made more than usual. suppress. As a result, even when the DC voltage is high, it is possible to suppress the overvoltage and turn it off.

  According to the eighth embodiment, the overvoltage of the switching element 1 can be suppressed by controlling the adjustment amount of the gate current according to the element voltage.

(Ninth embodiment)
FIG. 11 is a configuration diagram of the mirror period determining means and the gate circuit portion of the power converter according to the ninth embodiment of the present invention. The ninth embodiment is provided with an element temperature detecting means 15 for detecting the element temperature of the switching element 1 in contrast to the sixth embodiment shown in FIG. The gate current Ig is adjusted based on the element temperature of the switching element 1 detected by the means 15.

  In the sixth embodiment, the gate current is adjusted during the mirror period, but the characteristics of the switching element 1 change depending on the temperature and must be used below the specified value. It is not possible to cope with temperature simply by adjusting the current.

  Therefore, in the ninth embodiment, the output of the element temperature detecting means 15 is inputted to the gate current adjusting means 12, and when the temperature of the switching element 1 is high, the gate current Ig is injected more than usual to suppress the loss, It becomes possible to suppress the temperature rise of the switching element 1.

  According to the ninth embodiment, the loss of the switching element 1 can be suppressed by controlling the adjustment amount of the gate current Ig according to the element temperature.

  In each of the above embodiments, the switching element 1 has been described by taking an IGBT as an example. However, the switching element 1 is not limited to the IGBT, and any non-latching switching element controlled by voltage can be applied to a MOSFET or the like. Needless to say.

The block diagram of the power converter concerning the 1st Embodiment of this invention. The wave form diagram of the gate current at the time of normal operation of a power converter and element current in an embodiment of the invention. The wave form diagram of the gate current at the time of the short circuit of the power converter in embodiment of this invention, and element current. The block diagram of the power converter concerning the 2nd Embodiment of this invention. The block diagram of the power converter concerning the 3rd Embodiment of this invention. The block diagram of the power converter concerning the 4th Embodiment of this invention. The block diagram of the power converter concerning the 5th Embodiment of this invention. The block diagram of the mirror period determination means and gate circuit part of the power converter concerning the 6th Embodiment of this invention. The block diagram of the mirror period determination means and gate circuit part of the power converter concerning the 7th Embodiment of this invention. The block diagram of the mirror period determination means and gate circuit part of a power converter concerning the 8th Embodiment of this invention. The block diagram of the mirror period determination means and gate circuit part of the power converter concerning the 9th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Switching element, 2 ... Flywheel diode, 3 ... Gate circuit, 4 ... Gate current detection means, 5 ... Short circuit determination means, 6 ... Reference voltage generation means, 7 ... Comparison means, 8 ... Gate voltage detection means, 9 ... Mirror period determination means, 10 ... differentiation means, 11 ... integration means, 12 ... gate current adjustment means, 13 ... current detection means, 14 ... voltage detection means, 15 ... element temperature detection means

Claims (9)

Gate current detecting means for detecting a gate current of the switching element, first reference voltage generating means for generating a positive reference voltage, second reference voltage generating means for generating a negative reference voltage, and the gate First comparison means for comparing a voltage corresponding to the gate current detected by the current detection means and a positive reference voltage of the first reference voltage generation means; and a gate current detected by the gate current detection means A second comparison means for comparing a corresponding voltage with a negative reference voltage of the second reference voltage generation means, and a voltage corresponding to the gate current detected by the gate current detection means by the first comparison means. The voltage corresponding to the gate current detected by the gate current detection means by the second comparison means within a predetermined time after the voltage becomes equal to or higher than the positive reference voltage of the first reference voltage generation means Power converter when it becomes less negative reference voltage of the reference voltage generating means, characterized by comprising a determining short judging means and the short-circuit of the switching element. A gate current detecting means for detecting a gate current of the switching element; a reference voltage generating means for generating a reference voltage when the switching element is off; a voltage corresponding to the gate current detected by the gate current detecting means; Comparing means for comparing the reference voltage generating means with the off-time reference voltage, gate voltage detecting means for detecting the off-time gate voltage of the switching element, and the gate detected by the comparing means with the gate current detecting means When a mirror period in which the gate voltage detected by the gate voltage detecting means is substantially constant in a state where the voltage corresponding to the current is equal to or lower than the reference voltage when the reference voltage generating means is OFF is detected. A power converter comprising: a mirror period determination unit that suppresses a voltage at the time of OFF. Differentiating means for differentiating the gate voltage detected by the gate voltage detecting means is provided, and the mirror period determining means detects a period in which the differential value of the gate voltage obtained by the differentiating means is zero as a mirror period. The power converter according to claim 2. Gate current detecting means for detecting the gate current of the switching element, gate voltage detecting means for detecting the gate voltage when the switching element is off, and voltage corresponding to the gate current detected by the gate current detecting means Integrating means for integrating the mirror, and mirror period determining means for detecting the mirror period based on the correlation between the amount of charge obtained by integrating the gate current obtained by the integrating means and the gate voltage detected by the gate voltage detecting means And a power converter. Gate current detecting means for detecting the gate current of the switching element, gate voltage detecting means for detecting the gate voltage when the switching element is off, and voltage corresponding to the gate current detected by the gate current detecting means Integration means for obtaining a gate charge by previously integrating the relationship between the charge of the gate capacitance of the switching element and the gate voltage, the gate charge obtained by the integration means and the gate capacitance stored in advance A power converter comprising: mirror period determining means for detecting a mirror period based on a relationship between charge and gate voltage. 6. The power converter according to claim 2, further comprising a gate current adjusting unit configured to adjust a gate current during a mirror period detected by the mirror period determining unit. Current detecting means for detecting an element current of the switching element is provided, and the gate current adjusting means adjusts the gate current based on the magnitude of the element current of the switching element detected by the current detecting means. The power converter according to claim 6. Voltage detecting means for detecting an element voltage of the switching element is provided, and the gate current adjusting means adjusts the gate current based on the magnitude of the element voltage of the switching element detected by the voltage detecting means. The power converter according to claim 6. An element temperature detecting means for detecting an element temperature of the switching element is provided, and the gate current adjusting means adjusts the gate current based on the element temperature of the switching element detected by the element temperature detecting means. The power converter according to claim 6.

Images