JP2021068772A - Semiconductor device and manufacturing method for semiconductor device - Google Patents

Abstract

To provide a semiconductor device including nitride semiconductor with higher yield.SOLUTION: A semiconductor device includes a semiconductor layer provided on one surface of a substrate, a first etching stopper layer and a second etching stopper layer provided on the semiconductor layer, a veer hole penetrating the substrate and the semiconductor layer from the other surface of the substrate and using the first etching stopper layer and the second etching stopper layer as a bottom surface, a seed metal layer formed on the bottom surface and a side surface inside the veer hole, and a back electrode formed by plating on the seed metal layer. A central part of the bottom surface of the veer hole is formed by the first etching stopper layer and a corner part of the bottom surface is formed by the second etching stopper layer. The seed metal layer and the second etching stopper layer have the same ionization tendency, or the second etching stopper layer has smaller ionization tendency than the seed metal layer.SELECTED DRAWING: Figure 11

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Nitride semiconductors such as GaN, AlN, and InN, or materials having mixed crystals thereof have a wide bandgap and are used as high-power electronic devices, short-wavelength light emitting devices, and the like. Among these, as a high output device, a technology related to a high electron mobility transistor (HEMT) has been developed. As an electric field effect transistor using a nitride semiconductor, there is HEMT using GaN for the electron traveling layer and AlGaN for the electron supply layer, and two-dimensional electron gas in the electron traveling layer due to the action of piezo polarization and spontaneous polarization in GaN. (2DEG: Two-Dimensional Electron Gas) is generated.

Field-effect transistors using nitride semiconductors are mainly used as transmitter elements for wireless communication, radar, etc., because they are capable of high output and high withstand voltage operation. For example, a field-effect transistor using a nitride semiconductor and an MMIC (Monolithic Microwave Integrated Circuit) formed on the same semiconductor chip as a capacitor, resistor, wiring, etc. can realize a high-performance device with a small size. It is possible. Some such MMICs have a source electrode on the front surface side of the substrate and a ground on the back surface side connected by a via wiring formed on the substrate.

Japanese Patent No. 5168933 Japanese Unexamined Patent Publication No. 2013-89816

In a MMIC having a field effect transistor, which is a semiconductor device using a nitride semiconductor, a disconnection or the like may occur in the vicinity of the via wiring, which has been a factor in lowering the yield.

Therefore, a semiconductor device using a nitride semiconductor with a high yield has been required.

According to one aspect of the present embodiment, the semiconductor layer provided on one surface of the substrate, the first etching stopper layer and the second etching stopper layer provided on the semiconductor layer, and the substrate. A via hole that penetrates the substrate and the semiconductor layer from the other surface and has the first etching stopper layer and the second etching stopper layer as the bottom surfaces, and seeds formed on the bottom surface and side surfaces inside the via hole. It has a metal layer and a back surface electrode formed by plating on the seed metal layer, and the bottom surface of the via hole has a central portion formed by the first etching stopper layer and a corner portion formed by the first etching stopper layer. The seed metal layer and the second etching stopper layer are formed by a second etching stopper layer, and the ionization tendency is the same, or the second etching stopper layer is more than the seed metal layer. It is characterized by a small ionization tendency.

According to the disclosed semiconductor device, the yield can be improved in the semiconductor device using the nitride semiconductor.

Structural diagram of MMIC using nitride semiconductor Process diagram of a method for manufacturing an MMIC using a nitride semiconductor (1) Process diagram of a method for manufacturing an MMIC using a nitride semiconductor (2) Process diagram of a method for manufacturing an MMIC using a nitride semiconductor (3) Process diagram of a method for manufacturing an MMIC using a nitride semiconductor (4) Explanatory drawing of the mechanism that the etching stopper layer is eroded (1) Explanatory drawing of the mechanism that the etching stopper layer is eroded (2) Explanatory drawing of the mechanism that the etching stopper layer is eroded (3) Explanatory drawing showing how the etching stopper layer is eroded (1) Explanatory drawing showing how the etching stopper layer is eroded (2) Structural diagram of the semiconductor device according to the first embodiment Explanatory drawing of semiconductor device in 1st Embodiment Process diagram of the method for manufacturing a semiconductor device according to the first embodiment (1) Process diagram of the method for manufacturing a semiconductor device according to the first embodiment (2) Process diagram of the method for manufacturing a semiconductor device according to the first embodiment (3) Process diagram (4) of the method for manufacturing a semiconductor device according to the first embodiment. Process diagram (5) of the method for manufacturing a semiconductor device according to the first embodiment. Process diagram (6) of the method for manufacturing a semiconductor device according to the first embodiment. Structural diagram of the semiconductor device according to the second embodiment Process diagram of the method for manufacturing a semiconductor device according to the second embodiment (1) Process diagram of the method for manufacturing a semiconductor device according to the second embodiment (2) Process diagram of the method for manufacturing a semiconductor device according to the second embodiment (3) Process diagram (4) of the method for manufacturing a semiconductor device according to the second embodiment. Process diagram (5) of the method for manufacturing a semiconductor device according to the second embodiment. Process diagram (6) of the method for manufacturing a semiconductor device according to the second embodiment. Structural diagram of the semiconductor device according to the third embodiment Process diagram of the method for manufacturing a semiconductor device according to the third embodiment (1) Process diagram of the method for manufacturing a semiconductor device according to the third embodiment (2) Process diagram of the method for manufacturing a semiconductor device according to the third embodiment (3) Process diagram (4) of the method for manufacturing a semiconductor device according to the third embodiment. Process diagram (5) of the method for manufacturing a semiconductor device according to the third embodiment. Process diagram (6) of the method for manufacturing a semiconductor device according to the third embodiment. Structural diagram of the semiconductor device according to the fourth embodiment Process diagram of the method for manufacturing a semiconductor device according to the fourth embodiment (1) Process diagram of the method for manufacturing a semiconductor device according to the fourth embodiment (2) Process diagram of the method for manufacturing a semiconductor device according to the fourth embodiment (3) Process diagram of the method for manufacturing a semiconductor device according to the fourth embodiment (4) Process diagram (5) of the method for manufacturing a semiconductor device according to the fourth embodiment. Process diagram (6) of the method for manufacturing a semiconductor device according to the fourth embodiment.

The embodiment for carrying out will be described below. The same members and the like are designated by the same reference numerals and the description thereof will be omitted. Further, for convenience of explanation, the vertical and horizontal scales in the drawings may differ from the actual ones.

[First Embodiment]
First, a MMIC having a field effect transistor, which is a semiconductor device using a nitride semiconductor, will be described with reference to FIG.

In the MMIC shown in FIG. 1, a nitride semiconductor layer in which a buffer layer (not shown), an electron traveling layer 21, and an electron supply layer 22 are laminated in this order is formed on one surface 10a of the substrate 10 by epitaxial growth. The substrate 10 is made of a material such as SiC and has one surface 10a and the other surface 10b opposite to one surface. The buffer layer (not shown) is formed of AlN, GaN, or the like, the electron traveling layer 21 is formed of i-GaN, and the electron supply layer 22 is formed of AlGaN. As a result, in the electron traveling layer 21, 2DEG21a is generated in the vicinity of the interface between the electron traveling layer 21 and the electron supply layer 22. A gate electrode 31, a source electrode 32, and a drain electrode 33 are formed on the electron supply layer 22.

Further, an etching stopper layer 50 is formed in a predetermined region above the electron supply layer 22 by Al or the like. A via hole 60 penetrating the substrate 10, the buffer layer, the electron traveling layer 21, and the electron supply layer 22 is formed from the other surface 10b of the substrate 10 in the region where the etching stopper layer 50 is formed. The bottom surface is an etching stopper layer 50. An etching mask 72 for forming the via hole 60 is formed of Ni or the like on the other surface 10b of the substrate 10, and the seed metal layer 71 and the back surface are formed on the bottom surface and the side surface of the via hole 60 and the etching mask 72. The electrodes 70 are laminated and formed. Therefore, on the bottom surface of the via hole 60, the back surface electrode 70 and the etching stopper layer 50 are electrically connected via the seed metal layer 71. The etching stopper layer 50 and the source electrode 32 are connected by a wiring 51, and the ground potential applied to the back surface electrode 70 is applied to the source electrode 32 via the etching stopper layer 50 and the wiring 51.

Next, the manufacturing method of the semiconductor device shown in FIG. 1 will be described with reference to FIGS. 2 to 5.

First, as shown in FIG. 2, a buffer layer (not shown), an electron traveling layer 21, and an electron supply layer 22 are formed by epitaxially growing a nitride semiconductor layer on one surface 10a of the substrate 10. As a result, in the electron traveling layer 21, 2DEG21a is generated in the vicinity of the interface between the electron traveling layer 21 and the electron supply layer 22. The nitride semiconductor layer is formed by epitaxial growth by MOVPE (Metal Organic Vapor Phase Epitaxy). After that, the gate electrode 31, the source electrode 32, the drain electrode 33, and the etching stopper layer 50 are formed on the electron supply layer 22. A SiC substrate is used for the substrate 10, the electron traveling layer 21 is formed of i-GaN having a film thickness of about 3 μm, and the electron supply layer 22 is formed of AlGaN having a film thickness of about 6 nm. There is. The etching stopper layer 50 is formed of Al.

Next, as shown in FIG. 3, a via hole 60 is formed from the other surface 10b of the substrate 10 by dry etching using a fluorine-based gas as the etching gas. Specifically, the via hole 60 is formed by forming an etching mask 72 having an opening on the other surface 10b of the substrate 10 with Ni or the like and removing the substrate 10 or the like at the opening of the etching mask 72. The opening of the etching mask 72 is formed on the opposite side of the portion where the etching stopper layer 50 is formed, and the via hole 60 is stopped by stopping the etching when the bottom surface of the via hole 60 reaches the etching stopper layer 50. Is formed.

Next, as shown in FIG. 4, a seed metal layer 71 is formed on the other surface 10b of the substrate 10 and the bottom surface and side surfaces of the via hole 60 by sputtering or the like. The seed metal layer 71 is formed of a Ti / Au metal multilayer film in which a Ti film and an Au film are laminated in this order, and the Au film is exposed.

Next, as shown in FIG. 5, the back surface electrode 70 is formed by depositing an Au film on the seed metal layer 71 by plating. After that, as shown in FIG. 1, the etching stopper layer 50 and the source electrode 32 are connected by the wiring 51. The back surface electrode 70 may be formed by depositing a Cu film by plating.

In the above semiconductor device, Al (aluminum) or Ni (nickel) having high resistance to dry etching using a fluorine-based gas is used for the etching stopper layer 50.

By the way, in the semiconductor device manufactured by the above manufacturing method, a part of the etching stopper layer 50 may be eroded, resulting in disconnection or the like. Therefore, the inventor has studied that a part of the etching stopper layer 50 is eroded. As a result, it was found that the etching stopper layer 50 is eroded in the step of immersing the seed metal layer 71 in an electrolytic solution such as a developing solution or a plating solution after forming a film.

Here, it was examined that the etching stopper layer 50 formed of Al is eroded when immersed in the electrolytic solution. First, experiments were conducted on the resistance of Al and Ni to electrolytes. Since TMAH is contained in the developing solution and the like, it was confirmed that when Al and Ni were immersed in TMAH, Al and Ni were hardly eroded. Next, an Al film 82 was formed on the Si substrate 81 as shown in FIG. 6, and a sample 80 in which the Ti film 83 and the Au film 84 were laminated in this order on a part of the Al film 82 was prepared. Then, as shown in FIG. 7, an experiment of immersing in the electrolytic solution 85 of TMAH was carried out. As a result, it was confirmed that the Al film 82 was eroded at an etching rate of 10 nm / min or more.

Al alone is not eroded even if it is immersed in TMAH, but when the sample 80 is immersed in TMAH, the Al film 82 is eroded, so that both the Al film 82 and the Au film 84 like the sample 80 are exposed. It is presumed that the Al film 82 is eroded. That is, as shown in FIG. 8, when electrons (e ^{− ) are supplied from the conducting Al film 82 toward the Au film 84, H +} contained in the electrolytic solution 85 is supplied on the surface of the Au film 84. Hydrogen (H ₂ ) is generated by the ^{electron (e −} ) and the electron (e −). Therefore, Al contained in the Al film 82 loses electrons and is ionized to become Al ³⁺ , which dissolves in the electrolytic solution 85 and leads to the idea of a mechanism in which Al is eroded.

Such a phenomenon is caused by the potential difference between Al and Au that occurs in the electrolytic solution, and is considered to be caused by immersing two kinds of metals having a large difference in ionization tendency in the electrolytic solution. Even in the case of a Ni film instead of the Al film, it is eroded in the same manner, but the erosion is more remarkable in Al than in Ni.

From the results of the above experiments, it will be described that the etching stopper layer 50 is eroded. In the step shown in FIG. 4, the seed metal layer 71 is formed by film formation such as sputtering, and the bottom surface side at the back is thinner than the inlet side of the via hole 60. Further, since the film formed by sputtering grows from the surfaces on the bottom surface and the side surface of the via hole 60, as shown in FIG. 9, at the portion of the angle 60a between the bottom surface and the side surface, the gap 71a is formed in the seed metal layer 71. Is likely to occur.

Therefore, as shown in FIG. 10, the electrolytic solution invades from the gap 71a of the seed metal layer 71 as shown by the broken line arrow, and the etching stopper layer 50 formed of Al is eroded, and the etching stopper layer is eroded. It is considered that the hole 50a is formed in 50. That is, when the electrolytic solution penetrates through the gap 71a of the seed metal layer 71, both Au of the seed metal layer 71 and Al of the etching stopper layer 50 are immersed in the electrolytic solution. Therefore, it is presumed that the etching stopper layer 50 formed by Al is eroded so as to expand from the gap 71a, and a hole 50a penetrating the etching stopper layer 50 is formed, which causes disconnection.

Therefore, there is a demand for a semiconductor device capable of manufacturing with a high yield without eroding the etching stopper layer even when the seed metal layer is formed and then immersed in a developing solution or a plating solution. There is.

(Semiconductor device)
Next, the semiconductor device according to the first embodiment will be described with reference to FIG. FIG. 11 is a cross-sectional view of the semiconductor device according to the present embodiment.

In the semiconductor device of the present embodiment, a nitride semiconductor layer in which a buffer layer (not shown), an electron traveling layer 21, and an electron supply layer 22 are laminated in this order is formed on one surface 10a of the substrate 10 by epitaxial growth. .. The substrate 10 is made of a material such as SiC. The buffer layer (not shown) is formed of AlN, GaN, or the like, the electron traveling layer 21 is formed of i-GaN, and the electron supply layer 22 is formed of AlGaN. As a result, in the electron traveling layer 21, 2DEG21a is generated in the vicinity of the interface between the electron traveling layer 21 and the electron supply layer 22. A gate electrode 31, a source electrode 32, and a drain electrode 33 are formed on the electron supply layer 22.

Further, after forming the first etching stopper layer 151 and the second etching stopper layer 152 on the electron supply layer 22, the substrate 10, the buffer layer, and the electron traveling layer 21 are formed from the other surface 10b of the substrate 10. A via hole 160 penetrating the electron supply layer 22 is formed. The bottom surface 161 of the via hole 160 has a central portion 161a as a first etching stopper layer 151 and a peripheral corner portion 161b as a second etching stopper layer 152. An etching mask 172 for forming a via hole 160 is formed of Ni or the like on the other surface 10b of the substrate 10. Further, a seed metal layer 171 and a back surface electrode 170 are sequentially laminated and formed on the bottom surface 161 and the side surface 162 and the etching mask 172 inside the via hole 160.

Therefore, on the bottom surface 161 of the via hole 160, the back surface electrode 170, the first etching stopper layer 151, and the second etching stopper layer 152 are electrically connected via the seed metal layer 171. The first etching stopper layer 151 and the source electrode 32 are connected by a wiring 51, and the ground potential applied to the back surface electrode 170 is applied to the source electrode 32 via the first etching stopper layer 151 and the wiring 51. It is applied.

In the present embodiment, the seed metal layer 171 is formed of a Ti / Cu laminated film in which a Ti film and a Cu film are sequentially formed by sputtering, or a Ta / Cu laminated film in which a Ta film and a Cu film are sequentially formed. Has been done. Therefore, Cu is exposed on the surface of the seed metal layer 171. The second etching stopper layer 152 is formed of Au. Further, since the first etching stopper layer 151 is required to be a material having strong resistance to dry etching, it is formed of Al or Ni.

FIG. 12 shows a state after forming the via hole 160 and then forming the seed metal layer 171 by sputtering in the step of manufacturing the semiconductor device according to the present embodiment. The seed metal layer 171 formed by sputtering may have a gap 171a at the corner portion 161b of the bottom surface 161 of the via hole 160, and when immersed in an electrolytic solution such as a developing solution or a plating solution, the gap 171a of the seed metal layer 171 may be formed. More electrolyte will enter.

However, in the present embodiment, the second etching stopper layer 152 is formed of Au, which is a material having a lower ionization tendency than Cu on the surface of the exposed seed metal layer 171. Therefore, even if the electrolytic solution enters through the gap 171a of the seed metal layer 171, the second etching stopper layer 152 is not eroded.

That is, the second etching stopper layer 152 is eroded by forming the second etching stopper layer 152 formed at the corner portion 161b of the bottom surface 161 of the via hole 160 with a metal having a lower ionization tendency than the seed metal layer 171. I'm preventing that. Even if the second etching stopper layer 152 formed on the corner portion 161b of the bottom surface 161 of the via hole 160 is formed of the same material as the seed metal layer 171, the second etching stopper layer 152 is similarly eroded. Can be prevented.

In the present embodiment, the via hole 160 is formed by dry etching such as RIE (Reactive Ion Etching) using a fluorine-based gas as the etching gas. Since the power in dry etching is relatively weak at the corner portion 161b of the bottom surface 161 of the via hole 160, there is no problem even if the corner portion 161b of the bottom surface 161 of the via hole 160 is formed of a material having not so high resistance to dry etching. On the other hand, in the central portion 161a of the bottom surface 161 of the via hole 160, since the power in dry etching is relatively high, it is preferable that the material has high resistance in dry etching.

(Manufacturing method of semiconductor device)
Next, the method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 13 to 18.

First, as shown in FIG. 13, a buffer layer (not shown), an electron traveling layer 21, and an electron supply layer 22 are formed in this order by epitaxially growing a nitride semiconductor layer on one surface 10a of the substrate 10. As a result, in the electron traveling layer 21, 2DEG21a is generated in the vicinity of the interface between the electron traveling layer 21 and the electron supply layer 22. The nitride semiconductor layer is formed by epitaxial growth by MOVPE. After that, the gate electrode 31, the source electrode 32, and the drain electrode 33 are formed on the electron supply layer 22. A SiC substrate is used for the substrate 10, the electron traveling layer 21 is formed of i-GaN having a film thickness of about 3 μm, and the electron supply layer 22 is formed of AlGaN having a film thickness of about 6 nm. There is.

Next, as shown in FIG. 14, a second etching stopper layer 152 is formed on the electron supply layer 22. The second etching stopper layer 152 is formed at a portion corresponding to the corner portion 161b of the bottom surface 161 of the via hole 160, and is formed in an annular shape having an inner diameter of 30 μm and an outer diameter of 90 μm, for example. Specifically, a resist (not shown) having an opening in a region where the second etching stopper layer 152 is formed by applying a photoresist on the electron supply layer 22 and performing exposure and development with an exposure apparatus. Form a pattern. After that, an Au film is formed by vacuum vapor deposition and immersed in an organic solvent to remove the Au film on the resist pattern together with the resist pattern by lift-off. As a result, the second etching stopper layer 152 is formed by the remaining Au film. The second etching stopper layer 152 formed in this manner is formed in an annular shape at a portion corresponding to the corner portion 161b of the bottom surface 161 of the via hole 160, and is a portion corresponding to the central portion 161a of the bottom surface 161 of the via hole 160. Is open. The second etching stopper layer 152 has a film thickness of 100 nm or more and 1 μm or less.

The second etching stopper layer 152 may be formed by a method other than the lift-off as described above. For example, an Au film is formed, a resist pattern (not shown) is formed in a region on the Au film where a second etching stopper layer 152 or the like is formed, and a resist pattern is formed by dry etching such as RIE. It may be formed by removing the Au film in the non-existent region.

Next, as shown in FIG. 15, the first etching stopper layer is placed on the electron supply layer 22 surrounded by the second etching stopper layer 152 and on the second etching stopper layer 152 surrounding the electron supply layer 22. Form 151. Specifically, a photoresist is applied onto the second etching stopper layer 152 and the electron supply layer 22, and the region is exposed and developed by an exposure apparatus to form a region where the first etching stopper layer 151 is formed. A resist pattern (not shown) having an opening is formed. After that, an Al film is formed by vacuum vapor deposition and immersed in an organic solvent to remove the Al film on the resist pattern together with the resist pattern by lift-off. As a result, the first etching stopper layer 151 is formed by the remaining Al film. The first etching stopper layer 151 formed in this manner has a film thickness of 500 nm or more and 1 μm or less, and is formed in a portion corresponding to the central portion 161a of the via hole 160 to be formed later.

The first etching stopper layer 151 may be formed of Ni. Further, the first etching stopper layer 151 may be formed by a method other than the lift-off as described above. For example, an Al film is formed, a resist pattern (not shown) is formed in a region on the Al film on which the first etching stopper layer 151 or the like is formed, and a resist pattern is formed by dry etching such as RIE. It may be formed by removing the Al film in the non-existent region.

Next, as shown in FIG. 16, an etching mask 172 having an opening 172a is formed on the other surface 10b of the substrate 10, and the substrate 10 and the like are removed by dry etching using a fluorine-based gas as the etching gas. As a result, the via hole 160 is formed. The via hole 160 is, for example, a circle having a diameter of 50 μm. Specifically, a seed metal layer (not shown) is formed on the other surface 10b of the substrate 10 by sputtering, a photoresist is applied on the formed seed metal layer, and exposure and development by an exposure apparatus are performed. Do. As a result, a resist pattern (not shown) is formed in the region where the via hole 160 is formed. After that, a Ni film is deposited on the seed metal layer exposed in the region where the resist pattern is not formed by plating, and then the resist pattern (not shown) is removed with an organic solvent or the like to remove the opening. An etching mask 172 having 172a is formed. After that, after removing the seed metal layer exposed in the opening 172a of the etching mask 172, the substrate 10, the electron traveling layer 21, and the electron supply layer 22 in the opening 172a of the etching mask 172 are subjected to dry etching such as RIE. To remove. In this dry etching, a fluorine-based gas, for example, _{a mixed gas of SF 6} and oxygen (O ₂ ) is used as the etching gas, and etching is performed in a state where the first etching stopper layer 151 and the second etching stopper layer 152 are exposed. To stop. As a result, a via hole 160 having a bottom surface 161 in which the central portion 161a serves as the first etching stopper layer 151 and the corner portion 161b serves as the second etching stopper layer 152 is formed.

Next, as shown in FIG. 17, the seed metal layer 171 is formed by sputtering. Specifically, the seed metal layer 171 is formed by forming a Ti / Cu laminated film or a Ta / Cu laminated film on the bottom surface 161 and the side surface 162 of the via hole 160 and the etching mask 172 by sputtering. The Cu on the surface of the seed metal layer 171 formed has a higher ionization tendency than Au forming the second etching stopper layer 152.

Next, as shown in FIG. 18, the back surface electrode 170 is formed by depositing a Cu film on the seed metal layer 171 by plating.

Thereby, the semiconductor device according to the present embodiment can be manufactured.

In the semiconductor device of the present embodiment, the surface of the seed metal layer 171 is formed of Cu, the corner portion 161b of the bottom surface 161 of the via hole 160 is formed of Au, and the second etching stopper layer 152 is formed of Au. Au has a lower ionization tendency than Cu. Therefore, even if there is a gap or the like in the seed metal layer 171 at the corner portion 161b of the bottom surface 161 of the via hole 160, the second etching is performed by the electrolytic solution such as the plating solution that has entered the side of the second etching stopper layer 152. The stopper layer 152 is not eroded.

Therefore, disconnection or the like does not occur in the first etching stopper layer 151 and the second etching stopper layer 152, and the yield of the manufactured semiconductor device can be improved.

[Second Embodiment]
(Semiconductor device)
Next, the semiconductor device according to the second embodiment will be described with reference to FIG. In the semiconductor device of the present embodiment, the second etching stopper layer 252, the seed metal layer 271, and the back surface electrode 270 are formed of Au.

Specifically, in the bottom surface 161 of the via hole 160, the central portion 161a is the first etching stopper layer 151, and the peripheral corner portions 161b are the second etching stopper layer 252. A seed metal layer 271 and a back surface electrode 270 are laminated on the bottom surface 161 and the side surface 162 and the etching mask 172 inside the via hole 160.

In the present embodiment, the seed metal layer 271 is a Ti / Au laminated film in which a Ti film and an Au film are sequentially formed by sputtering, or a Ta / Au laminated film in which a Ta film and an Au film are sequentially formed. Is formed by. Therefore, Au is exposed on the surface of the seed metal layer 271. The second etching stopper layer 252 is formed of Au. In the present embodiment, the second etching stopper layer 252 formed at the corner portion 161b of the bottom surface 161 of the via hole 160 is formed of the same material as the seed metal layer 271, so that the second etching stopper layer 252 is eroded. It prevents being done.

(Manufacturing method of semiconductor device)
Next, the method of manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS. 20 to 25.

First, as shown in FIG. 20, a buffer layer (not shown), an electron traveling layer 21, and an electron supply layer 22 are formed by epitaxially growing a nitride semiconductor layer on one surface 10a of the substrate 10. After that, the gate electrode 31, the source electrode 32, and the drain electrode 33 are formed on the electron supply layer 22.

Next, as shown in FIG. 21, a second etching stopper layer 252 is formed by Au in a predetermined region on the electron supply layer 22. The second etching stopper layer 252 is formed at a portion corresponding to the corner portion 161b of the bottom surface 161 of the via hole 160, and is formed in an annular shape having an inner diameter of 30 μm and an outer diameter of 90 μm, for example. The second etching stopper layer 252 formed in this manner is formed at a portion corresponding to the corner portion 161b of the bottom surface 161 of the via hole 160, and the portion corresponding to the central portion 161a of the bottom surface 161 of the via hole 160 is opened. There is. The second etching stopper layer 252 has a film thickness of 100 nm or more and 1 μm or less.

Next, as shown in FIG. 22, on the electron supply layer 22 surrounded by the second etching stopper layer 252 and on the second etching stopper layer 252 around the electron supply layer 252, the first etching stopper layer 252 is formed by Al or the like. The etching stopper layer 151 is formed.

Next, as shown in FIG. 23, an etching mask 172 having an opening 172a is formed on the other surface 10b of the substrate 10, and the substrate 10 and the like are removed by dry etching using a fluorine-based gas as the etching gas. As a result, the via hole 160 is formed. As a result, a via hole 160 having a bottom surface 161 in which the central portion 161a serves as the first etching stopper layer 151 and the corner portion 161b serves as the second etching stopper layer 252 is formed.

Next, as shown in FIG. 24, the seed metal layer 271 is formed by sputtering. Specifically, the seed metal layer 271 is formed by forming a Ti / Au laminated film or a Ta / Au laminated film on the bottom surface 161 and the side surface 162 of the via hole 160 and the etching mask 172 by sputtering. The surface of the seed metal layer 271 is formed of the same Au as the second etching stopper layer 252, and has the same ionization tendency.

Next, as shown in FIG. 25, the back electrode 270 is formed by depositing an Au film on the seed metal layer 271 by plating.

Thereby, the semiconductor device according to the present embodiment can be manufactured.

In the semiconductor device of the present embodiment, the surface of the seed metal layer 271 has the corner portion 161b of the bottom surface 161 of the via hole 160 formed of the same Au as the second etching stopper layer 252, and the ionization tendency is also the same. Therefore, even if there is a gap or the like in the seed metal layer 271 at the corner portion 161b of the bottom surface 161 of the via hole 160, the second etching is performed by the electrolytic solution such as the plating solution that has entered the side of the second etching stopper layer 252. The stopper layer 252 is not eroded.

Therefore, disconnection or the like does not occur in the first etching stopper layer 151 and the second etching stopper layer 252, and the yield of the manufactured semiconductor device can be improved.

The contents other than the above are the same as those in the first embodiment.

[Third Embodiment]
(Semiconductor device)
Next, the semiconductor device according to the third embodiment will be described with reference to FIG. In the semiconductor device of the present embodiment, the second etching stopper layer 352, the seed metal layer 371, and the back surface electrode 370 are formed of Cu.

Specifically, in the bottom surface 161 of the via hole 160, the central portion 161a is the first etching stopper layer 151, and the peripheral corner portions 161b are the second etching stopper layer 352. A seed metal layer 371 and a back surface electrode 370 are laminated on the bottom surface 161 and the side surface 162 and the etching mask 172 inside the via hole 160.

In the present embodiment, the seed metal layer 371 is formed of a Ti / Cu laminated film in which a Ti film and a Cu film are sequentially formed by sputtering, or a Ta / Cu laminated film in which a Ta film and a Cu film are sequentially formed. Has been done. Therefore, Cu is exposed on the surface of the seed metal layer 371. Further, the second etching stopper layer 352 is formed of Cu. In the present embodiment, the second etching stopper layer 352 is eroded by forming the second etching stopper layer 352 formed on the corner portion 161b of the bottom surface 161 of the via hole 160 with the same material as the seed metal layer 371. It prevents being done.

(Manufacturing method of semiconductor device)
Next, the method of manufacturing the semiconductor device according to the third embodiment will be described with reference to FIGS. 27 to 32.

First, as shown in FIG. 27, a buffer layer (not shown), an electron traveling layer 21, and an electron supply layer 22 are formed by epitaxially growing a nitride semiconductor layer on one surface 10a of the substrate 10. After that, the gate electrode 31, the source electrode 32, and the drain electrode 33 are formed on the electron supply layer 22.

Next, as shown in FIG. 28, a second etching stopper layer 352 is formed by Cu in a predetermined region on the electron supply layer 22. The second etching stopper layer 352 is formed at a portion corresponding to the corner portion 161b of the bottom surface 161 of the via hole 160, and is formed in an annular shape having an inner diameter of 30 μm and an outer diameter of 90 μm, for example. The second etching stopper layer 352 formed in this manner is formed at a portion corresponding to the corner portion 161b of the bottom surface 161 of the via hole 160, and the portion corresponding to the central portion 161a of the bottom surface 161 of the via hole 160 is opened. There is. The second etching stopper layer 352 has a film thickness of 100 nm or more and 1 μm or less.

Next, as shown in FIG. 29, on the electron supply layer 22 surrounded by the second etching stopper layer 352 and on the second etching stopper layer 352 around the electron supply layer 352, a first surface is formed by Al or the like. The etching stopper layer 151 is formed.

Next, as shown in FIG. 30, an etching mask 172 having an opening 172a is formed on the other surface 10b of the substrate 10, and the substrate 10 and the like are removed by dry etching using a fluorine-based gas as the etching gas. As a result, the via hole 160 is formed. As a result, a via hole 160 having a bottom surface 161 in which the central portion 161a serves as the first etching stopper layer 151 and the corner portion 161b serves as the second etching stopper layer 352 is formed.

Next, as shown in FIG. 31, the seed metal layer 371 is formed by sputtering. Specifically, the seed metal layer 371 is formed by forming a Ti / Cu laminated film or a Ta / Cu laminated film on the bottom surface 161 and the side surface 162 of the via hole 160 and the etching mask 172 by sputtering. The surface of the seed metal layer 371 is formed of the same Cu as the second etching stopper layer 352, and has the same ionization tendency.

Next, as shown in FIG. 32, the back surface electrode 370 is formed by depositing a Cu film on the seed metal layer 371 by plating.

Thereby, the semiconductor device according to the present embodiment can be manufactured.

In the semiconductor device of the present embodiment, the surface of the seed metal layer 371 has the corner portion 161b of the bottom surface 161 of the via hole 160 formed of the same Cu as the second etching stopper layer 352, and the ionization tendency is also the same. Therefore, even if there is a gap or the like in the seed metal layer 371 at the corner portion 161b of the bottom surface 161 of the via hole 160, the second etching is performed by the electrolytic solution such as the plating solution that has entered the side of the second etching stopper layer 352. The stopper layer 352 is not eroded.

Therefore, disconnection or the like does not occur in the first etching stopper layer 151 and the second etching stopper layer 352, and the yield of the manufactured semiconductor device can be improved.

The contents other than the above are the same as those in the first embodiment.

[Fourth Embodiment]
(Semiconductor device)
Next, the semiconductor device according to the fourth embodiment will be described with reference to FIG. 33. In the semiconductor device of the present embodiment, the second etching stopper layer 452 is formed of an insulator.

Specifically, in the bottom surface 161 of the via hole 160, the central portion 161a is the first etching stopper layer 151, and the peripheral corner portions 161b are the second etching stopper layer 452. A seed metal layer 171 and a back surface electrode 170 are laminated on the bottom surface 161 and the side surface 162 and the etching mask 172 inside the via hole 160.

In the present embodiment, the seed metal layer 171 is formed of a Ti / Cu laminated film in which a Ti film and a Cu film are sequentially formed by sputtering, or a Ta / Cu laminated film in which a Ta film and a Cu film are sequentially formed. Has been done. Therefore, Cu is exposed on the surface of the seed metal layer 171. Since the second etching stopper layer 452 is formed of an insulator of an oxide such as nickel oxide (NiO) or aluminum oxide (AlO), the second etching stopper layer 452 is not eroded.

(Manufacturing method of semiconductor device)
Next, the method of manufacturing the semiconductor device according to the fourth embodiment will be described with reference to FIGS. 34 to 39.

First, as shown in FIG. 34, a buffer layer (not shown), an electron traveling layer 21, and an electron supply layer 22 are formed by epitaxially growing a nitride semiconductor layer on one surface 10a of the substrate 10. After that, the gate electrode 31, the source electrode 32, and the drain electrode 33 are formed on the electron supply layer 22.

Next, as shown in FIG. 35, a second etching stopper layer 452 is formed in a predetermined region above the electron supply layer 22. The second etching stopper layer 452 is formed at a portion corresponding to the corner portion 161b of the bottom surface 161 of the via hole 160, and is formed in an annular shape having an inner diameter of 30 μm and an outer diameter of 90 μm, for example. Specifically, an aluminum oxide film is formed on the electron supply layer 22 by sputtering, ALD (Atomic Layer Deposition), or the like, and a photoresist is further applied on the formed aluminum oxide film for exposure. Exposure and development by the device. As a result, a resist pattern (not shown) is formed in the region where the second etching stopper layer 452 is formed. After that, the aluminum oxide film in the region where the strike pattern is not formed is removed by dry etching such as RIE, ion milling, or wet etching using an alkaline solution. After that, by removing the resist pattern (not shown) with an organic solvent or the like, the second etching stopper layer 452 is formed by the remaining aluminum oxide film. The second etching stopper layer 452 formed in this way is formed in an annular shape at a portion corresponding to the corner portion 161b of the bottom surface 161 of the via hole 160, and is a portion corresponding to the central portion 161a of the bottom surface 161 of the via hole 160. Is open. The second etching stopper layer 452 has a film thickness of 100 nm or more and 1 μm or less, and then heat treatment is performed at a temperature of 600 ° C. or higher to enhance resistance in subsequent dry etching.

Next, as shown in FIG. 36, the first etching stopper layer is placed on the second etching stopper layer 452 and on the electron supply layer 22 surrounded by the second etching stopper layer 452 around the second etching stopper layer 452. Form 151.

Next, as shown in FIG. 37, an etching mask 172 having an opening 172a is formed on the other surface 10b of the substrate 10, and the substrate 10 and the like are removed by dry etching using a fluorine-based gas as the etching gas. As a result, the via hole 160 is formed. As a result, a via hole 160 having a bottom surface 161 in which the central portion 161a serves as the first etching stopper layer 151 and the corner portion 161b serves as the second etching stopper layer 452 is formed.

Next, as shown in FIG. 38, the seed metal layer 171 is formed by sputtering.

Next, as shown in FIG. 39, the back surface electrode 170 is formed by depositing a Cu film on the seed metal layer 171 by plating.

Thereby, the semiconductor device according to the present embodiment can be manufactured.

In the semiconductor device of the present embodiment, the second etching stopper layer 452 is formed of an insulator such as aluminum oxide. Therefore, even if a gap or the like is formed in the seed metal layer 171 at the corner portion 161b of the bottom surface 161 of the via hole 160, the second etching stopper layer 452 is not eroded by the electrolytic solution such as the plating solution.

Therefore, disconnection or the like does not occur in the first etching stopper layer 151, and the yield of the manufactured semiconductor device can be improved.

The contents other than the above are the same as those in the first embodiment.

Although the embodiments have been described in detail above, the embodiments are not limited to the specific embodiments, and various modifications and changes can be made within the scope of the claims.

Regarding the above explanation, the following additional notes will be further disclosed.
(Appendix 1)
A semiconductor layer provided on one surface of the substrate and
A first etching stopper layer and a second etching stopper layer provided on the semiconductor layer,
A via hole that penetrates the substrate and the semiconductor layer from the other surface of the substrate and has the first etching stopper layer and the second etching stopper layer as the bottom surfaces.
The seed metal layer formed on the bottom surface and the side surface inside the via hole,
A back electrode formed by plating on the seed metal layer,
Have,
The bottom surface of the via hole has a central portion formed by the first etching stopper layer and a corner portion formed by the second etching stopper layer.
A semiconductor device characterized in that the seed metal layer and the second etching stopper layer have the same ionization tendency, or the second etching stopper layer has a lower ionization tendency than the seed metal layer.
(Appendix 2)
The semiconductor device according to Appendix 1, wherein the second etching stopper layer has a lower ionization tendency than the seed metal layer.
(Appendix 3)
The semiconductor device according to Appendix 2, wherein the seed metal layer is made of copper, and the second etching stopper layer is made of gold.
(Appendix 4)
The semiconductor device according to Appendix 2, wherein the seed metal layer and the second etching stopper layer are made of the same material.
(Appendix 5)
The semiconductor device according to Appendix 4, wherein the seed metal layer and the second etching stopper layer are formed of gold or copper.
(Appendix 6)
A semiconductor layer provided on one surface of the substrate and
A first etching stopper layer and a second etching stopper layer provided on the semiconductor layer,
A via hole that penetrates the substrate and the semiconductor layer from the other surface of the substrate and has the first etching stopper layer and the second etching stopper layer as the bottom surfaces.
The seed metal layer formed on the bottom surface and the side surface inside the via hole,
A back electrode formed by plating on the seed metal layer,
Have,
The bottom surface of the via hole has a central portion formed by the first etching stopper layer and a corner portion formed by the second etching stopper layer.
The second etching stopper layer is a semiconductor device characterized in that it is formed of an insulating film.
(Appendix 7)
The semiconductor device according to Appendix 6, wherein the second etching stopper layer is formed of nickel oxide or aluminum oxide.
(Appendix 8)
The semiconductor device according to any one of Supplementary note 1 to 7, wherein the second etching stopper layer is formed of nickel or aluminum.
(Appendix 9)
The semiconductor device according to any one of Supplementary note 1 to 8, wherein the semiconductor layer is a nitride semiconductor layer.
(Appendix 10)
The nitride semiconductor layer is
An electronic traveling layer formed on one surface of the substrate and
An electron supply layer formed on the electron traveling layer and
The semiconductor device according to Appendix 9, wherein the semiconductor device has a gate electrode, a source electrode, and a drain electrode formed on the electron supply layer.
(Appendix 11)
The semiconductor device according to Appendix 10, wherein the electron traveling layer is formed of GaN.
(Appendix 12)
The semiconductor device according to any one of Supplementary note 1 to 11, wherein the substrate is a SiC substrate.
(Appendix 13)
The process of forming a semiconductor layer on one surface of the substrate,
A step of forming a second etching stopper layer on the semiconductor layer and
A step of forming a first etching stopper layer on the semiconductor layer and the second etching stopper layer, and
A step of penetrating the substrate and the semiconductor layer from the other surface of the substrate to form a via hole having the first etching stopper layer and the second etching stopper layer as bottom surfaces.
A step of forming a seed metal layer on the bottom surface and the side surface inside the via hole, and
A step of forming a back electrode by plating on the seed metal layer, and
Have,
The bottom surface of the via hole has a central portion formed by the first etching stopper layer and a corner portion formed by the second etching stopper layer.
The seed metal layer and the second etching stopper layer have the same ionization tendency, or the second etching stopper layer has a lower ionization tendency than the seed metal layer. Production method.
(Appendix 14)
The method for manufacturing a semiconductor device according to Appendix 13, wherein the seed metal layer is formed of copper, and the second etching stopper layer is formed of gold.
(Appendix 15)
The method for manufacturing a semiconductor device according to Appendix 13, wherein the seed metal layer and the second etching stopper layer are made of the same material.
(Appendix 16)
The method for manufacturing a semiconductor device according to Appendix 15, wherein the seed metal layer and the second etching stopper layer are formed of gold or copper.
(Appendix 17)
The process of forming a semiconductor layer on one surface of the substrate,
A step of forming a second etching stopper layer on the semiconductor layer and
A step of forming a first etching stopper layer on the semiconductor layer and the second etching stopper layer, and
A step of penetrating the substrate and the semiconductor layer from the other surface of the substrate to form a via hole having the first etching stopper layer and the second etching stopper layer as bottom surfaces.
A step of forming a seed metal layer on the bottom surface and the side surface inside the via hole, and
A step of forming a back electrode by plating on the seed metal layer, and
Have,
The bottom surface of the via hole has a central portion formed by the first etching stopper layer and a corner portion formed by the second etching stopper layer.
A method for manufacturing a semiconductor device, wherein the second etching stopper layer is formed of an insulating film.
(Appendix 18)
The method for manufacturing a semiconductor device according to Appendix 17, wherein the second etching stopper layer is formed of nickel oxide or aluminum oxide.
(Appendix 19)
The method for manufacturing a semiconductor device according to any one of Supplementary note 13 to 18, wherein the first etching stopper layer is formed of nickel or aluminum.
(Appendix 20)
The method for manufacturing a semiconductor device according to any one of Appendix 13 to 19, wherein the semiconductor layer is a nitride semiconductor layer.

10 Substrate 10a One surface 10b The other surface 21 Electron traveling layer 21a 2DEG
22 Electronic supply layer 31 Gate electrode 32 Source electrode 33 Drain electrode 51 Wiring 151 First etching stopper layer 152 Second etching stopper layer 160 Via hole 161 Bottom surface of via hole 161a Central part of bottom surface of via hole 161b Corner part 162 of bottom surface of via hole Side side of via hole 170 Back side electrode 171 Seed metal layer 172 Etching mask

Claims (10)

A semiconductor layer provided on one surface of the substrate and
A first etching stopper layer and a second etching stopper layer provided on the semiconductor layer,
A via hole that penetrates the substrate and the semiconductor layer from the other surface of the substrate and has the first etching stopper layer and the second etching stopper layer as the bottom surfaces.
The seed metal layer formed on the bottom surface and the side surface inside the via hole,
A back electrode formed by plating on the seed metal layer,
Have,
The bottom surface of the via hole has a central portion formed by the first etching stopper layer and a corner portion formed by the second etching stopper layer.
A semiconductor device characterized in that the seed metal layer and the second etching stopper layer have the same ionization tendency, or the second etching stopper layer has a lower ionization tendency than the seed metal layer. The semiconductor device according to claim 1, wherein the seed metal layer is formed of copper, and the second etching stopper layer is formed of gold. The semiconductor device according to claim 1, wherein the seed metal layer and the second etching stopper layer are made of the same material. A semiconductor layer provided on one surface of the substrate and
A first etching stopper layer and a second etching stopper layer provided on the semiconductor layer,
A via hole that penetrates the substrate and the semiconductor layer from the other surface of the substrate and has the first etching stopper layer and the second etching stopper layer as the bottom surfaces.
The seed metal layer formed on the bottom surface and the side surface inside the via hole,
A back electrode formed by plating on the seed metal layer,
Have,
The bottom surface of the via hole has a central portion formed by the first etching stopper layer and a corner portion formed by the second etching stopper layer.
The second etching stopper layer is a semiconductor device characterized in that it is formed of an insulating film. The semiconductor device according to claim 4, wherein the second etching stopper layer is formed of nickel oxide or aluminum oxide. The semiconductor device according to any one of claims 1 to 5, wherein the second etching stopper layer is formed of nickel or aluminum. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor layer is a nitride semiconductor layer. The nitride semiconductor layer is
An electronic traveling layer formed on one surface of the substrate and
An electron supply layer formed on the electron traveling layer and
The semiconductor device according to claim 7, further comprising a gate electrode, a source electrode, and a drain electrode formed on the electron supply layer. The process of forming a semiconductor layer on one surface of the substrate,
A step of forming a second etching stopper layer on the semiconductor layer and
A step of forming a first etching stopper layer on the semiconductor layer and the second etching stopper layer, and
A step of penetrating the substrate and the semiconductor layer from the other surface of the substrate to form a via hole having the first etching stopper layer and the second etching stopper layer as bottom surfaces.
A step of forming a seed metal layer on the bottom surface and the side surface inside the via hole, and
A step of forming a back electrode by plating on the seed metal layer, and
Have,
The bottom surface of the via hole has a central portion formed by the first etching stopper layer and a corner portion formed by the second etching stopper layer.
The seed metal layer and the second etching stopper layer have the same ionization tendency, or the second etching stopper layer has a lower ionization tendency than the seed metal layer. Production method. The process of forming a semiconductor layer on one surface of the substrate,
A step of forming a second etching stopper layer on the semiconductor layer and
A step of forming a first etching stopper layer on the semiconductor layer and the second etching stopper layer, and
A step of penetrating the substrate and the semiconductor layer from the other surface of the substrate to form a via hole having the first etching stopper layer and the second etching stopper layer as bottom surfaces.
A step of forming a seed metal layer on the bottom surface and the side surface inside the via hole, and
A step of forming a back electrode by plating on the seed metal layer, and
Have,
The bottom surface of the via hole has a central portion formed by the first etching stopper layer and a corner portion formed by the second etching stopper layer.
A method for manufacturing a semiconductor device, wherein the second etching stopper layer is formed of an insulating film.

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