JP2021012940A - Manufacturing method of semiconductor device - Google Patents

Abstract

To accurately form an end of a resist layer on an upper part of a trench.SOLUTION: A manufacturing method of a semiconductor device comprises the steps of: forming a first polysilicon layer within a trench and on an upper surface of a substrate; forming a second polysilicon layer on an upper surface of the first polysilicon layer; etching the polysilicon layer from an upper side by an etching method in which an etching rate for the second polysilicon layer is slower than an etching rate for the first polysilicon layer; forming a resist layer such that an end of the resist layer is positioned at an upper part of the trench; implanting impurities into the semiconductor substrate using the resist layer as a mask; removing the resist layer; and etching the polysilicon layer after removing the resist layer to leave the polysilicon layer within the trench.SELECTED DRAWING: Figure 10

Description

The techniques disclosed herein relate to methods of manufacturing semiconductor devices.

Patent Document 1 discloses a semiconductor device including an IGBT region and a diode region. A trench extends along the boundary between the IGBT region and the diode region. A gate insulating film and a gate electrode are arranged in the trench at the boundary. The IGBT region is provided with an n-type emitter region, a p-type body contact region, a p-type body region, and the like. A p-type anode region or the like is provided in the diode region. That is, the structure is different between the adjacent IGBT region and the diode region via the trench at the boundary.

JP-A-2017-135339

Figures 15-18 show how to form different structures in two adjacent regions via a trench. FIG. 15 shows a substrate 112 having a trench 150 and a gate insulating film 154. The substrate 112 has two regions 120, 122 adjacent to each other via a trench 150. In this method, first, as shown in FIG. 16, the polysilicon layer 152 is grown in the trench 150 and in the upper surface 112a of the substrate 112. At this time, the trench 150 is embedded with the polysilicon layer 152. When the polysilicon layer 152 is grown in this way, a recess 152a is formed on the upper surface of the polysilicon layer 152 at the upper part of the trench 150. Next, as shown in FIG. 17, the polysilicon layer 152 on the upper surface 112a of the substrate 112 is removed by etching the polysilicon layer 152 from above. The polysilicon layer 152 remains in the trench 150. The polysilicon layer 152 remaining in the trench 150 serves as a gate electrode. When the polysilicon layer 152 is etched in the trench 150, the etching rate is higher in the vicinity of the side surface of the trench 150 than in the vicinity of the central portion of the trench 150. Therefore, as shown in FIG. 17, the protrusion 152b is formed in the central portion of the upper surface of the polysilicon layer 152 remaining in the trench 150. Next, the resist layer 160 is formed as shown in FIG. Here, the resist layer 160 is formed so as to cover the region 120 and not cover the region 122. Next, the diffusion region 130 is formed inside the substrate 112 by injecting an n-type or p-type impurity into the region 122 not covered by the resist layer 160. The diffusion region 130 is not formed in the region 120 covered with the resist layer 160. Therefore, a structure different from that of the region 120 can be formed in the region 122.

However, in this method, as shown in FIG. 18, it is necessary to form the resist layer 160 so that the end 160a of the resist layer 160 is located above the trench 150 (that is, on the upper surface of the polysilicon layer 152). .. However, since the protrusion 152b is present on the upper surface of the polysilicon layer 152, the shape of the end portion 160a of the resist layer 160 is not stable. As a result, the injection range of impurities cannot be accurately controlled.

It is also conceivable to form a resist layer 160 on the top of the polysilicon layer 152 and inject impurities as shown in FIG. 19 before etching the polysilicon layer 152. However, in this case, since the recess 152a exists in the upper part of the trench 150 (the upper surface of the polysilicon layer 152), the shape of the end portion 160a of the resist layer 160 is not stable. Even with this method, the injection range of impurities cannot be accurately controlled.

This specification proposes a technique capable of accurately controlling the injection range of impurities by accurately forming the end portion of the resist layer on the upper part of the trench.

The method for manufacturing a semiconductor device disclosed in the present specification includes the first to eighth steps. In the first step, a semiconductor substrate, a trench provided on the upper surface of the semiconductor substrate, and a substrate having a gate insulating film arranged in the trench are prepared. In the second step, a first polysilicon layer made of polysilicon containing a p-type impurity is formed in the trench and on the upper surface of the substrate. In the second step, the trench is embedded with the first polysilicon layer. In the third step, a second polysilicon layer having a concentration of p-type impurities lower than that of the first polysilicon layer is formed on the upper surface of the first polysilicon layer. In the fourth step, the polysilicon layer composed of the first polysilicon layer and the second polysilicon layer is formed by an etching method in which the etching rate for the second polysilicon layer is slower than the etching rate for the first polysilicon layer. Etch from above. In the fourth step, the polysilicon layer is etched below the upper surface of the first polysilicon layer before etching and above the upper surface of the substrate. In the fifth step, a resist layer is formed on the upper surface of the polysilicon layer remaining after etching. In the fifth step, the resist layer is formed so that the end portion of the resist layer is located at the upper part of the trench. In the sixth step, impurities are injected into the semiconductor substrate using the resist layer as a mask. In the seventh step, the resist layer is removed. In the eighth step, after removing the resist layer, the polysilicon layer is etched to remove the polysilicon layer on the upper surface of the substrate and leave the polysilicon layer in the trench.

In this manufacturing method, first, a first polysilicon layer is formed so as to embed a trench. At this time, a recess is formed in the upper part of the first polysilicon layer in the upper part of the trench. Then, a second polysilicon layer is further formed on the upper surface of the first polysilicon layer. Therefore, a second polysilicon layer is formed in the recess. Next, the polysilicon layer composed of the first polysilicon layer and the second polysilicon layer is etched from above by an etching method in which the etching rate for the second polysilicon layer is slower than the etching rate for the first polysilicon layer. Here, the polysilicon layer is etched below the upper surface of the first polysilicon layer before etching. When the etching reaches the upper surface of the first polysilicon layer, the second polysilicon layer remains in the recess. That is, the second polysilicon layer remains on the upper part of the trench, and the first polysilicon layer is exposed in the region adjacent to the trench. If the etching proceeds further in this state, the etching rate for the second polysilicon layer is slower than the etching rate for the first polysilicon layer, so that the etching rate of the polysilicon layer is locally slowed at the upper part of the trench. Therefore, the recesses on the surface of the polysilicon layer are flattened. Here, the polysilicon layer is etched to the upper side of the upper surface of the substrate. That is, the polysilicon layer is left on the upper surface of the substrate. Next, a resist layer is formed on the upper surface of the polysilicon layer. Since the upper surface of the polysilicon layer on the upper part of the trench is flattened, the end portion of the resist layer can be formed with high accuracy. Then, by injecting impurities into the semiconductor substrate using the resist layer as a mask, a diffusion region is formed in one region adjacent to the trench. After that, the resist layer is removed, and the polysilicon layer is etched so that the polysilicon layer remains in the trench, thereby completing the trench-type gate electrode. As described above, according to this manufacturing method, the resist layer can be formed with high accuracy, and impurities can be accurately injected into one region adjacent to the trench. Therefore, the diffusion region can be formed accurately.

Partial sectional view of the semiconductor device manufactured by the manufacturing method of an embodiment. FIG. 3 is a partial cross-sectional view of a semiconductor device manufactured by the manufacturing method of the embodiment. The explanatory view of the manufacturing method of an embodiment. The explanatory view of the manufacturing method of an embodiment. The explanatory view of the manufacturing method of an embodiment. The explanatory view of the manufacturing method of an embodiment. The explanatory view of the manufacturing method of an embodiment. The explanatory view of the manufacturing method of an embodiment. The explanatory view of the manufacturing method of an embodiment. The explanatory view of the manufacturing method of an embodiment. The explanatory view of the manufacturing method of an embodiment. The explanatory view of the manufacturing method of an embodiment. The explanatory view of the manufacturing method of an embodiment. The explanatory view of the manufacturing method of an embodiment. Explanatory drawing of the conventional manufacturing method. Explanatory drawing of the conventional manufacturing method. Explanatory drawing of the conventional manufacturing method. Explanatory drawing of the conventional manufacturing method. Explanatory drawing of the conventional manufacturing method.

FIGS. 1 and 2 show a semiconductor device 10 manufactured by the manufacturing method of the embodiment. As shown in FIG. 2, the semiconductor device 10 has a semiconductor substrate 12, an upper electrode 14, a lower electrode 16, a gate electrode 20, a gate insulating film 22, and an interlayer insulating film 24. In FIG. 1, the upper electrode 14 and the interlayer insulating film 24 are not shown. The semiconductor substrate 12 is made of silicon. A plurality of trenches 26 are provided on the upper surface 12a of the semiconductor substrate 12. As shown in FIG. 1, each trench 26 extends linearly in the y direction on the upper surface 12a. The plurality of trenches 26 are arranged at intervals in the x direction. The inner surface of each trench 26 is covered with a gate insulating film 22. A gate electrode 20 is arranged in each trench 26. The gate electrode 20 is insulated from the semiconductor substrate 12 by the gate insulating film 22. The upper surface of the gate electrode 20 is covered with an interlayer insulating film 24. The upper electrode 14 covers the surface of the interlayer insulating film 24 and the upper surface 12a of the semiconductor substrate 12 in a range not covered by the interlayer insulating film 24. The upper electrode 14 is insulated from the gate electrode 20 by an interlayer insulating film 24. The lower electrode 16 covers the entire lower surface 12b of the semiconductor substrate 12.

The semiconductor substrate 12 has an IGBT region 90 in which an IGBT (insulated gate bipolar transistor) is formed and a diode region 92 in which a diode is formed. One of the plurality of trenches 26 described above (hereinafter referred to as a boundary trench 26a) extends along the boundary between the IGBT region 90 and the diode region 92. That is, the IGBT region 90 and the diode region 92 are partitioned by the boundary trench 26a.

The IGBT region 90 has an emitter region 30, a body contact region 32, a top body region 34, a separation region 36, a bottom body region 38, a drift region 40, a buffer region 41, and a collector region 42.

The emitter region 30 and the body contact region 32 are arranged in a range exposed on the upper surface 12a of the semiconductor substrate 12. The emitter region 30 is n-shaped and is in ohmic contact with the upper electrode 14. The emitter region 30 is in contact with the gate insulating film 22. The body contact region 32 is p-shaped and is in ohmic contact with the upper electrode 14. The body contact region 32 is in contact with the gate insulating film 22.

The top body region 34 is p-type and has a lower p-type impurity concentration than the body contact region 32. The top body region 34 is in contact with the emitter region 30 and the body contact region 32 from below. The top body region 34 is in contact with the gate insulating film 22 below the emitter region 30 and the body contact region 32.

The separation region 36 is n-shaped and is in contact with the top body region 34 from below. The separation region 36 is in contact with the gate insulating film 22 below the top body region 34.

The bottom body region 38 is p-type and has a lower p-type impurity concentration than the body contact region 32. The bottom body region 38 is in contact with the separation region 36 from below. The bottom body region 38 is in contact with the gate insulating film 22 below the separation region 36.

The drift region 40 is n-type and has an n-type impurity concentration lower than that of the emitter region 30. The drift region 40 is in contact with the bottom body region 38 from below. The drift region 40 is in contact with the gate insulating film 22 below the bottom body region 38.

The buffer region 41 is n-type and has an n-type impurity concentration higher than that of the drift region 40. The buffer area 41 is in contact with the drift area 40 from below.

The collector area 42 is p-type and is in contact with the buffer area 41 from below. The collector region 42 is in ohmic contact with the lower electrode 16.

Within the IGBT region 90, there are an emitter region 30, a body contact region 32, a top body region 34, a separation region 36, a bottom body region 38, a drift region 40, a buffer region 41, a collector region 42, a gate electrode 20, and gate insulation. The IGBT is formed by the film 22 and the like. In a state where the potential of the lower electrode 16 is higher than the potential of the upper electrode 14, when the potential of the gate electrode 20 becomes higher than the threshold, the IGBT is turned on and a current flows from the lower electrode 16 to the upper electrode 14.

The diode region 92 has an anode contact region 50, a top anode region 52, a separation region 54, a bottom anode region 56, a drift region 58, a buffer region 59, and a cathode region 60.

The anode contact region 50 is arranged in a range exposed on the upper surface 12a of the semiconductor substrate 12. The anode contact region 50 is p-shaped and is in ohmic contact with the upper electrode 14.

The top anode region 52 is p-type and has a lower p-type impurity concentration than the anode contact region 50. Further, the top anode region 52 has a lower p-type impurity concentration than the top body region 34. The top anode region 52 is in contact with the anode contact region 50 from below.

The separation region 54 is n-type and is in contact with the top anode region 52 from below.

The bottom anode region 56 is p-type and has a lower p-type impurity concentration than the anode contact region 50. The bottom anode region 56 is in contact with the separation region 54 from below.

The drift region 58 in the diode region 92 is a region continuous with the drift region 40 in the IGBT region 90. The drift region 58 is n-shaped and is in contact with the bottom anode region 56 from below.

The buffer region 59 in the diode region 92 is a region continuous with the buffer region 41 in the IGBT region 90. The buffer region 59 is n-type and has an n-type impurity concentration higher than that of the drift region 58. The buffer area 59 is in contact with the drift area 58 from below.

The cathode region 60 is n-type and has an n-type impurity concentration higher than that of the buffer region 59. The cathode region 60 is in contact with the buffer region 59 from below. The cathode region 60 is in ohmic contact with the lower electrode 16.

In the diode region 92, a diode is formed by an anode contact region 50, a top anode region 52, a separation region 54, a bottom anode region 56, a drift region 58, a buffer region 59, a cathode region 60, and the like. When the potential of the upper electrode 14 becomes higher than the potential of the lower electrode 16, the diode is turned on and a current flows from the upper electrode 14 to the lower electrode 16.

Next, a method of manufacturing the semiconductor device 10 will be described. The semiconductor device 10 is manufactured from the semiconductor substrate 12 before processing shown in FIG. The semiconductor substrate 12 before processing has the same n-type impurity concentration as the drift regions 40 and 58.

First, as shown in FIG. 4, a plurality of trenches 26 are formed on the upper surface 12a by selectively etching the upper surface 12a of the semiconductor substrate 12. In FIG. 4, the central trench 26 is the boundary trench 26a.

Next, as shown in FIG. 5, the gate insulating film 22 is formed so as to cover the upper surface 12a and the inner surface of the trench 26 by oxidizing the surface of the semiconductor substrate 12. In the following, the semiconductor substrate 12 and the gate insulating film 22 are collectively referred to as a substrate 70. The upper surface of the substrate 70 (that is, the upper surface of the gate insulating film 22) is referred to as the upper surface 70a.

Next, as shown in FIG. 6, the first polysilicon layer 71 is formed on the upper surface 70a of the substrate 70 and the inner surface of the trench 26 (that is, the surface of the gate insulating film 22 in the trench 26) by CVD (chemical vapor deposition). Grow. The first polysilicon layer 71 is made of polysilicon doped with p-type impurities. The trench 26 is embedded by the first polysilicon layer 71. A recess 71a is formed on the upper surface of the first polysilicon layer 71 above the trench 26.

Next, as shown in FIG. 7, the second polysilicon layer 72 is grown on the upper surface of the first polysilicon layer 71 by CVD. The second polysilicon layer 72 is composed of non-doped polysilicon (polysilicon containing no p-type impurities and n-type impurities). Therefore, the concentration of p-type impurities contained in the second polysilicon layer 72 is lower than the concentration of p-type impurities contained in the first polysilicon layer 71. The recess 71a is embedded by the second polysilicon layer 72. A minute recess 72a is formed on the upper surface of the second polysilicon layer 72. Hereinafter, the first polysilicon layer 71 and the second polysilicon layer 72 are collectively referred to as a polysilicon layer 74.

Next, the polysilicon layer 74 is wet-etched from the upper surface side. Here, the polysilicon layer 74 is etched with an etching solution in which the etching rate for the second polysilicon layer 72 is slower than the etching rate for the first polysilicon layer 71. Here, the polysilicon layer 74 is etched below the upper surface of the first polysilicon layer 71 before etching (that is, until the first polysilicon layer 71 is exposed). Then, as shown in FIG. 8, the first polysilicon layer 71 is exposed in the portion other than the recess 71a. The second polysilicon layer 72 remains in the recess 71a. At this stage, a recess is present on the upper surface of the polysilicon layer 74 along the recess 71a. Etching is further advanced from the state shown in FIG. Then, since the etching rate for the second polysilicon layer 72 is slower than the etching rate for the first polysilicon layer 71, the etching rate is locally slowed down in the upper part of the trench 26. As a result, as shown in FIG. 9, the recess disappears from the upper surface of the polysilicon layer 74, and the upper surface of the polysilicon layer 74 becomes substantially flat. Here, as shown in FIG. 9, the etching of the polysilicon layer 74 is stopped above the upper surface 70a of the substrate 70. That is, the polysilicon layer 74 remains on the upper surface 70a. In this step, the second polysilicon layer 72 may be removed from the polysilicon layer 74, or the second polysilicon layer 72 may remain in a part of the polysilicon layer 74 (the upper part of the trench 26). Good.

Next, as shown in FIG. 10, a resist layer 76 is formed on the polysilicon layer 74 so as to cover the diode region 92 by photolithography. Here, the resist layer 76 is formed so that the end portion 76a of the resist layer 76 is located above the boundary trench 26a. Since the upper surface of the polysilicon layer 74 is flat at the upper part of the boundary trench 26a, the end portion 76a of the resist layer 76 can be formed into an accurate shape. Next, as shown in FIG. 11, n-type and p-type impurities are injected into the IGBT region 90 using the resist layer 76 as a mask. As a result, the top body region 34, the separation region 36, and the bottom body region 38 are formed in the IGBT region 90. Since the polysilicon layer 74 on the substrate 70 is thinned by etching, the distance between the resist layer 76 and the substrate 70 is short. Further, as described above, the end portion 76a of the resist layer 76 is formed in an accurate shape. Therefore, impurities can be accurately injected into the IGBT region 90. Therefore, the top body region 34, the separation region 36, and the bottom body region 38 can be accurately formed. After forming the top body region 34, the separation region 36, and the bottom body region 38, the resist layer 76 is removed. Next, the emitter region 30 and the body contact region 32 are formed by injecting impurities into the IGBT region 90 using a resist layer having a patterned opening.

Next, as shown in FIG. 12, a resist layer 78 is formed on the polysilicon layer 74 so as to cover the IGBT region 90 by photolithography. Here, the resist layer 78 is formed so that the end 78a of the resist layer 78 is located above the boundary trench 26a. Since the upper surface of the polysilicon layer 74 is flat at the upper part of the boundary trench 26a, the end portion 78a of the resist layer 78 can be formed into an accurate shape. Next, as shown in FIG. 13, n-type and p-type impurities are injected into the diode region 92 using the resist layer 78 as a mask. As a result, the top anode region 52, the separation region 54, and the bottom anode region 56 are formed in the diode region 92. The top anode region 52 is injected with p-type impurities at a lower concentration than the top body region 34. Since the polysilicon layer 74 on the substrate 70 is thinned by etching, the distance between the resist layer 78 and the substrate 70 is short. Further, as described above, the end portion 78a of the resist layer 78 is formed in an accurate shape. Therefore, impurities can be accurately injected into the diode region 92. Therefore, the top anode region 52, the separation region 54, and the bottom anode region 56 can be accurately formed. After forming the top anode region 52, the separation region 54, and the bottom anode region 56, the resist layer 78 is removed. Next, the anode contact region 50 is formed by injecting impurities into the diode region 92 using a resist layer having a patterned opening.

Next, as shown in FIG. 14, the polysilicon layer 74 is wet-etched from the upper surface side. As a result, the polysilicon layer 74 on the upper surface 70a of the substrate 70 is removed. Further, the polysilicon layer 74 is left in the trench 26. In the trench 26, the etching rate becomes faster as the position is closer to the wall surface, so that the protrusion 74a is formed in the central portion of the upper surface of the polysilicon layer 74 remaining in the trench 26. The polysilicon layer 74 remaining in the trench 26 serves as the gate electrode 20. Although the protrusion 74a is present on the upper surface of the gate electrode 20, since the impurity injection from the upper surface side has already been completed, the protrusion 74a does not cause any trouble.

Next, the substrate 70 is heated to activate the impurities injected into the substrate 70. Next, the semiconductors shown in FIGS. 1 and 2 are formed by forming the interlayer insulating film 24, the upper electrode 14, the buffer regions 41 and 59, the collector region 42, the cathode region 60, and the lower electrode 16 by a conventionally known method. The device 10 is completed.

As described above, according to the above manufacturing method, the upper surface of the polysilicon layer 74 can be flattened at the upper part of the boundary trench 26a. Therefore, when the resist layers 76 and 78 are formed, the ends 76a and 78a of the resist layers 76 and 78 can be formed in an accurate shape at the upper part of the boundary trench 26a. Therefore, impurities can be accurately injected into the substrate 70. Therefore, according to this manufacturing method, the characteristics of the semiconductor device 10 can be stabilized more than before.

In the above-described embodiment, the impurity injection into the bottom body region 38 and the impurity injection into the bottom anode region 56 were performed in separate steps. However, impurities may be injected into the entire bottom body region 38 and the bottom anode region 56 at once. Further, in the above-described embodiment, the impurity injection into the separation region 36 and the impurity injection into the separation region 54 were performed in separate steps. However, impurities may be injected into the entire separation region 36 and the separation region 54 at once. Even in such a configuration, since the impurity injection into the top body region 34 and the impurity injection into the top anode region 52 are performed in separate steps, the characteristics of the IGBT and the diode can be optimized.

Further, in the impurity injection into the top anode region 52, impurities may be injected into the entire top anode region 52 and the top body region 34 at once. In this case, by further injecting impurities into the top body region 34 in another step, the top body region 34 having a higher p-type impurity concentration than the top anode region 52 can be formed.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in this specification or drawings achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness.

10: Semiconductor device 12: Semiconductor substrate 14: Upper electrode 16: Lower electrode 20: Gate electrode 22: Gate insulating film 24: Interlayer insulating film 26: Trench 26a: Boundary trench 30: Emitter region 32: Body contact region 34: Top Body area 36: Separation area 38: Bottom body area 40: Drift area 41: Buffer area 42: Collector area 50: Anode contact area 52: Top anode area 54: Separation area 56: Bottom anode area 58: Drift area 59: Buffer area 60: Anode region 70: Substrate 71: First polysilicon layer 72: Second polysilicon layer 74: Polysilicon layer 74a: Protrusion 76: Resist layer 76a: End 78: Resist layer 78a: End 90: IGBT region 92 : Diode area

Claims (1)

It is a manufacturing method of semiconductor devices.
A step of preparing a semiconductor substrate, a trench provided on the upper surface of the semiconductor substrate, and a substrate having a gate insulating film arranged in the trench.
A step of forming a first polysilicon layer made of polysilicon containing a p-type impurity in the trench and on the upper surface of the substrate, wherein the trench is embedded in the first polysilicon layer.
A step of forming a second polysilicon layer having a concentration of p-type impurities lower than that of the first polysilicon layer on the upper surface of the first polysilicon layer.
In the step of etching the polysilicon layer composed of the first polysilicon layer and the second polysilicon layer from above by an etching method in which the etching rate for the second polysilicon layer is slower than the etching rate for the first polysilicon layer. A step of etching the polysilicon layer below the position of the upper surface of the first polysilicon layer before etching and above the upper surface of the substrate.
A step of forming a resist layer on the upper surface of the polysilicon layer remaining after etching, and a step of forming the resist layer so that an end portion of the resist layer is located above the trench.
A step of injecting impurities into the semiconductor substrate using the resist layer as a mask,
The step of removing the resist layer and
A step of etching the polysilicon layer after removing the resist layer to remove the polysilicon layer on the upper surface of the substrate and leaving the polysilicon layer in the trench.
Manufacturing method having.

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