JP7294097B2 - Semiconductor device manufacturing method - Google Patents

Description

The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

A type of semiconductor device called a reverse conducting IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) is under development. The semiconductor substrate of a semiconductor device of this kind has an IGBT area in which an IGBT structure is provided and a diode area in which a diode structure is provided. The diode structure is connected antiparallel to the IGBT structure and can operate as a freewheeling diode.

Patent Document 1 discloses a technique for forming an n-type barrier region below a p-type body region in this type of semiconductor device. The barrier region is electrically connected to the emitter electrode through pillar regions extending from the surface of the semiconductor substrate. The pillar region is configured to make Schottky contact with the emitter electrode to reduce leakage current. Since the barrier region is electrically connected to the emitter electrode through the pillar region, the potential of the barrier region is maintained at a potential close to that of the emitter electrode. As a result, the forward voltage applied to the pn junction composed of the body region and the barrier region is suppressed, the amount of holes injected from the body region into the drift region is reduced, and the reverse recovery characteristic is improved.

JP 2018-125443 A

An alloy containing silicon (for example, aluminum silicon (AlSi)) is used as a material for the emitter electrode of this type of semiconductor device in order to achieve good electrical characteristics. Therefore, as pointed out in Japanese Unexamined Patent Application Publication No. 2002-200013, silicon contained in the emitter electrode precipitates on the surface of the semiconductor substrate to form silicon nodules. In particular, if such a silicon nodule is deposited at the position where the pillar region is to be formed, the barrier height between the pillar region and the surface electrode will change, which may cause a problem of increased leak current.

The present specification provides a technique for controlling deposition positions of silicon nodules and suppressing deposition of silicon nodules at positions where pillar regions are formed.

A method for manufacturing a semiconductor device disclosed in the present specification includes a semiconductor substrate, a trench gate portion provided on one main surface of the semiconductor substrate, and a trench gate portion covering the one main surface of the semiconductor substrate. and an interlayer insulating film insulating the trench gate portion from the surface electrode, wherein the semiconductor substrate includes a drift region of a first conductivity type and a drift region provided above the drift region. a body region of a second conductivity type provided below at least a portion of the body region; a barrier region of the first conductivity type provided below at least a portion of the body region; and a pillar region of the first conductivity type making Schottky contact with the surface electrode, and the surface electrode is an alloy containing silicon. A reverse conducting IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is exemplified as a type of this semiconductor device. Also, the trench gate portion may be a dummy gate. This manufacturing method includes steps of forming the interlayer insulating film on the one main surface of the semiconductor substrate having the trench gate formed thereon, and etching a part of the interlayer insulating film to form the body region. a step of forming a contact hole exposing the pillar region; and a mask layer covering the pillar region and separated from a side surface of the interlayer insulating film on the one main surface of the semiconductor substrate exposed in the contact hole. increasing the surface roughness of the surface of the interlayer insulating film and the one main surface of the semiconductor substrate not covered by the mask layer in the contact hole; and the mask The steps of removing the layer and depositing the surface electrode may be included. In the step of forming the mask layer, the mask layer may be formed so as to be in contact with a side surface of part of the interlayer insulating film.

According to the method for manufacturing a semiconductor device described above, the surface of the interlayer insulating film and the surface of the one main surface of the semiconductor substrate at a position corresponding to the lower end of the side surface of the interlayer insulating film. Because the roughness can be selectively increased, selective deposition of silicon nodules on these surfaces can be controlled. As a result, deposition of silicon nodules at the positions where the pillar regions are to be formed is suppressed.

1 schematically shows a plan view of a semiconductor device of this embodiment. FIG. FIG. 2 schematically shows a cross-sectional view of the main part of the boundary between the IGBT range and the diode range defined in the element region of the semiconductor device of the present embodiment, and is a cross-sectional view of the main part at a position corresponding to line II-II in FIG. be. FIG. 2 schematically shows an enlarged cross-sectional view of a main part in the vicinity of a contact hole of an interlayer insulating film of the semiconductor device of this embodiment. FIG. 2 schematically shows cross-sectional views of essential parts in the manufacturing process of the semiconductor device of the present embodiment, and is a cross-sectional view of essential parts at a position corresponding to the line II-II in FIG. FIG. 2 schematically shows cross-sectional views of essential parts in the manufacturing process of the semiconductor device of the present embodiment, and is a cross-sectional view of essential parts at a position corresponding to the line II-II in FIG. FIG. 2 schematically shows cross-sectional views of essential parts in the manufacturing process of the semiconductor device of the present embodiment, and is a cross-sectional view of essential parts at a position corresponding to the line II-II in FIG. FIG. 2 schematically shows cross-sectional views of essential parts in the manufacturing process of the semiconductor device of the present embodiment, and is a cross-sectional view of essential parts at a position corresponding to the line II-II in FIG. FIG. 2 schematically shows cross-sectional views of essential parts in the manufacturing process of the semiconductor device of the present embodiment, and is a cross-sectional view of essential parts at a position corresponding to the line II-II in FIG. FIG. 2 schematically shows cross-sectional views of essential parts in the manufacturing process of the semiconductor device of the present embodiment, and is a cross-sectional view of essential parts at a position corresponding to the line II-II in FIG. FIG. 2 schematically shows cross-sectional views of essential parts in the manufacturing process of the semiconductor device of the present embodiment, and is a cross-sectional view of essential parts at a position corresponding to the line II-II in FIG. FIG. 2 schematically shows cross-sectional views of essential parts in the manufacturing process of the semiconductor device of the present embodiment, and is a cross-sectional view of essential parts at a position corresponding to the line II-II in FIG. FIG. 2 schematically shows cross-sectional views of essential parts in the manufacturing process of the semiconductor device of the present embodiment, and is a cross-sectional view of essential parts at a position corresponding to the line II-II in FIG. FIG. 2 schematically shows cross-sectional views of essential parts in the manufacturing process of the semiconductor device of the present embodiment, and is a cross-sectional view of essential parts at a position corresponding to the line II-II in FIG. FIG. 2 schematically shows cross-sectional views of essential parts in the manufacturing process of the semiconductor device of the present embodiment, and is a cross-sectional view of essential parts at a position corresponding to the line II-II in FIG. FIG. 2 schematically shows cross-sectional views of essential parts in the manufacturing process of the semiconductor device of the present embodiment, and is a cross-sectional view of essential parts at a position corresponding to the line II-II in FIG. FIG. 2 schematically shows cross-sectional views of essential parts in the manufacturing process of the semiconductor device of the present embodiment, and is a cross-sectional view of essential parts at a position corresponding to line II-II in FIG. 1, showing the behavior of silicon contained in the emitter electrode. It is a figure for explaining.

A semiconductor device according to the present embodiment will be described below with reference to the drawings. In each drawing, for common components, only one component is given a reference numeral for the purpose of clarity of illustration, and reference numerals are omitted for the other components.

FIG. 1 schematically shows a plan view of a semiconductor device 1 according to this embodiment. The semiconductor device 1 is a type of semiconductor device called a reverse conducting IGBT, and is manufactured using a semiconductor substrate 10 . The semiconductor substrate 10 has an element region 10A and a peripheral region 10B located around the element region 10A. The element region 10A of the semiconductor substrate 10 is divided into an IGBT range 102 provided with an IGBT structure and a diode range 104 provided with a diode structure. The IGBT range 102 and the diode range 104 are oriented in the y direction within the element region 10A when viewed from a direction perpendicular to the surface of the semiconductor substrate 10 (hereinafter referred to as "plan view"). are alternately and repeatedly arranged along the A peripheral breakdown voltage structure such as a guard ring is formed in the semiconductor substrate 10 corresponding to the peripheral region 10B. Furthermore, a plurality of small signal pads 28 are provided on the semiconductor substrate 10 corresponding to the peripheral region 10B. Types of the small signal pads 28 include, for example, gate pads for inputting gate signals, temperature sense pads for outputting temperature sense signals, and current sense pads for outputting current sense signals.

FIG. 2 schematically shows a cross-sectional view of essential parts corresponding to the II-II line in FIG. FIG. 2 corresponds to the boundary between the IGBT area 102 and the diode area 104 . As shown in FIG. 2, the semiconductor device 1 includes a semiconductor substrate 10 which is a silicon substrate, a collector electrode 22 provided to cover the back surface of the semiconductor substrate 10, and a collector electrode 22 provided to cover the front surface of the semiconductor substrate 10. a trench gate portion 30 provided on the surface of the semiconductor substrate 10; and an interlayer insulating film 40 insulating the trench gate portion 30 from the emitter electrode 24. A contact hole 40a is formed in the interlayer insulating film 40, and a part of the surface of the semiconductor substrate 10 is exposed through the contact hole 40a. A portion of emitter electrode 24 is in contact with a portion of the surface of semiconductor substrate 10 through contact hole 40 a of interlayer insulating film 40 . The emitter electrode 24 is made of aluminum silicon (AlSi), which is an alloy containing aluminum and silicon.

The semiconductor substrate 10 includes a p ⁺ -type collector region 11, an n-type buffer region 12, an n ⁻ -type drift region 13, a p-type body region 14, an n-type barrier region 15, an n-type pillar region 16, n It has a ⁺ type emitter region 17 and an n ⁺ type cathode region 18 .

The collector region 11 is arranged in part of the back layer portion of the semiconductor substrate 10 and provided at a position exposed on the back surface of the semiconductor substrate 10 . Collector region 11 is in ohmic contact with collector electrode 22 covering the back surface of semiconductor substrate 10 . The collector region 11 is formed in the back layer portion of the semiconductor substrate 10 by implanting boron ions toward the back surface of the semiconductor substrate 10 using an ion implantation technique.

The cathode region 18 is arranged in a part of the back layer portion of the semiconductor substrate 10 and provided at a position exposed on the back surface of the semiconductor substrate 10 . Cathode region 18 is in ohmic contact with collector electrode 22 covering the back surface of semiconductor substrate 10 . The cathode region 18 is formed in the back layer portion of the semiconductor substrate 10 by implanting phosphorus ions toward the back surface of the semiconductor substrate 10 using an ion implantation technique.

In this manner, the collector region 11 and the cathode region 18 are arranged adjacent to each other in the back layer portion of the semiconductor substrate 10 . In the semiconductor substrate 10, the range in which the collector region 11 is formed is defined as an IGBT range 102, and the range in which the cathode region 18 is formed is defined as a diode range in combination with the presence or absence of the emitter region 17 on the surface layer of the semiconductor substrate 10. 104 are partitioned.

The buffer region 12 is provided on the surfaces of the collector region 11 and the cathode region 18, is arranged between the collector region 11 and the drift region 13, and is arranged between the cathode region 18 and the drift region 13. . The buffer region 12 is a region having a higher n-type impurity concentration than the drift region 13 . The buffer region 12 is formed by implanting phosphorus ions toward the back surface of the semiconductor substrate 10 using an ion implantation technique.

Drift region 13 is provided on the surface of buffer region 12 and arranged between buffer region 12 and body region 14 . Drift region 13 is the remainder of other semiconductor regions formed in semiconductor substrate 10 .

Body region 14 is provided on the surface of drift region 13 , is arranged in the surface layer portion of semiconductor substrate 10 , and is arranged at a position exposed to the surface of semiconductor substrate 10 . Body region 14 is in ohmic contact with emitter electrode 24 covering the surface of semiconductor substrate 10 . The body region 14 may have a contact region with a high p-type impurity concentration in order to improve ohmic properties with the emitter electrode 24 . The body region 14 is formed in the surface layer portion of the semiconductor substrate 10 by implanting boron ions toward the surface of the semiconductor substrate 10 using an ion implantation technique.

Barrier region 15 is provided in body region 14 and extends in the planar direction of semiconductor substrate 10 so as to be in contact with both side surfaces of adjacent trench gate portions 30 . Barrier region 15 is arranged so as to separate body region 14 in the thickness direction of semiconductor substrate 10 . The barrier region 15 may be arranged below the entire body region 14 , that is, between the drift region 13 and the body region 14 . Also, the barrier region 15 may be selectively formed only in the diode area 104 and not formed in the IGBT area 102 . The barrier region 15 is formed in the surface layer portion of the semiconductor substrate 10 by ion-implanting phosphorus toward the surface of the semiconductor substrate 10 .

The pillar region 16 is provided in the body region 14 and extends from the surface of the semiconductor substrate 10 through part of the body region 14 to the barrier region 15 . The pillar regions 16 are arranged between the adjacent trench gate portions 30 and away from the side surfaces of the trench gate portions 30 . Pillar region 16 is in Schottky contact with emitter electrode 24 covering the surface of semiconductor substrate 10 . Thereby, the barrier region 15 is electrically connected to the emitter electrode 24 via the pillar region 16. As shown in FIG. In addition, when the barrier region 15 is selectively formed only in the diode range 104 , the pillar region 16 may be selectively formed only in the diode range 104 and not formed in the IGBT range 102 . The pillar region 16 is formed in the surface layer portion of the semiconductor substrate 10 by ion-implanting phosphorus toward the surface of the semiconductor substrate 10 .

The emitter region 17 is provided on the surface of the body region 14 , arranged in the surface layer portion of the semiconductor substrate 10 , and arranged at a position exposed on the surface of the semiconductor substrate 10 . The emitter region 17 is in contact with the side surface of the trench gate portion 30 and is in ohmic contact with the emitter electrode 24 . The emitter region 17 is selectively formed in the IGBT area 102 of the semiconductor substrate 10 and is not formed in the diode area 104 of the semiconductor substrate 10 . The emitter region 17 is formed in the surface layer portion of the semiconductor substrate 10 by ion-implanting phosphorus toward the surface of the semiconductor substrate 10 using an ion implantation technique.

The trench gate portion 30 is provided in the trench TR1 formed in the surface of the semiconductor substrate 10 and has a gate electrode 32 and a gate insulating film 34 . The gate electrode 32 is insulated from the semiconductor substrate 10 by the gate insulating film 34 and insulated from the emitter electrode 24 by the interlayer insulating film 40 . Trench gate portion 30 extends from the surface of semiconductor substrate 10 through body region 14 to reach drift region 13 . In this example, the trench gate portion 30 extends in the element region 10A of the semiconductor substrate 10 along the x direction. That is, the trench gate portion 30 has a shape in which the x direction is the longitudinal direction and the y direction is the lateral direction. Also, in this example, a plurality of trench gate portions 30 are arranged in the element region 10A of the semiconductor substrate 10 so as to be aligned along the y direction at predetermined intervals. Thus, the plurality of trench gate portions 30 have a striped layout when viewed from above. Note that the layout of the plurality of trench gate portions 30 is not particularly limited. Instead of this example, the plurality of trench gate portions 30 may have a grid-like layout when viewed from above. A plurality of trench gate portions 30 are formed in both the IGBT area 102 and the diode area 104 . Among the plurality of trench gate portions 30, the trench gate portion 30 arranged in the diode range 104 may be used as a dummy gate. When used as a dummy gate, the gate electrode 32 may not be electrically connected to the gate wiring, and a voltage different in magnitude and/or phase from the gate voltage may be applied. When used as a dummy gate, the gate electrode 32 may be short-circuited to the emitter electrode 24, for example.

FIG. 3 shows an enlarged cross-sectional view of the vicinity of the contact hole 40a of the interlayer insulating film 40. As shown in FIG. Note that FIG. 3 corresponds to an enlarged view of a cross section parallel to the yz plane. 3 shows the interlayer insulating film 40 provided in the diode area 104, the interlayer insulating film 40 provided in the IGBT area 102 has the same structure.

The interlayer insulating film 40 is wider than the width of the trench gate portion 30 in the lateral direction (y direction) so as to completely cover the surface of the gate electrode 32 . Of the side surfaces 40S of the interlayer insulating film 40 defining the contact hole 40a, the upper side surface 40Sa is formed into a concave curved surface. As will be described later, the upper side surface 40Sa has a concave curved surface that reflects processing by isotropic etching. A lower side surface 40Sb of the side surfaces 40S of the interlayer insulating film 40 defining the contact hole 40a is a flat surface. As will be described later, the lower side surface 40Sb has a flat surface shape reflecting processing by anisotropic etching. As described above, since the upper side surface 40Sa of the side surfaces 40S of the interlayer insulating film 40 is configured with a concave curved surface, the upper and lower ends of the upper side surface 40Sa have corner portions formed between the top surface 40T and the top surface 40T. 42 and the lower side surface 40Sb.

As shown in FIG. 3, the surface of the interlayer insulating film 40 (the surface including the top surface 40T and the side surface 40S) is formed with minute unevenness, and the surface roughness of the interlayer insulating film 40 is configured to be large. . Further, of the surface of the semiconductor substrate 10, the surface corresponding to the lower end of the side surface of the interlayer insulating film 40 (the position surrounded by the dashed line 100) is also formed with minute irregularities, and the surface roughness of this portion is small. is also largely constructed. As will be described later, such irregularities are formed by damage caused by ion implantation.

The semiconductor device 1 can control on/off of the current flowing through the IGBT region 102 from the collector electrode 22 toward the emitter electrode 24 based on the gate voltage applied to the gate electrode 32 of the trench gate portion 30 . Furthermore, the semiconductor device 1 allows the diode structure formed in the diode area 104 to operate as a freewheeling diode. In particular, in the semiconductor device 1, the provision of the barrier region 15 and the pillar region 16 improves reverse recovery characteristics in diode operation. This diode operation will be described below.

When a higher potential is applied to emitter electrode 24 than to collector electrode 22, a return current flows through each of IGBT area 102 and diode area 104. FIG. A case will be described below in which the potential of the emitter electrode 24 is gradually increased from the same potential as that of the collector electrode 22 . When the potential of the emitter electrode 24 rises, the Schottky junction between the pillar region 16 and the emitter electrode 24 becomes conductive. Electrons thereby flow from the collector electrode 22 toward the emitter electrode 24 . Thus, when the potential of the emitter electrode 24 is relatively low, the Schottky barrier diode becomes conductive and current flows from the emitter electrode 24 to the collector electrode 22 .

When the Schottky barrier diode conducts, the potential of the barrier region 15 is maintained at a potential close to the potential of the emitter electrode 24, so that the forward voltage applied to the pn junction composed of the body region 14 and the barrier region 15 is kept low. be done. Therefore, when the potential of the emitter electrode 24 is relatively low, the pn diode does not conduct. When the potential of the emitter electrode 24 becomes relatively high, the current flowing through the Schottky barrier diode increases. When the current flowing through the Schottky barrier diode increases, the potential difference between the emitter electrode 24 and the barrier region 15 increases, and the forward voltage applied to the pn junction composed of the body region 14 and the barrier region 15 also increases. , holes are injected from the body region 14 through the barrier region 15 . As a result, holes flow from the emitter electrode 24 toward the collector electrode 22 . On the other hand, electrons flow from the collector electrode 22 toward the emitter electrode 24 . Thus, when the potential of the emitter electrode 24 is relatively high, the pn diode conducts.

As described above, when the potential of the emitter electrode 24 rises, the Schottky barrier diode becomes conductive first, delaying the timing of the pn diode becoming conductive. This suppresses the amount of holes injected from body region 14 into drift region 13 when return current flows. Thereafter, when a potential higher than that of the emitter electrode 24 is applied to the collector electrode 22, the pn diode performs reverse recovery operation. At this time, since the amount of holes injected from the body region 14 into the drift region 13 is suppressed, the reverse current when the pn diode performs the reverse recovery operation also becomes small. As described above, in the semiconductor device 1, the provision of the barrier region 15 and the pillar region 16 improves reverse recovery characteristics in diode operation.

Next, a method for manufacturing the semiconductor device 1 will be described with reference to the drawings. First, as shown in FIG. 4, a semiconductor substrate 10 is prepared in which various semiconductor regions are formed on the surface layer of the semiconductor substrate 10 . Note that at least some of the various semiconductor regions may be formed after performing the below-described steps.

Next, as shown in FIG. 5, an anisotropic dry etching technique is used to form trench TR1 extending from the surface of semiconductor substrate 10 through body region 14 to reach drift region 13 . Next, a gate insulating film 34 is formed on the inner surface of the trench TR1 and the surface of the semiconductor substrate 10 using a thermal oxidation technique.

Next, as shown in FIG. 6, the CVD technique is used to form a polysilicon gate electrode 32 in the trench TR1 to form the trench gate portion 30. Next, as shown in FIG. Gate electrode 32 is formed to partially fill trench TR1.

Next, as shown in FIG. 7, an interlayer insulating film 40 is formed using CVD technology so as to cover the entire surface of the semiconductor substrate 10 . Silicon oxide containing a large amount of boron, phosphorus, or the like is used for the interlayer insulating film 40 .

Next, as shown in FIG. 8, a mask layer 52 of photoresist is patterned on the surface of the interlayer insulating film 40 using photolithography technology and etching technology. The mask layer 52 is selectively arranged corresponding to the position where the trench gate portion 30 is formed.

Next, as shown in FIG. 9, an isotropic etching technique (eg, Chemical Dry Etching (CDE) technique) is used to partially etch the interlayer insulating film 40 . At this time, the interlayer insulating film 40 existing under the mask layer 52 is etched isotropically from the lateral direction, and the side surface of the interlayer insulating film 40 is processed into a concave curved surface. This portion becomes the upper side surface 40Sa of the interlayer insulating film 40 (see FIG. 3).

Next, as shown in FIG. 10, an anisotropic etching technique (for example, Reactive Ion Etching (RIE) technique) is used to etch a portion of the interlayer insulating film 40 to form a body region 14 and a pillar region 16. Next, as shown in FIG. A contact hole 40a is formed so that the emitter region 17 is exposed. At this time, the side surface of the interlayer insulating film 40 existing under the mask layer 52 is processed into a flat plane. This portion becomes the lower side surface 40Sb of the interlayer insulating film 40 (see FIG. 3).

Next, as shown in FIG. 11, the mask layer 52 is removed using a wet etching technique. In the interlayer insulating film 40 formed through these processes, the upper side surface 40Sa of the side surfaces 40S is processed into a concave curved surface, and corners 42 and 44 are formed at both upper and lower ends of the upper side surface 40Sa.

Next, as shown in FIG. 12, a mask layer 54 of photoresist is patterned on a portion of the surface of the semiconductor substrate 10 exposed in the contact hole 40a of the interlayer insulating film 40. Next, as shown in FIG. The mask layer 54 is formed so as to cover the pillar region 16 and separate from the side surface 40S of the interlayer insulating film 40 .

Next, as shown in FIG. 13, an ion implantation technique is used to implant ions into the surface of the interlayer insulating film 40 and the surface of the semiconductor substrate 10 that is not covered with the mask layer 54, and these surfaces are then implanted with ions. Increase roughness. As a result, minute irregularities are formed on the surface of the interlayer insulating film 40 and the surface of the semiconductor substrate 10 not covered with the mask layer 54 (see FIG. 3). Ion species to be ion-implanted are not particularly limited. Ion species, implantation energy, and dose are appropriately set in consideration of the influence of electrical characteristics. As the ion species, an ion species having a large atomic weight is desirable in order to effectively increase the surface roughness.

In this example, both the body region 14 and the emitter region 17 are exposed on the surface of the semiconductor substrate 10 not covered by the mask layer 54 . Alternatively, the mask layer 54 may be deposited such that only the body region 14 is exposed on the surface of the semiconductor substrate 10 not covered by the mask layer 54 . In this case, the mask layer 54 is also formed in the area where the emitter region 17 is formed in the IGBT area, and is formed so as to be in contact with part of the side surface 40S of the interlayer insulating film 40 . When such a mask layer 54 is formed, only the body region 14 is exposed on the surface of the semiconductor substrate 10 not covered with the mask layer 54 . Therefore, by selecting a p-type dopant as the ion species used for ion implantation, it is possible to increase the surface roughness while suppressing the influence on the electrical characteristics.

Next, as shown in FIG. 14, the mask layer 54 is removed using a wet etching technique.

Next, as shown in FIG. 15, a sputtering technique is used to form an emitter electrode 24 of aluminum silicon so as to cover the surface of the semiconductor substrate 10 and the surface of the interlayer insulating film 40 . The behavior of silicon contained in the emitter electrode 24 at this time will be described with reference to FIG.

As shown in FIG. 16, the deposited emitter electrode 24 has aluminum grain boundaries 24a. The aluminum grain boundary 24a is formed extending upward from corners 42 and 44 of the interlayer insulating film 40 in the process of forming the emitter electrode 24 (in this example, the corner 42 is illustrated, An aluminum grain boundary 24a may be formed starting from the corner 44). Specifically, the aluminum crystals deposited from the top surface 40T of the interlayer insulating film 40 and the aluminum crystals deposited from the upper side surface 40Sa of the interlayer insulating film 40 grow as aluminum crystals with different orientations. Aluminum grain boundaries 24a are formed between. If such an aluminum grain boundary 24a exists, the silicon exceeding the solid solubility in the silicon contained in the emitter electrode 24 moves to the aluminum grain boundary 24a. The silicon that has migrated to the aluminum grain boundaries 24a diffuses along the aluminum grain boundaries 24a. The silicon diffused along the aluminum grain boundaries 24 a reaches the surface of the interlayer insulating film 40 or reaches the surface of the semiconductor substrate 10 beyond the surface of the interlayer insulating film 40 . In the semiconductor device 1, the surface roughness of the surface of the interlayer insulating film 40 and the surface of the semiconductor substrate 10 corresponding to the lower end portion of the side surface of the interlayer insulating film 40 is increased, and minute unevenness is formed. It is Since silicon nuclei grow starting from the projections of such fine unevenness, silicon nodules 62 are formed on the surface of the interlayer insulating film 40 and the surface of the semiconductor substrate 10 corresponding to the lower end of the side surface of the interlayer insulating film 40 . becomes stable.

As described above, according to the manufacturing method described above, by selectively increasing the surface roughness of the surface of the semiconductor substrate 10 corresponding to the surface of the interlayer insulating film 40 and the lower end portion of the side surface of the interlayer insulating film 40, The position of the aluminum grain boundary 24a formed in the emitter electrode 24 can be controlled, so that the semiconductor substrate 10 corresponding to the surface of the interlayer insulating film 40 or the lower end of the side surface of the interlayer insulating film 40. silicon nodules 62 can be selectively deposited on the surface of the These positions are sufficiently distant from the formation positions of the pillar regions 16 . Therefore, according to the manufacturing method described above, the deposition of the silicon nodules 62 at the formation positions of the pillar regions 16 is suppressed.

Next, the emitter electrode 24 is processed so as to remove the emitter electrode 24 on the peripheral region 10B (see FIG. 1) of the semiconductor substrate 10, and a protective film (for example, , polyimide film). Finally, after thinning the semiconductor substrate 10, various semiconductor regions and a collector electrode 22 are formed on the back surface of the semiconductor substrate 10, and the semiconductor device 1 is completed.

As described above, according to the manufacturing method of the present embodiment, the deposition of the silicon nodules 62 at the formation positions of the pillar regions 16 is suppressed. A situation in which the silicon nodules 62 are deposited at the formation position of the pillar region 16 to change the barrier height between the pillar region 16 and the emitter electrode 24 is suppressed. That is, in the semiconductor device 1, since the barrier height between the pillar region 16 and the emitter electrode 24 is stable, the problem of increased leak current is suppressed. The semiconductor device 1 can have high reliability.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or in the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims as of the filing. In addition, the techniques exemplified in this specification or drawings achieve multiple purposes at the same time, and achieving one of them has technical utility in itself.

Reference Signs List 1: semiconductor device 10: semiconductor substrate 11: collector region 12: buffer region 13: drift region 14: body region 15: barrier region 16: pillar region 17: emitter region 18: cathode region 22: collector electrode 24: emitter electrode 30: Trench gate portion 32 : Gate electrode 34 : Gate insulating film 40 : Interlayer insulating film

Claims (1)

a semiconductor substrate; a trench gate portion provided on one main surface of the semiconductor substrate; a surface electrode covering the one main surface of the semiconductor substrate; an interlayer insulating film insulated from the semiconductor substrate, the semiconductor substrate comprising: a drift region of a first conductivity type; a body region of a second conductivity type provided above the drift region; a barrier region of a first conductivity type provided below at least a portion of the region; and a first conductivity type extending from the one main surface of the semiconductor substrate to the barrier region and making Schottky contact with the surface electrode. a pillar region of a mold, wherein the surface electrode is an alloy containing silicon, comprising:
forming the interlayer insulating film on the one main surface of the semiconductor substrate on which the trench gate portion is formed;
etching a portion of the interlayer insulating film to form a contact hole exposing the body region and the pillar region;
forming a mask layer covering the pillar region and separated from the side surface of the interlayer insulating film on the one main surface of the semiconductor substrate exposed to the contact hole;
increasing the surface roughness of the surface of the interlayer insulating film and the one main surface of the semiconductor substrate not covered by the mask layer in the contact hole;
removing the mask layer;
and a step of forming the surface electrode.

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