JP2022055943A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device in which the occurrence of a hump can be suppressed without affecting the threshold voltage of a transistor.SOLUTION: A semiconductor device 100 includes a first well region 15 formed extending from one surface of a semiconductor substrate 10 to the inside, a second well region 16 extending from the one surface of the semiconductor substrate to the inside in a first region thereof and including a source region formed at one end part and a drain region formed at the other end part, a plurality of insulating parts 14 formed in a second region existing between the source region and the drain region and ranging from a plurality of regions disposed in an island-shape on the one surface of the semiconductor substrate to the inside of the second well, an element separation layer 11 formed in the semiconductor substrate so as to surround the periphery of the first region, a conductive layer (gate electrode 13) formed over the second region and the element separation layer on the one surface of the semiconductor substrate, and a gate oxide film 17 formed between a surface of the second well region and the conductive layer.SELECTED DRAWING: Figure 2

Description

The present invention relates to a semiconductor device.

In semiconductor devices such as HVMOS (High Voltage Metal Oxide Semiconductor), the hump characteristic that appears in the Id-Vg characteristic (drain current-gate voltage characteristic) has become an issue. The hump characteristic is caused by a parasitic transistor formed at the boundary between the device separation layer and the gate oxide film by STI (Shallow Trench Isolation).

The threshold voltage of the parasitic transistor is lower than the threshold voltage of the original transistor. Therefore, when the gate voltage increases, the parasitic transistor is turned on first, and when the gate voltage is further increased, the original transistor is turned on. When the gate voltage is equal to or higher than the threshold voltage of the parasitic transistor and lower than the threshold voltage of the original transistor, the drain current corresponding to the parasitic transistor flows between the source and the drain. When the gate voltage becomes equal to or higher than the threshold voltage of the original transistor, the parasitic transistor and the drain current corresponding to the original transistor flow between the source and the drain. This causes a hump in the Id-Vg characteristics.

Due to the occurrence of the hump, the characteristics of the semiconductor device change to the characteristics different from the design. Therefore, the occurrence of hump causes a decrease in the operating margin of the semiconductor device. Therefore, a technique has been proposed in which an impurity is injected into a region where a parasitic transistor is formed to raise the threshold voltage of the parasitic transistor and suppress the hump characteristic (for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2011-176115

Since the region where the parasitic transistor is formed is located at the end of the active region, in the method of injecting impurities as in the above-mentioned prior art, when misalignment occurs in the process of forming the resist pattern, the impurities are found. There is a possibility that the injection position will be displaced and the threshold voltage of the transistor will be different from the designed voltage value. In particular, when the width of the active region is small, there is a problem that the deviation of the injection position of impurities has a large influence on the threshold voltage of the transistor.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of suppressing the occurrence of hump without affecting the threshold voltage of the transistor.

The semiconductor device according to the present invention is a semiconductor device having a semiconductor substrate and a transistor formed on the semiconductor substrate, and the transistor extends inward from one surface of the semiconductor substrate. In the first well region formed in the above, and in the first region of the first well region, the semiconductor substrate is formed so as to extend from the first surface of the semiconductor substrate toward the inside of the semiconductor substrate, and one direction. A second well region having a source region formed at one end and a drain region formed at the other end in one direction, and the source region and the drain region of the second well region. With a plurality of insulating portions formed in a second region located between the semiconductor substrates and extending from a plurality of regions arranged in an island shape on the first surface of the semiconductor substrate to the inside of the second well. The element separation layer formed on the semiconductor substrate so as to surround the peripheral edge of the first region extends in a direction intersecting the direction 1 on the surface 1 of the semiconductor substrate, and the second It is characterized by having a conductive layer formed over the region and above the element separation layer, and an oxide film formed between the surface of the second well region and the conductive layer.

According to the semiconductor device of the present invention, it is possible to suppress the occurrence of hump without affecting the threshold voltage of the transistor.

It is a top view which shows the structure of the semiconductor device which concerns on this invention. It is sectional drawing along the one-dot chain line of the semiconductor device of FIG. It is a flowchart which shows the manufacturing procedure of a semiconductor device. It is a top view which shows the structure of the semiconductor device of 1st comparative example. It is a top view which shows the structure of the semiconductor device of the 2nd comparative example. It is sectional drawing along the one-dot chain line of the semiconductor device of FIG. It is a top view which shows the structure of the semiconductor device of 3rd comparative example.

Hereinafter, preferred embodiments of the present invention will be described in detail. In the description and the accompanying drawings in the following examples, substantially the same or equivalent parts are designated by the same reference numerals.

FIG. 1 is a top view of the semiconductor device 100 according to the present embodiment as viewed from above the element forming surface. The semiconductor device 100 is composed of a semiconductor substrate and a transistor made of HVMOS (High Voltage Metal Oxide Semiconductor) formed on the semiconductor substrate. The transistor constituting the semiconductor device 100 has an element separation layer 11 formed on the semiconductor substrate and an active region 12 formed in the element region of the semiconductor substrate defined by the element separation layer 11.

The element separation layer 11 has an insulator (element separation insulating film) embedded in a trench formed so as to extend inward from one surface of the semiconductor substrate (hereinafter, simply referred to as the surface of the semiconductor substrate). Is formed by. The element separation layer 11 is formed so as to surround the peripheral edge of the element forming region of the semiconductor substrate.

The active region 12 is a region formed in the element forming region (first region) of the semiconductor substrate and constituting the active region of the transistor. The active region 12 is composed of an N-type well region formed so as to extend inward from the surface of the semiconductor substrate and a P-type well region formed in the N-type well region.

The active region 12 has, for example, a rectangular shape when viewed from above. One end in the longitudinal direction in which the active region 12 extends is a region that functions as a source region 12A of the transistor, and the other end is a region that functions as a drain region 12B of the transistor. Therefore, the direction from the source region 12A to the drain region 12B is the channel direction of the transistor.

A gate electrode 13 is formed on the upper surfaces of the active region 12 and the element separation region 11 with a gate oxide film interposed therebetween. The gate electrode 13 has a rectangular shape when viewed from above, extends in a direction intersecting the longitudinal direction of the active region 12, and is a region (second region) between the source region 12A and the drain region 12B of the active region 12. ), It is formed so as to cover the upper surface of the element separation layer 11 and straddle the element separation layer 11. The gate electrode 13 is composed of a single conductive layer made of a polysilicon film.

A plurality of insulating portions 14 are formed in a region (second region) located between the source region 12A and the drain region 12B of the active region 12. The plurality of insulating portions 14 extend toward the inside of the semiconductor substrate from the plurality of regions (hereinafter referred to as opening regions) formed in an island shape on the surface of the active region 12 (that is, the surface of the semiconductor substrate). It is formed. In this embodiment, the plurality of regions have a rectangular shape (for example, a square) when viewed from above. Each of the insulating portions 14 is formed by, for example, STI (Shallow Trench Isolation), and has a structure in which an insulator is embedded in a trench.

In this embodiment, each of the opening regions constituting the insulating portion 14 intersects the extension direction of the active region (that is, the channel direction of the transistor) and the region where the active region 12 and the gate electrode 13 intersect at least. It is formed in a matrix along each of the directions. In other words, the active region 12 has a grid-like shape in which a plurality of opening regions of the insulating portion 14 are formed in a matrix in a top view in the region between the source region 12A and the drain region 12B.

FIG. 2 is a cross-sectional view taken along the alternate long and short dash line of FIG. The semiconductor device 100 is formed on the upper surface of the first well region 15 and the second well region 16 formed on the semiconductor substrate 10, the element separation layer 11 and the insulating portion 14 formed by STI, and the second well region 16. It is composed of a gate oxide film 17 and a gate electrode 13. In FIG. 2, the portion of the semiconductor substrate 10 constituting the semiconductor device 100 in which the well region is not formed is shown as the silicon substrate 18.

The first well region 15 is a first conductive type well region formed by injecting a first conductive type (N type in this embodiment) impurities into the semiconductor substrate 10. The first well region 15 is formed so as to extend inward from the surface of 1 of the semiconductor substrate 10. The second well region 16 is formed in the region defined by the element separation layer 11 of the first well region 15.

The second well region 16 is a second conductive type well region formed by injecting a second conductive type (P type in this embodiment) impurities into the first well region 15. The second well region 16 is formed so as to extend from one surface of the semiconductor substrate 10 toward the inside of the semiconductor substrate 10 in the first region (element forming region) of the first well region 15. The second well region 16 is a region that functions as an active region of the semiconductor device 100. A gate oxide film 17 is formed on the surface of the second well region 16 (that is, between the second well region 16 and the gate electrode 13).

The gate oxide film 17 is composed of, for example, a silicon oxide film. The gate oxide film 17 is formed so as to cover the upper surface of the second well region 16 other than the portion where the insulating film 14 is formed.

Next, the manufacturing method of the semiconductor device 100 of this embodiment will be described along with the manufacturing flow shown in FIG.

First, a resist film patterned by photolithography is formed on the surface of a second conductive type semiconductor substrate 10 (for example, a P-type Si substrate), and the first conductive type (N type in this embodiment) is implanted by ion implantation. Inject impurities. As a result, the first well region 15 is formed (STEP 101).

Next, the surface of the semiconductor substrate 10 on which the first well region 15 is formed is etched to form a trench. Specifically, a trench for element separation is formed on the peripheral edge of the element forming region on the surface of the semiconductor substrate 10, and a plurality of trenches having a substantially square shape in a top view are formed in the element forming region. Then, an insulating film such as SiO ₂ is formed on the entire surface of the semiconductor substrate 10 including these trenches by a CVD (Chemical Vapor Deposition) method. As a result, the element separation layer 11 and the plurality of insulating portions 14 are formed (STEP 102).

Next, a resist film is formed on the surface of the first well region 15 and impurities of the second conductive type (P type in this embodiment) are injected. As a result, the second well region 16 is formed (STEP 103).

Next, a silicon oxide film covering the exposed portion of the surface of the second well region 16 is formed by a thermal oxidation method. As a result, a gate oxide film 17 is formed on the portion (STEP 104).

Next, a polysilicon film is formed so as to cover the surfaces of the element separation layer 11, the insulating portion 14, and the gate oxide film 17 by the CVD method. As a result, the gate electrode 13 is formed (STEP 105).

Through the above steps, the semiconductor memory 100 of this embodiment is manufactured.

In the semiconductor device 100 of this embodiment, a plurality of insulating portions 14 are formed in the active region 12. A plurality of insulating portions 14 are arranged vertically and horizontally along the channel direction of the transistor and the direction orthogonal to the channel direction of the transistor in the region (second region) where the active region 12 and the gate electrode 13 intersect in the top view. .. With this configuration, in the semiconductor device 100 of the present implementation, it is possible to suppress the occurrence of hump in the Id-Vg characteristics of the transistor. This will be described below while comparing the semiconductor device 100 of this embodiment with the semiconductor device of the comparative example.

In a semiconductor device in which an element separation layer is formed by STI as an element separation structure, a parasitic transistor is formed at a boundary portion between the element separation layer and the gate oxide film. Since the parasitic transistor has a lower threshold voltage than the original transistor, when a voltage is applied to the transistor, electric field concentration occurs at the location where the parasitic transistor is formed.

FIG. 4 is a top view of the semiconductor device 200 of the first comparative example as viewed from above the device forming surface. In the semiconductor device 200 of the first comparative example, a plurality of insulating portions as in the present invention are not formed in the active region 12. Therefore, electric field concentration due to the parasitic transistor occurs in the end AE located at the boundary with the element separation layer 11 in the central region (second region) of the active region 12. Therefore, the characteristics of the parasitic transistor appear in the Id-Vg characteristics of the transistor in addition to the characteristics of the original transistor, and a so-called hump occurs.

On the other hand, in the semiconductor device 100 of this embodiment, a plurality of insulating portions 14 formed by STI are provided in the active region 12 as in the device separation layer 11. Therefore, the parasitic transistor is generated not only at the boundary portion between the element separation layer 11 and the gate oxide film 17, but also at the boundary portion between the insulating portion 14 and the gate oxide film 17. Therefore, in the semiconductor device 100 of this embodiment, the electric field concentration due to the parasitic transistor occurs in the region EP indicated by the broken line circle in FIG. Therefore, since the electric field concentration is uniformly generated over the entire second region of the active region 12 (that is, the region near the central portion intersecting with the gate electrode 13), the occurrence of hump in the Id-Vg characteristics of the transistor is suppressed. Will be done.

FIG. 5 is a top view showing the configuration of the semiconductor device 300 of the second comparative example. FIG. 6 is a cross-sectional view taken along the alternate long and short dash line of FIG. In the semiconductor device 300 of the second comparative example, the impurity injection region 21 is formed in the end AE of the active region 12 shown in the first comparative example, and impurities such as boron are injected.

As in the semiconductor device 300 of the second comparative example, the threshold voltage of the parasitic transistor can be increased by injecting an impurity into the end AE of the active region 12 in which the parasitic transistor is formed. As the threshold voltage of the parasitic transistor rises, it approaches the threshold voltage of the original transistor, so that the occurrence of hump can be suppressed as compared with the semiconductor device 200 of the first comparative example shown in FIG.

However, in the semiconductor device 300 of the second comparative example, when a misalignment occurs in the process of forming the resist pattern when forming the impurity forming region 21, the injection of impurities is required by the threshold voltage of the transistor (that is, design requirement). It may affect the threshold voltage).

On the other hand, in the semiconductor device 100 of the present embodiment, since the impurities are not injected as in the second comparative example, the generation of hump can be suppressed without being affected by the injection of the impurities.

FIG. 7 is a top view showing the configuration of the semiconductor device 400 of the third comparative example. In the semiconductor device 400 of the third comparative example, a plurality of insulating portions 24 are formed in the active region 12. Each of the insulating portions 24 has a strip-like shape extending along the channel direction of the transistor (that is, the direction from the source region 12A toward the drain region 12B) in the top view.

In the semiconductor device 400 of the third comparative example, a plurality of insulating portions 24 are formed so as to be arranged along the direction perpendicular to the channel direction in the top view. Each of the insulating portions 24 is composed of a trench and an insulator embedded in the trench as in the element separation layer 11, and is parasitic on the boundary portion TE (the portion shown by the alternate long and short dash line in FIG. 7) with the gate oxide film. Transistors are generated. Therefore, a plurality of electric field concentration points are formed, and the occurrence of hump in the Id-Vg characteristics of the transistor is suppressed.

However, in the semiconductor device 400 of the third comparative example, the band-shaped insulating portions 24 extending in the channel direction in the top view are arranged along the direction orthogonal to the channel direction, whereas the semiconductor device 100 of the present embodiment is arranged. Then, the plurality of insulating portions 14 are arranged vertically and horizontally in an island shape (for example, in a matrix shape) in a top view. Therefore, the semiconductor device 100 of this embodiment has more electric field concentration points than the semiconductor device 400 of the third comparative example, and has a great effect of suppressing the occurrence of hump.

Further, in the semiconductor device 400 of the third comparative example, since each of the insulating portions 24 has a strip-shaped shape extended in the channel direction, the width of the active region 12 in the direction orthogonal to the channel direction is at most. Limited to the distance between the insulating parts. On the other hand, in the semiconductor device 100 of the present embodiment, since the insulating portions 14 are arranged in an island shape, the width of the active region 12 intersecting with the gate electrode 13 can be widened in the direction orthogonal to the channel direction. can. Therefore, the semiconductor device 100 of the present embodiment can carry a larger current than the semiconductor device 400 of the third comparative example.

As described above, according to the semiconductor device 100 of this embodiment, it is possible to suppress the occurrence of hump in the Id-Vg characteristics of the transistor without injecting impurities. Therefore, it is possible to suppress the occurrence of hump without affecting the threshold voltage of the transistor.

The present invention is not limited to that shown in the above examples. For example, in the above embodiment, the case where the shape of the insulating portion 14 in the top view (that is, the shape of the opening region) is rectangular has been described as an example. However, the shape of the insulating portion 14 when viewed from above is not limited to this, and may be a polygon other than a rectangle or a circle.

Further, in the above embodiment, the case where the insulating portions 14 are arranged in a matrix in a top view has been described as an example. However, the shape and formation position of the insulating portion 14 are not limited to this. For example, the insulating portions 14 may be arranged in a houndstooth shape or a shape close to a hexagonal close-packed structure. That is, the insulating portion 14 may be formed in an island shape so as to have a spread in the vicinity of the central portion (second region) of the active region 12.

Further, in the above embodiment, the case where the semiconductor device 100 is composed of a transistor of HVMOS (High Voltage Metal Oxide Semiconductor) has been described as an example. However, the configuration of the transistor is not limited to this, and may be composed of, for example, a normal MOS transistor having a high withstand voltage.

Further, the manufacturing method shown in the above embodiment is an example, and the semiconductor device 100 may be manufactured by a process different from the above.

100 Semiconductor device 10 Semiconductor substrate 11 Element separation layer 12 Active region 13 Gate electrode 14 Insulation unit 15 First well region 16 Second well region 17 Gate oxide film 18 Silicon substrate

Claims (6)

A semiconductor device including a semiconductor substrate and a transistor formed on the semiconductor substrate.
The transistor is
A first well region formed so as to extend inward from one surface of the semiconductor substrate,
In the first region of the first well region, the semiconductor substrate is formed so as to extend from the first surface of the semiconductor substrate toward the inside of the semiconductor substrate, and extends in one direction, and one end in the first direction. A second well region having a source region formed in the portion and a drain region formed in the other end portion,
The second well is formed from a plurality of regions formed in a second region located between the source region and the drain region of the second well region and arranged in an island shape on the first surface of the semiconductor substrate. With multiple insulating parts, each extending to the inside of the
A device separation layer formed on the semiconductor substrate so as to surround the peripheral edge of the first region,
A conductive layer extending in a direction intersecting the direction 1 on the surface 1 of the semiconductor substrate and formed over the second region and the element separation layer.
An oxide film formed between the surface of the second well region and the conductive layer,
A semiconductor device characterized by having The semiconductor device according to claim 1, wherein the plurality of regions are formed in a matrix on a surface exposed on the first surface of the semiconductor substrate in the second region. The semiconductor device according to claim 2, wherein the plurality of regions are arranged along each of the direction 1 and the directions intersecting the directions 1. The semiconductor device according to claim 1, wherein the plurality of insulating portions are formed by embedding an insulator in a trench formed in the plurality of regions. The semiconductor device according to claim 4, wherein the plurality of insulating portions are formed by STI (Shallow Trench Isolation). The semiconductor device according to any one of claims 1 to 5, wherein each of the plurality of regions has a rectangular shape in a top view.

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