TWI397154B - Trenched power semiconductor structure with schottky diode and fabrication method thereof - Google Patents

Description

Trench type power semiconductor structure with Schottky diode and manufacturing method thereof

The present invention relates to a trench power semiconductor structure and a method of fabricating the same, and more particularly to a trench semiconductor structure having a Schottky Diode and a method of fabricating the same.

In the field of application of trench power semiconductors, more and more attention is paid to the performance of the switching speed, and the improvement of this characteristic can significantly contribute to the switching loss in the operation of the high frequency circuit. The use of Schottky diodes to improve the switching losses of power semiconductor components is a common solution.

Fig. 1 is a circuit diagram showing the improvement of the switching loss of the MOS transistor T1 using the Schottky diode SD1. As shown in the figure, the body diode D1 of the MOS transistor T1 is connected in parallel to the Schottky diode SD1. Since the starting voltage of the Schottky diode SD is lower than that of the body diode D1. Therefore, when the source bungee of the MOS transistor T1 has a forward bias, the Schottky diode SD1 can prevent the body diode D1 from being turned on. That is, in this case, the current flows from the source S to the drain D through the Schottky diode SD1.

It is worth noting that the Schottky diode does not have a time delay due to the presence of a minority carrier in the process of turning the body diode D1 from turn-on to turn-off. A small number of carriers, therefore, can avoid time delays and help improve switching losses.

Therefore, the main object of the present invention is to provide a trench power semiconductor structure and a manufacturing method thereof, which can make a Schottky diode parallel to the trench while fabricating a trench power transistor by using an existing semiconductor process. Slotted power transistor.

To achieve the above object, the present invention provides a method of fabricating a trench power semiconductor structure having a Schottky diode, comprising the steps of: a) forming a drain region in a substrate; b) forming At least one gate structure is above the drain region, and a body and at least one source region are formed between adjacent two gate structures; c) forming a first dielectric structure to cover the gate structure; d) Forming at least one contact window on the body through the first dielectric structure, the side of the contact window is adjacent to the source region, and the source region is exposed outside; e) forming a second dielectric structure in the contact window a second dielectric structure having at least one second opening exposing a portion of the bottom surface of the contact window; f) etching the body through the second dielectric structure to form a narrow trench extending to the drain region below the body; and g) The contact window and the narrow trench are filled with a metal layer.

The present invention also provides a trench power semiconductor structure having a Schottky diode. The trench power semiconductor structure includes a drain region, at least two gate structures, a body, at least one source region, a dielectric structure, a contact window, a narrow trench and a metal layer. Wherein, the gate structure is located above the bungee region. The system is located above the bungee zone and is located between two adjacent gate structures. The source region is located within the body and is adjacent to the gate structure. The dielectric structure covers the gate structure. A contact window is located in the upper portion of the body and the dielectric structure and is adjacent to the source region. The narrow trench extends downward from the bottom surface of the contact window to the drain region. The width of the narrow trench is less than the width of the contact window. The metal layer is located in the contact window and the narrow trench to be electrically connected to the source region and form a Schottky diode at the junction of the metal layer and the drain region.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

The spirit of the present invention is to utilize a spacer manufacturing technique in a semiconductor process, after forming a contact window, forming a spacer layer structure in the contact window, and then forming a narrow trench into the bottom of the body by etching. . At this time, the metal layer filled in the contact window can simultaneously contact the potential of the source, the body and the drain. Thus, a Schottky Barrier Diode (SBD) can be formed on the interface contacting the drain, and the Schottky diode system is connected in parallel to the junction between the body and the drain. (Si junction Zener Diode), thus avoiding the time delay of the switching process of the transistor element, thereby reducing the switching loss.

2E is a schematic cross-sectional view showing an embodiment of a trench type power semiconductor structure having a Schottky diode of the present invention. As shown in the figure, the trench power semiconductor structure has an N-type substrate 100, an N-type epitaxial layer 110, at least two gate structures 140, a P-type body 120, and at least one N-type source. The pole region 150, a first dielectric structure 162, a contact window 170, a narrow trench 172 and a metal layer 190. The N-type epitaxial layer 110 is formed on the N-type substrate 100. The N-type epitaxial layer 110 and the N-type substrate 100 constitute one of the trench power semiconductor structures.

A gate structure 140, such as a gate polysilicon structure, is formed over the N-type epitaxial layer 110. The P-type body is also formed over the N-type epitaxial layer 110, and the P-type body 120 is located between the adjacent two gate structures 140. A gate dielectric layer 130 is disposed around the gate structure 140 for isolating the gate structure 140 from the P-type body 120 and the N-type epitaxial layer 110. The N-type source region 150 is located within the body 120 and is adjacent to the gate structure 140. The first dielectric structure 162 covers the gate structure 140. The contact window 170 is located above the P-body 120 and extends upward into the first dielectric structure 162. Moreover, the contact window 170 is adjacent to the N-type source region 150.

A body 120 is disposed within the body 120 below the contact window 170 to reduce the contact resistance of the metal layer 190 to the body 120. The narrow trench 172 is formed by the bottom surface of the contact window 170, through the heavily doped region 180, and extends down to the N-type epitaxial layer 110. Also, the width w3 of the narrow trench 172 is smaller than the width w2 of the contact window 170. The metal layer 190 is located in the contact window 170 and the narrow trench 172, electrically connected to the N-type source region 150, and forms a Schottky diode at the junction of the metal layer 190 and the N-type epitaxial layer 110.

2A to 2E are views showing a first embodiment of a method of fabricating a trench type power semiconductor structure having a Schottky diode of the present invention. As shown in FIG. 2A, first, an N-type epitaxial layer 110 is formed on an N-type substrate 100 to form a drain region. Subsequently, at least two gate structures 140 are formed over the drain regions, and a body 120 and at least one source region 150 are formed between the adjacent two gate structures 140.

The gate structure 140, the body 120 and the source region 150 can be fabricated by a conventional power transistor process. For example, at least two gate trenches may be formed on the upper portion of the epitaxial layer 110, and then the gate dielectric layer 130 and the gate structure 140 are sequentially formed in the trenches. Subsequently, a portion of the P-type body 120 above the epitaxial layer 110 is formed by ion implantation. Next, the position of the source region 150 is defined in the P-type body 120, and the N-type source region 150 is formed on the side of the gate structure 140 by ion implantation.

Subsequently, as shown in FIGS. 2A and 2B, a first dielectric layer 160 is entirely deposited, and at least one opening defined in the first dielectric layer 160 corresponds to the body 120 between the adjacent two gate structures 140. . Then, an opening is formed in the first dielectric layer 160 by etching, and a planarization step is applied to form a first dielectric structure 162. As shown in the figure, the first dielectric structure 162 covers the gate structure 140 and has at least one opening corresponding to the P-type body 120.

Next, as shown in FIG. 2C, the P-type body 120 is etched through the first dielectric structure 162 to form a contact window 170 on the upper portion of the P-type body 120. This contact window 170 exposes the source region 150 to the outside. The opening formed in the first dielectric structure 162 corresponds to the contact window 170 formed on the P-type body 120. Then, a P-type heavily doped region 180 is formed in the P-type body 120 below the bottom surface of the contact window 170 by ion implantation.

Subsequently, as shown in FIG. 2D, a second dielectric structure 164 is formed in the contact window 170. The second dielectric structure 164 has at least one opening that exposes a portion of the bottom surface of the contact window 170. For the fabrication steps of the second dielectric structure 164, for example, a second dielectric layer (not shown) may be entirely deposited along the surface of the first dielectric structure 162 and the contact window 170. Subsequently, A portion of the second dielectric layer on the upper surface of the first dielectric structure 162 and the bottom surface of the contact window 170 is removed by etching to form the second dielectric structure 164. It should be noted that this etching step does not require the use of a photomask to form the second dielectric structure 164 within the contact window 170.

As shown in the figure, the second dielectric structure 164 includes at least one sidewall structure extending upward from the bottom surface of the contact window 170 to the first dielectric structure 162 to cover the sidewall of the contact window 170. At the same time, the second dielectric structure 164 has at least one opening defining a location of the narrow trench 172 at the bottom surface of the contact window 170. Next, the P-type body 120 is etched through the second dielectric structure 164 to form a narrow trench 172 extending through the P-type heavily doped region 180 and the P-type body 120, and extending to the N-type epitaxial layer below the P-type body 120. 110.

Finally, as shown in FIG. 2E, the second dielectric structure 164 is removed by selective etching to expose the contact window 170, but retains the first dielectric structure 162 that covers the gate structure 140. For example, the first dielectric structure 162 can be made of tantalum oxide and the second dielectric structure 164 can be made of tantalum nitride. However, the invention is not limited thereto. Any dielectric material that can be selectively etched can be applied to the present invention. Then, a metal layer 190 is electrically connected to the source region 150, the P-type body 120 and the N-type epitaxial layer 110 in the contact window 170 and the narrow trench 172 to complete the Schottky diode. The fabrication process of the trench power semiconductor structure.

3A and 3B are views showing a second embodiment of a method of fabricating a trench type power semiconductor structure having a Schottky diode of the present invention. Different from the foregoing first embodiment, as shown in FIGS. 2B and 2C, the first dielectric structure 162 is formed over the P-type body 120, and then the P-type body 120 is etched by using the first dielectric structure 162 as a mask. To form the contact window 170. After defining the position of the contact window 170', the first embodiment directly etches the first dielectric layer 160 and the P-body 120 below it to form a contact window 170'. The subsequent steps are the same as the first embodiment of the manufacturing method of the present invention, and are not described herein.

4I is a cross-sectional view showing another embodiment of the trench power semiconductor structure having a Schottky diode of the present invention. Different from the embodiment of FIG. 2E, the gate structure 240 of the trench power semiconductor structure of the embodiment protrudes upwardly from the upper surface of the P-type body 120, and the trench power semiconductor structure has a first interface. The electrical structure 262 and a second dielectric structure 264' respectively cover the side and upper surfaces of the gate structure 240 to isolate the gate structure 240 from the metal layer 290. In this embodiment, the first dielectric structure 262 and the second dielectric structure 264' are made of tantalum oxide and tantalum nitride, respectively. However, the invention is not limited thereto. The first dielectric structure 262 and the second dielectric structure 264' can also be fabricated from other dielectric materials that can be selectively etched.

Figures 4A through 4I show a third embodiment of a method of fabricating a trench power semiconductor structure having a Schottky diode of the present invention. As shown in FIG. 4A, first, an epitaxial layer 210 is formed on a substrate 200. Then, a pattern layer 260 is formed on the upper surface of the epitaxial layer 210. Next, the epitaxial layer 210 is etched through the pattern layer 260 to form a plurality of trenches 222 in the epitaxial layer 210. Next, a gate dielectric layer 230 is formed to cover the inner wall of the trench 222. Then, as shown in FIG. 4B, the polysilicon material is filled in the openings of the trenches 222 and the pattern layer 260 without removing the pattern layer 260 to form a plurality of gate structures 240 in the trenches 222. These gate structures 240 protrude upward from the upper surface of the epitaxial layer 210.

Next, as shown in FIG. 4C, the pattern layer 260 is removed. Then, a P-type dopant is implanted into the epitaxial layer 210 by ion implantation to form a P-type body 220. Next, an N-type dopant is implanted into the surface region of the P-type body 220 by ion implantation to form an N-type doped region 250 on the upper portion of the P-type body 220. The N-doped region 250 is used as a source region of the transistor.

Subsequently, as shown in FIG. 4D, a first dielectric structure 262 is formed to cover at least the sidewalls of the gate structure 240. For the fabrication steps of the first dielectric structure 262, for example, a first dielectric layer may be deposited along the surface of the epitaxial layer 210 and the gate structure 240. Then, a portion of the first dielectric layer on the epitaxial layer 210 is removed by etching to form the first dielectric structure 262 covering at least the sidewall of the gate structure 240. It should be noted that after the foregoing etching step, the upper surface of the gate structure 240 is exposed to the outside.

Subsequently, as shown in FIG. 4E, the P-type body 220 is etched through the first dielectric structure 262, and a contact window 270 is partially formed on the P-type body 220. The contact window 270 divides the N-type doped region 250 into two portions, corresponding to the adjacent two gate structures 240, respectively. Next, the P-type dopant is implanted by ion implantation to form a heavily doped region 280 in the P-type body 220 below the bottom surface of the contact window 270. It should be noted that since the upper surface of the gate structure 240 is exposed, the gate structure 240 and the P-type body 220 are both formed of germanium. Therefore, the etching step of FIG. 4E simultaneously etches the upper surface of the gate structure 240, and a recess is formed in the first dielectric structure 262 over the gate structure 240.

Subsequently, as shown in FIGS. 4F and 4G, a second dielectric structure 264 is formed in the contact window 270. In the present embodiment, the second dielectric structure 264 covers the sidewalls of the contact window 270 and also covers the upper surface of the gate structure 240. As for the fabrication steps of the second dielectric structure 264, as shown in FIG. 4F, a second dielectric layer 263 may be entirely deposited along the surface of the first dielectric structure 262 and the contact window 270. The second dielectric layer 263 needs to substantially fill the recess above the gate structure 240. Then, as shown in FIG. 4G, a portion of the second dielectric layer 263 located on the bottom surface of the contact window 270 is removed by etching to form the second dielectric structure 264. It should be noted that since the thickness t1 of the second dielectric layer 263 overlying the gate structure 240 is greater than the thickness t2 of the second dielectric layer 263 covering the bottom surface of the contact window 270, the contact window is removed by etching. After a portion of the second dielectric layer 263 of the bottom surface 270, a portion of the second dielectric layer 263 may remain to cover the sidewalls of the contact window 270 and the upper surface of the gate structure 240.

As shown in FIG. 4G, after the fabrication of the second dielectric structure 264 is completed, the P-type body 220 is etched through the second dielectric structure 264 to form a narrow trench 272 extending through the P-type heavily doped region 280 and the P-type. The body 220 extends to the N-type epitaxial layer 210 under the P-type body 220.

Next, as shown in FIG. 4H, a portion of the second dielectric structure 264 covering the sidewalls of the contact window 270 is removed by etching to expose the source region 250. In the present embodiment, the width w1 of the contact window 270 is greater than the width w2 of the gate structure 240, and the second dielectric layer 263 deposited in the step of FIG. 4F has a sufficient thickness to fill the gate. An opening above structure 240. therefore. After this etching process, a portion of the second dielectric structure 264' is left overlying the upper surface of the gate structure 240. Finally, as shown in FIG. 4I, a metal layer 290 is filled in the contact window 270 and the narrow trench 272 to complete the fabrication process of the trench power semiconductor structure having the Schottky diode.

In the present embodiment, the first dielectric structure 262 and the second dielectric structure 264 are made of different dielectric materials. For example, the first dielectric structure 262 and the second dielectric structure 264 may be respectively made of yttrium oxide. Made with tantalum nitride. However, the invention is not limited thereto. 5A to 5D are diagrams showing an embodiment in which the first dielectric structure 262 and the second dielectric structure 264 are made of the same dielectric material. As shown in FIG. 5A, after the contact window 370 is formed on the P-type body 320, a second dielectric layer 363 is entirely deposited. The second dielectric layer 363 and the first dielectric structure 362 are made of the same material. Subsequently, as shown in FIG. 5B, the dielectric structure 364 at the sidewall of the contact window 370 is used as a mask by an anisotropic etching technique to form a narrow trench 372 under the recess, penetrating the heavily doped region 380, and Extending to the N-type epitaxial layer 310.

Next, as shown in FIG. 5C, the dielectric structure 364 overlying the sidewalls of the contact window 370 is removed to expose the source region 350 adjacent the contact window 370. It should be noted that, as in the third embodiment of the manufacturing method of the present invention, the width of the contact window 370 formed in the present embodiment is larger than the width of the gate structure 340, and is deposited in the step shown in FIG. 5A. The second dielectric layer 363 has a sufficient thickness to fill the opening above the gate structure 340. Therefore, after passing through the etching step of FIG. 5C, a portion of the dielectric structure 366 is still left over the upper surface of the gate structure 340. Finally, as shown in FIG. 5D, a metal layer 390 is filled in the contact window 370 and the narrow trench 372 to complete the fabrication process of the trench power semiconductor structure having the Schottky diode.

As described above, the method for fabricating the trench type power semiconductor structure of the present invention can be combined with the process of the existing trench type MOS transistor, and is particularly applicable to a process of narrow line width. Since the related process equipment and conditions have been maturely used in the process of trench power transistors, the fabrication method of the present invention has the advantages of low cost and high feasibility. At the same time, the present invention does not require the use of an additional lithography process to define the location of the Schottky diode. It can help reduce production costs.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.

SD1‧‧‧ Schottky diode

T1‧‧‧ gold oxide semi-transistor

D1‧‧‧ body diode

G‧‧‧ gate

S‧‧‧ source

D‧‧‧汲

100,200,300‧‧‧N type substrate

110,210,310‧‧‧N type epitaxial layer

120,220,320‧‧‧P type ontology

130,230,330‧‧‧gate dielectric layer

140,240,340‧‧‧ gate structure

150, 250, 350‧‧‧N-type source area

162,262,362‧‧‧First dielectric structure

164,264,264'‧‧‧second dielectric structure

170,170’,270,370‧‧‧Contact window

172,272,372‧‧‧Narrow trench

180,280,380‧‧‧P type heavily doped area

190,290,390‧‧‧metal layer

260‧‧‧pattern layer

222‧‧‧ trench

160‧‧‧First dielectric layer

263,363‧‧‧second dielectric layer

364,366‧‧‧ dielectric structure

Figure 1 is a schematic diagram of a circuit for improving the switching loss of a gold-oxide-semiconductor using a Schottky diode.

2A to 2E are views showing a first embodiment of a method of fabricating a trench type power semiconductor structure having a Schottky diode of the present invention.

3A and 3B are views showing a second embodiment of a method of fabricating a trench type power semiconductor structure having a Schottky diode of the present invention.

Figures 4A through 4I show a third embodiment of a method of fabricating a trench power semiconductor structure having a Schottky diode of the present invention.

Figures 5A through 5D show a fourth embodiment of a method of fabricating a trench power semiconductor structure having a Schottky diode of the present invention.

200. . . N-type substrate

210. . . N-type epitaxial layer

220. . . P-type ontology

230. . . Gate dielectric layer

240. . . Gate structure

250. . . N-type source region

262. . . First dielectric structure

264. . . Second dielectric structure

270. . . Contact window

272. . . Narrow groove

280. . . P-type heavily doped region

Claims (15)

A method of fabricating a trench power semiconductor structure having a Schottky diode, comprising: forming a drain region in a substrate; forming at least two gate structures above the drain region And forming a body and at least one source region between the adjacent two gate structures; forming a first dielectric structure covering the gate structure; and forming at least one contact window through the first dielectric structure In the body, the side of the contact window is adjacent to the source region, and the source region is exposed; a second dielectric structure is formed in the recess, and the second dielectric structure has at least a second Opening a portion of the bottom surface of the contact window; etching the body through the second dielectric structure to form a narrow trench extending to the drain region below the body, the narrow trench having a width smaller than a width of the contact window; And filling a metal layer in the contact window and the narrow trench, the metal layer is electrically connected to the source region, and forming the Schottky diode in the metal layer and the drain region surface. The method for fabricating a trench type power semiconductor structure having a Schottky diode according to claim 1, wherein the step of forming the first dielectric structure comprises: depositing a first dielectric layer; The first dielectric layer defines a location of the contact window, the contact window corresponding to the body between two adjacent gate structures; and etching the first dielectric layer to form at least one first opening corresponding to the contact window. A method of fabricating a trench type power semiconductor structure having a Schottky diode according to claim 1, wherein the step of forming the contact window to expose the source region to the outside includes forming a heavily doped The impurity region is within the body below the contact window, and the narrow trench extends through the heavily doped region. A method of fabricating a trench type power semiconductor structure having a Schottky diode according to claim 1, wherein the second dielectric structure comprises at least one sidewall structure extending upward from a bottom surface of the contact window to the The first dielectric structure. A method of fabricating a trench type power semiconductor structure having a Schottky diode according to claim 1, wherein the step of forming the second dielectric structure comprises: along the first dielectric structure Forming a second dielectric layer on the surface of the contact window; and removing a portion of the second dielectric layer on the upper surface of the first dielectric structure and the bottom surface of the contact window by etching to form a second dielectric layer The second dielectric structure covers at least a sidewall of the contact window. A method of fabricating a trench type power semiconductor structure having a Schottky diode according to claim 1, wherein the step of forming the gate structure and the first dielectric structure comprises: forming a pattern layer An upper surface of the substrate; the substrate is etched through the pattern layer to form a plurality of trenches in the substrate; a gate dielectric layer is formed to cover the inner walls of the trenches; and polysilicon material is filled in the trenches And the opening of the pattern layer to form a plurality of gate structures over the drain region and protruding over the upper surface of the substrate; removing the pattern layer; undulating along the surface of the substrate and the gate structure Depositing a first dielectric layer; removing a portion of the first dielectric layer on the substrate by etching to form the first dielectric structure covering at least a sidewall of the gate structure. A method of fabricating a trench type power semiconductor structure having a Schottky diode according to claim 6 wherein a portion of the first dielectric layer is removed by etching to form the first dielectric structure. After the step, the upper surface of the gate structure is exposed, and in the step of etching the body through the first dielectric structure, the gate structure is simultaneously etched to form a recess above the gate structure. In the first dielectric structure. A method of fabricating a trench type power semiconductor structure having a Schottky diode according to claim 7 wherein the step of forming the second dielectric structure comprises: along the first dielectric structure The surface of the contact window is undulating, and a second dielectric layer is substantially deposited, the second dielectric layer substantially filling the recess above the gate structure; and the second portion of the bottom surface of the contact window is removed by etching The electrical layer forms the second dielectric structure to cover at least a sidewall of the contact window and an upper surface of the gate structure. A method of fabricating a trench type power semiconductor structure having a Schottky diode according to claim 8 wherein, after the step of forming the narrow trench, further comprising removing a portion covering a sidewall of the contact window The second dielectric structure is exposed to expose the source region and leave a portion of the second dielectric structure overlying the gate structure. A method of fabricating a trench power semiconductor structure having a Schottky diode according to claim 1 wherein the width of the contact window is greater than the width of the gate structure. A trench power semiconductor structure having a Schottky diode comprising: a drain region; at least two gate structures above the drain region; a body above the drain region and located Between two adjacent gate structures; at least one source region is located in the body and adjacent to the gate structure; a dielectric structure covering the gate structure; a contact window formed on the body And a portion of the dielectric structure adjacent to the source region; a narrow trench extending downward from a bottom surface of the contact window to the drain region, the narrow trench having a width smaller than a width of the contact window; A metal layer is filled in the contact window and the narrow trench to be electrically connected to the source region, and the Schottky diode is formed on the junction of the metal layer and the drain region. The trench power semiconductor structure having a Schottky diode according to claim 11 further includes a heavily doped region located in the body below the contact window, and the narrow trench is penetrated through the body Heavy doped area. A trench type power semiconductor structure having a Schottky diode according to claim 11 wherein the gate structure protrudes from an upper surface of the body. A trench type power semiconductor structure having a Schottky diode according to claim 13 wherein the dielectric structure comprises a first portion and a second portion, the first portion being the body The upper surface extends upwardly to cover the sidewall of the gate structure, and the second portion covers the upper surface of the gate structure. A trench power semiconductor structure having a Schottky diode according to claim 11 wherein the width of the contact window is greater than the width of the gate structure.