TWI246194B - Self-aligned schottky-barrier clamped trench DMOS transistor structure and its manufacturing methods - Google Patents

Abstract

The self-aligned Schottky-barrier clamped trench DMOS transistor structure of the present invention comprises a Schottky-barrier diode being formed in a middle semiconductor portion of a self-aligned source region. The self-aligned source region comprises a lightly-doped epitaxial semiconductor layer, a moderately-doped base diffusion ring being formed on a portion of the lightly-doped epitaxial semiconductor layer surrounded by a trench gate region, a self-aligned heavily-doped source diffusion ring being formed in a side surface portion of the moderately-doped base diffusion ring, and a self-aligned source contact being formed on a semiconductor surface of the self-aligned source region surrounded by a sidewall dielectric spacer. The trench gate region comprises a self-aligned conductive gate layer being formed over a gate dielectric layer formed over a trenched semiconductor surface in a shallow trench with or without a thicker isolation dielectric layer being formed on a bottom trench surface of the shallow trench.

Description

1246194 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a trench-type double-diffusion metal-oxide-semiconductor (DM0s) power transistor and a manufacturing method thereof, particularly to an automatic alignment A quasi-Schottky barrier (clamped) grooved double-diffusion metal-oxide semiconductor structure and its manufacturing method are related. [Prior art]

A double-diffused metal-oxide half-power transistor with a very low on-resistance has become an important semiconductor element for battery protection, switching, voltage regulators, amplifiers, and power management.

FIG. 1A shows a schematic cross-sectional view of a non-auto-aligned source structure of a planar double-diffused metal-oxide semiconductor transistor of the prior art. One of them: the P-based diffusion region 104a uses a first mask photoresist Step and forming a lightly doped layer over a highly doped N + silicon substrate 100 through a patterned polysilicon gate layer 103a over a gate oxide layer 102a and a patterned window Within the hetero-N epitaxial silicon layer 1 〇1; a highly doped P diffusion region 1 0 5 a is formed by implanting a high energy ion through the forming window, the p-based diffusion region 1 〇 4 a Within; a highly doped n + source diffusion ring 1 0 6 a is formed in the forming window through a second mask photoresist step (not shown) and through a forming photoresist layer (not shown) A non-auto-aligned ion implantation window within the middle portion of the formed polycrystalline silicon gate layer and the gate oxide layer over the gate oxide layer 〇2a to form the p-based diffusion

1246194 V. Description of the invention (2) A surface portion of the region 1 0 4a is placed on the highly doped p side surface portions; a non-automatic alignment source and a third mask photoresist step (not shown) (Pictured) is formed in a #etched hole surrounded by the object layer 1 0 7 a; and a source system is formed on the shaped oxide layer 10 7 a and the height surrounded by the source diffusion ring 1 0 6 a The doped p + diffusion region η + source diffusion ring 1 0 6 a on one side surface portion of the planar double-diffusion metal-oxide half-power transistor, which is not shown in Figure 1A, requires two rigorous curtain lights. Resistance step curtain photoresist step) to manufacture. However, these two rigorous misalignments can cause layout, which in turn can cause serious component reliability issues. The source area of a double-diffused metal-oxide half-power transistor is difficult. If there are a large number of transistor cells connected, the 103a as a gate conductive layer will have a higher resistance to reduce the switching speed. A typical example of the planar double-diffusion gold can be found in S. M u k h e r j e e e1 No. 5, 2 6 8, 5 8 6. FIG. 1B shows a representative symbol of an equivalent element of the planar double-expanded crystal shown in FIG. 1A. One (D1) is a p-based diffusion-doped N-epitaxial silicon through the source and the drain electrode. The P-η junction between layers 101 to shape the celestial body (D1) will be conductive in some circuit applications, while the body (D1) has a minority carrier storage diffusion region under forward bias 1 0 5 a A contact window passes through a shaped oxide contact metal layer 108a from the highly doped η + 105a and the highly doped ^. Obviously, the structure of the active alignment source is not equal to the current distribution in the second and third mask photoresist steps. Therefore, the planar type is further miniaturized. In addition, the formed polycrystalline silicon gate layer is large. Gate-connected stray oxygen half-power transistor ^: a 1. US patent bulk gold-oxygen half-power transistor ρ-η junction diode scattering region 104a and the light I. The ρ-η junction interface is the ρ -η junction diode will reduce the planar type 1246194 V. Description of the invention (3). The switching speed of the double-diffused metal-oxide half-power transistor. Therefore, a Schottky barrier diode is proposed to be placed in the source There are many complicated methods in the literature that have been proposed to integrate a planar double-diffused metal-oxide semiconductor and a Schottky diode into a transistor cell. A typical For an example, see US Patent No. 6,6 8 6, 6 1 4 disclosed by J. Tihanji, as shown in Figures 2A and 2B, where Figure 2A shows a brief cross-sectional view and Figure 2B shows An equivalent element is shown in the table. From Figure 2A, we can see that a Schottky barrier diode (Ds ) Is formed on a lightly doped N-epitaxial silicon layer 20 through a non-automatically aligned groove window formed in a middle portion of a P-based diffusion region 50. It can be clearly seen here Therefore, Figure 2A does not have the Schottky barrier to contact the metal 9 0 ^ required diffusion protection ring to eliminate edge leakage and soft (so ft) collapse; the P-based diffusion region 50 is floating and does not have a high The doped η + source diffusion ring 60 is short-circuited; the non-automatically aligned groove window will cause an uneven current distribution in the adjacent planar double-diffused metal-oxide semi-electric crystal cell. The Schottky barrier diode has one A low value energy barrier exhibits a large leakage current under a forward blocking (b 1 ock i ng) state. Therefore, a main object of the present invention is to provide an automatic alignment of Schottky barrier energy recesses. Type double-diffused metal-oxide-semiconductor structure without the need for rigorous masking photoresist steps. Another object of the present invention is to provide an automatic alignment Schottky barrier. Crystal structure has a grooved double-diffused metal-oxide semiconductor A moderately doped P-based diffusion ring in the somatic cell acts as a diffusion protection ring for a Schottky barrier diode to eliminate edge leakage

Page 9 1246194 V. Description of the invention (4) Flow and soft collapse. The p-based diffusion ring of an energy-inserting barrier recess of the present invention and a highly doped η + source expansion The barrier-recessing recessed double-expanding diode of the present invention can be formed between the crystal layers. Eliminate the reverse of the forward barrier-shaped energy-barrier diode. [Content of the invention] Double concave recessed groove type short-circuit short circuit important loose gold mode one state of electricity leakage step by step metal oxygen half-diffusion to eliminate the target oxygen The semi-electrically doped P- ρ-η is provided with a current of 0. The transistor is provided with a metal-oxygen semi-structured transistor body. An automatic seed is provided to automatically align the Schottky with one of the moderately doped cells. There is a low value energy effect in the empty region of the crystal junction-base diffusion interface. The Schottky energy structure has a scatter ring of the Schottky barrier ring and a lightly doped ΙΓ 磊 加 to stop the scattered ring layer of the Schottky scattered gold bipolar half-potential concave source region. The invention discloses an oxygen semi-electric crystal system with a crystal trough type and an enveloping formation, and the cells are double-expanded. The one side of the one is aligned with the Schottky barrier inlay structure and its manufacturing method. Alignment and meta-product integration. According to the present invention, the metal oxide semiconductor transistor structure trench gate region, wherein the automatic alignment source region includes at least one lightly doped and highly doped η + source diffusion ring surrounded by a middle groove gate region. Within the mid-surface portion, an automatic pair, one of the grooves is automatically aligned with at least one groove including Schott-type double-expanded Schottky, a self-type double-expanded energy barrier, and a gold-oxygen barrier. P-based expansion semiconductors with embedded alignment groove gates are doped with N-doped P-based expanded source contact windows

Page 10, 1246194 V. Description of the invention is formed on the semiconductor layer diffusion ring, one on top of the other, and one on top of the other, one by one from the silicon gate doped with the middle flow and the trench impurity trench energy barrier edge The brakes come from the top. A shallow and bottom-moving layer is coated with a compound crystal (5) The side edges of the middle and the source regions are moved to the concave groove or the groove height is mixed into the inner wall of the gold groove gate. Without a surface doped hetero-p-based diffusion ring doped with η + a source diffusion ring surrounded by the lightly-enclosed one of the side walls of the recessed gate region, doped with η automatically to a buffer dielectric The silicide layer forming region of the electric pad layer surrounded by the layers includes at least one groove and a thickness above. The polycrystalline silicon gate semiconductor isolation medium automatically covers a self-covering metal chip layer on the surface of the self-aligned surface electric layer quasi-conductor, or a silicon gate layer is filled with a high temperature resistant impurity P- Basic expansion a soft collapse of diffusion protection. The double-diffused metal-oxygen half-type is changed to double-diffused metal-oxygen semi-clamped grooved double-battery transistor loose ring system as a ring to eliminate the described automatic transistor junction to form an automatic transistor junction diffused metal oxide (IGBT). Aligning Xiao Gou for one of these Schott can aim at Xiao Gou. In addition, the semi-transistor or metal oxide metal automatic base is easy to special, and the body junction semi-control is formed on the gate layer. The automatic barrier or the metal barrier is embedded in the energy barrier. The semi-energy barrier is embedded in the automatic barrier. The structure can be doped with the doping degree of the thyristor, and the gates of the surface source expansion and quasi-source switches should be at least partially exchanged and aligned at the edge of the lithographic base of the kiwi chemical base, the η-conductor position, and the P-alignment. The high-layer layer including a hetero-polycrystalline groove is formed in the loose ring and the contact window layer formed in this part, and the dielectric layer groove is formed. The barrier channel of the leakage channel of the electrical leakage channel can be changed. the way

Page 11 1246194 V. Description of the invention (6) Please refer to FIG. 3A to FIG. 3G, which discloses the manufacture of a first type of self-aligned Schottky barrier with recessed double-diffusion metal-oxide halves of the present invention. The process steps of the transistor structure and its brief cross-sectional view. FIG. 3A shows a lightly doped N-epitaxial silicon layer 2 0 1 forming a highly doped N + silicon substrate 2 0 0; a buffer oxide layer 2 0 2 is formed on the < lightly doped N -Epitaxial silicon layer 201; then, a mask dielectric layer 203 is formed on the buffer oxide layer 202; then, a first mask photoresist (PR1) is performed Steps to define a complex automatic alignment source region (SR) and a groove gate region (TGR), wherein each of the complex automatic alignment source region (SR) is surrounded by the groove gate region (TGR). The highly doped N + silicon substrate 200 has a resistivity between 0.01 ohm · cm to 0.04 ohm · cm and a resistance coefficient between 300 micrometers and 800 micrometers. The thickness is determined by the wafer size. The lightly doped N-epitaxial silicon layer 201 has a resistivity between 100 ohm · cm to 0.1 ohm · cm and a thickness between 100 micrometers and 1 micrometer. The buffer oxide layer 202 is a 4 thermal silicon dioxide layer and has a thickness between 200 angstroms and 100 angstroms. It is important to note here that the shape of each of the complex auto-alignment source regions (SR) can be square, rectangular, hexagonal, circular or cylindrical, and so on. Figure three B shows that the mask dielectric layer 203 located in the groove gate region (TGR) is removed by anisotropic dry etching, and then the formed mask photoresist (PR1) is removed; Then, boron ion implantation is performed through a forming window in the groove gate region (TGR) and then driven to form a P-diffusion region 2 0 4a on the lightly doped N-epitaxial silicon layer 201 Within; then

Page 12 1246194 V. Description of the invention (7), arsenic or phosphorus ion implantation is performed through the same forming window to form an η + diffusion region 2 0 5 a at a surface portion of the p-diffusion region 2 0 4 a Within. The implantation dose of the boron ion implantation is between 10 13 / cm 2 and 5 * 1 0 14 / cm 2. Therefore, the p-diffusion region 2 0 4 a is moderately doped (m 〇derate 1). y-doped) and has a junction depth between 0.8 microns and 3 microns. The implantation dose of phosphorus or arsenic ions is between 10 15 / cm 2 and 10 16 / cm 2. Therefore, the η + diffusion region 2 0 5 a is highly doped (heavi 1 yd 〇ped) and has one The surface depth is between 0.2 micron and 1 micron. FIG. 3C shows that the buffer oxide layer 202 in the groove gate region (TGR) is removed by anisotropic dry etching or wet etching; then, anisotropic dry etching is used. A shallow groove is formed in the lightly doped N-epitaxial silicon layer 201; then, a cleaning step is performed to eliminate defects generated on the silicon surface of the shallow groove; then, a gate dielectric Layer 2 6 a is formed on the silicon surface of the shallow groove. It is worth noting here that the cleaning step is to form a liner (1 iner) oxide layer on the silicon surface of the shallow groove before removing the liner oxide layer. The gate dielectric layer 2 0 6 a is a thermal dioxide fragmentation layer or a thermal dioxide fragmentation layer which is pre-nitrided in a laughing gas (N 20) environment and its thickness is between 100 angstroms and 1 0 0 0 Angstroms. It can be clearly seen from FIG. 3C that a thicker silicon dioxide layer system is formed on a highly doped N + source diffusion ring 2 0 5 b, and the P-diffusion region 2 0 in FIG. 3B 4a is separated by the shallow groove into a moderately doped p-based diffusion ring 204b located within each of the plurality of auto-aligned source regions (SR). In addition, it can be clearly seen here that the depth of the shallow groove is slightly deeper than the junction depth of the p-diffusion region 204a. It is worth emphasizing here that the thicker 1246194 V. Invention Description (8), a silicon dioxide layer formed on the highly doped η + source diffusion ring 2 0 5b is conducive to providing the highly doped η + source There is a good isolation layer between the diffusion ring 2 0 5b and the conductive gate layer formed subsequently. FIG. 3D shows that an etch-back polycrystalline silicon layer 2 0 7a is formed on the gate dielectric layer 20 6a within the groove gate region (TGR); then, it is laid out in an automatic alignment manner. Plant a high dose of phosphorus or arsenic impurities. The etch-back polycrystalline silicon layer 2 7a is first deposited by a LPCVD method with a polycrystalline silicon layer 2 7 (not shown) having a thickness approximately equal to or greater than half the width of the groove gate region (TGR). Then, the stacked polycrystalline silicon layer 207 is etched back to a level slightly above the top of the shaped buffer oxide layer 202a. FIG. 3E shows that a thermal oxidation process is performed to oxidize the etch-back highly doped polycrystalline silicon layer 207a to form a planarized overlying oxide layer 208a located in the trench gate region (TGR) and at the same time Redistributes a dopant that automatically aligns within the highly doped complex silicon gate layer 207b. It is worth noting here that the top surface level of the planarized overlay oxide layer 208a may be higher than the shaped mask dielectric layer within each of the plurality of auto-aligned source regions (SR). The top surface level of 2 0 3a ^ is horizontal, and a top surface level of the auto-aligned highly doped complex crystalline silicon gate layer 2 7b is located at the thicker oxide layer of the gate dielectric layer 2 6 a An upper part of it. Figure 3F shows that the shaped mask dielectric layer 203a within each of the plurality of auto-aligned source regions (SR) is removed using hot phosphoric acid or anisotropic dry-type engraving; one side The side wall dielectric cushion layer 2 0 9 a is formed on a side wall of the planarized oxide layer 2 8 a within the groove gate region (TGR) and is placed on the plurality of automatic alignment sources. Every area (SR)

Page 14 1246194 V. Description of the invention (10) A diffusion protection ring to eliminate the edge leakage current and soft breakdown of the Schottky barrier diode. In addition, the moderately doped P-diffusion ring 2 04b and the highly doped η + source diffusion ring 2 05 are dirty to eliminate the critical voltage body of the grooved double-diffused gold-oxide semi-electric crystal cell. )effect. In addition, the lightly doped n- epitaxial silicon layer 2 0 1 surrounded by the moderately doped p-based diffusion ring 2 0 4 b can be used in a forward blocking state by

The moderately doped P-based diffusion ring 6 is doped with U +. An empty area formed by a p-n junction of π / w is added to stop the elimination of the Schottky barrier diode with a low value barrier height due to a known image power reduction effect (Image-force i〇wering effect) A large reverse leakage current. — Please refer to FIG. 4A to FIG. 4E, which shows the continuation diagrams of the fabrication of a second type of self-aligned Schottky barrier double-diffusion metal-oxide semiconductor structure of the present invention. Simplified process steps and a brief cross-sectional view. Figure 4A shows a thick isolation dielectric layer 2 is tied to the shape of the layer 形! = Shallow concave, a bottom stone surface. The thickness = first piled up and right-lice silicon and stacked using lpcvd method, 4) "; f is approximately equal to or slightly larger than the groove gate area (TR (

-D = Shi Xi layer 212 (not shown) in the shallow groove to fill the silicon dioxide of i area; 212 to ': Rong Li ^ isotropic dry etching method to etch back the bottom of i; if two At this moderately doped side edge = Z1, 2′7 ′ gate dielectric layer 2 061) is formed on the second surface of the groove. Similarly, a thicker silicon dioxide layer is formed on the surface.

Page 16 1246194 V. Description of the invention (11) A groove on the silicon surface of β highly doped η + source diffusion ring 2 0 5b. It is worth noting here that before the thick isolation dielectric layer 2 1 2 a is formed or after the thick isolation dielectric layer 2 1 2 a is formed, a cleaning step may be performed to eliminate defects caused by the trenching. FIG. 4C shows that an etch-back polycrystalline silicon layer 207a is formed on the gate dielectric layer 206b and is placed on the thick isolation dielectric layer 212a. Then, the automatic alignment is performed. The high-dose phosphorus or arsenic ions are implanted to restore the etch-back. The grain fragment layer 207 a force π gives high replacement. FIG. 4D shows that a thermal oxidation process is performed to form a cover oxide layer 208a located in the trench gate region (TGR), as shown in FIG. 3E. According to the process steps shown in Figure 3F and Figure 3G, Figure 4E can be easily obtained. Obviously, except that a thick isolation dielectric layer 2 1 2 is formed on the bottom silicon surface of the shallow groove to reduce the capacitance between the gate and the drain and increase the breakdown voltage between the gate and the drain. The four E series are very similar to the three G in FIG. Please refer to FIG. 5A and FIG. 5B, which discloses a method for manufacturing a third type of self-aligning Schottky-type recessed double-diffused metal-oxide semiconductor structure with self-aligning Schottky in accordance with the present invention. And its brief cross-section. FIG. 5A shows that an auto-aligned polycrystalline silicon gate layer 2 7b is formed on the gate dielectric layer 2 6a; then, a pair of side wall dielectric pad layers 21 3a is formed on the shape. The mask dielectric layer 2 0 3 a is on the side wall and is placed on the side surface portion of the self-aligned highly doped polycrystalline silicon gate layer 2 7b; then, an auto-aligned highly conductive A layer 2 1 4a is formed on the self-aligned highly doped complex crystalline silicon gate layer 2 0 7b between the pair of side wall dielectric pads 21 3a.

Page 17 1246194 V. Description of the invention (12); Then, a planarized cover oxide layer 2 0b is formed on the auto-aligned highly conductive layer 2 1 4a. The pair of side wall dielectric pads 2 1 3 a are composed of silicon dioxide and are stacked by LPCVD. First, a silicon dioxide layer 21 3 (not shown) is deposited on the surface of the structure. And then etch back a thickness of the stacked silicon dioxide layer 2 1 3. The self-aligning highly conductive layer 2 1 4a may be a metal silicide layer formed by a conventional auto-alignment silicidation process or by filling a high-temperature-resistant metal silicide or high-temperature-resistant metal layer first to fill the area. Etching back the high temperature resistant metal silicide or high temperature metal layer deposited to a gap covering the side wall dielectric cushion layer 2 1 3 a to an etch back high temperature resistant metal silicide or high temperature resistant metal of a predetermined thickness Made up of layers. The metal petrified material layer is composed of titanium petrified material (T i S i 0, cobalt silicide (CoS i 2) or nickel silicide (NiSi 2). The high temperature resistant metal petrified material layer may be made from petrified material Yan (WS i 0 and the high-temperature-resistant metal layer is composed of tungsten (W). The planarized cover oxide layer 2 8b is composed of silicon dioxide and is deposited by LPCVD method. The silicon dioxide layer 2 0 8 (not shown) fills the gap between the pair of side wall dielectric pads 2 1 3 a, and then etches back the deposited silicon dioxide layer 2 0 8 A thickness; or use chemical-mechanical polishing (CMP) to planarize the stacked SiO 2 layer 2 0 8 and use the formed mask dielectric layer 2 0 3 a as a flat surface It is worth noting here that the auto-aligned highly doped polycrystalline silicon gate layer 2 7a can be implanted with a high dose before or after the pair of side wall dielectric pads 2 1 3 a is formed. Phosphorus or arsenic dopants are used to add high doping. According to the same process steps shown in Figure 3F and Figure 3G, Figure 5B can

Page 18 1246194 V. Description of the invention (13) Easily available. It can be clearly seen from FIG. 5B that the auto-aligned highly conductive layer 2 1 4 a is the auto-aligned highly doped complex crystal formed between the pair of side wall dielectric pads 2 1 3 a The silicon gate layer is above 207b, so the stray resistance of the gate connection is more effectively reduced than that shown in Fig. 3G. In addition, the pair of side wall dielectric pads 2 1 3 a shown in FIG. 5B can eliminate the highly doped η + diffusion ring 2 0 5 b and the conductive gate layer 2 0 7b / 2 1 4a Possible leakage path and reduce the capacitance between the source ^ and the gate. _ Now refer to FIG. 6A and FIG. 6B, which discloses a continuation of the fabrication of a fourth type of self-aligned Schottky barrier barrier recessed double-diffused metal-oxide semiconductor structure of the present invention. Process steps and their brief cross-sectional views. FIG. 6A shows a self-aligned highly doped compound silicon gate layer 2 0 7b system p formed on the gate dielectric layer 2 0 6 a, and then a pair of side wall dielectric pad layers 2 1 is formed. 3 a, as shown in FIG. 5A; then, the self-aligned highly doped complex crystalline silicon gate layer 2 7b located between the pair of overlying side wall dielectric pads 21 3a uses anisotropic dry etching Farad pre-etching is used to form a groove highly doped polycrystalline silicon gate layer 2 0c; then, an etch-back conductive layer 21 5a is filled between the pair of side wall dielectric pad layers 2 1 3 a A part of the void is formed. Then, a planarized cover oxide layer 2 0b is formed on the etch-back conductive layer 21 5a. The etch-back conductive layer 2 1 5 a is composed of tungsten silicide (WS i 2) or tungsten (W), and a conductive layer 2 1 5 (not shown) is first stacked to fill the pair of side walls. A gap between the dielectric pad layers 2 1 3 a is then etched back to the stacked conductive layers 2 1 5 to a predetermined thickness. Similarly, the planarized capping oxide layer 208b is formed by the same steps as described in FIG. 5A. According to the same process steps described in FIG. 3F and FIG. 3G, FIG. 6B may

Page 19, 1246194 V. Description of the invention to easily 2 1 5 a can now invite the figure of the fifth type of self-structure 70% on the gate to cover the side of 2 0 3 a 2 0 7b side 2 14a series The quasi-highly-doped oxide layer is obtained in accordance with the process steps except for the bottom silicon surface. The continuation of the auto-match on-demand auto-configuration Figure 8 is obtained from the gate (14). It can be clearly seen from FIG. 6B that the etch-back conductive layer can reduce the stray resistance of the gate connection more than that of FIG. 5B. Referring to FIG. 7A and FIG. 7B, it is disclosed that the manufacturing method of a dynamically aligned Schottky barrier barrier-type recessed double-diffusion metal-oxide semiconductor transistor is continued from FIG. 4B and a simplified cross-sectional view thereof. A shows an automatic alignment of a highly doped complex crystalline silicon gate layer 2 0 7b series dielectric layer 2 6 6 b and the thick isolation dielectric layer 2 1 2 a; then, a side wall dielectric pad layer 2 1 3 a is formed on the side wall of the dielectric layer of the forming mask and is formed on the edge surface portion of the self-aligned highly-doped polycrystalline silicon gate layer; then, an auto-aligned highly conductive layer is formed on The pair covers the self-hybrid polysilicon gate layer 2 7b between the side wall dielectric pads 2 1 3 a; then, a planarized cover 2 8b is formed on the auto-aligned highly conductive layer 2 14a above. A thick isolation dielectric layer 2 1 2 a is formed on the surface of the shallow groove. The process steps for forming FIG. 7A are the same as the steps for forming FIG. 6A, so further description may be omitted. Figure 7F and Figure 3G have the same process steps. Figure 7B can be easily compared with Figure 7B and Figure 4E. It can be clearly seen that Figure 7B provides a quasi-high conductive layer 2 1 4a to reduce the spurious of the gate connection. resistance. Referring to FIG. 8A and FIG. 8B, it is disclosed that the sixth quasi-Schottky barrier-type recessed double-diffused metal-oxide semiconductor transistor of the present invention is fabricated. FIG. 4B is a simplified process step and a schematic cross-sectional view thereof. B shows an automatic alignment of the highly doped complex crystalline silicon gate layer 2 0 7b series dielectric layer 2 6 b and the thick isolation dielectric layer 2 1 2; then,

Page 20, 1246194 V. Description of the invention (15) Screen dielectric layer, crystalline silicon gate layer, side wall dielectric 2 0 7b is doped with multiple crystals, and then a layer of 2 1 5 a has the thickness and formation. As shown in FIG. 8B, the stray electricity in FIG. 8 can be summarized. A pair of dielectric layer 2 1 3 a covering the side wall is formed on the side wall of the forming cover 2 0 3 a and is formed on The auto-aligned highly doped complex 207b is above the side surface portion; then, the auto-aligned highly-doped complex crystalline silicon gate layer is located between the pair of overlying electrical pads 2 1 3 a. Isotropic dry etching is used to etch to form a grooved high silicon gate layer 2 0 7 c; then, an etch-back conductive layer 2 1 5 a is formed to form a gap between the side wall dielectric pad 2 1 3 a A part of the planarized oxide layer 2 0 b is formed on the etch-back conductive layer. Basically, the process steps for forming FIG. 8A are the same as in FIG. 8A, except that the isolation dielectric layer 2 1 2 is formed on the surface of the bottom of the shallow groove, so further description can be omitted. It can be easily obtained according to the same process steps described in FIG. 3F and FIG. 3G. Comparing FIG. 8B and FIG. 7B, it can be clearly seen that B has the conductive layer 2 1 5 a to further reduce the gate connection resistance. According to the foregoing description, the advantages and features of the present invention can be as follows: (a) The self-aligning Schottky barrier recessed double-diffusion metal-oxide semiconductor structure of the present invention provides an automatic alignment in the source region. One of the intermediate semiconductor parts is automatically aligned with the Schottky barrier diode and its fabrication does not require a rigorous masking photoresist step. (b) The self-aligning Schottky barrier type recessed double-diffusion gold of the present invention

Page 21 1246194 V. Description of the invention (16) The oxygen semi-electric crystal structure provides an auto-aligned Schottky barrier diode with a moderately doped P-based diffusion ring as a diffusion protection ring to eliminate the automatic Leakage current and soft breakdown at the edge of the Schottky diode. (c) The self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semiconductor structure of the present invention provides an auto-aligned source metal silicide layer that combines a highly doped η + source diffusion ring with a middle The degree-doped p-based diffusion ring is short-circuited to eliminate the bulk effect of the grooved double-diffused metal-oxide semi-electric crystal cell and at the same time act as an auto-alignment Schottky barrier to contact the metal layer. (d) The self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semiconductor structure of the present invention provides a moderately doped P-based diffusion ring and a lightly doped N-epitaxial semiconductor layer. A reverse-biased pn junction is used to squeeze the lightly doped N-epitaxial semiconductor layer under the self-aligning Schottky contact metal layer, so the low-value energy due to the image power reduction effect is generated. A high reverse leakage current at the barrier height can be eliminated. (e) The self-aligning Schottky barrier barrier recessed double-diffusion metal-oxide semiconductor structure of the present invention provides a pair of side wall dielectric pads formed on an auto-aligned highly doped polycrystalline silicon The side surface portion of the gate layer is overlying to eliminate a leakage current path between an auto-aligned highly-doped η + source diffusion ring and the auto-aligned highly-doped complex silicon gate layer. (f) The self-aligning Schottky barrier type recessed double-diffusion gold of the present invention

Page 22 1246194 V. Description of the invention (17) The oxygen semi-electric crystal structure provides an auto-aligned high-conductivity layer formed between the pair of side wall dielectric pads. A etch-back conductive layer in a groove in a highly-doped polycrystalline silicon gate layer above the layer or between the pair of covering side wall dielectric pads to reduce stray resistance of the gate line (g) The self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semiconductor structure provides a thick isolation dielectric layer formed on a bottom semiconductor surface of the shallow recess to reduce the gate-to-drain capacitance. And increase the breakdown voltage between the gate and the pole. The aforementioned self-aligned Schottky barrier barrier recessed η-channel double-diffused metal-oxide semiconductor structure can be easily fabricated by changing the dopant type of the semiconductor region. Bit-groove P-channel double-diffused metal-oxide semiconductor structure. Similarly, the self-aligning Schottky barrier barrier recessed double-diffusion metal-oxide semi-transistor structure can be extended to manufacture insulated gate bipolar transistor (IGBT) and metal-oxide semi-controlled gate fluid (MCT). ). Although the present invention is particularly illustrated and described with reference to the attached examples or connotations, it is only a representative statement and not a limitation. Furthermore, the present invention is not limited to the listed details. Those skilled in the art can also understand that changes of various shapes or details can be made without departing from the true spirit and scope of the present invention, but also belong to the present invention. The category of invention.

Page 1246194 Brief Description of Drawings Figures 1A and 1B show a schematic diagram of a planar double-diffusion metal-oxide half-power transistor of the prior art, wherein Figure 1A shows a schematic cross-sectional view thereof and Figure 1B shows Its equivalent element represents the drawing. FIG. 2A and FIG. 2B are schematic diagrams showing a planar double-diffused metal-oxide semi-electric crystal structure and a Schottky barrier diode bipolar volume structure of the prior art. FIG. 2A shows a schematic cross-sectional view thereof. Figure 2B shows its equivalent component representation. Figures 3A to 3G show the manufacturing steps and a schematic cross-sectional view of manufacturing a first type of self-aligning Schottky barrier double-diffusion metal-oxide semiconductor structure with Schottky barriers. FIGS. 4A to 4E show the continuation of manufacturing a second type of self-aligned Schottky barrier barrier recessed double-diffused metal-oxide semiconductor structure in accordance with the present invention. FIG. Illustration. FIG. 5A and FIG. 5B show the continuation of manufacturing a third type of self-aligning Schottky barrier barrier recessed double-diffusion metal-oxide semiconductor structure of the present invention. FIG. Illustration. FIG. 6A and FIG. 6B show the continuation of manufacturing a fourth type of self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semiconductor structure in accordance with the present invention. FIG. Illustration. FIG. 7A and FIG. 7B show the continuation of manufacturing a fifth type of self-aligned Schottky barrier barrier recessed double-diffused metal-oxide semiconductor structure in accordance with the present invention. FIG. Illustration. FIG. 8A and FIG. 8B show the continuation diagrams of the manufacture of a sixth type of self-alignment Schottky energy barrier recessed double-diffused metal-oxide semiconductor crystal structure of the present invention.

Page 24 1246194 The diagram briefly illustrates the simplified process steps of four A and its brief cross-sectional view represents the figure number description: 201 Lightly doped N- epitaxial silicon layer 2 0 0 Highly doped N + silicon substrate 2 0 2 Buffer oxide layer 2 0 2a / 2 0 2b Shaped buffer oxide layer 2 0 3 Mask dielectric layer 203a Shape mask dielectric layer 2 0 4a P-diffusion region 2 0 4b Moderately doped p-based diffusion ring 2 0 5 a Highly doped η + diffusion region 2 0 5 b Highly doped η + source diffusion ring 2 0 6a / 2 0 6b gate dielectric layer 20 7a etch back highly doped polycrystalline silicon layer 2 0 7b automatically aligned with high doping Complex silicon gate layer 2 0 7c Automatically aligned grooves Highly doped compound silicon gate layer 2 0 8a Planarized oxide layer 208b Planarized oxide layer 209a Side wall dielectric pad 2 1 0 a Tiki contact metal layer 211 source metal layer 212a thick isolation dielectric layer 213a covers side wall dielectric pad layer 2 1 4 a Automatically aligns high temperature metal or metal oxide layer 215a etch back conductive layer _

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Claims (1)

1246194 VI. Scope of patent application 1. A self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semiconductor structure at least includes: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate includes at least A lightly doped epitaxial semiconductor layer is formed on a highly doped semiconductor substrate; an auto-aligned source region is formed on the lightly doped epitaxial semiconductor layer surrounded by a groove gate region, wherein the The alignment source region includes at least a moderately doped radical diffusion ring of a second conductivity type formed in a side portion of the lightly doped epitaxial semiconductor layer and a highly doped source of the first conductivity type. A diffusion ring is formed within a side surface portion of the moderately doped base diffusion ring, and an auto-alignment source contact window is formed in the lightly doped epitaxial semiconductor surrounded by the moderately doped base diffusion ring. Layer, a moderately doped base diffusion ring surrounded by the highly doped source diffusion ring, and a semiconductor surface composed of the highly doped source diffusion ring surrounded by a side wall dielectric pad layer; A recessed gate region is formed in the lightly doped epitaxial semiconductor layer through a forming window, wherein the recessed gate region includes at least one shallow recess for separating a highly doped diffusion region of the first conductivity type into the The highly doped source diffusion ring and a moderately doped diffusion region of the second conductivity type become the moderately doped base diffusion ring, a gate dielectric layer is formed on a groove semiconductor surface of the shallow groove, An auto-aligned high-conductive gate layer is formed on the gate dielectric layer, and an overlying dielectric layer is formed on the auto-aligned high-conductive gate layer; and a source metal layer is formed at least on the auto-aligned source. The zone Page 26 1246194 VI. Scope of patent application Align the source contact window. 2. The self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semi-electric crystal structure as described in item 1 of the patent application scope, wherein the side wall dielectric cushion layer is composed of silicon nitride. Formed on a side wall of the cover dielectric layer within the groove gate region and placed on a side surface portion of a buffer oxide layer within the auto-aligned source region. 3. The self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semiconductor structure described in item 1 of the patent application scope, wherein the forming window uses a mask photoresist step to place the groove A mask dielectric layer over a buffer oxide layer within the gate region is formed by removal. a 4. The self-aligning Schottky barrier barrier-type recessed double-diffused metal-oxide semi-electric crystal structure as described in item 1 of the patent application scope, wherein the moderately doped diffusion region f is used to form the intermediate The doped diffusion ring is formed by implanting a medium-dose dopant in the lightly doped epitaxial semiconductor layer through the forming window. 5. The self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semiconductor structure as described in item 1 of the patent application scope, wherein the highly doped diffusion region is used to form the highly doped source diffusion The ring system uses a rotating high-angle ion implanter to implant a high dose of dopants into a surface portion of the moderately doped diffusion region through the forming window. Page 27 1246194 6. The scope of the patent application is based on the thickness of the base and the surface that can be separated from the upper surface. It is more accurate than the surface of the Xiao individual. It is centered and semi-moved, and the concave structure is described at the bottom. Xiang Jingyi 1 Electric's first half-slot oxygen-concave concave fan Fan Jin shallowly disperses. This special expansion is required in the double-shen type. The concave layer of the groove system 6 should be placed on the forming system layer than the upper and lower dielectric gates. The high-level quasi-dielectrics on the conductive layer of the gate are separated from the thick-segment electrical barriers with high-energy quasi-bases and the special-movements are designed by Xiao Zun. The pair moves its Aa. Fan Jinli San specially invited the double-shen formula such as the groove 7 · concave to have a unique structure, and the layers of the gate are interspersed with broken crystals, complex and complex doped with a high-level accuracy, and the movements should be done automatically. A layer of a shaped electric cladding layer is covered by a small amount of material to cover the layer of oxygen. The heat of the gate is a high-energy quasi-base pair of special electric barriers. Xiao Zizhun moves the pair to 4a. The second half of the oxygen fan Jinli San specifically expanded the double application type such as the groove 8 concave self-covering one pair and one layer in the gate into a silicon-shaped crystal layer is complex miscellaneous gold doped with ancient intertemporary anti-pairing or self-chemical silicon A gold-containing cladding temperature is as high as the resistance layer quasi-gate pair, and the dielectric layer on the side of the wall layer of the gate layer is covered with crystals. Layers of animal electricity are self-chemically covered by the cover of the oxygen cover. The layers are layered and flattened. The walls of the walls are layered with electrical barriers, electrical barriers, barrier heights, and level-to-level barriers. Special action broken Xiao Zijing should be mixed in the complex and mixed with # §, Gao Zhigou's grooves and recesses in the quasi-term crystal pair 1 electric half self-contained oxygen Fan Jinyili scattered containing special expansion package please double Shen type to 9 groove gate Page 28 1246194 VI. Patent application scope Etching automatic alignment of high-temperature-resistant metal silicide or high-temperature-resistant metal layer formed between a pair of side wall dielectric pads The highly-aligned grooves are highly doped polycrystalline The overlying dielectric layer includes at least the pair of overlying side wall dielectric pads and a planarized overlying oxide layer formed between the overlying side wall dielectric pads. 10. The self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semi-electric crystal structure according to item 1 of the scope of patent application, wherein the source metal layer includes at least one self-aligning metal silicide layer A metal layer is formed on the auto-alignment source contact window and a metal layer is placed on a barrier metal layer at least on the auto-alignment metal silicide layer. 1 1. An auto-aligned Schottky barrier-type recessed double-diffused metal-oxide semiconductor device structure comprising at least: a single-crystal silicon substrate of a first conductivity type, wherein the single-crystal silicon substrate includes at least one A lightly doped epitaxial silicon layer is formed on a highly doped silicon substrate; an auto-aligned source region is formed on the lightly doped epitaxial silicon layer surrounded by a recessed gate region, wherein the automatic alignment The quasi-source region includes at least a moderately doped radical diffusion ring of a second conductivity type formed in a side portion of the lightly doped epitaxial silicon layer, and a highly doped source diffusion of the first conductivity type. A ring is formed within a side surface portion of the moderately doped radical diffusion ring, and an auto-aligned source contact window is formed in the lightly-doped heterogeneous stupid stone surrounded by the moderately doped radical diffusion. Layer, surrounded by the diffusive soil of the southern seeding source Page 29 1246194 VI. A forming area of one of the moderately doped base expansion walls in the scope of the patent application is diffused on the concave dielectric gate layer and half of the concave window on the side. Area-shaped grooves are scattered on top of a doped silicon layer with a moving pair and an automatic quasi-source quasi-resistance alignment is placed on the side wall conductor groove gate. With the source gold contacting South Wen, a golden fortune, and a dielectric surface region, the crystals are sequentially staggered into the 1¾ diffusion ring buffer layer, and the silicon layer is doped to a doped ring, and formed. A mask photoresist step is formed by a diffusion ring on a side surface portion of the highly doped source region surrounded by one side of the groove gate oxide layer to define a second conductive type Medium and one of the heterodiffusion regions of the first conductivity type includes a shallow top, an automatic and a cover dielectric power diffusion ring, and a gate dielectric layer aligned with the upper layer to form a conductive surface recess. The grooves are formed with moderate doping at the conductive gate in the self-portion to partially diffuse and expand the shallow shaped pair to form doping. The grooves inward from the scattered region are formed at a quasi-high diffusion doping, and the high doping becomes One of the gate conductive and metal layer window metal metal layer temperature gold is formed at least on the inside of the auto-aligned source region, wherein the source metal layer includes at least one silicide layer formed on the auto-opposition barrier The metal layer is above the stone oxide layer. The quasi-source contact window is formed at least in the second. The self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semiconductor structure is described in item 11 of the patent application scope, wherein the forming window is made of A mask photoresist step is performed by removing a mask dielectric layer over the buffer oxide layer within the groove gate region and forming it sequentially. Page 30 1246194 VI. Scope of patent application An automatic alignment ion implantation window for the moderately doped diffusion region and the highly doped diffusion region. 1 3. The self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semi-electric crystal structure according to item 11 of the patent application scope, wherein the self-aligning highly conductive gate layer includes at least one auto-pair Quasi-highly doped polycrystalline silicon gate or an auto-aligned highly doped poly-crystalline silicon gate with a pair of side walls covering the dielectric pad with an auto-aligned high-temperature resistant metal silicide or high-temperature resistant Metal layer 14 4. The self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semiconductor structure as described in item 11 of the scope of patent application, wherein the self-aligning highly conductive gate layer includes at least one Highly doped compound silicon gate layer with automatic alignment groove and an etchback automatic alignment high temperature resistant metal silicide or high temperature resistant metal layer formed between a pair of side wall dielectric pads The trench is highly doped on the polycrystalline silicon gate layer. 1 5. A type of self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semi-electric crystal structure, including at least: a single-crystal silicon substrate of a first conductivity type, wherein the single-crystal silicon substrate includes at least A lightly doped stupid stone layer is formed on a highly doped stone layer; an auto-aligned source region is formed on the lightly doped epitaxial silicon layer surrounded by a groove gate region, wherein The auto-aligned source area contains at least one Page 31, 1246194 VI. Patent application scope One side diffusion ring of the second conductivity type silicon layer, and the middle and south of the forming window area enclosed by the ring, the recessed impurity diffusion in the diffusion area, and moderate formation At a self-enclosed gate of the doped hetero-source doping groove, the light doping is formed in the trench gate region to become a middle portion of the doping base. A source contact window-shaped stupid layer of the first conductive doped radical diffusion ring, the ring, and a half formed by two sides of the doped radical diffusion ring in the first conductive doped radical diffusion ring are formed in the step of pushing the side wall conductor. Formed on the sides of the medium heterodielectric dielectric surface to determine the edge of the doped heterodiffusion layer surrounded by the heterodiffusion diffusion ring of a highly doped source surface portion of the lightly doped heterogeneous crystal. Each of the mask photoresistance two-conductivity type and the moderately doped diffusion region within the first layer and the first layer further includes at least one heterodiffusion ring and a bottom groove of the groove in the gate. Dielectric coating Cover the dielectric layer. A source gold alignment source contact window is aligned on the high-temperature resistant gold and a metal is aligned on the high temperature. The two exchange diffusion bad grooves are on the silicon side wall and formed on the metal layer to the mouth. The silicidation layer is placed on the thicker surface of the metal silicon and is formed on the automatic pair, wherein the upper and a thicker barriers are highly conductive to the barrier metallization layer formed from the source gold layer. on. One guide, one shallow recess, one intermediate gate, one pair of dielectric gates, one pair of dielectric gates, one layer of electrical layer surface layer, one layer of doped layer, one layer of dielectric, and one layer of quasi-high electrical layer. Partially diffuses to form a layered conductive layer; the area contains the source contact and the shape of the dopant; the doped region is separated from the scattered region in the gate layer and a diffusion dopant, and its surface becomes Dimple the shallow to form one of the touch windows to form the auto Page 32, 1246194 VI. Application scope of patent 16. As described in item 15 of the scope of patent application, the self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semi-electric crystal structure is adopted, in which the side wall A dielectric pad layer composed of silicon nitride is formed on a side wall of the covering dielectric layer within the gate region of the groove and is a buffer oxide layer disposed within the auto-aligned source region. On one of the side surface parts. Special application for Ru Ru Arc " High-energy quasi-base pair of oxygen-embedded guide barriers with scattered double-slot recesses, special movements, Xiao Zi-zhuan, and JJy ^ α, the structure of the pair FO # > € & gt 1 drink half covered cladding gate silicon crystal complex. The layer-changing high-electricity quasi-dielectric cover is moved from the one to the other. It contains a cladding-less silicon to chemical layer oxygen gate thermoelectric rod. The recessed gate is electrically embedded and the barrier is highly capable. The quasi-covered base is overlaid with a special layer. The self-aligned layer of the silicon is moved by its complex structure. Since the gold temperature and high resistance to the ground from the 1st floor. The electric layer is a dielectric metal wall with a warm side and a high-side cover or covering. The silicon alloy belongs to the 11th category. Fan Li specially invited Zhongru ^ ¾ semi-oxygen gold diffused double slot recessed embedded guide barrier high energy standard To Xiao Qin Αν Xiao Zizhun should visit Zhongli ali JJy, and the structure of the structure of the crystal and the layered gate layer of the crystal is re-warming, mixed with high-doped high-resistance or groove-concave quasi-silicon. The quasi-packed pair is less moving to the self-level layer. The gate is returned with a complex mixed high-groove recessed quasi-paired layer. Capping on the side Page 33, 1246194 VI. Patent application scope 20. The self-aligning Schottky barrier barrier recessed double-diffused metal-oxide semiconductor structure described in item 15 of the patent application scope, wherein the thicker isolation The dielectric layer is composed of silicon dioxide.A silicon dioxide layer is first stacked to fill the shallow groove, and then the silicon dioxide layer is etched back to a depth equal to or less than the junction depth of the moderately doped base diffusion ring. A depth. Page 34