JP2020519996A5 - - Google Patents

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Publication number
JP2020519996A5
JP2020519996A5 JP2019559364A JP2019559364A JP2020519996A5 JP 2020519996 A5 JP2020519996 A5 JP 2020519996A5 JP 2019559364 A JP2019559364 A JP 2019559364A JP 2019559364 A JP2019559364 A JP 2019559364A JP 2020519996 A5 JP2020519996 A5 JP 2020519996A5
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JP
Japan
Prior art keywords
packet
processor
transmitter circuit
processing
output data
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JP2019559364A
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English (en)
Japanese (ja)
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JP7073403B2 (ja
JP2020519996A (ja
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Priority claimed from US15/595,242 external-priority patent/US10872393B2/en
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JP2019559364A 2017-05-15 2018-01-05 高スループット内部通信プロトコルを用いる画像処理プロセッサ Active JP7073403B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/595,242 US10872393B2 (en) 2017-05-15 2017-05-15 Image processor with high throughput internal communication protocol
US15/595,242 2017-05-15
PCT/US2018/012521 WO2018212793A1 (en) 2017-05-15 2018-01-05 Image processor with high throughput internal communication protocol

Publications (3)

Publication Number Publication Date
JP2020519996A JP2020519996A (ja) 2020-07-02
JP2020519996A5 true JP2020519996A5 (enExample) 2020-10-01
JP7073403B2 JP7073403B2 (ja) 2022-05-23

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ID=61094589

Family Applications (1)

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JP2019559364A Active JP7073403B2 (ja) 2017-05-15 2018-01-05 高スループット内部通信プロトコルを用いる画像処理プロセッサ

Country Status (7)

Country Link
US (1) US10872393B2 (enExample)
EP (1) EP3625755B1 (enExample)
JP (1) JP7073403B2 (enExample)
KR (1) KR102284078B1 (enExample)
CN (1) CN110574068B (enExample)
TW (1) TWI718359B (enExample)
WO (1) WO2018212793A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10489878B2 (en) * 2017-05-15 2019-11-26 Google Llc Configurable and programmable image processor unit
WO2021050951A1 (en) * 2019-09-11 2021-03-18 Intel Corporation Hardware queue scheduling for multi-core computing environments
KR102632507B1 (ko) * 2023-06-20 2024-01-31 쿠팡 주식회사 스트리밍 서비스를 위한 비디오 가공 방법 및 그 시스템

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JPH11203192A (ja) * 1998-01-16 1999-07-30 Sony Corp 並列プロセッサおよび演算処理方法
US7453878B1 (en) * 2000-07-21 2008-11-18 Silicon Graphics, Inc. System and method for ordering of data transferred over multiple channels
US7966661B2 (en) * 2004-04-29 2011-06-21 Microsoft Corporation Network amplification attack mitigation
US7478811B2 (en) 2004-08-02 2009-01-20 Garrett Johnson Wave driven gaming apparatus
US7793074B1 (en) * 2006-04-14 2010-09-07 Tilera Corporation Directing data in a parallel processing environment
WO2008005629A2 (en) * 2006-05-26 2008-01-10 Riverbed Technology, Inc. Throttling of predictive acks in an accelerated network communication system
US8478834B2 (en) * 2007-07-12 2013-07-02 International Business Machines Corporation Low latency, high bandwidth data communications between compute nodes in a parallel computer
JP2010218415A (ja) * 2009-03-18 2010-09-30 Olympus Corp ハードウエアスイッチ及び分散処理システム
JP5316131B2 (ja) * 2009-03-18 2013-10-16 株式会社リコー データ転送システム及びデータ転送方法
US8700877B2 (en) 2009-09-25 2014-04-15 Nvidia Corporation Address mapping for a parallel thread processor
US20110249744A1 (en) * 2010-04-12 2011-10-13 Neil Bailey Method and System for Video Processing Utilizing N Scalar Cores and a Single Vector Core
US9021237B2 (en) * 2011-12-20 2015-04-28 International Business Machines Corporation Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source thread
JP5966561B2 (ja) * 2012-04-20 2016-08-10 富士通株式会社 通信装置および通信方法
US9489322B2 (en) 2013-09-03 2016-11-08 Intel Corporation Reducing latency of unified memory transactions
US20160188519A1 (en) * 2014-12-27 2016-06-30 Intel Corporation Method, apparatus, system for embedded stream lanes in a high-performance interconnect
US9965824B2 (en) * 2015-04-23 2018-05-08 Google Llc Architecture for high performance, power efficient, programmable image processing
US9792044B2 (en) * 2016-02-12 2017-10-17 Oracle International Corporation Decompression history buffer read/write pipelines
US10437616B2 (en) * 2016-12-31 2019-10-08 Intel Corporation Method, apparatus, system for optimized work submission to an accelerator work queue
US10764209B2 (en) * 2017-03-28 2020-09-01 Mellanox Technologies Tlv Ltd. Providing a snapshot of buffer content in a network element using egress mirroring

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