JP7073403B2 - 高スループット内部通信プロトコルを用いる画像処理プロセッサ - Google Patents

高スループット内部通信プロトコルを用いる画像処理プロセッサ Download PDF

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Publication number
JP7073403B2
JP7073403B2 JP2019559364A JP2019559364A JP7073403B2 JP 7073403 B2 JP7073403 B2 JP 7073403B2 JP 2019559364 A JP2019559364 A JP 2019559364A JP 2019559364 A JP2019559364 A JP 2019559364A JP 7073403 B2 JP7073403 B2 JP 7073403B2
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data
data packet
processor
receiver
transmitter circuit
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Japanese (ja)
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JP2020519996A (ja
JP2020519996A5 (enExample
Inventor
レッドグレイブ，ジェイソン・ルパート
メイクスナー，アルバート
ヂュー，チウリン
キム，ジ
バシリエブ，アルテム
シャチャム，オフェル
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Google LLC
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Google LLC
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/39—Credit based
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9078—Intermediate storage in different physical parts of a node or terminal using an external memory or storage device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
JP2019559364A 2017-05-15 2018-01-05 高スループット内部通信プロトコルを用いる画像処理プロセッサ Active JP7073403B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/595,242 US10872393B2 (en) 2017-05-15 2017-05-15 Image processor with high throughput internal communication protocol
US15/595,242 2017-05-15
PCT/US2018/012521 WO2018212793A1 (en) 2017-05-15 2018-01-05 Image processor with high throughput internal communication protocol

Publications (3)

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JP2020519996A JP2020519996A (ja) 2020-07-02
JP2020519996A5 JP2020519996A5 (enExample) 2020-10-01
JP7073403B2 true JP7073403B2 (ja) 2022-05-23

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JP2019559364A Active JP7073403B2 (ja) 2017-05-15 2018-01-05 高スループット内部通信プロトコルを用いる画像処理プロセッサ

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Country Link
US (1) US10872393B2 (enExample)
EP (1) EP3625755B1 (enExample)
JP (1) JP7073403B2 (enExample)
KR (1) KR102284078B1 (enExample)
CN (1) CN110574068B (enExample)
TW (1) TWI718359B (enExample)
WO (1) WO2018212793A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10489878B2 (en) * 2017-05-15 2019-11-26 Google Llc Configurable and programmable image processor unit
WO2021050951A1 (en) * 2019-09-11 2021-03-18 Intel Corporation Hardware queue scheduling for multi-core computing environments
KR102632507B1 (ko) * 2023-06-20 2024-01-31 쿠팡 주식회사 스트리밍 서비스를 위한 비디오 가공 방법 및 그 시스템

Citations (3)

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JP2010218415A (ja) 2009-03-18 2010-09-30 Olympus Corp ハードウエアスイッチ及び分散処理システム
JP2010218351A (ja) 2009-03-18 2010-09-30 Ricoh Co Ltd データ転送システム及びデータ転送方法
US20160314555A1 (en) 2015-04-23 2016-10-27 Google Inc. Architecture for high performance, power efficient, programmable image processing

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US7453878B1 (en) * 2000-07-21 2008-11-18 Silicon Graphics, Inc. System and method for ordering of data transferred over multiple channels
US7966661B2 (en) * 2004-04-29 2011-06-21 Microsoft Corporation Network amplification attack mitigation
US7478811B2 (en) 2004-08-02 2009-01-20 Garrett Johnson Wave driven gaming apparatus
US7793074B1 (en) * 2006-04-14 2010-09-07 Tilera Corporation Directing data in a parallel processing environment
WO2008005629A2 (en) * 2006-05-26 2008-01-10 Riverbed Technology, Inc. Throttling of predictive acks in an accelerated network communication system
US8478834B2 (en) * 2007-07-12 2013-07-02 International Business Machines Corporation Low latency, high bandwidth data communications between compute nodes in a parallel computer
US8700877B2 (en) 2009-09-25 2014-04-15 Nvidia Corporation Address mapping for a parallel thread processor
US20110249744A1 (en) * 2010-04-12 2011-10-13 Neil Bailey Method and System for Video Processing Utilizing N Scalar Cores and a Single Vector Core
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JP5966561B2 (ja) * 2012-04-20 2016-08-10 富士通株式会社 通信装置および通信方法
US9489322B2 (en) 2013-09-03 2016-11-08 Intel Corporation Reducing latency of unified memory transactions
US20160188519A1 (en) * 2014-12-27 2016-06-30 Intel Corporation Method, apparatus, system for embedded stream lanes in a high-performance interconnect
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US10437616B2 (en) * 2016-12-31 2019-10-08 Intel Corporation Method, apparatus, system for optimized work submission to an accelerator work queue
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JP2010218415A (ja) 2009-03-18 2010-09-30 Olympus Corp ハードウエアスイッチ及び分散処理システム
JP2010218351A (ja) 2009-03-18 2010-09-30 Ricoh Co Ltd データ転送システム及びデータ転送方法
US20160314555A1 (en) 2015-04-23 2016-10-27 Google Inc. Architecture for high performance, power efficient, programmable image processing

Non-Patent Citations (1)

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Title
Nicola Concer et al.，"CTC: an End-To-End Flow Control Protocol for Multi-Core Systems-on-Chip"，2009 3rd ACM/IEEE International Symposium on Networks-on-Chip，米国，IEEE，2009年05月10日，pp.1-10

Also Published As

Publication number Publication date
TWI718359B (zh) 2021-02-11
US20180330465A1 (en) 2018-11-15
CN110574068A (zh) 2019-12-13
CN110574068B (zh) 2023-06-27
US10872393B2 (en) 2020-12-22
EP3625755B1 (en) 2024-09-04
KR20190133028A (ko) 2019-11-29
WO2018212793A1 (en) 2018-11-22
TW201901609A (zh) 2019-01-01
JP2020519996A (ja) 2020-07-02
EP3625755A1 (en) 2020-03-25
KR102284078B1 (ko) 2021-07-30

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