CN110574068B - 具有高吞吐量内部通信协议的图像处理器 - Google Patents

具有高吞吐量内部通信协议的图像处理器 Download PDF

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Publication number
CN110574068B
CN110574068B CN201880028900.3A CN201880028900A CN110574068B CN 110574068 B CN110574068 B CN 110574068B CN 201880028900 A CN201880028900 A CN 201880028900A CN 110574068 B CN110574068 B CN 110574068B
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China
Prior art keywords
receiver
processor
data packet
data
sent
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Chinese (zh)
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CN110574068A (zh
Inventor
J.R.雷德格雷夫
A.梅克斯纳
Q.朱
J.金
A.瓦西尔耶夫
O.沙查姆
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Google LLC
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Google LLC
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/39—Credit based
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9078—Intermediate storage in different physical parts of a node or terminal using an external memory or storage device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
CN201880028900.3A 2017-05-15 2018-01-05 具有高吞吐量内部通信协议的图像处理器 Active CN110574068B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/595,242 US10872393B2 (en) 2017-05-15 2017-05-15 Image processor with high throughput internal communication protocol
US15/595,242 2017-05-15
PCT/US2018/012521 WO2018212793A1 (en) 2017-05-15 2018-01-05 Image processor with high throughput internal communication protocol

Publications (2)

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CN110574068A CN110574068A (zh) 2019-12-13
CN110574068B true CN110574068B (zh) 2023-06-27

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US (1) US10872393B2 (enExample)
EP (1) EP3625755B1 (enExample)
JP (1) JP7073403B2 (enExample)
KR (1) KR102284078B1 (enExample)
CN (1) CN110574068B (enExample)
TW (1) TWI718359B (enExample)
WO (1) WO2018212793A1 (enExample)

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* Cited by examiner, † Cited by third party
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US10489878B2 (en) * 2017-05-15 2019-11-26 Google Llc Configurable and programmable image processor unit
WO2021050951A1 (en) * 2019-09-11 2021-03-18 Intel Corporation Hardware queue scheduling for multi-core computing environments
KR102632507B1 (ko) * 2023-06-20 2024-01-31 쿠팡 주식회사 스트리밍 서비스를 위한 비디오 가공 방법 및 그 시스템

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JP2010218415A (ja) * 2009-03-18 2010-09-30 Olympus Corp ハードウエアスイッチ及び分散処理システム
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JP5966561B2 (ja) * 2012-04-20 2016-08-10 富士通株式会社 通信装置および通信方法
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Also Published As

Publication number Publication date
TWI718359B (zh) 2021-02-11
US20180330465A1 (en) 2018-11-15
CN110574068A (zh) 2019-12-13
US10872393B2 (en) 2020-12-22
JP7073403B2 (ja) 2022-05-23
EP3625755B1 (en) 2024-09-04
KR20190133028A (ko) 2019-11-29
WO2018212793A1 (en) 2018-11-22
TW201901609A (zh) 2019-01-01
JP2020519996A (ja) 2020-07-02
EP3625755A1 (en) 2020-03-25
KR102284078B1 (ko) 2021-07-30

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