KR102284078B1 - 고 처리율의 내부 통신 프로토콜을 구비한 이미지 프로세서 - Google Patents

고 처리율의 내부 통신 프로토콜을 구비한 이미지 프로세서 Download PDF

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Publication number
KR102284078B1
KR102284078B1 KR1020197031167A KR20197031167A KR102284078B1 KR 102284078 B1 KR102284078 B1 KR 102284078B1 KR 1020197031167 A KR1020197031167 A KR 1020197031167A KR 20197031167 A KR20197031167 A KR 20197031167A KR 102284078 B1 KR102284078 B1 KR 102284078B1
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South Korea
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processor
packet
data
image
packets
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Korean (ko)
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KR20190133028A (ko
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제이슨 루퍼트 레드그레이브
알버트 마익스너
치울링 주
지 김
아르팀 바실리에프
오페르 샤캄
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구글 엘엘씨
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/39—Credit based
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9078—Intermediate storage in different physical parts of a node or terminal using an external memory or storage device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
KR1020197031167A 2017-05-15 2018-01-05 고 처리율의 내부 통신 프로토콜을 구비한 이미지 프로세서 Active KR102284078B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/595,242 US10872393B2 (en) 2017-05-15 2017-05-15 Image processor with high throughput internal communication protocol
US15/595,242 2017-05-15
PCT/US2018/012521 WO2018212793A1 (en) 2017-05-15 2018-01-05 Image processor with high throughput internal communication protocol

Publications (2)

Publication Number Publication Date
KR20190133028A KR20190133028A (ko) 2019-11-29
KR102284078B1 true KR102284078B1 (ko) 2021-07-30

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US (1) US10872393B2 (enExample)
EP (1) EP3625755B1 (enExample)
JP (1) JP7073403B2 (enExample)
KR (1) KR102284078B1 (enExample)
CN (1) CN110574068B (enExample)
TW (1) TWI718359B (enExample)
WO (1) WO2018212793A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10489878B2 (en) * 2017-05-15 2019-11-26 Google Llc Configurable and programmable image processor unit
US12309067B2 (en) * 2019-09-11 2025-05-20 Intel Corporation Hardware queue scheduling for multi-core computing environments
KR102632507B1 (ko) * 2023-06-20 2024-01-31 쿠팡 주식회사 스트리밍 서비스를 위한 비디오 가공 방법 및 그 시스템

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101312905B1 (ko) * 2004-04-29 2013-09-30 마이크로소프트 코포레이션 네트워크 증폭 공격 완화 방법
US20150067433A1 (en) * 2013-09-03 2015-03-05 Mahesh Wagh Reducing Latency OF Unified Memory Transactions

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11203192A (ja) * 1998-01-16 1999-07-30 Sony Corp 並列プロセッサおよび演算処理方法
US7453878B1 (en) * 2000-07-21 2008-11-18 Silicon Graphics, Inc. System and method for ordering of data transferred over multiple channels
US7478811B2 (en) 2004-08-02 2009-01-20 Garrett Johnson Wave driven gaming apparatus
US7793074B1 (en) * 2006-04-14 2010-09-07 Tilera Corporation Directing data in a parallel processing environment
WO2008005629A2 (en) * 2006-05-26 2008-01-10 Riverbed Technology, Inc. Throttling of predictive acks in an accelerated network communication system
US8478834B2 (en) * 2007-07-12 2013-07-02 International Business Machines Corporation Low latency, high bandwidth data communications between compute nodes in a parallel computer
JP5316131B2 (ja) * 2009-03-18 2013-10-16 株式会社リコー データ転送システム及びデータ転送方法
JP2010218415A (ja) * 2009-03-18 2010-09-30 Olympus Corp ハードウエアスイッチ及び分散処理システム
US8700877B2 (en) 2009-09-25 2014-04-15 Nvidia Corporation Address mapping for a parallel thread processor
US20110249744A1 (en) * 2010-04-12 2011-10-13 Neil Bailey Method and System for Video Processing Utilizing N Scalar Cores and a Single Vector Core
US9021237B2 (en) * 2011-12-20 2015-04-28 International Business Machines Corporation Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source thread
JP5966561B2 (ja) * 2012-04-20 2016-08-10 富士通株式会社 通信装置および通信方法
US20160188519A1 (en) * 2014-12-27 2016-06-30 Intel Corporation Method, apparatus, system for embedded stream lanes in a high-performance interconnect
US9965824B2 (en) * 2015-04-23 2018-05-08 Google Llc Architecture for high performance, power efficient, programmable image processing
US9792044B2 (en) * 2016-02-12 2017-10-17 Oracle International Corporation Decompression history buffer read/write pipelines
US10437616B2 (en) * 2016-12-31 2019-10-08 Intel Corporation Method, apparatus, system for optimized work submission to an accelerator work queue
US10764209B2 (en) * 2017-03-28 2020-09-01 Mellanox Technologies Tlv Ltd. Providing a snapshot of buffer content in a network element using egress mirroring

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101312905B1 (ko) * 2004-04-29 2013-09-30 마이크로소프트 코포레이션 네트워크 증폭 공격 완화 방법
US20150067433A1 (en) * 2013-09-03 2015-03-05 Mahesh Wagh Reducing Latency OF Unified Memory Transactions

Also Published As

Publication number Publication date
KR20190133028A (ko) 2019-11-29
JP7073403B2 (ja) 2022-05-23
EP3625755A1 (en) 2020-03-25
CN110574068B (zh) 2023-06-27
CN110574068A (zh) 2019-12-13
US20180330465A1 (en) 2018-11-15
TW201901609A (zh) 2019-01-01
EP3625755B1 (en) 2024-09-04
JP2020519996A (ja) 2020-07-02
TWI718359B (zh) 2021-02-11
US10872393B2 (en) 2020-12-22
WO2018212793A1 (en) 2018-11-22

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KR102284078B1 (ko) 고 처리율의 내부 통신 프로토콜을 구비한 이미지 프로세서

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