JP2020515050A - ディープソースコンタクトを備えたパワーmosfet - Google Patents
ディープソースコンタクトを備えたパワーmosfet Download PDFInfo
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- JP2020515050A JP2020515050A JP2019539222A JP2019539222A JP2020515050A JP 2020515050 A JP2020515050 A JP 2020515050A JP 2019539222 A JP2019539222 A JP 2019539222A JP 2019539222 A JP2019539222 A JP 2019539222A JP 2020515050 A JP2020515050 A JP 2020515050A
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Abstract
Description
Claims (16)
- 集積回路(IC)であって、
頂部表面及び底部表面を有する半導体基板、及び
前記半導体基板に形成される少なくとも1つの金属酸化物半導体電界効果トランジスタ(MOSFET)セル、
を含み、
前記MOSFETセルが、共通ドレインコンタクトにおいて互いに結合される一対のMOSFETデバイスを含み、
少なくとも1つのMOSFETデバイスが、前記底部表面近傍の前記半導体基板における基板コンタクト領域内へ延在するソースコンタクト(SCT)トレンチを含み、前記SCTトレンチが、前記少なくとも1つのMOSFETデバイスのポリシリコンゲートの線形部より短い前記頂部表面に沿った長さを有し、前記SCTトレンチが、曲線レイアウトジオメトリを有する前記ポリシリコンゲートの相補的輪郭に整合する、
IC。 - 請求項1に記載のICであって、MOSFETセルのアレイを更に含み、
前記アレイの周辺セルが、前記半導体基板に形成される周辺MOSFETデバイスと非活性回路部とを含む、
IC。 - 請求項2に記載のICであって、前記周辺MOSFETデバイスが、前記頂部表面に沿って第2の長さを有する第2のポリシリコンゲートを含み、前記第2の長さが、前記少なくとも1つのMOSFETデバイスの前記ポリシリコンゲートの長さより短い、IC。
- 請求項2に記載のICであって、前記周辺MOSFETデバイスが、前記頂部表面に沿って第2の長さを有する第2のポリシリコンゲートを含み、前記第2の長さが、前記少なくとも1つのMOSFETデバイスの前記ポリシリコンゲートの長さと同じである、IC。
- 請求項2に記載のICであって、前記周辺MOSFETデバイスのフィールドプレートに結合されるグラウンドタブを更に含む、IC。
- 請求項5に記載のICであって、前記フィールドプレートが、チタン、窒化チタン(Ti/TiN)、タングステン、及びTiタングステン(Ti−W)のグループから選択される材料で形成される、少なくとも1つの耐火性金属材料層を含む、IC。
- 請求項1に記載のICであって、前記SCTトレンチが、少なくとも2:1のアスペクト比を有する、IC。
- 請求項1に記載のICであって、前記SCTトレンチが、前記少なくとも1つのMOSFETデバイスのソース端子との電気的接触を形成するための耐火性金属又は白金族金属(PGM)フィラーを含む金属性プラグで充填される、IC。
- 横方向拡散金属酸化物半導体トランジスタ(LDMOS)デバイスであって、
頂部表面及び底部表面を有する半導体基板であって、前記頂部表面に近接して配置されるドープされた層を有し、上側表面を有する、前記半導体基板、
前記ドープされた層の前記上側表面近傍の前記ドープされた層において配置される第1の導電型のソース及びドレイン領域であって、前記ソース及びドレイン領域が、互いに離間され、前記ドープされた層に形成される第2の導電型のチャネル領域によって分離され、前記チャネル領域が、前記ソース領域の下に延在する部分を有し、前記ドレイン領域が、前記チャネル領域に近接して形成される軽くドープされたドレイン(LDD)領域を含む、前記第1の導電型のソース及びドレイン領域、
前記軽くドープされたドレイン領域によって前記チャネル領域から離間されるドープされたドレインコンタクト領域、
上側表面及び側壁表面を有する導電ゲートであって、前記チャネル領域の上に形成されるゲート誘電体層の上に形成され、前記ソース及びドレイン領域に少なくとも部分的に重なる、前記導電ゲート、
前記ドープされた層に形成されるソースコンタクト(SCT)トレンチに配置される導体を介して前記ソース領域及び前記半導体基板を接続し、前記半導体基板における基板コンタクト領域内へ延在する導電経路であって、前記SCTトレンチが、前記導電ゲートの線形部より短い前記頂部表面に沿った長さを有し、前記SCTトレンチが、曲線ジオメトリを有する前記導電ゲートの相補的輪郭と整合される、前記導電経路、
前記導電ゲートの前記上側表面及び側壁表面の上の第1の絶縁層、
前記軽くドープされたドレイン領域及び前記第1の絶縁層の少なくとも一部の上のフィールドプレート層であって、前記ソース領域に接続される、前記フィールドプレート、
前記フィールドプレートの層、前記第1の絶縁層、及び前記トレンチの上の第2の絶縁層、及び
前記ドレインコンタクト領域に電気的に結合されるドレイン電極、
を含む、LDMOSデバイス。 - 請求項9に記載のLDMOSデバイスであって、前記SCTトレンチが、少なくとも2:1のアスペクト比を有する、LDMOSデバイス。
- 請求項9に記載のLDMOSデバイスであって、前記フィールドプレートが、チタン、窒化チタン(Ti/TiN)、タングステン、及びTiタングステン(Ti−W)のグループから選択される材料で形成される、少なくとも1つの耐火性金属材料層を含む、LDMOSデバイス。
- 請求項9に記載のLDMOSデバイスであって、前記SCTトレンチが、耐火性金属又は白金族金属(PGM)フィラーを含む導体を形成する金属性プラグで充填される、LDMOSデバイス。
- パワー金属酸化物半導体電界効果トランジスタ(MOSFET)集積回路を製造する方法であって、
頂部表面及び底部表面を有する半導体基板を提供すること、
前記半導体表面の前記頂部表面に近接し、上側表面を有する、ドープされた層を形成すること、
前記ドープされた層の前記上側表面近傍の前記ドープされた層において配置される第1の導電型のソース及びドレイン領域を形成することであって、前記ソース及びドレイン領域が、互いに離間され、前記ドープされた層に形成される第2の導電型のチャネル領域によって分離され、前記チャネル領域が、前記ソース領域の下に延在する部分を有し、前記ドレイン領域が、前記チャネル領域に近接して形成される軽くドープされたドレイン(LDD)領域を含む、前記第1の導電型のソース及びドレイン領域を形成すること、
前記軽くドープされたドレイン領域によって前記チャネル領域から離間される、ドープされたドレインコンタクト領域を形成すること、
上側表面及び側壁表面を有する導電ゲートを形成することであって、前記チャネル領域の上に形成されるゲート誘電体層の上に形成され、前記ソース及びドレイン領域に少なくとも部分的に重なる前記導電ゲートを形成すること、
前記ドープされた層に形成されるソースコンタクト(SCT)トレンチに配置される導体を介して前記ソース領域及び前記半導体基板を接続し、前記半導体基板における基板コンタクト領域内へ延在する、導電経路を形成することであって、前記SCTトレンチが、前記導電ゲートの線形部より短い前記頂部表面に沿った長さを有し、前記SCTトレンチが、曲線ジオメトリを有する前記導電ゲートの相補的輪郭と整合される、前記導電経路を形成すること、
前記導電ゲートの前記上側表面及び側壁表面の上に第1の絶縁層を形成すること、
前記軽くドープされたドレイン領域の上にフィールドプレート層を形成することであって、前記ソース領域に接続される、前記フィールドプレート層を形成すること、
前記フィールドプレートの層、及び前記第1の絶縁層、及び前記トレンチの上の第2の絶縁層を形成すること、及び、
前記ドレインコンタクト領域に電気的に結合されるドレイン電極を形成すること、
を含む、方法。 - 請求項13に記載の方法であって、前記SCTトレンチが、少なくとも2:1のアスペクト比を有する、方法。
- 請求項13に記載の方法であって、前記フィールドプレート層が、チタン、窒化チタン(Ti/TiN)、タングステン、及びTiタングステン(Ti−W)のグループから選択される材料で形成される、少なくとも1つの耐火性金属材料層を含む、方法。
- 請求項13に記載の方法であって、前記SCTトレンチが、耐火性金属又は白金族金属(PGM)フィラーを含む導体を形成する金属性プラグで充填される、方法。
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