JP2020194900A - Electronic circuit device - Google Patents

Electronic circuit device Download PDF

Info

Publication number
JP2020194900A
JP2020194900A JP2019100087A JP2019100087A JP2020194900A JP 2020194900 A JP2020194900 A JP 2020194900A JP 2019100087 A JP2019100087 A JP 2019100087A JP 2019100087 A JP2019100087 A JP 2019100087A JP 2020194900 A JP2020194900 A JP 2020194900A
Authority
JP
Japan
Prior art keywords
electronic circuit
circuit device
electronic component
electronic
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2019100087A
Other languages
Japanese (ja)
Other versions
JP7332094B2 (en
Inventor
緒方 敏洋
Toshihiro Ogata
敏洋 緒方
明彦 松延
Akihiko Matsunobe
明彦 松延
恒平 池田
Kohei Ikeda
恒平 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP2019100087A priority Critical patent/JP7332094B2/en
Publication of JP2020194900A publication Critical patent/JP2020194900A/en
Application granted granted Critical
Publication of JP7332094B2 publication Critical patent/JP7332094B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10Energy storage using batteries

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Battery Mounting, Suspending (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

To provide an electronic circuit device capable of facilitating achievement of high-density packaging and airtight structure as well as size reduction and high reliability.SOLUTION: An electronic circuit 20 is configured so that an electronic component is packaged into a recessed part formed at one surface of a packaging substrate and sealed with resin 7 to package the electronic component under an airtight state. At the other surface of the packaging substrate, other electronic components 6b-6d are packaged for high-density packaging. Through a wiring pattern 9, a plurality of electrodes 5 connected with the electronic components are set as a small-sized aggregate of divided electrodes for miniaturization and high reliability.SELECTED DRAWING: Figure 6

Description

本発明は、電子部品が実装基板に実装されている電子回路装置に関し、特に気密状態の実装が求められる電子部品が実装される電子回路装置に関する。 The present invention relates to an electronic circuit device in which electronic components are mounted on a mounting board, and more particularly to an electronic circuit device in which electronic components required to be mounted in an airtight state are mounted.

スマートフォンやタブレット端末などのモバイル機器、腕時計型歩数計などのウェアラブル機器等では高機能化と小型化の要請が強く、これらの機器に搭載される電子回路装置は、小型化が求められている。 Mobile devices such as smartphones and tablet terminals, wearable devices such as wristwatch-type pedometers, etc. are strongly required to have higher functionality and miniaturization, and the electronic circuit devices mounted on these devices are required to be miniaturized.

電子回路装置を小型化するためには、実装基板に電子部品を高密度実装するのが好ましい。高密度実装された電子回路装置は種々提案されている(例えば、特許文献1等)。 In order to reduce the size of an electronic circuit device, it is preferable to mount electronic components on a mounting board at a high density. Various high-density mounted electronic circuit devices have been proposed (for example, Patent Document 1 and the like).

一方、実装基板に実装される電子部品の中には、大気中の水分等により特性が劣化するため、気密状態で実装する必要があることが知られている。例えば、全固体電池では、ガラス封止により気密状態を保つ方法が採用されている(特許文献2)。 On the other hand, it is known that some electronic components mounted on a mounting board need to be mounted in an airtight state because their characteristics deteriorate due to moisture in the atmosphere and the like. For example, in an all-solid-state battery, a method of maintaining an airtight state by sealing with glass is adopted (Patent Document 2).

特開2002−76561号公報JP-A-2002-76561 特開2018−170297号公報JP-A-2018-170297

従来の高密度実装構造では、電子部品を気密状態に実装することができなかった。そのため、電子部品自体を気密構造とする複雑な製造工程を付加しなければならなかった。本発明はこのような実状に鑑み、簡便に高密度実装、気密構造を実現することができるとともに小型で、信頼性の高い電子回路装置を提供することを目的とする。 With the conventional high-density mounting structure, electronic components cannot be mounted in an airtight state. Therefore, it is necessary to add a complicated manufacturing process in which the electronic component itself has an airtight structure. In view of such an actual situation, it is an object of the present invention to easily realize a high-density mounting and an airtight structure, and to provide a compact and highly reliable electronic circuit device.

上記目的を達成するため、請求項1に係る電子回路装置は、実装面と、該実装面に連続し断面形状をコの字型とする壁部とを備えた実装基板と、該実装基板の前記壁部の間の一方の表面に実装された第1の電子部品と、前記壁部間に充填され、前記第1の電子部品を被覆する封止樹脂と、前記実装基板の他方の表面に実装された第2の電子部品とを備え、前記壁部に直交する側面は、一部あるいは全部が前記封止樹脂で構成されていることと、前記壁部の表面に前記第1の電子部品あるいは前記第2の電子部品に接続する電極が露出している電子回路装置であって、前記電極は、複数の分割電極の集合体からなる電極を含むことを特徴とする。 In order to achieve the above object, the electronic circuit device according to claim 1 comprises a mounting surface, a mounting board having a wall portion continuous with the mounting surface and having a U-shaped cross section, and the mounting board. A first electronic component mounted on one surface between the wall portions, a sealing resin filled between the wall portions and covering the first electronic component, and the other surface of the mounting substrate. The side surface orthogonal to the wall portion is provided with the mounted second electronic component, and a part or all of the side surface is made of the sealing resin, and the first electronic component is on the surface of the wall portion. Alternatively, it is an electronic circuit device in which an electrode connected to the second electronic component is exposed, and the electrode includes an electrode composed of an aggregate of a plurality of divided electrodes.

本願請求項2に係る発明は、請求項1記載の電子回路装置において、前記第1の電子部品が全固体電池であることを特徴とする。 The invention according to claim 2 of the present application is characterized in that, in the electronic circuit device according to claim 1, the first electronic component is an all-solid-state battery.

本発明は、気密状態の実装が要求される電子部品、例えば全固体電池を封止樹脂による封止を行うのみで気密性良く封止でき、非常に簡便に全固体電池を備えた電子回路装置を形成することが可能となる。一方気密状態の実装が要求されない電子部品は、実装基板上に露出して実装された構造とすることができ、部品の交換等が容易となるという利点がある。 According to the present invention, an electronic component that is required to be mounted in an airtight state, for example, an all-solid-state battery can be sealed with good airtightness only by sealing with a sealing resin, and an electronic circuit device including the all-solid-state battery can be very easily sealed. Can be formed. On the other hand, electronic components that are not required to be mounted in an airtight state can have a structure in which they are exposed and mounted on a mounting board, and have an advantage that parts can be easily replaced.

本発明は、実装基板に連続する壁部を備える構成とすることで、外部引出用の分割電極の形成が容易となる。さらに、電子回路装置が実装されるマザー基板等と熱膨張率が等しく、あるいは近い材料を選択することで、信頼性の向上も図ることが可能となる。 In the present invention, the mounting substrate is provided with a continuous wall portion, which facilitates the formation of a split electrode for external extraction. Further, by selecting a material having a coefficient of thermal expansion equal to or close to that of a mother substrate or the like on which an electronic circuit device is mounted, it is possible to improve reliability.

また両端の壁部に直交する位置に、一方から他方側に壁部を突出させる構成とすると、凹部間の間隔を狭くすることができるので集合基板上に多数の電子回路装置を形成することが可能となる。この一方から他方へ突出する壁部は、一部に切り欠きを有するため、製造工程で注入される樹脂厚のばらつきを抑えることができるという利点がある。 Further, if the wall portion is projected from one side to the other side at a position orthogonal to the wall portions at both ends, the distance between the recesses can be narrowed, so that a large number of electronic circuit devices can be formed on the collective substrate. It will be possible. Since the wall portion protruding from one side to the other has a notch in a part, there is an advantage that the variation in the resin thickness injected in the manufacturing process can be suppressed.

さらにまた、電極を複数の分割電極の集合体とすると、各分割電極の熱容量を小さくでき、そのばらつきも小さくできる。その結果、半田実装する際に、各分割電極毎の半田が溶融するタイミングが揃い、電子回路装置が傾いたり、位置ずれを起こすことなく実装することが可能となる。また、各分割電極を小さく形成することができ、分割電極への半田の這い上がりが良くなり、実装信頼性が向上するという利点がある。視認性が良くなるという利点もある。 Furthermore, when the electrodes are an aggregate of a plurality of divided electrodes, the heat capacity of each divided electrode can be reduced and the variation thereof can be reduced. As a result, when the solder is mounted, the timing at which the solder melts for each divided electrode is aligned, and the electronic circuit device can be mounted without tilting or misalignment. Further, each divided electrode can be made small, which has an advantage that the solder creeps up to the divided electrode is improved and the mounting reliability is improved. It also has the advantage of improving visibility.

本発明の第1の実施例の電子回路装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the electronic circuit apparatus of 1st Example of this invention. 本発明の第1の実施例の電子回路装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the electronic circuit apparatus of 1st Example of this invention. 本発明の第1の実施例の電子回路装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the electronic circuit apparatus of 1st Example of this invention. 本発明の第1の実施例の電子回路装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the electronic circuit apparatus of 1st Example of this invention. 本発明の第1の実施例の電子回路装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the electronic circuit apparatus of 1st Example of this invention. 本発明の第1の実施例の電子回路装置の説明図である。It is explanatory drawing of the electronic circuit apparatus of 1st Example of this invention. 本発明の第2の実施例の電子回路装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the electronic circuit apparatus of the 2nd Example of this invention. 本発明の第2の実施例の電子回路装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the electronic circuit apparatus of the 2nd Example of this invention. 本発明の第3の実施例の電子回路装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the electronic circuit apparatus of the 3rd Example of this invention. 本発明の第3の実施例の電子回路装置の説明図である。It is explanatory drawing of the electronic circuit apparatus of the 3rd Example of this invention. 本発明の第3の実施例の電子回路装置の変形例の説明図である。It is explanatory drawing of the modification of the electronic circuit apparatus of the 3rd Example of this invention.

本発明の電子回路装置は、気密状態の実装が求められる電子部品と、気密状態の実装が求められない電子部品とを高密度に実装することができ、さらに小型が可能で、信頼性の高い電子回路装置に関する。以下、本発明の実施例について詳細に説明する。 The electronic circuit device of the present invention can mount electronic components that are required to be mounted in an airtight state and electronic components that are not required to be mounted in an airtight state at high density, and can be further miniaturized and highly reliable. Regarding electronic circuit devices. Hereinafter, examples of the present invention will be described in detail.

本発明の第1の実施例について、その製造工程に従い説明する。まず、エポキシ樹脂等からなる集合基板1を用意する。この種の集合基板1は、通常の半導体装置の製造工程で使用されている樹脂基板(有機基板)を使用することができる。集合基板1は、完成する電子回路装置が実装されるマザー基板の材質に応じて、適宜選択するのが好ましく、例えば熱膨張率の等しいあるいは近い材質を選択すると、実装信頼性の向上を図ることができる。集合基板1は個片化により分割されると、個々の実装基板を構成する。 The first embodiment of the present invention will be described according to the manufacturing process thereof. First, an assembly substrate 1 made of an epoxy resin or the like is prepared. As the collective substrate 1 of this type, a resin substrate (organic substrate) used in a normal manufacturing process of a semiconductor device can be used. The collective substrate 1 is preferably selected as appropriate according to the material of the mother substrate on which the completed electronic circuit device is mounted. For example, if a material having the same or close coefficient of thermal expansion is selected, the mounting reliability is improved. Can be done. When the assembly board 1 is divided by individualization, it constitutes an individual mounting board.

図1は、凹部2が形成された集合基板1の説明図で、図1(a)に断面図を、図1(b)に平面図を示している。図1に示す例では、後述する工程に従い、4個の電子回路装置が形成される。凹部2を備えた集合基板1は、絶縁層の両面に所望の配線パターンが形成された導電膜を備えた両面板1aと、凹部2に相当する貫通孔を備えた枠板1bとを貼り合せて用意することができる。 1A and 1B are explanatory views of an assembly substrate 1 in which a recess 2 is formed, FIG. 1A shows a cross-sectional view, and FIG. 1B shows a plan view. In the example shown in FIG. 1, four electronic circuit devices are formed according to the steps described later. In the collective substrate 1 provided with the recess 2, a double-sided plate 1a having a conductive film having a desired wiring pattern formed on both sides of the insulating layer and a frame plate 1b having a through hole corresponding to the recess 2 are bonded together. Can be prepared.

凹部2の両端には壁部3が形成されており、この壁部3を構成する集合基板1に円形の貫通孔4を形成する。この円形の貫通孔4はドリルを用いて形成することができ、低コストで加工時間も短く、簡便に形成することができる。貫通孔4内および集合基板1の表裏面には電極5を形成する。電極5はメッキ法等の周知の方法で形成することができる。電極5は両面板1aに形成された所望の配線パターンと導通している。 Wall portions 3 are formed at both ends of the recess 2, and a circular through hole 4 is formed in the collective substrate 1 constituting the wall portion 3. The circular through hole 4 can be formed by using a drill, and can be easily formed at low cost and in a short processing time. Electrodes 5 are formed in the through hole 4 and on the front and back surfaces of the assembly substrate 1. The electrode 5 can be formed by a well-known method such as a plating method. The electrode 5 is conductive with a desired wiring pattern formed on the double-sided plate 1a.

ところで本実施例では、3個の電極5が一組の電極群5aを構成し、後述するように電極群5aがそれぞれ配線パターンと接続するように構成している。図1に示す例では、各電子回路装置毎に4組の電極群5aが形成されている。 By the way, in this embodiment, the three electrodes 5 form a set of electrode groups 5a, and the electrode groups 5a are configured to be connected to the wiring pattern as described later. In the example shown in FIG. 1, four sets of electrode groups 5a are formed for each electronic circuit device.

次に図2に示すように、凹部2内に電子部品6a(第1の電子部品に相当)を実装する。凹部2の底面には、電子部品6aに接続する配線パターンが形成されており、電子部品6aは所望の方法により接続される。このとき凹部2内には、隣接する電子回路装置の形成予定領域との間に壁部等が無いので、実装のための凹部2の底部への接着部材の滴下や、電子部品の搬送を容易に行うことができる。特に接着部材を滴下する際、ディスペンサーを用いて半田を凹部2の底面に塗布する方法を採用することで、深い凹部2の底面に、確実に半田等の接着部材を供給することができ、実装信頼性が確保でき好ましい。また、凹部2内に複数の電子部品を容易に実装することが可能となる。 Next, as shown in FIG. 2, the electronic component 6a (corresponding to the first electronic component) is mounted in the recess 2. A wiring pattern for connecting to the electronic component 6a is formed on the bottom surface of the recess 2, and the electronic component 6a is connected by a desired method. At this time, since there is no wall or the like in the recess 2 between the recess 2 and the region where the electronic circuit device is to be formed, it is easy to drop the adhesive member to the bottom of the recess 2 for mounting and to transport the electronic components. Can be done. In particular, when the adhesive member is dropped, by adopting a method of applying solder to the bottom surface of the recess 2 using a dispenser, the adhesive member such as solder can be reliably supplied to the bottom surface of the deep recess 2 and mounted. It is preferable because reliability can be ensured. Further, it becomes possible to easily mount a plurality of electronic components in the recess 2.

凹部2内に実装される電子部品6aは、実装される電子部品のうち、気密状態の実装が求められるものを選択することができる。例えば、全固体電池を選択することができる。一般的に全固体電池は、大気中の水分等により特性が劣化してしまう。そこでこのような特性劣化を防止するため、図3に示すようにエポキシ樹脂等の封止樹脂7を凹部2内に充填して樹脂封止する。十分な気密性を保つためは、電子部品6aの表面を封止樹脂7で十分に覆う必要がある。そのため凹部2の深さ(換言すると、壁部3の高さ)は、集合基板1上に実装される電子部品6aの高さより深く(高く)するのが好ましい。具体的には、電子部品6aの高さが0.6mmのとき、凹部2の壁部3の高さを0.8mm程度とすることで、電子部品6aを凹部2の底部に実装するための接着部材の高さ等のばらつき等が発生しても、水分の侵入等のない気密構造を形成することができる。気密構造の形成するためさらに厚く封止樹脂7を形成する必要がある場合には、その厚さや、電子部品6aの高さ等を考慮し、枠板1bの厚さを適宜選択すればよい。 As the electronic component 6a mounted in the recess 2, it is possible to select an electronic component to be mounted that is required to be mounted in an airtight state. For example, an all-solid-state battery can be selected. In general, the characteristics of an all-solid-state battery deteriorate due to moisture in the atmosphere and the like. Therefore, in order to prevent such deterioration of characteristics, as shown in FIG. 3, a sealing resin 7 such as an epoxy resin is filled in the recess 2 and sealed with the resin. In order to maintain sufficient airtightness, it is necessary to sufficiently cover the surface of the electronic component 6a with the sealing resin 7. Therefore, the depth of the recess 2 (in other words, the height of the wall portion 3) is preferably deeper (higher) than the height of the electronic component 6a mounted on the collective substrate 1. Specifically, when the height of the electronic component 6a is 0.6 mm, the height of the wall portion 3 of the recess 2 is set to about 0.8 mm so that the electronic component 6a can be mounted on the bottom of the recess 2. Even if the height of the adhesive member varies, it is possible to form an airtight structure in which moisture does not enter. When it is necessary to form the sealing resin 7 thicker in order to form the airtight structure, the thickness of the frame plate 1b may be appropriately selected in consideration of the thickness thereof, the height of the electronic component 6a, and the like.

なお図2では、気密状態の実装が求められる電子部品6aを2個ずつ実装した例を示しているが、気密状態の実装が求められない別の種類の電子部品を組み合わせて実装しても良い。 Although FIG. 2 shows an example in which two electronic components 6a that are required to be mounted in an airtight state are mounted, another type of electronic component that is not required to be mounted in an airtight state may be mounted in combination. ..

このように集合基板1の表面は封止樹脂7により平坦化される(図3)。使用される封止樹脂7は、ディスペンサーから滴下して平坦化できるように、粘度100Pa・s程度以下が好ましい。また耐薬品性、耐リフロー性等を考慮し、例えばエポキシ系樹脂を選択するのが好ましい。二酸化シリコン等のフィラーの充填量を多くし(例えば60wt%程度以上)、吸水率を0.3wt%程度以下の樹脂を用いることで、気密状態の実装が可能となる。電子部品6aを実装する際、半田を用いた場合にはフラックス除去の工程を追加しても良い。なおこの平坦化は、実装される電子部品のいずれも気密封止が求められない場合であっても、後述する製造工程を進めるために好適となる。 In this way, the surface of the assembly substrate 1 is flattened by the sealing resin 7 (FIG. 3). The sealing resin 7 used preferably has a viscosity of about 100 Pa · s or less so that it can be dropped from a dispenser and flattened. Further, it is preferable to select, for example, an epoxy resin in consideration of chemical resistance, reflow resistance and the like. By increasing the filling amount of a filler such as silicon dioxide (for example, about 60 wt% or more) and using a resin having a water absorption rate of about 0.3 wt% or less, it is possible to implement an airtight state. When mounting the electronic component 6a, if solder is used, a flux removing step may be added. It should be noted that this flattening is suitable for advancing the manufacturing process described later even when none of the mounted electronic components is required to be airtightly sealed.

その後、集合基板1の裏面(他方の表面に相当)に別の電子部品を実装する。図4に示す例では、3個の電子部品6b、6c、6d(第2の電子部品に相当)を実装している。 After that, another electronic component is mounted on the back surface (corresponding to the other surface) of the assembly substrate 1. In the example shown in FIG. 4, three electronic components 6b, 6c, and 6d (corresponding to the second electronic component) are mounted.

図4に示すようにこの種の電子回路装置では、集合基板1上に様々な大きさの電子部品が実装される。このような場合、裏面側の電子部品6b〜6dを実装した後、表面側の電子部品6aを実装して樹脂封止する工程とすると、電子部品6b〜6dが脱落する可能性がある。そのため、上述のように表面側に電子部品6aを実装し、樹脂封止する工程を先に行うのが好ましい。当然ながら、電子部品の脱落等が無ければ、工程を逆にすることは可能である。 As shown in FIG. 4, in this type of electronic circuit device, electronic components of various sizes are mounted on the collective substrate 1. In such a case, if the electronic components 6b to 6d on the back surface side are mounted and then the electronic components 6a on the front surface side are mounted and resin-sealed, the electronic components 6b to 6d may fall off. Therefore, it is preferable to first perform the step of mounting the electronic component 6a on the surface side and sealing the resin as described above. Of course, it is possible to reverse the process as long as the electronic components do not fall off.

次に、集合基板を個片化する。この個片化は、電極5が電子回路装置の外周に露出するように行う。具体的には図5に示すように、貫通孔4の中央部が切断位置8となる格子状に、例えばダイシングソーを走行させて行う。ダイシングソーを用いた切断方法では、集合基板1を所定の寸法だけ切削除去することになる。本実施例では、貫通孔4を比較的小さい径となるように形成しているため、図5に示すように切断位置8の端部が貫通孔4の中央に位置するようにする。凹部2間の切断位置8は、両端が貫通孔4の中央に位置するように配置している。凹部2間の切断は、必ずしも1回の切断で両端の貫通孔4を切断する必要は無く、一方の貫通孔4を切断した後、他方の貫通孔4を切断するように構成してもよい。 Next, the assembly substrate is individualized. This individualization is performed so that the electrode 5 is exposed on the outer periphery of the electronic circuit device. Specifically, as shown in FIG. 5, for example, a dicing saw is run in a grid pattern in which the central portion of the through hole 4 is the cutting position 8. In the cutting method using a dicing saw, the assembly substrate 1 is cut and removed by a predetermined size. In this embodiment, since the through hole 4 is formed so as to have a relatively small diameter, the end portion of the cutting position 8 is located at the center of the through hole 4 as shown in FIG. The cutting positions 8 between the recesses 2 are arranged so that both ends are located at the center of the through holes 4. The cutting between the recesses 2 does not necessarily have to cut the through holes 4 at both ends in one cutting, and may be configured such that one through hole 4 is cut and then the other through hole 4 is cut. ..

図5に示す例では、4個の電子回路装置に個片化される。一般的に個片化工程は、集合基板を固定するためのシートに貼り付けて行うため、集合基板の裏面が封止樹脂の充填により平坦化されていることは、集合基板あるいは個片化後の電子回路装置をシートに確実に接着できる点で好ましい。また壁部3と電子部品6aとの隙間に切削屑が入り込むこともなく好ましい。 In the example shown in FIG. 5, it is individualized into four electronic circuit devices. In general, the individualization step is performed by attaching to a sheet for fixing the assembly substrate, so that the back surface of the assembly substrate is flattened by filling with a sealing resin means that the assembly substrate or after individualization It is preferable in that the electronic circuit device of the above can be reliably adhered to the sheet. Further, it is preferable that cutting chips do not enter the gap between the wall portion 3 and the electronic component 6a.

図6は、個片化後の電子回路装置20の斜視図を示す。図6に示すように個片化された電子回路装置20は、個片化された集合基板(実装基板)の表面に複数の電子部品6b、6c、6dが実装され、実装基板の逆の面には、電子部品6aが封止樹脂7で被覆された状態で実装されている。また壁部3には、配線パターン9に接続する電子回路装置の外部引出用の電極5(分割電極に相当)が露出している。 FIG. 6 shows a perspective view of the electronic circuit device 20 after the individualization. As shown in FIG. 6, in the individualized electronic circuit device 20, a plurality of electronic components 6b, 6c, and 6d are mounted on the surface of the individualized assembly board (mounting board), and the opposite surface of the mounting board. The electronic component 6a is mounted in a state of being coated with the sealing resin 7. Further, an electrode 5 (corresponding to a divided electrode) for external extraction of an electronic circuit device connected to the wiring pattern 9 is exposed on the wall portion 3.

本実施例では、貫通孔4の開口径を小さくすることで、壁部3として残る厚さを薄くしている。これは、大きな開口径の貫通孔を形成する場合と比較して、電子回路装置を小型化できることを示している。一方図面上下方向の両端には、壁部3は残らないように切断することも小型化を実現することとなる。 In this embodiment, the thickness remaining as the wall portion 3 is reduced by reducing the opening diameter of the through hole 4. This indicates that the electronic circuit device can be miniaturized as compared with the case where a through hole having a large opening diameter is formed. On the other hand, cutting so that the wall portions 3 do not remain at both ends in the vertical direction of the drawing also realizes miniaturization.

本実施例の電子回路装置20は、複数の電子部品6a〜6dを高密度実装することができ、さらに電子部品6aが、気密状態の実装が求められる場合には、封止樹脂によって被覆することで気密封止することが可能となっている。また、電極5が電子回路装置の側壁に露出する構造となっているため、電子回路装置を実装する際、半田等の接続部材が電極5の側壁を這い上がり、確実な接続を形成でき、目視検査等も容易となる。特に本実施例の配線パターン9に接続する電極を比較的小さな形状の電極5の集合体としての電極群とすることで、各電極5は熱容量が小さく、他の基板へ実装するため半田接続を形成する際、半田が溶融するタイミングが揃い、電子回路装置の傾きや位置ずれを防止することができる。また半田が這い上がるフィレット高さが高くなり、実装信頼性の向上や半田接続の良否判定のための視認性が向上するという利点もある。 In the electronic circuit device 20 of this embodiment, a plurality of electronic components 6a to 6d can be mounted at high density, and when the electronic components 6a are required to be mounted in an airtight state, they are coated with a sealing resin. It is possible to seal airtightly with. Further, since the electrode 5 has a structure exposed on the side wall of the electronic circuit device, when mounting the electronic circuit device, a connecting member such as solder crawls up the side wall of the electrode 5, and a reliable connection can be formed by visual inspection. Inspection etc. will be easy. In particular, by forming the electrodes connected to the wiring pattern 9 of this embodiment into a group of electrodes as an aggregate of electrodes 5 having a relatively small shape, each electrode 5 has a small heat capacity, and a solder connection is made for mounting on another substrate. When forming, the timing at which the solder melts is aligned, and it is possible to prevent tilting and misalignment of the electronic circuit device. In addition, the fillet height at which the solder crawls up becomes high, which has the advantage of improving mounting reliability and visibility for determining the quality of the solder connection.

次に第2の実施例について説明する。上記第1の実施例では、円形の貫通孔4を形成して電極5を形成する場合について説明したが、貫通孔4の形状を変形することも可能である。 Next, a second embodiment will be described. In the first embodiment, the case where the circular through hole 4 is formed to form the electrode 5 has been described, but the shape of the through hole 4 can be modified.

図7は、第1の実施例で説明した図1に相当する図である。凹部2間の貫通孔4の形状を横長の楕円形に変更している。図7では、図面両端の貫通孔4は円形のままとしているが、両端の貫通孔4を横長の楕円形としても良い。この貫通孔4は、ルーター加工やレーザー照射による加工により形成することができる。 FIG. 7 is a diagram corresponding to FIG. 1 described in the first embodiment. The shape of the through hole 4 between the recesses 2 is changed to a horizontally long ellipse. In FIG. 7, the through holes 4 at both ends of the drawing are left circular, but the through holes 4 at both ends may be formed into a horizontally long ellipse. The through hole 4 can be formed by router processing or processing by laser irradiation.

以下、上記第1の実施例同様、凹部2内に電子部品6aを実装する。凹部2の底面には、電子部品6aに接続する配線パターンが形成されており、電子部品6aは所望の方法により接続される(図2に相当)。 Hereinafter, as in the first embodiment, the electronic component 6a is mounted in the recess 2. A wiring pattern for connecting to the electronic component 6a is formed on the bottom surface of the recess 2, and the electronic component 6a is connected by a desired method (corresponding to FIG. 2).

その後、エポキシ樹脂等の封止樹脂7を凹部2内に充填して樹脂封止する(図3に相当)。 After that, a sealing resin 7 such as an epoxy resin is filled in the recess 2 and sealed with the resin (corresponding to FIG. 3).

その後、集合基板1の裏面(他方の面に相当)に別の電子部品を実装する(図4に相当)。 After that, another electronic component is mounted on the back surface (corresponding to the other surface) of the assembly substrate 1 (corresponding to FIG. 4).

次に、集合基板を個片化する。この個片化は、図8に示す切断位置8に沿うように、貫通孔4の中央が切断位置8となる格子状に、例えばダイシングソーを走行させて行う。ダイシングソーを用いた切断方法では、集合基板1を所定の寸法だけ切削除去することになる。本実施例では、図面両端に配置された貫通孔4は比較的小さい径としているため、図8に示すように切断位置8の端部が貫通孔4の中央に位置するようにしている。また中央の切断位置8は、横長の楕円形の貫通孔4の中央に位置し、図面両端に配置された貫通孔4の切断により残る分割電極と同じ形状の分割電極が残るように配置している。なお横長の楕円形の貫通孔4の切断は、必ずしも1回の切断で中央部を切削除去する必要は無く、貫通孔4の一方の側を切断した後他方の側を切断するように構成してもよい。 Next, the assembly substrate is individualized. This individualization is performed by running, for example, a dicing saw in a grid pattern in which the center of the through hole 4 is the cutting position 8 along the cutting position 8 shown in FIG. In the cutting method using a dicing saw, the assembly substrate 1 is cut and removed by a predetermined size. In this embodiment, since the through holes 4 arranged at both ends of the drawing have a relatively small diameter, the ends of the cutting positions 8 are located at the center of the through holes 4 as shown in FIG. Further, the central cutting position 8 is located at the center of the horizontally long elliptical through hole 4, and is arranged so that the divided electrode having the same shape as the divided electrode remaining by cutting the through hole 4 arranged at both ends of the drawing remains. There is. It should be noted that the cutting of the horizontally long elliptical through hole 4 does not necessarily require cutting and removing the central portion by one cutting, and the through hole 4 is configured to cut one side and then the other side. You may.

図面両端に配置された貫通孔4を横長の楕円形にした場合であっても、切断位置8を所定の位置に配置すれば、切断されずに残る電極5は、同様の形状とすることができる。 Even when the through holes 4 arranged at both ends of the drawing have a horizontally long elliptical shape, if the cutting position 8 is arranged at a predetermined position, the electrode 5 remaining uncut can have the same shape. it can.

その結果、図6に示す形状の電子回路装置20を得ることができる。貫通孔4の形状を変形した場合であっても完成した電子回路装置20は同じ形状となるので、本実施例の電子回路装置20においても、複数の電子部品6a〜6dを高密度実装することができ、さらに電子部品6aが、気密状態の実装が求められる場合には、封止樹脂によって被覆することで気密封止することが可能となる。また、電極5が電子回路装置の側壁に露出する構造となっているため、電子回路装置を実装する際、半田等の接続部材が電極5の側壁を這い上がり、確実な接続を形成でき、目視検査等も容易となる。さらに各電極5は熱容量が小さく、他の基板へ実装するため半田接続を形成する際、半田が溶融するタイミングが揃い、電子回路装置の傾きや位置ずれを防止することができる。また半田が這い上がるフィレット高さが高くなり、実装信頼性の向上や半田接続の良否判定のための視認性が向上するという利点もある。 As a result, the electronic circuit device 20 having the shape shown in FIG. 6 can be obtained. Even if the shape of the through hole 4 is deformed, the completed electronic circuit device 20 has the same shape. Therefore, also in the electronic circuit device 20 of the present embodiment, a plurality of electronic components 6a to 6d are mounted at high density. Further, when the electronic component 6a is required to be mounted in an airtight state, it can be hermetically sealed by coating it with a sealing resin. Further, since the electrode 5 has a structure exposed on the side wall of the electronic circuit device, when mounting the electronic circuit device, a connecting member such as solder crawls up the side wall of the electrode 5, and a reliable connection can be formed by visual inspection. Inspection etc. will be easy. Further, since each electrode 5 has a small heat capacity and is mounted on another substrate, the timing at which the solder melts is aligned when the solder connection is formed, and the inclination and misalignment of the electronic circuit device can be prevented. In addition, the fillet height at which the solder crawls up becomes high, which has the advantage of improving mounting reliability and visibility for determining the quality of the solder connection.

次に第3の実施例について説明する。上記第1および第2の実施例では、集合基板1に形成される凹部2は、縦長の形状とした。ここで、集合基板1から形成できる電子回路装置の数を多くしたり、個片化のための切断位置8を配置するため、隣接する凹部2間の間隔を狭くすると、凹部2間に残る壁部を構成する集合基板1の一部が変形してしまうおそれがある。そこで、凹部2の形状を変形することも可能である。 Next, a third embodiment will be described. In the first and second embodiments, the recess 2 formed in the assembly substrate 1 has a vertically long shape. Here, in order to increase the number of electronic circuit devices that can be formed from the collective substrate 1 or to arrange the cutting position 8 for individualization, if the space between the adjacent recesses 2 is narrowed, the wall remaining between the recesses 2 is left. There is a risk that a part of the collective substrate 1 constituting the part will be deformed. Therefore, it is possible to deform the shape of the recess 2.

図9は、上記第1の実施例で説明した図1に相当する図である。図9に示すように、凹部2内に突出部10を形成することができる。この突出部10は、個片化の際、切断領域となる位置に配置することで、電子部品を実装する領域に影響を及ぼすことはない。なお、突出部10は一方の壁部3から延出し、その先端は対向する壁部3との間に隙間を設けている。これは、例えば図3で説明したように凹部2内に封止樹脂を滴下した際、凹部2内の封止樹脂の厚さを均一にするためである。 FIG. 9 is a diagram corresponding to FIG. 1 described in the first embodiment. As shown in FIG. 9, the protrusion 10 can be formed in the recess 2. By arranging the protruding portion 10 at a position to be a cutting region at the time of individualization, the protruding portion 10 does not affect the region on which the electronic component is mounted. The protruding portion 10 extends from one wall portion 3, and the tip thereof provides a gap between the protruding portion 10 and the opposing wall portion 3. This is for example, when the sealing resin is dropped into the recess 2 as described with reference to FIG. 3, the thickness of the sealing resin in the recess 2 becomes uniform.

この突出部10の形成は、凹部2を形成する際、例えばルーター加工により突出部10を残すように形成すれば良い。 The protrusion 10 may be formed so that the protrusion 10 is left when the recess 2 is formed, for example, by processing a router.

以下、上記第1の実施例同様、凹部2内に電子部品6aを実装し、封止樹脂7を凹部2内に充填して封止する。その後、集合基板1の裏面(図4の表面側)に別の電子部品6b、6c、6dを実装し個片化する。この個片化は、図5に示す貫通孔4の中央と通る格子状に、例えばダイシングソーを走行させて行う。 Hereinafter, as in the first embodiment, the electronic component 6a is mounted in the recess 2, and the sealing resin 7 is filled in the recess 2 for sealing. After that, another electronic component 6b, 6c, 6d is mounted on the back surface (front surface side in FIG. 4) of the assembly substrate 1 to be separated into individual pieces. This individualization is performed by running, for example, a dicing saw in a grid pattern passing through the center of the through hole 4 shown in FIG.

突出部10の幅をダイシングソーにより切削除去される切削幅より狭い幅とすると、個片化の際、突出部10が切削除去され、図6に示す形状の電子回路装置20が完成する。この場合、実装基板は実装面に連続したコの字型の壁面を有し、これに直交する側面は実装面に連続する壁部の全部が切り欠かれた構造となる。また突出部10の幅を切削除去される幅より広くし、突出部10の一部を残す形状とすると、図10に示す形状の電子回路装置20が完成する。この場合、実装基板は実装面に連続したコの字型の側面を有し、これに直交する側面は、実装面に連続する壁部の一部が切り欠かれた構造となる。 Assuming that the width of the protruding portion 10 is narrower than the cutting width cut and removed by the dicing saw, the protruding portion 10 is cut and removed at the time of individualization, and the electronic circuit device 20 having the shape shown in FIG. 6 is completed. In this case, the mounting substrate has a U-shaped wall surface continuous with the mounting surface, and the side surface orthogonal to the U-shaped wall surface has a structure in which the entire wall portion continuous with the mounting surface is cut out. Further, if the width of the protruding portion 10 is made wider than the width to be cut off and a part of the protruding portion 10 is left, the electronic circuit device 20 having the shape shown in FIG. 10 is completed. In this case, the mounting substrate has a U-shaped side surface that is continuous with the mounting surface, and the side surface orthogonal to this has a structure in which a part of the wall portion continuous with the mounting surface is cut out.

この突出部10の配置は、図9に示す場合に限定されない。例えば、凹部2の長さが長く、突出部10を複数形成する必要がある場合には、一方の壁部から対向する壁部に向かって突出する配置としたり、両方の壁部から交互に対向する壁部に向かって突出する配置(千鳥構造)としたり、隣接する凹部内に配置される突出部の配置を変えたり、種々変更可能である。特に個片化の際、突出部10を全て除去する場合には、電子回路装置に突出部10が残らないため、種々変更可能である。一方、突出部10の一部が残る場合には、電子回路装置のどの位置に突出部10が残るかを考慮し、突出部10の配置を決定する必要がある。 The arrangement of the protrusions 10 is not limited to the case shown in FIG. For example, when the length of the recess 2 is long and it is necessary to form a plurality of projecting portions 10, the arrangement is such that the recesses 2 project from one wall portion toward the opposite wall portion, or both wall portions alternately face each other. It is possible to change the arrangement (staggered structure) so as to project toward the wall portion to be formed, or to change the arrangement of the protruding portions arranged in the adjacent recesses. In particular, when the protruding portion 10 is completely removed at the time of individualization, the protruding portion 10 does not remain in the electronic circuit device, so that various changes can be made. On the other hand, when a part of the protruding portion 10 remains, it is necessary to determine the arrangement of the protruding portion 10 in consideration of the position where the protruding portion 10 remains in the electronic circuit device.

この突出部10の高さも適宜変更可能で、凹部2内への接着部材の滴下を行う際にディスペンサーに接触する等の不具合があれば、突出部10の高さを低くすることも可能である。この突出部10の幅を切削除去される幅より狭い幅とすると、個片化の際、突出部10が切削除去され、図6に示す形状の電子回路装置を完成させることが可能である。この場合、実装基板は実装面に連続したコの字型の壁面を有し、これに直交する側面は実装面に連続する壁部の全部が切り欠かれた構造となる。また突出部10の幅を切削除去される幅より広くし、突出部10の一部を残す形状とすると、図11に示す形状の電子回路装置20が完成する。この場合、実装基板は実装面に連続したコの字型の側面を有し、これに直交する側面は、実装面に連続する壁部の一部が切り欠かれた構造となる。 The height of the protruding portion 10 can be changed as appropriate, and if there is a problem such as contact with the dispenser when the adhesive member is dropped into the recess 2, the height of the protruding portion 10 can be lowered. .. If the width of the protruding portion 10 is narrower than the width to be removed by cutting, the protruding portion 10 is cut and removed at the time of individualization, and the electronic circuit device having the shape shown in FIG. 6 can be completed. In this case, the mounting substrate has a U-shaped wall surface continuous with the mounting surface, and the side surface orthogonal to the U-shaped wall surface has a structure in which the entire wall portion continuous with the mounting surface is cut out. Further, if the width of the protruding portion 10 is made wider than the width to be cut off and a part of the protruding portion 10 is left, the electronic circuit device 20 having the shape shown in FIG. 11 is completed. In this case, the mounting substrate has a U-shaped side surface that is continuous with the mounting surface, and the side surface orthogonal to this has a structure in which a part of the wall portion continuous with the mounting surface is cut out.

以上の説明は、上記第1の実施例で説明した電子回路装置の変更例として説明したが、電極構造の異なる上記第2の実施例に適用可能であることは言うまでもない。 The above description has been described as a modification of the electronic circuit device described in the first embodiment, but it goes without saying that the above description can be applied to the second embodiment having a different electrode structure.

以上本発明の実施例について説明したが、本発明はこれら実施例に限定されるものでないことは言うまでもない。例えば、電極5の形状は、電子回路装置が実装されるマザー基板との接続構造に応じて適宜変更可能である。また分割電極の集合体を構成する電極5の数は、電子回路装置上に実装される電子部品や回路構成に応じて適宜変更可能で、例えば、1個の電極と複数の電極の集合体を組み合わせて構成したり、異なる数の電極の集合体を組み合わせて構成したり、適宜変更可能である。また電子回路装置に実装される電子部品の数も適宜変更可能である。 Although the examples of the present invention have been described above, it goes without saying that the present invention is not limited to these examples. For example, the shape of the electrode 5 can be appropriately changed according to the connection structure with the mother substrate on which the electronic circuit device is mounted. The number of electrodes 5 constituting the aggregate of the divided electrodes can be appropriately changed according to the electronic components mounted on the electronic circuit device and the circuit configuration. For example, an aggregate of one electrode and a plurality of electrodes can be used. It can be configured in combination, configured by combining an aggregate of different numbers of electrodes, and can be changed as appropriate. Further, the number of electronic components mounted on the electronic circuit device can be changed as appropriate.

1: 集合基板、1a:両面板、1b:枠板、2:凹部、3:壁部、4:貫通孔、5:電極、6a〜6d:電子部品、7:封止樹脂、8:切断位置、9:配線パターン、10:突出部、20:電子回路装置 1: Assembly board, 1a: Double-sided plate, 1b: Frame plate, 2: Recessed part, 3: Wall part, 4: Through hole, 5: Electrode, 6a to 6d: Electronic component, 7: Encapsulating resin, 8: Cutting position , 9: Wiring pattern, 10: Protruding part, 20: Electronic circuit device

Claims (2)

実装面と、該実装面に連続し断面形状をコの字型とする壁部とを備えた実装基板と、
該実装基板の前記壁部の間の一方の表面に実装された第1の電子部品と、
前記壁部間に充填され、前記第1の電子部品を被覆する封止樹脂と、
前記実装基板の他方の表面に実装された第2の電子部品とを備え、
前記壁部に直交する側面は、一部あるいは全部が前記封止樹脂で構成されていることと、
前記壁部の表面に前記第1の電子部品あるいは前記第2の電子部品に接続する電極が露出している電子回路装置であって、
前記電極は、複数の分割電極の集合体からなる電極を含むことを特徴とする電子回路装置。
A mounting board provided with a mounting surface and a wall portion continuous with the mounting surface and having a U-shaped cross section.
A first electronic component mounted on one surface between the walls of the mounting board,
A sealing resin filled between the walls and covering the first electronic component,
It comprises a second electronic component mounted on the other surface of the mounting board.
The side surface orthogonal to the wall portion is partially or wholly made of the sealing resin.
An electronic circuit device in which an electrode connected to the first electronic component or the second electronic component is exposed on the surface of the wall portion.
The electrode is an electronic circuit device including an electrode composed of an aggregate of a plurality of divided electrodes.
請求項1記載の電子回路装置において、
前記第1の電子部品が全固体電池であることを特徴とする電子回路装置。
In the electronic circuit apparatus according to claim 1,
An electronic circuit device characterized in that the first electronic component is an all-solid-state battery.
JP2019100087A 2019-05-29 2019-05-29 electronic circuit device Active JP7332094B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2019100087A JP7332094B2 (en) 2019-05-29 2019-05-29 electronic circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019100087A JP7332094B2 (en) 2019-05-29 2019-05-29 electronic circuit device

Publications (2)

Publication Number Publication Date
JP2020194900A true JP2020194900A (en) 2020-12-03
JP7332094B2 JP7332094B2 (en) 2023-08-23

Family

ID=73545948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019100087A Active JP7332094B2 (en) 2019-05-29 2019-05-29 electronic circuit device

Country Status (1)

Country Link
JP (1) JP7332094B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003197164A (en) * 2001-12-26 2003-07-11 Matsushita Electric Ind Co Ltd All solid battery built-in semiconductor device
JP2005229766A (en) * 2004-02-16 2005-08-25 Nec Tokin Corp Power supply module and method for manufacturing same
JP2012049480A (en) * 2010-08-30 2012-03-08 Sharp Corp Semiconductor device, inspection method of the same and electrical equipment
JP2020170803A (en) * 2019-04-04 2020-10-15 新日本無線株式会社 Electronic circuit device and manufacturing method therefor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003197164A (en) * 2001-12-26 2003-07-11 Matsushita Electric Ind Co Ltd All solid battery built-in semiconductor device
JP2005229766A (en) * 2004-02-16 2005-08-25 Nec Tokin Corp Power supply module and method for manufacturing same
JP2012049480A (en) * 2010-08-30 2012-03-08 Sharp Corp Semiconductor device, inspection method of the same and electrical equipment
JP2020170803A (en) * 2019-04-04 2020-10-15 新日本無線株式会社 Electronic circuit device and manufacturing method therefor

Also Published As

Publication number Publication date
JP7332094B2 (en) 2023-08-23

Similar Documents

Publication Publication Date Title
JP2008166373A (en) Semiconductor device and its manufacturing method
US9615444B2 (en) Manufacturing of a heat sink by wave soldering
US10403616B2 (en) Method of manufacturing a semiconductor device
US6627987B1 (en) Ceramic semiconductor package and method for fabricating the package
KR20150092876A (en) Electric component module and manufacturing method threrof
JP2009004461A (en) Electronic component package and manufacturing method thereof
KR20140136812A (en) Electric component module and manufacturing method threrof
JP6314591B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2020170803A (en) Electronic circuit device and manufacturing method therefor
JP7332094B2 (en) electronic circuit device
JP2012015554A (en) Semiconductor device manufacturing method and multilayer semiconductor device manufacturing method
JP4497304B2 (en) Semiconductor device and manufacturing method thereof
JP2009188005A (en) Surface-mounted semiconductor device
JP2009099816A (en) Semiconductor device, method of manufacturing the same and mounting method of semiconductor device
JP2007103681A (en) Semiconductor device and its manufacturing method
KR20130086110A (en) Assembly of multi-pattern wiring substrate and method of assembling multi-pattern wiring substrate
KR101516371B1 (en) Chip substrate comprising a bonding groove and a sealing member for the chip substrate
JP2004253518A (en) Semiconductor device and method of manufacturing same
JP2014165481A (en) Semiconductor device mounting body
KR102212340B1 (en) Chip substrate comprising junction groove in lens insert
JP5261851B2 (en) Manufacturing method of semiconductor device
KR20180058174A (en) Semiconductor package
JP2011187546A (en) Semiconductor device
JP2012227320A (en) Semiconductor device
KR101910587B1 (en) Substrate and unit substrate for optical device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220328

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20230213

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230221

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230313

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230711

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230731

R150 Certificate of patent or registration of utility model

Ref document number: 7332094

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150