JP2020136463A - Processing method of wafer - Google Patents
Processing method of wafer Download PDFInfo
- Publication number
- JP2020136463A JP2020136463A JP2019027489A JP2019027489A JP2020136463A JP 2020136463 A JP2020136463 A JP 2020136463A JP 2019027489 A JP2019027489 A JP 2019027489A JP 2019027489 A JP2019027489 A JP 2019027489A JP 2020136463 A JP2020136463 A JP 2020136463A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- protective tape
- processing
- tape
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 8
- 230000001681 protective effect Effects 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 15
- 239000013078 crystal Substances 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 description 2
- 230000003028 elevating effect Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Dicing (AREA)
Abstract
Description
本発明は、複数のデバイスが分割予定ラインによって区画され表面に形成されると共に結晶方位を示すノッチが外周に形成されたウエーハを加工するウエーハの加工方法に関する。 The present invention relates to a method for processing a wafer in which a plurality of devices are partitioned by scheduled division lines and formed on the surface of the wafer and a notch indicating a crystal orientation is formed on the outer periphery thereof.
ＩＣ、ＬＳＩ等の複数のデバイスが分割予定ラインによって区画され表面に形成されたウエーハは、裏面が研削手段によって研削され所定の厚みに加工された後、ダイシング装置等によって個々のデバイスチップに分割され、分割された各デバイスチップは携帯電話、パソコン等の電気機器に利用される。 A wafer in which a plurality of devices such as ICs and LSIs are partitioned by a scheduled division line and formed on the front surface is divided into individual device chips by a dicing device or the like after the back surface is ground by a grinding means and processed to a predetermined thickness. , Each divided device chip is used for electric devices such as mobile phones and personal computers.
また、ウエーハの裏面を研削する際、研削装置のチャックテーブルでウエーハの表面を保持する必要から、ウエーハの表面を守るためにウエーハの表面に保護テープが貼着される。 Further, when grinding the back surface of the wafer, it is necessary to hold the surface of the wafer with the chuck table of the grinding device, so a protective tape is attached to the surface of the wafer to protect the surface of the wafer.
そして、研削加工が施された後、ウエーハを収容する開口部を有するフレームの開口部にウエーハを位置付けてウエーハの裏面とフレームとをダイシングテープに貼着し、その後、ウエーハの表面から保護テープを剥離している（たとえば特許文献１参照）。 Then, after grinding, the wafer is positioned in the opening of the frame having the opening for accommodating the wafer, the back surface of the wafer and the frame are attached to the dicing tape, and then the protective tape is applied from the front surface of the wafer. It is peeled off (see, for example, Patent Document 1).
しかし、保護テープがウエーハに比較的強固に貼着されており、ウエーハの表面から保護テープを容易に剥離できないという問題がある。 However, there is a problem that the protective tape is relatively firmly attached to the wafer and the protective tape cannot be easily peeled off from the surface of the wafer.
上記した問題は、分割予定ラインにデバイスチップの仕上がり厚みに対応した深さの溝を形成し、その後、ウエーハの表面に保護テープを貼着してウエーハの裏面に分割溝を表出させて個々のデバイスチップに分割する先ダイシング加工（たとえば特公平５−５４２６２号公報参照）、ウエーハの裏面を研磨する研磨加工、ウエーハの裏面からレーザー光線を照射してウエーハに加工を施すレーザー加工等においても起こり得る。 The problem described above is that a groove having a depth corresponding to the finished thickness of the device chip is formed on the planned division line, and then a protective tape is attached to the front surface of the wafer to expose the division groove on the back surface of the wafer. It also occurs in the dicing process that divides the wafer into device chips (see, for example, Japanese Patent Publication No. 5-54262), the polishing process that polishes the back surface of the wafer, and the laser process that irradiates the back surface of the wafer with a laser beam to process the wafer. obtain.
上記事実に鑑みてなされた本発明の課題は、ウエーハの表面から保護テープを容易に剥離することができるウエーハの加工方法を提供することである。 An object of the present invention made in view of the above facts is to provide a method for processing a wafer, which can easily peel off the protective tape from the surface of the wafer.
上記課題を解決するために本発明が提供するのは以下のウエーハの加工方法である。すなわち、複数のデバイスが分割予定ラインによって区画され表面に形成されると共に結晶方位を示すノッチが外周に形成されたウエーハを加工するウエーハの加工方法であって、ウエーハの表面に保護テープを配設する保護テープ配設工程と、チャックテーブルでウエーハの保護テープ側を保持し、ウエーハの裏面に加工を施す裏面加工工程と、ウエーハの表面から保護テープを剥離する保護テープ剥離工程と、を含み、該保護テープ剥離工程において、ノッチが形成された領域の保護テープに対して剥離用テープを圧着し剥離用テープによって保護テープをウエーハの表面から剥離するウエーハの加工方法である。 In order to solve the above problems, the present invention provides the following wafer processing method. That is, it is a method of processing a wafer in which a plurality of devices are partitioned by scheduled division lines and formed on the surface and a notch indicating a crystal orientation is formed on the outer periphery, and a protective tape is arranged on the surface of the wafer. Includes a protective tape disposing step, a back surface processing step of holding the protective tape side of the wafer with a chuck table and processing the back surface of the wafer, and a protective tape peeling step of peeling the protective tape from the front surface of the wafer. In the protective tape peeling step, the peeling tape is crimped to the protective tape in the region where the notch is formed, and the protective tape is peeled from the surface of the wafer by the peeling tape.
好ましくは、該裏面加工工程には、研削加工、研磨加工、レーザー加工が含まれる。該保護テープ剥離工程において、ウエーハを収容する開口部を有するフレームの該開口部にウエーハを位置付けてウエーハの裏面とフレームとをダイシングテープに貼着し、その後、ウエーハの表面から保護テープを剥離するのが好適である。 Preferably, the back surface processing step includes grinding processing, polishing processing, and laser processing. In the protective tape peeling step, the wafer is positioned in the opening of the frame having an opening for accommodating the wafer, the back surface of the wafer and the frame are attached to the dicing tape, and then the protective tape is peeled from the surface of the wafer. Is preferable.
本発明が提供するウエーハの加工方法は、ウエーハの表面に保護テープを配設する保護テープ配設工程と、チャックテーブルでウエーハの保護テープ側を保持し、ウエーハの裏面に加工を施す裏面加工工程と、ウエーハの表面から保護テープを剥離する保護テープ剥離工程と、を含み、該保護テープ剥離工程において、ノッチが形成された領域の保護テープに対して剥離用テープを圧着し剥離用テープによって保護テープをウエーハの表面から剥離するので、ノッチを覆う保護テープはウエーハから剥離された状態になっており、ノッチを覆う保護テープが剥離のきっかけとなって、ウエーハの表面から保護テープを容易に剥離することができる。 The method for processing a waiha provided by the present invention includes a protective tape arranging step of arranging a protective tape on the surface of the waha and a back surface processing step of holding the protective tape side of the waha on a chuck table and processing the back surface of the waha. And a protective tape peeling step of peeling the protective tape from the surface of the wafer, and in the protective tape peeling step, the peeling tape is crimped to the protective tape in the notched area and protected by the peeling tape. Since the tape is peeled off from the surface of the wafer, the protective tape covering the notch is in a state of being peeled off from the wafer, and the protective tape covering the notch triggers the peeling, and the protective tape can be easily peeled off from the surface of the wafer. can do.
以下、本発明のウエーハの加工方法の好適実施形態について図面を参照しつつ説明する。 Hereinafter, preferred embodiments of the wafer processing method of the present invention will be described with reference to the drawings.
図１には、本発明のウエーハの加工方法によって加工が施されるウエーハ２が示されている。円盤状のウエーハ２の表面２ａは、格子状の分割予定ライン４によって複数の矩形領域に区画され、複数の矩形領域のそれぞれにはデバイス６が形成されている。また、ウエーハ２の外周には、ウエーハ２の結晶方位を示すノッチ８が形成されている。そして、図示の実施形態のウエーハの加工方法では、まず、図１に示すとおり、ウエーハ２の表面２ａに、デバイス６を保護するための保護テープ１０を配設する保護テープ配設工程を実施する。 FIG. 1 shows a wafer 2 processed by the wafer processing method of the present invention. The surface 2a of the disk-shaped wafer 2 is divided into a plurality of rectangular regions by a grid-like division schedule line 4, and a device 6 is formed in each of the plurality of rectangular regions. Further, a notch 8 indicating the crystal orientation of the wafer 2 is formed on the outer periphery of the wafer 2. Then, in the wafer processing method of the illustrated embodiment, first, as shown in FIG. 1, a protective tape arranging step of arranging the protective tape 10 for protecting the device 6 on the surface 2a of the wafer 2 is carried out. ..
保護テープ配設工程を実施した後、チャックテーブルでウエーハ２の保護テープ１０側を保持し、ウエーハ２の裏面２ｂに加工を施す裏面加工工程を実施する。図示の実施形態の裏面加工工程では、図２に一部を示す研削装置１２を用いて裏面研削加工を実施する。なお、裏面加工工程では、研磨装置（図示していない。）を用いてウエーハ２の裏面２ｂを研磨する裏面研磨加工や、レーザー加工装置（図示していない。）を用いてウエーハ２の裏面２ｂからレーザー光線を照射してウエーハ２に加工を施すレーザー加工を実施してもよい。 After performing the protective tape disposing step, the back surface processing step of holding the protective tape 10 side of the wafer 2 on the chuck table and processing the back surface 2b of the wafer 2 is performed. In the back surface processing step of the illustrated embodiment, the back surface grinding process is performed using the grinding device 12 shown in part in FIG. In the back surface processing step, a back surface polishing process for polishing the back surface 2b of the wafer 2 using a polishing device (not shown) or a back surface 2b of the wafer 2 using a laser processing device (not shown). The wafer 2 may be subjected to laser processing by irradiating the wafer with a laser beam.
図２を参照して研削装置１２について説明する。研削装置１２は、ウエーハ２を吸引保持する回転可能な円形状のチャックテーブル１４と、チャックテーブル１４に保持されたウエーハ２の裏面２ｂを研削する研削手段１６とを備える。 The grinding apparatus 12 will be described with reference to FIG. The grinding device 12 includes a rotatable circular chuck table 14 that sucks and holds the wafer 2 and a grinding means 16 that grinds the back surface 2b of the wafer 2 held by the chuck table 14.
チャックテーブル１４の上端部分には、吸引手段（図示していない。）に接続された多孔質の吸着チャック（図示していない。）が配置され、チャックテーブル１４においては、吸引手段で吸着チャックの上面に吸引力を生成することにより吸着チャックの上面に載せられたウエーハ２を吸引保持するようになっている。また、チャックテーブル１４は、チャックテーブル１４の径方向中心を通って上下方向に延びる軸線を回転中心としてチャックテーブル用モータ（図示していない。）によって回転される。 A porous suction chuck (not shown) connected to a suction means (not shown) is arranged at the upper end portion of the chuck table 14, and in the chuck table 14, the suction chuck is used to hold the suction chuck. By generating a suction force on the upper surface, the wafer 2 mounted on the upper surface of the suction chuck is sucked and held. Further, the chuck table 14 is rotated by a chuck table motor (not shown) about an axis extending in the vertical direction through the radial center of the chuck table 14 as a rotation center.
研削手段１６は、スピンドル用モータ（図示していない。）に連結され、かつ上下方向に延びるスピンドル１８と、スピンドル１８の下端に固定された円板状のホイールマウント２０とを含む。ホイールマウント２０の下面にはボルト２２によって環状の研削ホイール２４が固定されている。研削ホイール２４の下面の外周縁部には、周方向に間隔をおいて環状に配置された複数の研削砥石２６が固定されている。 The grinding means 16 includes a spindle 18 connected to a spindle motor (not shown) and extending in the vertical direction, and a disc-shaped wheel mount 20 fixed to the lower end of the spindle 18. An annular grinding wheel 24 is fixed to the lower surface of the wheel mount 20 by bolts 22. A plurality of grinding wheels 26 arranged in an annular shape at intervals in the circumferential direction are fixed to the outer peripheral edge of the lower surface of the grinding wheel 24.
図２を参照して説明を続けると、裏面加工工程では、まず、ウエーハ２の裏面２ｂを上に向けると共に保護部材１０側を下に向けて、チャックテーブル１４の上面でウエーハ２を吸引保持する。次いで、上方からみて反時計回りに所定の回転速度（たとえば３００ｒｐｍ）でチャックテーブル１４をチャックテーブル用モータで回転させる。また、上方からみて反時計回りに所定の回転速度（たとえば６０００ｒｐｍ）でスピンドル１８をスピンドル用モータで回転させる。次いで、研削装置１２の昇降手段（図示していない。）でスピンドル１８を下降させ、ウエーハ２の裏面２ｂに研削砥石２６を接触させる。ウエーハ２の裏面２ｂに研削砥石２６を接触させた後は所定の研削送り速度（たとえば１．０μｍ／ｓ）でスピンドル１８を下降させる。これによって、ウエーハ２の裏面２ｂを研削してウエーハ２を所望の厚みに薄化することができる。なお、図２（ｂ）には、裏面加工工程を実施したことによって、ウエーハ２の裏面２ｂにおいて、ウエーハ２の径方向中心から放射状に複数の弧状研削痕２８が発生した状態が示されている。 Continuing the description with reference to FIG. 2, in the back surface processing step, first, the back surface 2b of the wafer 2 is directed upward and the protective member 10 side is directed downward, and the wafer 2 is sucked and held on the upper surface of the chuck table 14. .. Next, the chuck table 14 is rotated by the chuck table motor at a predetermined rotation speed (for example, 300 rpm) counterclockwise when viewed from above. Further, the spindle 18 is rotated by the spindle motor at a predetermined rotation speed (for example, 6000 rpm) counterclockwise when viewed from above. Next, the spindle 18 is lowered by an elevating means (not shown) of the grinding device 12, and the grinding wheel 26 is brought into contact with the back surface 2b of the wafer 2. After the grinding wheel 26 is brought into contact with the back surface 2b of the wafer 2, the spindle 18 is lowered at a predetermined grinding feed rate (for example, 1.0 μm / s). As a result, the back surface 2b of the wafer 2 can be ground to thin the wafer 2 to a desired thickness. Note that FIG. 2B shows a state in which a plurality of arc-shaped grinding marks 28 are radially generated from the radial center of the wafer 2 on the back surface 2b of the wafer 2 due to the back surface processing step. ..
裏面加工工程を実施した後、ウエーハ２の表面２ａから保護テープ１０を剥離する保護テープ剥離工程を実施する。保護テープ剥離工程では、まず、図３（ａ）に示すとおり、ノッチ８が形成された領域の保護テープ１０に対して、長方形状の剥離用テープ３０の長手方向一端側を圧着する。次いで、図３（ｂ）に示すとおり、剥離用テープ３０の長手方向他端側を把持して、剥離用テープ３０を図３（ｂ）に矢印Ａで示す方向（ウエーハ２の径方向中心とノッチ８とを結ぶウエーハ２の径方向）に剥離用テープ３０を引っ張る。そうすると、ノッチ８を覆う保護テープ１０はウエーハ２から剥離された状態になっているため、ノッチ８を覆う保護テープ１０が、ウエーハ２の表面２ａから保護テープ１０を剥離するきっかけとなり、図３（ｃ）および図３（ｄ）に示すとおり、ウエーハ２の表面２ａから保護テープ１０を容易に剥離することができる。 After carrying out the back surface processing step, the protective tape peeling step of peeling the protective tape 10 from the front surface 2a of the wafer 2 is carried out. In the protective tape peeling step, first, as shown in FIG. 3A, one end side of the rectangular peeling tape 30 in the longitudinal direction is crimped to the protective tape 10 in the region where the notch 8 is formed. Next, as shown in FIG. 3 (b), the other end side of the release tape 30 in the longitudinal direction is gripped, and the release tape 30 is moved to the direction indicated by the arrow A in FIG. 3 (b) (with the radial center of the wafer 2). The peeling tape 30 is pulled in the radial direction of the wafer 2 connecting the notch 8. Then, since the protective tape 10 covering the notch 8 is in a state of being peeled off from the wafer 2, the protective tape 10 covering the notch 8 triggers the peeling of the protective tape 10 from the surface 2a of the wafer 2, and FIG. As shown in c) and FIG. 3D, the protective tape 10 can be easily peeled off from the surface 2a of the wafer 2.
また、保護テープ剥離工程においては、図４（ａ）に示すとおり、ウエーハ２を収容する円形の開口部３２ａを有する環状のフレーム３２の開口部３２ａにウエーハ２を位置付けて、ウエーハ２の裏面２ｂとフレーム３２とを円形のダイシングテープ３４に貼着し、その後、図４（ｂ）ないし図４（ｄ）に示すとおり、ウエーハ２の表面２ａから保護テープ１０を剥離するようにしてもよい。 Further, in the protective tape peeling step, as shown in FIG. 4A, the wafer 2 is positioned in the opening 32a of the annular frame 32 having the circular opening 32a for accommodating the wafer 2, and the back surface 2b of the wafer 2 is positioned. And the frame 32 may be attached to the circular dicing tape 34, and then the protective tape 10 may be peeled off from the surface 2a of the wafer 2 as shown in FIGS. 4 (b) to 4 (d).
２：ウエーハ
２ａ：ウエーハの表面
２ｂ：ウエーハの裏面
４：分割予定ライン
６：デバイス
８：ノッチ
１０：保護テープ
３０：剥離用テープ
３２：フレーム
３２ａ：開口部
３４：ダイシングテープ
2: Wafer 2a: Wafer front surface 2b: Wafer back surface 4: Scheduled division line 6: Device 8: Notch 10: Protective tape 30: Peeling tape 32: Frame 32a: Opening 34: Dicing tape
Claims (3)
ウエーハの表面に保護テープを配設する保護テープ配設工程と、
チャックテーブルでウエーハの保護テープ側を保持し、ウエーハの裏面に加工を施す裏面加工工程と、
ウエーハの表面から保護テープを剥離する保護テープ剥離工程と、
を含み、
該保護テープ剥離工程において、ノッチが形成された領域の保護テープに対して剥離用テープを圧着し剥離用テープによって保護テープをウエーハの表面から剥離するウエーハの加工方法。 This is a wafer processing method for processing a wafer in which a plurality of devices are partitioned by scheduled division lines and formed on the surface and a notch indicating a crystal orientation is formed on the outer circumference.
Protective tape placement process for arranging protective tape on the surface of the wafer,
The back surface processing process, in which the protective tape side of the wafer is held by the chuck table and the back surface of the wafer is processed,
The protective tape peeling process that peels the protective tape from the surface of the wafer,
Including
A method for processing a wafer in which in the protective tape peeling step, the peeling tape is pressed against the protective tape in the region where the notch is formed and the protective tape is peeled from the surface of the wafer by the peeling tape.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019027489A JP2020136463A (en) | 2019-02-19 | 2019-02-19 | Processing method of wafer |
| KR1020200008309A KR20200101282A (en) | 2019-02-19 | 2020-01-22 | Processing method of a wafer |
| CN202010095180.1A CN111584394A (en) | 2019-02-19 | 2020-02-14 | Method for processing wafer |
| TW109104956A TW202032641A (en) | 2019-02-19 | 2020-02-17 | Wafer processing method capable of easily peeling the protective tape from the surface of the wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019027489A JP2020136463A (en) | 2019-02-19 | 2019-02-19 | Processing method of wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2020136463A true JP2020136463A (en) | 2020-08-31 |
Family
ID=72126031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019027489A Pending JP2020136463A (en) | 2019-02-19 | 2019-02-19 | Processing method of wafer |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2020136463A (en) |
| KR (1) | KR20200101282A (en) |
| CN (1) | CN111584394A (en) |
| TW (1) | TW202032641A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113013080A (en) * | 2021-02-24 | 2021-06-22 | 中芯集成电路制造(绍兴)有限公司 | Film uncovering method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09115863A (en) * | 1995-10-23 | 1997-05-02 | Oki Electric Ind Co Ltd | Method and apparatus for adhering surface protective tape |
| JP2004128147A (en) * | 2002-10-01 | 2004-04-22 | Nitto Denko Corp | Method and device for removing protection tape from semiconductor wafer |
| JP2006278927A (en) * | 2005-03-30 | 2006-10-12 | Takatori Corp | Method and device for pasting tape to wafer |
| JP2012033671A (en) * | 2010-07-30 | 2012-02-16 | Toyota Motor Corp | Protective tape peeling method |
| JP2015167205A (en) * | 2014-03-04 | 2015-09-24 | 株式会社ディスコ | Protection tape peeling device and protection tape peeling method |
| JP2015532007A (en) * | 2012-08-31 | 2015-11-05 | セミコンダクター テクノロジーズ アンド インストゥルメンツ ピーティーイー リミテッド | Multifunctional wafer and film frame handling system |
| JP2018160522A (en) * | 2017-03-22 | 2018-10-11 | 東芝メモリ株式会社 | Semiconductor device and method of manufacturing the same |
| JP2018190940A (en) * | 2017-05-11 | 2018-11-29 | 株式会社ディスコ | Sheet sticking method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005086074A (en) | 2003-09-10 | 2005-03-31 | Disco Abrasive Syst Ltd | Method for transferring semiconductor wafer |
-
2019
- 2019-02-19 JP JP2019027489A patent/JP2020136463A/en active Pending
-
2020
- 2020-01-22 KR KR1020200008309A patent/KR20200101282A/en not_active Application Discontinuation
- 2020-02-14 CN CN202010095180.1A patent/CN111584394A/en active Pending
- 2020-02-17 TW TW109104956A patent/TW202032641A/en unknown
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09115863A (en) * | 1995-10-23 | 1997-05-02 | Oki Electric Ind Co Ltd | Method and apparatus for adhering surface protective tape |
| JP2004128147A (en) * | 2002-10-01 | 2004-04-22 | Nitto Denko Corp | Method and device for removing protection tape from semiconductor wafer |
| JP2006278927A (en) * | 2005-03-30 | 2006-10-12 | Takatori Corp | Method and device for pasting tape to wafer |
| JP2012033671A (en) * | 2010-07-30 | 2012-02-16 | Toyota Motor Corp | Protective tape peeling method |
| JP2015532007A (en) * | 2012-08-31 | 2015-11-05 | セミコンダクター テクノロジーズ アンド インストゥルメンツ ピーティーイー リミテッド | Multifunctional wafer and film frame handling system |
| JP2015167205A (en) * | 2014-03-04 | 2015-09-24 | 株式会社ディスコ | Protection tape peeling device and protection tape peeling method |
| JP2018160522A (en) * | 2017-03-22 | 2018-10-11 | 東芝メモリ株式会社 | Semiconductor device and method of manufacturing the same |
| JP2018190940A (en) * | 2017-05-11 | 2018-11-29 | 株式会社ディスコ | Sheet sticking method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20200101282A (en) | 2020-08-27 |
| CN111584394A (en) | 2020-08-25 |
| TW202032641A (en) | 2020-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8513096B2 (en) | Wafer dividing method | |
| JP2011124266A (en) | Method of processing wafer | |
| KR102216978B1 (en) | Support plate, method of forming same, and wafer processing method | |
| KR20160033631A (en) | Wafer processing method | |
| JP2015217461A (en) | Processing method of wafer | |
| JP2010186971A (en) | Wafer processing method | |
| TW201820436A (en) | Wafer processing method does not require forming a plurality of laser processing grooves on the front surface of the wafer to improve productivity | |
| KR20150131964A (en) | Wafer processing method and intermediate member | |
| JP2014093444A (en) | Wafer processing method | |
| JP2020136463A (en) | Processing method of wafer | |
| JP6066672B2 (en) | Wafer processing method | |
| JP2012222310A (en) | Method for processing wafer | |
| JP6066673B2 (en) | Wafer processing method | |
| JP7404007B2 (en) | Wafer processing method | |
| JP2021005621A (en) | Wafer processing method | |
| JP7355568B2 (en) | Wafer processing method | |
| JP2021048287A (en) | Wafer processing method | |
| JP6086754B2 (en) | Wafer processing method | |
| JP5441579B2 (en) | Workpiece support sheet | |
| JP7313968B2 (en) | Wafer processing method | |
| JP7343339B2 (en) | Wafer processing method | |
| TWI773838B (en) | Grinding method of workpiece | |
| JP2010118588A (en) | Protection tape peeling method | |
| KR20230163297A (en) | Method of processing wafer and support table | |
| JP2021048151A (en) | Wafer processing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20211210 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20221031 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20221129 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20230116 |
|
| RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20230116 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20230516 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20231107 |