JP2020043304A - Heat dissipation substrate and manufacturing method thereof - Google Patents

Abstract

To provide a heat dissipation substrate capable of controlling the temperature by switching between heat generation and heat absorption, and a manufacturing method thereof.SOLUTION: A heat dissipation substrate 10 includes a core substrate having a cavity, a plurality of thermoelectric elements arranged in a matrix in the cavity, and an insulating layer and a conductor layer laminated on both front and back surfaces of the core substrate. The conductor layer is provided with an electrode pattern for connecting adjacent thermoelectric elements in series, the thermoelectric element includes a semiconductor block, and metal layers stacked on both front and back surfaces of the semiconductor block, and an insulating film covering at least the edge of the metal layer is formed, and an outer surface of the insulating film is formed flush with the outer surface of the metal layer.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a heat dissipation board and a method of manufacturing the same.

  Conventionally, as this kind of heat radiating substrate, a substrate having a built-in metal block as a heat radiating component is known (for example, see Patent Document 1).

JP 2008-160144 A (paragraph [0032], FIG. 1)

  In the above-described substrate, not only heat dissipation but also temperature control by switching between heat generation and heat absorption is required.

  In order to solve the above-mentioned problem, the heat dissipation board according to claim 1 is a core board having a cavity, a plurality of thermoelectric elements arranged in a matrix in the cavity, and an insulating layer laminated on both front and back surfaces of the core board. And a conductor layer. The conductor layer is provided with an electrode pattern for connecting adjacent thermoelectric elements in series, and the thermoelectric element has a semiconductor block and metal layers stacked on both front and back surfaces of the semiconductor block, and at least one of the metal layers An insulating film covering the edge is formed, and the outer surface of the insulating film and the outer surface of the metal layer are formed flush.

  In order to solve the above-mentioned problem, a method of manufacturing a heat-dissipating substrate includes forming a core substrate having a cavity, a plurality of thermoelectric devices each including a semiconductor block, and metal layers stacked on both front and back surfaces of the semiconductor block. Preparing the element, arranging a plurality of thermoelectric elements in a matrix in the cavity, laminating the insulating layer and the conductor layer on the core substrate, and forming an electrode pattern for connecting the thermoelectric elements adjacent to the conductor layer in series Forming. The preparation of the thermoelectric element includes cutting out the thermoelectric element from a large-sized thermoelectric element plate, and covering the surface of the metal layer of the thermoelectric element with an insulating film before cutting.

Side sectional view of the heat dissipation board according to the present invention Side sectional view showing the manufacturing process of the heat radiation component Side sectional view showing the manufacturing process of the heat dissipation board Side sectional view showing the manufacturing process of the heat dissipation board Side sectional view showing the manufacturing process of the heat dissipation board Side sectional view showing the manufacturing process of the heat dissipation board Side sectional view showing the manufacturing process of the heat dissipation board

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the heat dissipation board 10 of the present embodiment has a structure having an insulating layer 21 and a conductor layer 22 on both the front and back surfaces of a core substrate 11.

  The core substrate 11 has a structure in which a conductive circuit layer 12 is provided on an F surface 11F which is a front surface of the insulating base material 11K and an S surface 11S which is a back surface. Further, a cavity 16 and a plurality of conductive through holes 14 are formed in the insulating base material 11K. Hereinafter, the F surface 11F and the S surface 11S of the insulating base material 11K will be referred to as the F surface 11F and the S surface 11S of the core substrate 11 as appropriate.

  The conductive through-hole 14 is formed in an intermediate constricted shape in which ends of tapered holes that are respectively pierced from both sides of the F surface 11F and the S surface 11S of the insulating base material 11K and that gradually decrease in diameter toward the back communicate with each other. Has made. A plurality of through-hole conductors 15 are formed in each of the conductive through-holes 14 by being filled with plating. The through-hole conductors 15 allow the conductor circuit layer 12 on the F surface 11F and the conductor circuit layer 12 on the S surface 11S to be formed. Are connected.

  A cavity 16 penetrating the core substrate 11 is provided. A plurality of thermoelectric elements 40 are accommodated in the cavity 16. The plurality of thermoelectric elements 40 include a P-type thermoelectric element 40P having a P-type semiconductor block 41P, and an N-type thermoelectric element 40N having an N-type semiconductor block 41N formed of a metal different from the P-type semiconductor block 41P. Is done. The P-type thermoelectric elements 40P and the N-type thermoelectric elements 40N are alternately arranged in a matrix at a predetermined interval. In addition, each thermoelectric element 40P, 40N is arrange | positioned at intervals of about 50-200 micrometers.

  The adjacent P-type thermoelectric element 40P and N-type thermoelectric element 40N are connected in series via an electrode pattern 46 formed on the conductor layer 22. The electrode pattern 46, the P-type thermoelectric element 40P, and the N-type thermoelectric element 40N are electrically connected by a plurality of electrode vias 45 penetrating the insulating layer 21. The P-type thermoelectric element 40P, the N-type thermoelectric element 40N, the electrode via 45, and the electrode pattern 46 constitute a Peltier element module 50. The electrode pattern 46 connected to the thermoelectric elements 40P and 40N, which are the ends of the Peltier element module 50, is referred to as a connection end 46K.

  The thermoelectric element 40 includes a semiconductor block 41 and metal layers 42 stacked on the front and back sides. The metal layer 42 is made of, for example, copper or nickel. The thickness of the metal layer 42 is about 5 to 30 μm. Note that the P-type semiconductor block 41P and the N-type semiconductor block 41N have a rectangular parallelepiped shape, and are configured to be substantially the same shape and size. The P-type semiconductor block 41P and the N-type semiconductor block 41N are made of, for example, Bi or Te. The thickness of the P-type semiconductor block 41P and the N-type semiconductor block 41N is 0.3 to 0.8 mm.

  Both front and back surfaces of the thermoelectric elements 40 </ b> P and 40 </ b> N of the present embodiment are covered with the insulating film 43. The metal layer 42 and the insulating film 43 have the same shape and the same size in the laminating direction. The metal layer 42 and the insulating film 43 are formed so as to overlap in the stacking direction of the heat dissipation substrate 10. The outer surface 42M of the metal layer 42 of each of the thermoelectric elements 40P and 40N and the outer surface 43M of the insulating film 43 are flush. The outer surface 41M of each of the semiconductor blocks 41P and 41N and the outer surface 42M of the metal layer 42 are also flush. For example, it is made of an epoxy resin. The thickness of the insulating film 43 is about 5 to 20 μm. In the present embodiment, the entire front and back surfaces of the thermoelectric elements 40P and 40N are entirely covered with the insulating film 43, but may be a structure that covers only the outer edge.

  The gap between the thermoelectric elements 40P and 40N and the gap between the cavity 16 and the thermoelectric elements 40P and 40N are filled with the resin forming the insulating layer 21.

  As shown in FIG. 1, an insulating layer 21 and a conductor layer 22 are laminated on the F plane 11F and the S plane 11S of the core substrate 11, and a solder resist layer 26 is laminated on the conductor layer 22. The conductor layer 22 has a predetermined wiring pattern 22A and an electrode pattern 46. A plurality of via holes 21H and 21D are formed in the insulating layer 21, respectively. The plurality of via holes 21H and 21D have a first via hole 21H formed on the conductive circuit layer 12 and a second via hole 21D formed on the thermoelectric elements 40P and 40N. The second via hole 21D penetrates through the insulating layer 21 and the insulating film 43 and communicates with the metal layers 42 of the thermoelectric elements 40P and 40N.

  The via holes 21H and 21D are filled with plating to form a plurality of via conductors 17 and 45. Then, the wiring pattern 22 </ b> A of the conductor circuit layer 12 and the conductor layer 22 is connected by the via conductor 17. The electrode vias 45 connect between the thermoelectric elements 40P and 40N and the electrode pattern 46. The diameter of the electrode via 45 is smaller than the diameter of the via conductor 17. Further, the Peltier device module 50 is composed of the thermoelectric devices 40P and 40N, the electrode via 45 and the electrode pattern 46.

  A plurality of bump openings 26H are formed in the solder resist layer 26, and portions of the conductor layer 22 exposed from the openings 26H are pads 29.

  In the manufacture of the heat radiation board 10, thermoelectric elements 40P and 40N are prepared. The thermoelectric elements 40P and 40N are manufactured as follows.

  (A1) As shown in FIG. 2A, a large-sized N-type thermoelectric element plate 40NB having a metal layer 42 laminated on both front and back surfaces is prepared.

  (A2) Next, as shown in FIG. 2B, an insulating film 43 covering the N-type thermoelectric element plate 40NB is formed. In the present embodiment, the insulating film 43 is configured to cover the entire N-type thermoelectric element plate 40NB, but may be configured to cover only the F surface 40F and the S surface 40S of the N-type thermoelectric element plate 40NB.

  Next, the N-type thermoelectric element plate 40NB is cut into a predetermined size in a state where the insulating films 43 are formed on both the front and back surfaces of the N-type thermoelectric element plate 40NB. As a result, a plurality of N-type thermoelectric elements 40N including the N-type semiconductor blocks 41N having the metal layers 42 on the front and back surfaces are formed. An insulating film 43 is formed on both the front and back surfaces of the N-type thermoelectric element 40N. As shown in FIG. 2C, the outer surface 43M of the insulating film 43, the outer surface 42M of the metal layer 42, and the outer surface 41M of the N-type semiconductor block 41N are formed flush.

  (A4) As for the P-type thermoelectric element 40P, similarly to the N-type thermoelectric element 40N, a P-type thermoelectric element plate in which the metal layers 42 are laminated on both front and back surfaces is prepared. Then, an insulating film covering the P-type thermoelectric element plate is formed, and a thermoelectric element block in which the surface of the P-type thermoelectric element plate is covered with the insulating film is formed.

  (A5) Next, the P-type thermoelectric element plate is cut into a predetermined size in a state where the insulating films 43 are formed on both the front and back surfaces of the P-type thermoelectric element plate. Thereby, as shown in FIG. 2C, a plurality of P-type thermoelectric elements 40P including the P-type semiconductor blocks 41P having the metal layers 42 on the front and back surfaces are formed. An insulating film 43 is formed on both the front and back surfaces of the P-type thermoelectric element 40P. The outer surface 43M of the insulating film 43, the outer surface 42M of the metal layer 42, and the outer surface 41M of the P-type semiconductor block 41P are formed flush. In the present embodiment, the insulating film 43 is formed on all of the P-type thermoelectric element 40P and the N-type thermoelectric element 40N, but either one may be used.

The heat dissipation board 10 is manufactured as follows.
(1) As shown in FIG. 3A, copper foil 11C is laminated on both front and back surfaces of an insulating base material 11K made of an epoxy resin or a BT (bismaleimide triazine) resin and a reinforcing material such as a glass cloth. Copper-clad laminate 11Z is prepared.

  (2) As shown in FIG. 3 (B), the copper clad laminate 11Z is irradiated with, for example, a CO2 laser from the F surface 11F side of the insulating base material 11K, and the conductive through-hole 14 (see FIG. ) Are formed in a tapered hole 14A.

  (3) As shown in FIG. 3 (C), a position directly behind the tapered hole 14A on the F surface 11F side of the copper-clad laminate 11Z is irradiated with a CO2 laser to form a tapered hole 14A, The conductive through-holes 14 are formed from the tapered holes 14A, 14A.

  (4) An electroless plating process is performed to form an electroless plating film (not shown) on the copper foil 11 </ b> C and on the inner surface of the conductive through-hole 14.

  (5) As shown in FIG. 3D, a plating resist 33 having a predetermined pattern is formed on the electroless plating film on the copper foil 11C.

  (6) The electrolytic plating is performed, and as shown in FIG. 4A, the electrolytic plating is filled in the conductive through-holes 14 to form the through-hole conductors 15 and the copper plating 11C is formed. An electrolytic plating film 34 is formed on a portion of the electrolytic plating film (not shown) exposed from the plating resist 33.

  (7) While the plating resist 33 is peeled off, the electroless plating film (not shown) below the plating resist 33 and the copper foil 11C are removed, and as shown in FIG. The conductive circuit layer 12 is formed on the F surface 11F of the insulating base material 11K by the plating film 34, the electroless plating film, and the copper foil 11C, and the conductive circuit layer 12 is formed on the S surface 11S of the insulating base material 11K. Is formed. Then, the conductor circuit layer 12 on the F surface 11F and the conductor circuit layer 12 on the S surface 11S are connected by the through-hole conductor 15. Thereby, the core substrate 11 is obtained.

  (8) As shown in FIG. 4C, a cavity 16 is formed in the core substrate 11 by a router or a CO2 laser.

  (9) As shown in FIG. 4D, a tape 90 made of a PET film is adhered on the S surface 11S of the core substrate 11 so that the cavity 16 is closed.

  (10) As shown in FIG. 5A, the thermoelectric elements 40P and 40N covered with the insulating film 43 are housed in the cavity 16 by a mounter (not shown). P-type thermoelectric elements 40P and N-type thermoelectric elements 40N are alternately arranged with a gap.

  (11) As shown in FIG. 5 (B), after the prepreg is laminated as the insulating layer 21 and the copper foil 37C is laminated on the conductive circuit layer 12 on the F surface 11F of the core substrate 11 Hot pressed. At this time, the space between the conductor circuit layers 12 on the F surface 11F of the core substrate 11 is filled with the prepreg. In addition, the thermosetting resin that oozes out of the prepreg fills the gap between the inner surface of the cavity 16 and the thermoelectric elements 40P and 40N and the gap between the P-type thermoelectric element 40P and the N-type thermoelectric element 40N.

  (13) As shown in FIG. 5C, the tape 90 is removed.

  (14) As shown in FIG. 5D, the prepreg as the insulating layer 21 and the copper foil 37C are laminated on the conductive circuit layer 12 on the S surface 11S of the core substrate 11, and then hot pressed. At this time, the space between the conductor circuit layers 12 on the S surface 11S of the core substrate 11 is filled with the prepreg.

  Note that, instead of the prepreg, a resin film containing no reinforcing material and containing an inorganic filler may be used as the insulating layer 21. In that case, the conductor circuit layer can be formed directly on the surface of the resin film by a semi-additive method without laminating a copper foil.

  (14) As shown in FIG. 6A, the insulating layer 21 and the copper foil 37C on both sides of the core substrate 11 formed by the above-described prepreg are irradiated with laser to form a plurality of via holes 21H and 21D. It is formed. Specifically, first via hole 21H is formed on conductive circuit layer 12, and second via hole 21D is formed on thermoelectric elements 40P and 40N.

  (15) When a plurality of via holes 21H and 21D are formed in the insulating layer 21, an electroless plating process is performed, and an electroless plating film (not shown) is formed on the copper foil 37C and in the plurality of via holes 21H and 21D. ) Is formed.

  (16) As shown in FIG. 6B, a plating resist 33 having a predetermined pattern is formed on the electroless plating film.

  (17) As shown in FIG. 6C, electrolytic plating is performed, and the electrolytic plating is filled in the via holes 21H and 21D to form via conductors 17 and 45. Further, as shown in FIG. An electrolytic plating film 39 is formed on a portion of the electroless plating film (not shown) exposed from the plating resist 33.

  (18) While the plating resist 33 is peeled off, the electroless plating film (not shown) and the copper foil 37C below the plating resist 33 are removed, and as shown in FIG. By the plating film 39, the electroless plating film, and the copper foil 37C, the conductor layer 22 having the wiring pattern 22A and the electrode pattern 46 is formed on each of the insulating layers 21 on the front and back of the core substrate 11. In addition, the wiring pattern 22 </ b> A of the conductor circuit layer 12 and the conductor layer 22 is connected by the via conductor 17. The electrode vias 45 connect between the thermoelectric elements 40P and 40N and the electrode pattern 46.

  (19) As shown in FIG. 7B, a solder resist layer 26 is laminated on each conductor layer 22 on the front and back of the core substrate 11.

  (20) Next, an opening 26H for a bump is formed at a predetermined position of the solder resist layer 26, and a portion of each conductor layer 22 exposed from the opening becomes a pad 29. Thus, the heat dissipation board 10 shown in FIG. 1 is completed.

  The description of the structure and the manufacturing method of the heat dissipation board 10 of the present embodiment has been described above. Next, the function and effect of the heat dissipation board 10 will be described. The heat dissipation board 10 of the present embodiment has a Peltier element module 50 built therein. Thus, not only heat dissipation but also temperature control by switching between heat generation and heat absorption can be performed.

  The thermoelectric elements 40P and 40N are cut after the front and back surfaces of the N-type thermoelectric element plate 40NB and the P-type thermoelectric element plate are covered with the insulating film 43. This suppresses generation of burrs on the cut surfaces of the metal layers 42 of the thermoelectric elements 40P and 40N, and suppresses a short circuit due to burrs between the thermoelectric elements 40P and 40N.

  If burrs are generated on the metal layer 42, the outer edges of the thermoelectric elements 40P and 40N are cut off, and the surface area of the metal layer 42 is reduced. On the other hand, since the heat dissipation board 10 of the present embodiment covers the front and back surfaces of the N-type thermoelectric element plate 40NB and the P-type thermoelectric element plate with the insulating film 43 before cutting, the occurrence of burrs is suppressed. Since the outer edge does not need to be cut off and the surface area does not decrease, the total area of the electrode vias 45 that can be arranged on the metal layer 42 can be increased.

[Other embodiments]
The present invention is not limited to the above-described embodiment. For example, embodiments described below are also included in the technical scope of the present invention, and various other than the following are provided without departing from the gist. It can be changed and implemented.

  (1) In the above embodiment, the entire front and back surfaces of each of the thermoelectric elements 40P and 40N are covered with the insulating film 43. However, the configuration may be such that only the outer edges are covered.

  (2) In the above embodiment, the P-type thermoelectric element 40P and the N-type thermoelectric element 40N are both covered with the insulating film 43. However, only one of the P-type thermoelectric element 40P and the N-type thermoelectric element 40N is used. The cover may be configured.

  (3) The planar shape of the P-type thermoelectric element 40P and the N-type thermoelectric element 40N of the above embodiment is rectangular, but may be other polygonal shapes, circular, elliptical, or oblong. You may.

  (5) In the above embodiment, a gap is formed between the inner surface of the cavity 16 of the core substrate 11 and the P-type thermoelectric element 40P and the N-type thermoelectric element 40N. The element 40P and the N-type thermoelectric element 40N may be configured to be in contact with each other.

  (6) In the above embodiment, only one cavity 16 is formed, but a configuration having a plurality of cavities 16 may be employed.

DESCRIPTION OF SYMBOLS 10 Heat dissipation board 11 Core board 12 Conductor circuit layer 15 Through-hole conductor 16 Cavity 17 Via conductor 21 Insulating layer 22 Conductive layer 22A Wiring pattern 40N N-type thermoelectric element 40P P-type thermoelectric element 41N N-type semiconductor block 41P P-type semiconductor block 42 Metal Layer 43 Insulating film 45 Electrode via 46 Electrode pattern 46K Connection end 50 Peltier element module

Claims (5)

A core substrate having a cavity;
A plurality of thermoelectric elements arranged in a matrix in the cavity,
A heat dissipation substrate having an insulating layer and a conductor layer laminated on both the front and back surfaces of the core substrate,
The conductor layer is provided with an electrode pattern for connecting adjacent thermoelectric elements in series,
The thermoelectric element,
A semiconductor block;
Having a metal layer laminated on both the front and back surfaces of the semiconductor block,
An insulating film covering at least an edge of the metal layer is formed,
An outer surface of the insulating film and an outer surface of the metal layer are formed flush. The heat dissipation board according to claim 1,
The insulating film covers the entire upper and lower surfaces of the thermoelectric element. The heat dissipation board according to claim 1 or 2,
The electrode pattern and each of the thermoelectric elements are connected by a plurality of vias penetrating the insulating layer. The heat dissipation board according to any one of claims 1 to 3, wherein
The plurality of thermoelectric elements include a P-type thermoelectric element and an N-type thermoelectric element,
The insulating film covers only one of the P-type thermoelectric element and the N-type thermoelectric element. Forming a core substrate having a cavity;
Preparing a plurality of thermoelectric elements having a semiconductor block and metal layers stacked on both the front and back surfaces of the semiconductor block;
Arranging a plurality of thermoelectric elements in a matrix in the cavity,
Laminating an insulating layer and a conductor layer on the core substrate,
Forming an electrode pattern for connecting the thermoelectric elements adjacent to the conductor layer in series, comprising:
Preparation of the thermoelectric element,
Cutting out the thermoelectric elements from a large-format thermoelectric element plate,
Covering the surface of the metal layer of the thermoelectric element with an insulating film before the cutting.

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