JP2020022692A - Game machine - Google Patents

Abstract

To provide a game machine having a configuration enabling a more improved lamp presentation.SOLUTION: A computer circuit GEPR for controlling a lamp presentation performs a control so that drive data of a same logic level is to be output from a predetermined plurality of output terminals of a predetermined lamp driver DR. At the same time, due to the predetermined plurality of output terminals being connected to each other, predetermined presentation lamps are driven by the drive data of the same logic level.SELECTED DRAWING: Figure 11

Description

  The present invention relates to an electronic game machine having a built-in computer device, and is particularly suitably applied to a spinning game machine and a ball game machine.

  In a spinning machine such as a slot machine, when a player inserts a medal into a medal insertion slot and operates a start lever, the rotation of the spinning reel is started in response thereto. Then, when the player presses the stop button to stop the spinning reel, if a symbol is aligned with an effective stop line (hereinafter, referred to as an effective line), a payout medal according to the symbol is paid out.

  However, actually, the winning / non-winning state of each game is determined in advance by an internal lottery process in the main control unit before the player starts the stop operation, and the symbol internally won by the lottery process is displayed by the player. The payout medals are paid out by aligning on the activated line.

  Of the winning symbols, the combination having a particularly high value is a combination of the big bonus (BB) symbols. When the player wins the BB role internally and the player aligns the BB symbol on the activated line, a big bonus game is started, and thereafter, the winning probability of the small symbol symbol is maintained at a remarkably high level. The number of payout medals can be expected.

JP 2017-184932 JP JP 2016-150261 JP JP 2016-150260 JP JP 2016-106018 JP

  In this type of gaming machine, image effects, sound effects, and ramp effects are generally executed in synchronization, but there is a strong demand to enrich these game operations. Here, the applicant has also made various proposals for an image effect that is easy to appeal to the player (Patent Documents 1 to 4), but the lamp effect is somewhat uniform, and the number of lamps and It is necessary to increase the power by increasing the brightness.

  However, if the number of lamps is increased unnecessarily, the wiring becomes complicated and the control load increases accordingly. Further, when the light emission luminance is increased, the power consumption is increased accordingly, and the internal heat generation of the driver circuit may exceed the limit.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine having a configuration capable of performing an improved lamp effect.

  In order to achieve the above object, the present invention provides a main control unit for executing a lottery process based on a predetermined switch signal, and an effect control for executing an effect operation including a lamp effect based on an instruction from the main control unit. Means, and the lamp effect, the computer circuit constituting the effect control means, a built-in register of a lamp driver for driving and controlling the effect lamp, a group of serial data Is transmitted at an appropriate timing, and the computer circuit controls the drive data of the same logic level to be output from a predetermined plurality of output terminals of a predetermined lamp driver, while controlling the predetermined plurality of outputs. A predetermined effect lamp is configured to be driven based on drive data transmitted by connecting the terminals.

  In the operation mode of the lamp driver, the inflow current to the output terminal is an open mode defined by the resistance value of an external resistor, and the inflow current to the output terminal is based on a value set in a built-in register. Preferably, a settable constant current mode is included. Here, it is more preferable that some of the plurality of output terminals of the predetermined lamp driver function in the constant current mode, and the remaining output terminals function in the open mode. .

  Current total current value and the same value which flows into the predetermined plurality of output terminals, a particular one of the effect lamp, or is preferred that the flows to a plurality of series-connected director lamps, also, the predetermined plurality of It is also preferable that the current divided into the total current value flowing into the output terminal is flowing to one specific effect lamp or a plurality of effect lamps connected in series.

  It is also preferable that the effect lamp is a white lamp and a red lamp arranged between the white lamps. Wherein the white lamp is a plurality being aligned, the number of the red lamp is a small number from the white lamp, it is preferable that is disposed between the white light lamp.

  Further, it is preferable that the effect lamp is arranged so as to be located on a rear side of a display device through which a display screen can be transmitted, and emits light toward the display screen. In any case, the logic level of the drive data output by the driver is determined based on the duty ratio of PWM control, and the computer circuit appropriately sets the duty ratio to change the light emission state of the effect lamp. It is preferably configured to be

  Further, the lamp driver has a built-in power supply circuit for generating a reference level internal power supply voltage by lowering a power supply voltage, and the operation mode is set based on the internal power supply voltage output from the lamp driver. capable is preferred that is configured, the external device to the internal power supply voltage outputted from the lamp driver is connected, based on the voltage of the external device, power reset operation of the lamp driver is realized It is more preferable that such a configuration is adopted.

  In each of the above configurations, the lamp driver defines a maximum current value in a constant current mode based on an externally connected resistance value, and determines a maximum current value in a constant current mode based on a set value in a built-in register of the lamp driver. It is preferable that the configuration is such that the constant current value is defined within a range not exceeding the maximum current value.

  According to the present invention described above, the internal heat generation of the driver circuit does not exceed the limit, it is possible to realize a lamp production which has been further improved.

FIG. 3 is a front view of the slot machine according to the embodiment. It is a right side view of the slot machine shown in FIG. 1 (a) and plan view (b). It is the figure which showed the front panel of the slot machine from the back. FIG. 3 is an internal front view of the main body case of the slot machine. FIG. 2 is a block diagram showing a circuit configuration of the slot machine of FIG. FIG. 3 is a block diagram illustrating a circuit configuration of a main control board. FIG. 2 is a block diagram illustrating a circuit configuration of an LED substrate and an internal configuration of a lamp driver. 4 is a diagram illustrating an internal configuration and a method of using the lamp driver. It is a drawing explaining another use of a lamp driver. FIG. 3 is a block diagram illustrating a circuit configuration of a backlight substrate. FIG. 9 is a block diagram illustrating another circuit configuration of the backlight substrate. 3 is a diagram illustrating a configuration of a transmissive LCD and a backlight unit. It is a diagram illustrating a circuit configuration for driving the transmission type LCD. 5 is a flowchart illustrating a control operation of a main control unit. It is a flowchart explaining the control operation of the effect control unit. Is a flowchart illustrating the lamp control operation of the effect control section.

  Hereinafter, the present invention will be described in more detail based on examples. 1 to 4 illustrate a slot machine SL according to the embodiment. The slot machine SL is configured such that a rectangular box-shaped main body case 1 and a front panel 2 on which various game members are mounted are connected via hinges 3 so that the front panel 2 can be opened and closed with respect to the main body case 1. (FIG. 2). 1 is a front view of the front panel 2, FIG. 2 is a right side view (a) and a plan view (b) of the slot machine SL, FIG. 3 is a rear view of the front panel 2, and FIG. It shows a front view.

  As shown in FIG. 4, a symbol rotating unit 4 including three rotating reels 4a to 4c is arranged substantially at the center of the main body case 1, and a medal payout device 5 is arranged below the symbol rotating unit 4. On each of the rotating reels 4a to 4c, a BB symbol, an RB symbol, various fruit symbols, a replay symbol, and the like are drawn. The medal payout device 5 includes a medal hopper 5a for storing medals, a payout motor M, a medal payout control board ME, a payout relay board PAY, and a payout sensor (not shown). Here, the medal is derived from the payout port 5b toward the front of the drawing based on the rotation of the payout motor M. Note that medals stored beyond the limit amount are configured to fall into the auxiliary tank 6 through the overflow section 5c.

  Power supply boards 62A and 62B are arranged adjacent to the above-mentioned medal payout apparatus 5, and a main control board 50 is arranged above the symbol rotation unit 4, and a turn setting board SET is arranged adjacent to the main control board 50. It is located. In addition, inside the symbol rotation unit 4, a turning LED drive board DR <b> 1 and a turning relay board IM <b> 2 are provided, and an external concentrated terminal board OT is arranged adjacent to the symbol rotating unit 4.

  As shown in FIG. 1, the display device (LCD unit) 7 is disposed on top of the front panel 2. Then, various characters are displayed on the display device 7, thereby effectively enlivening the game operation. Further, the lower portion of the display device 7, three display windows 8a~8c corresponding to the rotation reels 4a~4c are arranged. Through the display windows 8a to 8c, about three symbols can be seen in the rotating direction of each of the rotating reels 4a to 4c, respectively, and a total of nine symbols of three symbols in the horizontal direction and two symbols in the diagonal direction are provided. Becomes a virtual stop line.

  On the left side of such a display window 8a, an LED group 9 indicating a game state is provided. Below the display group 8a, a payout display unit 10 for displaying the number of medals to be paid out as a game result and a medal number in a credit state are displayed. A stored number display section 11 for displaying is provided.

  Payout display unit 10 is constituted by two continuously provided the 7-segment LED, while specifying the number of payout medals, in the event of some abnormality, and also functions as an error indicator for indicating the abnormal content .

  At the center of the front panel 2 in the vertical direction, a medal insertion slot 12 for inserting medals is provided, and a return button 13 for returning a medal clogged in the medal insertion slot 12 is provided adjacent to the medal insertion slot 12. Further, a credit settlement button 14 for paying out a medal in a credit state, an insertion button 15 for inserting one medal in a credit state in place of inserting a medal into the medal insertion slot 12, and a medal in a credit state are pseudo. And a MAX input button 16 for inputting three sheets.

  Below these game members, a start lever 17 for starting rotation of the rotating reels 4a to 4c and a stop button 18a to 18c for stopping the rotating reels 4a to 4c are provided.

  In the present embodiment, an internal lottery process is executed due to the operation of the start lever 17, and it is determined whether or not the BB symbol or the small winning symbol is in an internal winning state. Normally, the three spinning reels 4a to 4c start normal rotation in the forward direction, but all or a part of the spinning reels 4a to 4c rotate irregularly as a notice effect for announcing the internal winning state. sometimes it starts normal rotation on the at. Note that the announcement effect means an effect in which the lottery result of the internal lottery process is reported indefinitely.

  Such During announcement attraction, image effects and the display device 7, a lamp effect or to blink an LED lamp, all or part of the sound effect of driving the speaker are selectively executed appropriately.

  As shown in FIG. 1, the downward front panel 2, a laterally long pan 19 for storing medals, a medal outlet 20 communicating with is provided in the dispensing opening 5b of the dispensing device 5. Further, left and right lower speakers SPbL and SPbR for bass are arranged on the left and right of the medal outlet 20, and upper speakers SPtL and SPtR are also arranged on the left and right of the display device 7. Here, the lower speakers SPbL and SPbR are large speakers emphasizing heavy bass, and output monaural background music (BGM) and the like at the same left and right volume.

  On the other hand, the upper speakers SPtL and SPtR output music of a stereo sound and effect sound when necessary. Here, the music includes a background sound output as a stereo sound. In addition, the announcement effect by the effect sound includes, for the upper speakers SPtL and SPtR, operations such as audio output of only one of the speakers, horizontal voice movement, and left-right voice reciprocation.

  As shown in FIG. 3, on the back side of the front panel 2, a medal selecting device 21 for selecting the medals inserted into the medal insertion slot 12 and a medal that is determined to be inappropriate by the medal selecting device 21 are provided in a medal outlet. A return passage 22 for guiding to 20 is provided. A board case 23 that accommodates the effect control board 60, the effect interface board 61, and the like is arranged on the upper rear side of the front panel 2. A game relay board IM1 that relays signals between the various game members shown in FIG. 1 and the main control board 50 is provided above the medal selection device 21.

  FIG. 5A is a block diagram illustrating a circuit configuration of the slot machine SL according to the embodiment. As shown in the figure, the slot machine SL performs various staging operations based on a main control board 50 for controlling operations of various game members including the rotating reels 4a to 4c, and control commands CMD received from the main control board 50. An effect control board 60 to be realized and a power supply board 62 (62A, 62B) which receives a commercial power supply (100V), converts it into a DC voltage (5V, 12V, 18V, 24V, 36V) and supplies it to each part of the apparatus. Is configured.

  As shown in the lower center of FIG. 5A, the power supply board 62 of the present embodiment includes a first power supply board 62A that directly receives commercial power (100 V), and a power supply board 62A that receives 24 V AC and 24 V DC from the first power supply board 62A. , And a second power supply board 62B that outputs a power reset signal RES and power interruption signals ABN1 and ABN2.

  Here, the power reset signal RES is transmitted to each unit of the apparatus including the main control board 50 and the effect interface board 61 when the AC power is turned on. On the other hand, the power interruption signals ABN1 and ABN2 are output synchronously when the AC power supply is cut off, the power interruption signal ABN1 is transmitted to the main control board 50, and the power interruption signal ABN2 is transmitted to the effect interface board 61. .

  As shown in the upper center of FIG. 5 (a), the director interface board 61, via an appropriate relay board, power board 62A, various level of the DC voltage from 61B (5VB, 12VB, 18V, 36V) and, The power supply reset signal RES and the power interruption signal ABN2 are received (FIGS. 5 and 7).

  The effect interface board 61 receives a control command CMD and a strobe signal STB from the main control board 50 via an appropriate relay board. Then, various control signals (CMD, STB, ABN2) received by the effect interface board 61 are transferred to the effect control board 60 together with the DC voltage (5VB, 3.3V).

  The DC voltage 3.3 V is generated in the converter circuit DC / DC of the effect interface board 61 based on the DC voltage 5 VB received from the second power supply board 62B. It becomes the power supply voltage of the memory SDROM.

  Incidentally, as shown by the broken line in the top center of FIG. 5 (a), the performance control board 60, the effect interface board 61 are integrated by the connector connection. The computer circuit GEPR of the effect control board 60 controls the image effect on the display device 7, the sound effect by the speakers SPt and SPb, and the lamp effect by an LED lamp or the like.

  That is, the performance control board 60, a control processor (computer circuit) which is realized by a general-purpose one-chip microcomputer GEPR and an image processor VDP (Video Display Processor to implement the image effect on the display device 7 under the control of control processor GEPR ), A watchdog timer WDT that outputs an abnormal reset signal ERST when the computer circuit GEPR runs out of control, a control memory PROM that stores a control program of the control processor GEPR, and an image memory that stores basic image data of the image processor VDP. And a CGROM.

  On the other hand, the effect interface board 61 includes a sound processor (speech synthesis circuit) SDPR for realizing a sound effect based on the control of the control processor GEPR, a sound memory SDROM for storing sound source data of the sound processor SDPR, and a sound processor SDPR. The first and second digital amplifiers AMP1 and AMP2 for amplifying and outputting the audio signal output from the first and second amplifiers, and receiving the DC voltage 3.3 V and the power reset signal RES, the audio memory SDROM, the image processor VDP and the control processor GEPR. A first reset circuit RST1 for resetting the power supply, a second reset circuit RST2 for abnormally resetting the audio processor SDPR in response to the DC voltage 3.3V and the abnormal reset signal ERST, and a converter circuit DC / DC for level-converting the DC voltage; Is installed

  As shown, the first digital amplifier AMP1 drives upper speaker SPtL, the sptr, second digital amplifier AMP2 is driven lower speaker SPbL, the SPBR. In addition, the effect interface substrate 61, LED substrate 25 and the reel back light substrate 26 are connected, each substrate 25 and 26, lamp driver DR for driving the LED group (see FIG. 7 (b)) Is arranged. A plurality of lamp drivers DR are arranged on the LED board 25, and drive a large number of LED lamps for lamp effect.

  On the other hand, one lamp driver DR is arranged on the backlight substrate 26, and drives a high-brightness backlight lamp LP for brightly illuminating three symbols in the rotating direction from the inside of the three rows of rotating reels 4a to 4c. ing. Incidentally, LED lamp and lamp driver DR is operating on the basis of the DC 12V received from director interface board 61.

  FIG. 5B schematically shows three rotating body backlight portions BL1 to BL3 corresponding to the three rows of rotating reels 4a to 4c. Each backlight unit BLi is configured by connecting three lamp boxes BX that spread radially, and at the bottom of each lamp box BX, for example, three LED lamps LP are arranged. The inner surface of the lamp box BX is mirror-finished, so that the radiated light from the LED lamp is mirror-reflected and collected on the back side of the three symbols in the rotating direction. As the LED lamp LP, a high-luminance white LED lamp is used.

  By the way, as described above, the effect control board 60 and the effect interface board 61 are integrated by connector connection, and the control processor GEPR of the effect control board 60 receives the control command CMD received from the main control board 50. , The image effect, the sound effect, and the lamp effect are collectively controlled to achieve an effect operation that proceeds synchronously. Specifically, the control processor GEPR operates based on the control program of the control memory PROM, by issuing the command list to the image processor VDP controls the image effect, issues a voice command to the voice processor SDPR with voice The production is controlled.

  In addition to the built-in CPU, the control processor GEPR has a plurality of serial ports SIO (Serial Input / Output Port) and a plurality of parallel ports PIO (Parallel Input / Output Port). The serial port SIO, includes a serial output port So that operates in serial synchronous mode, the first output port So1 is connected to the lamp driver DR of the LED substrate 25, the second output port So2, the backlight substrate 26 lamp drivers DR.

  Each output port So1, So2, to the lamp driver DR, in synchronization with the clock signal SPCK, are serially transmitted to the lamp driving data SPO. In this specification, a lamp driving data SPO, not only various types of setting data defining the operation contents of the lamp driver DR (see FIG. 8 (a)), Slave Address and registers address of lamp driver DR to be described later This is a concept that includes address information, and needs to be interpreted in a broad sense.

  Next, the parallel port PIO includes a parallel output port Po for outputting an operation enable signal OE (Output Enable). In the embodiment of FIG. 7A, the operation enable signal is supplied to the SDEN terminal of the lamp driver DR. We supply OE. As shown in FIG. 8 (b) (c), prior to the start of operation of the serial transmission of the lamp drive data SPO, parallel output port Po changes the operation permission signal OE to the active (H) level, the serial transmission after operation ends, thereby returning the operation permission signal OE inactive (L) level.

  The parallel port PIO includes a parallel input port Pi for receiving a control command CMD issued from the main control board 50, a parallel output port P1 for issuing a display list to the image processor VDP, and an audio command to the audio processor SDPR. The issuing parallel output port P2 is also included (see FIG. 13).

  Next, the main control board 50 will be described. The main control board 50 is connected to various game members of the slot machine through the game relay board IM1. More specifically, a start switch for the start lever 17, a stop switch for the stop buttons 18a to 18c, a close switch for the closing buttons 15 and 16, a clearing switch for the clearing button 14, a door sensor for recognizing opening and closing of the front panel 2, an upstream sensor lever detection sensor constituting the S0, photointerrupter PH1 constituting the medal passing sensor S1, S2, PH2, blockers solenoid SL that blockers of ON / OFF control to block passage of unauthorized medal, and various LED elements 9-11, etc. It is connected to the.

  The medal selection device 21 of the present embodiment includes an upstream sensor S0 (lever detection sensor), medal passage sensors S1 and S2 (photo interrupters PH1 and PH2), and a blocker solenoid SL. close to the medal insertion slot 12 upstream sensor S0 is located at the most upstream position, through the blocker, a pair of medal passage sensor S1, S2 are arranged in proximity to its downstream position.

  Upstream sensor S0 is, specifically, is configured to have a lever LV swinging by being pressed by the medal surface, and photo-interrupter PH to ON / OFF operation in response to the swing of the lever LV, the I have. The upstream sensor S0 is configured to be in the ON state when the medal surface passes the medal pressing the lever LV, and to return to the OFF state after the medal passes.

  The blocker is disposed at a position downstream of the upstream sensor S0 described above. The blocker has an introduction position that allows passage of medals when the blocker solenoid SL is energized, and has a return position that rejects the passage of medals when not energized.

  As shown in FIG. 5, the main control board 50 is provided with three stepping motors for rotating the rotating reels 4a to 4c via the turnover relay board IM2, and for detecting the reference positions of the rotating reels 4a to 4c. Connected to index sensor. Then, by driving or stopping the stepping motor, and the rotation of the rotating reels 4 a to 4 c, realizes the stop operation at the target position.

  The main control board 50 is also connected to the medal payout device 5 through the payout relay board PAY. The medal payout device 5 is provided with a medal payout control board ME, a medal full sensor, a medal payout sensor, and a payout motor M. The medal payout control board ME receives control commands from the main control board 50. The payout motor M is rotated based on this, and a predetermined amount of medals is paid out.

  The medal full sensor detects an overflow abnormality in which the auxiliary storage is full of medals, and the medal payout sensor detects an insufficient abnormality in which the number of payout medals is insufficient or an abnormal payout that does not involve a payout operation by the gaming machine. ing. Other main control board 50 includes an external common terminal plate OT, is also connected to the reel-setting substrate SET. The external central terminal board OT is connected to, for example, a hall computer HC, and the main control board 50 outputs the number of inserted medals and the number of paid out medals through the external centralized terminal board OT.

  Further, the turning body setting board SET outputs a setting key signal or the like indicating a setting value set by a clerk using a setting key. Here, the set value defines the winning probability of the lottery process executed in the gaming machine in six steps from setting 1 to setting 6, and is appropriately set based on the business strategy of the gaming hall. . For example, a gaming machine set to the highest rank is the most advantageous for a player because the expected value of the number of paid-out medals is the highest level.

  Figure 6 illustrates the circuit configuration of the main control board 50. As shown, the main control board 50 includes a one-chip microcomputer 64, an I / O port circuit 65 for inputting / outputting 8-bit parallel data, a counter circuit 66 for generating a random number value by hardware, an effect control board 60, and the like. And an interface circuit with an external substrate. Here, the one-chip microcomputer 64 incorporates a CTC (Counter / Timer Circuit) 64b, an interrupt controller 64c, and the like in addition to the CPU core 64a, ROM, RAM, and the like, which are equivalent to Z80.

  The CTC 64b is a circuit in which an 8-bit counter and timer are integrated, and provides a Z80 system with a periodic interrupt, a pulse output generation function (bit rate generator) of a fixed period, and a time measurement function. Therefore, in this embodiment, by utilizing the CTC64b, it is causing a timer interrupt at time intervals of 1.5 mS tau in Z80CPU64a.

  As the interface circuit, an interface circuit 67 with the power supply circuit, an interface circuit 68 with the game relay board IM1, a winding motor drive circuit 69, an interface circuit 70 with the effect control board 60, and the like are provided. I have. When the power is cut off (at the time of power cut), a voltage drop interrupt is issued to the Z80 CPU 64a through the interface circuit 67.

  The interface circuit 70 is an 8-bit parallel port for outputting a control command to the effect control board 60, and the winding drum motor drive circuit 69 is a circuit that generates a drive signal for a stepping motor of the rotating reels 4a to 4c. . Each of the three stepping motors for rotating the rotating reels 4a to 4c is a two-phase motor having two sets of drive windings, and is driven by a 1-2-phase excitation that repeats one-phase excitation and two-phase excitation. I have.

  Interface circuit 68 of the street, the main control board 50 shown in FIG. 6, the medal sorting device 21 through a game relay substrate IM1 is connected. The sensor signal S0 of the upstream sensor S0 is input to the input circuit IN0, and the sensor signals S1 and S2 of the medal passing sensor S1 and the medal passing sensor S2 are input to the input circuits IN1 and IN2. The energization state of the blocker solenoid SL is controlled by an output circuit.

  Subsequently, the LED board 25 and the backlight board 26 will be described with reference to FIG. First, the LED substrate 25, lamp driver DR shown in FIG. 7 (b), a plurality, are mounted. The plurality of lamp drivers DR are connected in parallel in a cascade connection format shown in FIG. 7A or 9A. On the other hand, as shown in FIGS. 10 and 11, the LED substrate 26 turns on the backlights BL1 to BL3 (see FIG. 5B) arranged inside the rotating reels 4a to 4c with high luminance. , And one lamp driver DR.

  The lamp driver DR mounted on the LED board 25 and the backlight board 26 has the same circuit configuration as shown in FIG. 7B, and its clock terminal SCLK and serial terminal SDATA have a serial output port So1 / The clock signal SPCK and the lamp drive data SPO are supplied from So2. In the embodiment of FIG. 7A, the operation permission signal OE is supplied from the parallel output port Po to the control terminal SDEN of the lamp driver DR.

  The lamp driver DR according to the embodiment operates in an open drain mode, a constant current mode, or a mixed mode based on a voltage level (H / L / M) received at an operation mode setting terminal OUTSET. Through the built-in current introduction circuit OUT, a maximum of eight (24 in total) LED lamps of three colors of RGB can be driven.

  Here, the open drain mode is an operation mode in which the current introduction circuit OUT drives the LED lamp with a current value specified by the external resistor RL (FIG. 7C), while the constant current mode is This is an operation mode in which the current introduction circuit OUT drives the LED lamp at a predetermined constant current value CST regardless of the value of the external resistance RL. The mixed mode is an operation mode in which part of the current introduction circuit OUT functions in the open drain mode, and the rest of the current introduction circuit OUT functions in the constant current mode.

  The open drain mode and the mixed mode are suitably used, for example, when it is desired to emit only a predetermined LED lamp with high luminance. As described later with reference to FIG. 7B, in the open drain mode, since the output transistor performs ON / OFF switching operation, the internal power loss is smaller than in the case of operating in the constant current mode, and a relatively large current flows. can.

  On the other hand, in the constant current mode, although a part of the output transistor operates linearly, the internal power loss is slightly large. However, the constant current mode is preferably used, for example, when it is desired to make adjacent LED groups emit light with the same luminance. That is, when operating in the open drain mode, the emission intensity does not become constant due to variation in the resistance value of the external resistor (current limiting resistor), but in the constant current mode, the problem does not occur, so that the emission intensity is kept constant. It is suitable when it does. Incidentally, when the luminance of the adjacent LED groups different feel uncomfortable to the player, in the extreme case causes the flicker.

  As shown in FIG. 7B, the lamp driver DR has a total of 24 output terminals (LEDR, LEDG_1-8, LEDB_1-8) and a 5-bit address terminal (A0) for defining a slave address unique to each driver. and to A4), a clock terminal SCLK for receiving a clock signal SPC, the serial terminal SDATA receiving the lamp driving data SPO, and a control terminal SDEN receiving an operation permission signal OE, and the operation mode setting terminal OUTSET, the current setting terminal RT1, It is configured to have a reset terminal rESET, a.

  As shown in FIG. 7A, the clock terminal SCLK, the serial terminal SDATA, and the control terminal SDEN are commonly supplied to all the lamp drivers DR1 to DRn. In FIG. 7A, address signals 00000b to 11111b are supplied to the address terminals (A0 to A4) of the 32 lamp drivers DRi, and the slave address of the 32 lamp drivers DRi is 0. Are shown. Therefore, in this configuration, 256 (= 32 × 8) LED lamps of each color of RGB can be arranged.

  Further, the lamp driver DR is defined for LED lamps 24 (one for each RGB color is 8), respectively, the emission luminance is configured to be able to PWM control (Brightness Control), the duty ratio of the PWM control in each 8-bit including 24 possible internal register R00~R29 of 30 in total it is built. In each of the built-in registers R00 to R29, it is necessary to set 8-bit length setting data such as a duty ratio of PWM control for defining light emission luminance. Each built-in register has an 8-bit length register address (00h to 00h). 1Dh).

  Therefore, in order for the lamp driver DR to perform the PWM control of the light emission brightness of the total of 24 LED lamps, it is necessary for the total of 30 built-in registers (R00 to R29) to specify the slave address of the lamp driver DR. Configuration data must be transmitted. In the present embodiment, the setting data for the built-in register does not include bit data for turning on / off the lamp, so that the number of built-in registers is suppressed and the setting operation for the built-in register is simplified. I have. Therefore, the lamp extinguishing operation is realized by setting the duty ratio to 0 in the PWM control of the light emission luminance.

  FIG. 7C illustrates a characteristic portion of the internal circuit of the lamp driver DR. The power supply voltage (12 V) received from the outside to the SVCC terminal is stepped down, and the voltage is accurately calculated based on the BGR (Band Gap Reference). a power supply circuit PC which generates an internal power supply voltage VREF (5V) such, based on the voltage level (H / L / M) for receiving the operation mode setting terminal OUTSET, generates a 2-bit length of the internal control signal (D1, D0) an operation control circuit CTL which, on the basis of the voltage received to the reset terminal rESET, a reset circuit power on reset to power reset the internal circuit, on the basis of the voltage received on the current setting terminal RT1, the constant current value CST in the constant current mode A specified current setting circuit (I-REG + D / A) and, as an example, a current introduction circuit OUT when operating in the constant current mode are shown. .

  When the lamp driver DR operates in the open drain mode, the internal connection is changed in the illustrated current introduction circuit OUT so that the transistors Q1 to Q8 function as constant resistance elements (resistance value r ≒ 10Ω). that. However, FIG. 7C shows a circuit configuration in the constant current mode, and the illustrated current introduction circuit OUT drives the eight LED lamps LP at a constant current value CST at a constant current. The LED lamps LP are all of the same standard, and are connected to a power supply voltage of 12 V via an external resistor RL having the same resistance value.

  In the constant current mode, the resistance value of the external resistor RL is determined based on the voltage drop Vo inside the lamp driver DR, the forward voltage drop VF of the LED lamp LP, and the required number of LED lamps connected in series. Is determined. Specifically, it is necessary to satisfy 12−N × VF−RL × I = Vo for the number N of lamps. In this conditional expression, I is a drive current value of the LED lamp LP. For example, the driving current I (constant current value CST) = 20 mA, as in the case of the order of VF = 2V is tentatively Vo = 1V approximately, the resistance value of the external resistor RL [kW] is (11-N × 2) / 20.

  However, in the constant current mode, the resistance value of the external resistor RL is not particularly definite. That is, in the constant current mode, external resistor RL, since only be placed in applications that absorbs lamp driver DR internal voltage drop Vo, inversely corresponding to the resistance value of the external resistor RL, lamp driver DR Only the internal voltage drop Vo changes.

  On the other hand, in the open drain mode, the external resistor RL functions as a current limiting resistor and is definitively defined corresponding to the drive current I of the LED lamp LP. Specifically, RL × I = 12−VF × relationship of N-r × I is established. Here, r is an internal resistance when made to function transistor Q1~Q8 as a resistance element (≒ 10Ω).

  Based on the above, the internal circuit of the lamp driver DR will be described. First, the power supply circuit PC includes a voltage drop Pch transistor Q13, a comparator CM1, a comparison reference voltage Vr, and voltage dividing resistors R1 and R2. It is configured. The comparator CM1 compares the divided value of the output voltage Vo of the transistor Q13 with a comparison reference voltage Vr based on BGR (Band Gap Reference).

  The output voltage Vo is defined as Vo = Vr × (R1 + R2) / R2 by causing the comparator CM1 to match the voltage across the resistor R2 (= Vo × R2 / (R1 + R2)) with the comparison voltage Vr. . The output voltage Vo is set to 5 V in this embodiment, and this 5 V is nothing but the internal power supply voltage VREF.

  As described above, the lamp driver DR of the present embodiment incorporates the power supply circuit PC that generates the accurate internal power supply voltage VREF (= 5 V) by lowering the power supply voltage 12 V, so that the LED board 25 and the backlight board 26 In addition, there is simplicity in which it is not necessary to supply a power supply voltage of 5 V to the lamp driver DR, and a high-brightness lamp effect can be realized while minimizing the internal power loss of the lamp driver DR.

  Although the power supply voltage VREF of the internal circuit of the lamp driver DR can be made equal to the power supply voltage of 12 V, a configuration corresponding to an increase in the internal power consumption of the lamp driver DR is required separately. On the other hand, the power supply voltage to the LED board 25 and the backlight board 26 can be set to 5 V, but since the forward voltage drop of the LED lamp is 2 to 3 V, a plurality of LED lamps can be connected in series. As a result, as a result, the lamp effect and the brightness of the backlight portion of the turning body are reduced.

  The above points are taken into consideration. The comparison reference voltage Vr is a voltage based on the bandgap voltage of the constituent material (silicon) of the lamp driver DR, which is a semiconductor IC, and is stable and constant with respect to fluctuations in external temperature and power supply voltage. Since the value is maintained, the output voltage Vo can be accurately maintained at 5V. The output voltage Vo (= 5 V) is supplied to the internal circuit of the lamp driver DR as the internal power supply voltage VREF, and is also output to the external VREF terminal to perform a setting operation and a power reset operation described below. Has been realized.

  The reset circuit Power On Reset receives the voltages of the bias resistors R5 and R6 having a resistance ratio of about 10: 1, the overvoltage protection diode D10 disposed between the bias resistor R6 and the ground, and the connection point of the bias resistors R5 and R6. And a buffer BF of the Schmitt trigger type.

  The reset terminal RESET connected to the cathode terminal of the diode D10 and the bias resistor R6 is directly connected to the external VREF terminal and is connected to the ground via the capacitor Cre. The direct connection of the reset terminal RESET to the external VREF terminal is not essential, and the reset terminal RESET and the external reset terminal RESET may be connected via a resistor. However, a long power reset time is not required at all, and an extremely short time is sufficient.

  In any case, in this embodiment, since the reset terminal RESET is externally connected as described above, the output of the buffer BF becomes L level when the power is turned on, and thereafter, until the capacitor Cre is charged to the predetermined level. Since the L level is maintained for only a short time, the internal reset signal surely resets the power of the internal circuit of the lamp driver DR.

  By this power reset, the built-in registers R00 to R29 of the lamp driver DR are all initialized to 00H, and this value becomes a default value at the start of operation (see FIG. 8C). In the setting values of the built-in registers R00 to R29 (register numbers 00h to 1dh) shown in FIG. 8, the bit value 00000000 indicates a default value after a power reset.

  By the way, in the conventional device, the reset signal is repeatedly supplied to the reset terminal RESET every predetermined time (see the broken line in FIG. 7B). However, in the present embodiment, the reset operation for the lamp driver DR is limited to a power reset. Therefore, there is a possibility that the set values of the built-in registers R00 to R29 may be garbled due to the influence of noise or the like. The complexity of repeated signal transmission is eliminated (this point will be described later).

  Next, the operation control circuit CTL connects the voltage dividing resistors R8 to R11 for dividing the internal power supply voltage VREF, the Pch transistor Q11 receiving the voltage at the connection point of the voltage dividing resistors R8 and R9, and the connection of the voltage dividing resistors R10 and R11. the Nch transistor Q12 which receives the voltage at the point, and the protective resistor R12, is configured to include an overvoltage protection diodes D11, D12, and.

  The voltages at the drain terminals of the transistors Q11 and Q12 are 2-bit internal control signals D1 and D0, and the internal control signals D1 and D0 define the operation mode of the current introduction circuit OUT. .

  The resistance ratio between the voltage dividing resistors R8 and R19 is about 10: 1, and the resistance ratio between the voltage dividing resistors R10 and R11 is about 1:10. Then, the internal power supply voltage VREF is connected to an external VREF terminal, a connection point of the voltage dividing resistors R9, R10 are connected to the operation setting terminals OUTSET.

  Since the operation control circuit CTL is configured as described above, when the operation setting terminal OUTSET is connected to the external VREF terminal and becomes H level, the transistor Q11 is turned off, and the transistor Q11 is turned on. The internal control signals D1 and D0 are at L and L levels. Then, in this case, the current introduction circuit OUT functions in the open drain mode.

  Further, connected operation setting terminals OUTSET is to ground, when the L level, the transistor Q11 is ON, the transistor Q11 becomes OFF state, the internal control signals D1, D0 is H, the H level, the current introducing The circuit OUT functions in the constant current mode.

  On the other hand, as shown by the broken line in the figure, when the resistor Rt is connected between the operation setting terminal OUTSET and the external VREF terminal and the resistor Rt is connected between the operation setting terminal OUTSET and the ground, the operation setting terminal OUTSET The potential becomes the M level of VREF / 2. In this case, the two transistors Q11 and Q12 are both ON, so that the internal control signals D1 and D0 are at H and L levels, and the current introduction circuit OUT functions in the mixed mode.

  Although not particularly limited, in the mixed mode, for example, the current introducing circuits OUT of the LEDs 1 to 6 (R / G / B) function in the constant current mode, whereas the current introducing circuits OUT of the LEDs 7 to 8 (R / G / B) function. Are configured to function in a constant current mode.

  Current setting circuit (I-REG + D / A) is with electric feed circuit OUT functions in constant current mode, a portion defining a constant current value CST, constant current mode by detecting the current in the external setting resistor RT7 And a resistor ladder circuit Lad receiving the digital output of the first circuit I-REG and the set values of the built-in registers R00 to R01. .

  Here, three sets of resistance ladder circuits Lad are provided corresponding to eight R-type LEDs, eight G-type LEDs, and eight B-type LEDs. Then, each pair of the resistance ladder circuit Lad, based on the set value for the internal register (R00~R01) (3 bits), the resistance value is generating current prescribed resistor R4 are either eight.

  In this embodiment, since each set of resistance ladder circuits Lad sets the current regulating resistor R4, each of the eight LEDs of the R type, the eight LEDs of the G type, and the eight LEDs of the B type. Can be set to any one of 3 bits and 8 gradations.

  That is, in the present embodiment, the constant current value CST is defined based on the set resistor RT7 and the set value of 3 bits, and the drive current of each type (R / G / B) of 8 LED lamps is 3 bits and 8 floors. Since the constant current value CST is any one of the adjustment values, by making the duty ratios of the PWM control for the 24 LED lamps appropriately different, an extremely complicated and sophisticated lamp effect can be achieved.

  On the other hand, by sharing the duty ratio of the PWM control, eight LEDs of each type (R / G / B) can be made to emit light at the same optimal luminance. Anyway, the duty ratio of the PWM control, which means ON / OFF operation time ratio of the transistor Q1o~Q8o constituting the output circuit OUT, the average value of the drive current flowing to the LED lamp (light emission luminance of the LED lamp) Will be defined.

  On the upper right side of FIG. 7C, as an example, a portion for driving eight LEDs of any one type of R / G / B in the current introduction circuit OUT functioning in the constant current mode is described. As shown, the current introduction circuit OUT copies a constant current source IG that generates a constant current value CST based on a set value of a current setting circuit (I-REG + D / A), and a constant current value CST of the constant current source IG. The current mirror circuit CM is described.

  Constant current source IG is a zener diode ZD, a current limiting resistor R3, a comparator CM2, a Pch transistor Q14, a current prescribed resistor R4, in being configured. Since the voltage across the current regulating resistor R4 matches the breakdown voltage Vz of the Zener diode ZD, the drain current of the transistor Q14 always has a constant current value CST = Vz / R4.

  Next, the current mirror circuit CM performs an ON / OFF operation based on an Nch transistor Q0 through which a constant current value CST = Vz / R4 flows, Nch transistors Q1 to Q8 mirror-connected to the transistor Q0, and PWM control of a predetermined duty ratio. And Nch transistors Q1o to Q8o for controlling the conduction of the currents of the transistors Q1 to Q8.

  Since the current mirror circuit CM is configured as described above, the constant current value CST = Vz / R4 flowing through the transistor Q0 can be copied to all the transistors Q1 to Q8, and the duty ratio τ of the PWM control is temporarily reduced. when common, since oN / OFF time of the transistor Q1o~Q8o match, eight LED lamps L1~L8 the average current matches that emits light with the same brightness.

  FIG. 8A is a diagram for explaining the functions of the built-in registers R00 to R29 of the lamp driver DR. As shown, the lower three bits of the registers R00 to R02 are set values that define the constant current value CST in the constant current mode, and a constant current value of eight gradations can be set. The upper three bits of the built-in register R00 are set values that define the operation period of the control time in the PWM control.

  24-bit internal registers R03~R05 the 24 output terminals (LEDR_1-8, LEDG_1-8, LEDB_1-8) for each output signal of the duty ratio in the PWM control of the light emission luminance, and 100% fixed value Or a setting value that specifies whether to set arbitrarily. In this embodiment, the luminance of the LED lamp is controlled by arbitrarily setting the duty ratio.

  The remaining 24 built-in registers R06 to R29 are, as in the present embodiment, provided for each output signal of the 24 output terminals (LEDR_1-8, LEDG_1-8, LEDB_1-8) for the duty ratio in the PWM control of the light emission luminance. the when any setting is a register that defines the arbitrary value.

  Each output signal of the 24 output terminals (LEDR_1-8, LEDG_1-8, LEDB_1-8) has a duty cycle of 0 to 255/256 based on the set value of each 8 bits in the built-in registers R06 to R29. The ratio can be arbitrarily set, and can be controlled from a light-off state with a duty ratio of 0 to a high luminance state with a duty ratio of 99.6%.

  In the constant current mode described with reference to FIG. 7C, the current flowing through the LED lamp is PWM-controlled to a constant current value CST or zero based on a predetermined duty ratio τ. By increasing or decreasing CST × τ / 100, the emission luminance changes. As described above, when the duty ratio is 0, the light is off.

  As described above, in the present embodiment, in accordance with the number N (≦ 24) of LED lamps driven by one lamp driver DR, a predetermined time period is required for N required among the 24 built-in registers R06 to R29. (e.g. 1 / 30S) for each, by setting appropriate duty ratio τ a (0 to 99.6%), is realized emission control of the LED lamps. On the other hand, the built-in register R00~R06 is once but never set value set is changed, every predetermined time, and repeatedly set to the same value. This is because even if the set value is garbled due to noise or the like, the abnormality is quickly eliminated.

  Thus, in this embodiment, also you need not set value to be changed, so repeatedly reset every predetermined time, as in the conventional configuration, there is no need to supply repeatedly reset signal RESET at predetermined time intervals , also implements simplification of the equipment configuration by eliminating the need for wiring of the reset signal line.

  Based on the internal configuration and circuit operation of the lamp driver DR described above, the lamped driver DR mounted on the backlight board 26 may be in a constant current mode or an open drain mode depending on the type of gaming machine (necessary light emission intensity). Function. On the other hand, most of the lamp driver DR mounted on the LED substrate 25 functions in the constant current mode, and only part of the lamp driver DR functions in the mixed mode.

  The lamp driver DR of the LED substrate 25 to function in mixed mode, an output terminal of the constant current mode, the output terminal of the open drain mode are mixed, the LED lamp is connected to the output terminal of the open drain mode, When necessary, this is driven with the maximum current specified in the specification, thereby realizing a noticeable effect and a notification operation with a vivid and luminous impact.

  On the other hand, in the LED substrate 25, for LED lamps connected to the output terminal of the multiple lamp driver DR to function in constant current mode, as appropriate to the R (red) / G (green) / B (blue) type lamps By arranging and driving LED lamps having different light emission characteristics for each type at an optimum constant current value, light is emitted in three balanced primary colors.

  Although not particularly limited, the duty ratio τ of the PWM control is set to, in principle, 100% when turned on and 0% when turned off to simplify drive control. On the other hand, with respect to the predetermined LED lamp, a sophisticated lamp effect such as emission of fireflies is realized by gradually changing the duty ratio τ.

  FIG. 8B is a time chart showing an operation procedure when writing 8-bit length setting data to a predetermined built-in register of the lamp driver DR, and shows an operation of the serial output ports So1 / So2.

  As shown, the operation permission signal OE supplied to the control terminal SDEN while maintaining active (H) level, in synchronism with the clock signal SPCK supplied to the clock terminal SCLK, in a broad lamp driving data SPO, slave address And then serially transmit the register address specifying the built-in register as lamp drive data SPO in a broad sense. As described previously, in the present specification, the lamp drive data SPO has to be interpreted broadly or narrowly.

  After the above operation, the setting data (lamp drive data in a narrow sense) to be set in the specified built-in register is serially transmitted. In the lamp driver DR, with the control terminal SDEN being at the active level, at the rising edge of the 24th clock signal SPCK, the setting data transmitted thirdly is written in the internal register specified before that. It is configured to be inserted. Since this operation mode requires a signal to the control terminal SDEN, it is referred to as a three-wire transmission system in this specification for convenience.

  The case where a single 8-bit setting data is set in a specific built-in register has been described above. However, a case where setting data is set in all the built-in registers (R00 to R29), that is, one lamp driver DR has 24 When driving the LED lamps, the operation of the serial output ports So1 / So2 is as shown in FIG. That is, with the operation permission signal OE supplied to the control terminal SDEN set to the active level, the slave address is transmitted serially first, then the first register address (00h) is transmitted serially, Serial transmission of setting data.

  By these operations, the setting operation to the leading internal register (R00) is completed. However, if serial transmission is continued thereafter, the slave address is incremented by the internal operation, and then the serially transmitted setting data is reduced to 8 bits. Each time it reaches, the setting data is set in each of the built-in registers (R01 to R29).

  Since the lamp driver DR of the embodiment operates as described above, a total of 256 clock signals SPCK must be transmitted to write the setting data to one lamp driver DR. Note that the 256 bits are the same as the number of bits of the transmission data (drive data SPO), that is, 8 bits of the slave address, 8 bits of the register address, and 30 × 8 bits for 30 built-in registers. is there.

  As described above, the three-wire transmission method is used, but it is also preferable to adopt a two-wire transmission method that does not use the control terminal SDEN of the lamp driver DR (see FIG. 9A). In the two-wire transmission system shown in FIG. 9A, since the control terminal SDEN is not used, the wiring between the LED board 25 or the backlight board 26 and the effect interface board 61 is simplified, and the parallel output port Po is used. required to output an operation permission signal OE from disappears.

  In the two-wire transmission system, when the serial bit string to be transmitted satisfies the start condition in the bit mode shown in FIG. 9B, each lamp driver DRi is activated. However, it is necessary to output the BLANK bit at each break of the start condition (9 bits), the slave address (8 bits), the register address (8 bits), and the setting data (8 bits). Then, the rising edge of the BLANK bits, each column is grasped lamp driver DRi, setting data to any crab 30 of the internal registers is obtained.

  Even in the operation mode of the two-wire transmission system, after transmitting the register address of the first built-in register, the register address is automatically incremented by the internal operation, so that all the built-in registers (30 ), The transmission of 10 + 9 + 9 + 9 × 30 = 298 bits of serial data is required. As described above, in the case of the two-wire transmission method, the number of data to be transmitted to one lamp driver DR increases by the start bit (9 bits) and the BLANK bit. there is an advantage that a stretch can finish the transmission of serial data.

  That is, 3 in the case of wire transmission method, one lamp for each serial transmission of 256 bits to the driver DR, it is necessary to re-outputs an operation permission signal OE, a two-wire transmission system, N pieces of the lamp Since a total of 298 × N bits of data can be output to the drivers DR1 to DRn at a stretch, the control load on the host CPU 50 is reduced.

  FIG. 9 (c), the serial output port So1 / So2, for example, illustrates a case of driving the 32 lamp driver DR1～DR32, data in total 9536 bits as a lamp drive data SDATA (SPO), This shows a state of serial transmission.

  FIG. 10 illustrates the relationship between the backlight board 26 and the turning LED (backlight unit BL), and the backlight units BL1 to BL1 provided corresponding to the three rows of rotating reels 4a to 4c. Of the light section BL3, the backlight section BL1 is described. As described with reference to FIG. 5B, the backlight units BL1 to BL3 are directed from the inside of the rotating reels 4a to 4c to illuminate three symbols (upper, middle, and lower) in the rotating direction. Emitting light.

  As shown in FIGS. 10 and 5 (b), the backlight unit BL1 is configured by connecting three lamp boxes BX. In this embodiment, three white lamps are provided at the bottom of the lamp box BX. An LED lamp is arranged. The illustrated lamp driver DR operates in the constant current mode, and has nine output terminals (LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, and LEDB3) during the ON operation of the PWM control. , The built-in register Rij of the lamp driver DR is set so that a driving current of 40 mA flows in each.

  As shown in FIG. 10, the first lamp LP1 is connected in series to a resistor r1, the second lamp LP2 and the third lamp LP3 are connected in series to a resistor r2, and these series-connected circuits are connected in parallel to form the same standard. The same driving current of 20 mA flows through the LED lamps LP1 to LP3.

  In this embodiment, 20 mA × r2 = 20 mA × r1 + VF. Here, if the forward voltage drop VF of the LED lamp LPi is 2 V at a drive current of 20 mA, based on the relational expression of r2 = r1 + 2/20 mA and the internal voltage drop Vo of the lamp driver DR, Resistance values r1 and r2 can be set. That is, for example, when the internal voltage drop Vo is set to Vo = 1.4 V, r1 = 430Ω and r2 = 330Ω from 20mA × r2 + 4 = 20mA × r1 + 2 = 10.6.

  As described above, the design example is specifically described. However, the three LED lamps do not always emit light with exactly the same luminance based on the variation in the characteristics of the LED lamp LPi and the resistance elements r1 and r2. However, as shown in FIG. 5B, the backlight portion is arranged on the back side of the rotating reels 4a to 4c and only illuminates the design from the inside. It doesn't matter.

  However, depending on the model of the gaming machine, in many cases it wants to increase the emission intensity of the LED lamp more. FIG. 11 illustrates a configuration example in such a case, in which a high-luminance white LED lamp LP is disposed at the bottom of a lamp box BX that constitutes the turning backlight BL. Is not particularly limited, in this embodiment, the LED lamp LP bottom six to portions of the lamp box BX is placed on one of the backlight unit BLi, total of 18 LED lamp LP is disposed.

  Here, each LED lamp LP has a luminous intensity at a drive current of 80 mA, for example, about 11 cd (Candela), and is simply calculated to be 66 cd in one lamp box BX. Note that the forward voltage drop VF of the LED lamp LP is about 3V, The protective element PT to clamp reverse overvoltage is connected in parallel.

  FIG. 11 illustrates the connection state of the LED lamps of the backlight unit BL1. A total of 18 LED lamps LP are arranged at the bottom of the three lamp boxes BX to BX, which are upper, middle, and lower. ing. As shown, three LED lamps LP to LP are connected in series, and one unit of lamp block is connected in parallel with each other, and two units of lamp blocks are arranged in one lamp box BX.

  The two lamp blocks arranged in one lamp box BX are connected to the connector CN of the backlight board 26 via one transmission line LNi. Therefore, the upper, middle, and lower three lamp boxes BX to BX are connected to the backlight substrate 26 by a total of four wirings of a 12V power supply line and three transmission lines LN1 to LN3. .

  In this embodiment, the lamp driver DR functions in the open drain mode, and the current flowing into one output terminal is set to 50 mA based on the resistance value of the external resistor (current limiting resistor) Re. That is, open in the drain mode, the internal voltage drop Vo of the lamp driver DR during ON operation are the order of 0.5V, in response to the supply voltage 12V Re / 2 × Io = 12-0.5-3 × The resistance value Re corresponding to the drive current Io can be determined from the relational expression of VF.

  Thus, in this embodiment, each transmission line LN1～LN3 (backlight unit total nine), it is necessary to respectively flow 100mA. Therefore, in order to allow this drive current to flow smoothly, the 18 output terminals (LEDR3 to LEDR8, LEDG3 to LEDG8, LEDB3 to LEDB8) of the lamp driver DR are used. Then, two adjacent output terminals are connected to each other (multiple connection), and then connected to the connection connector CN. Therefore, the current in each transmission line LNi, although considerably larger (100 mA), current flowing into the output terminals is suppressed to 50 mA, there is no imposing an excessive burden on the internal circuit of the lamp driver DR.

  That is, there is no possibility that the internal circuit of the lamp driver DR abnormally operates due to an overheated state or the like. Moreover, on the two units of the ramp block (LED lamp 6), it can supply a driving current for each 50mA by a single transmission line LNi. When a plurality of output terminals are multiplexed, it is needless to say that the set value of the internal register Rij is maintained so that the logical level of each output terminal is always the same.

  For example, in the multiplex connection shown in FIG. 11, when one output terminal is at L level and the other output terminal is at H level due to noise or the like, a current of 100 mA flows into the L level output terminal. That is, if this state is prolonged, the internal circuit may be damaged. However, in the present embodiment, even if the setting values are the same, since the setting operation to the built-in register Rij is repeated in a short time cycle (1/30 second), the above problem does not occur.

  Above, a display device (LCD unit) 7 has been described a slot machine to place completely separating the rotation reel 4 a to 4 c, it is also possible to adopt a configuration that uses a transmissive LCD eliminating the color filter. FIGS. 12A and 12B are views for explaining a transmissive LCD, and show a display device 7 which realizes color display by a color field sequential system. Here, the color field sequential method is a method in which three colors of LCD backlight light of red (R), green (G), and blue (B) are switched at high speed, and a display image is switched at high speed in synchronization with the backlight. Means

  As shown in the schematic cross-sectional view of FIG. 12B, in this display device, the liquid crystal between the front and back glass substrates provided with the polarizing film is controlled based on a control voltage to the transparent conductive film ITO. In synchronization with this, color display is realized by switching the three colors of RGB backlight light (RGB light). The RGB light is emitted from above the display device 7, and is emitted from the back to the front of the display device 7 via a transparent light guide plate (not shown) (see FIG. 12B).

  In this embodiment, the rotating reels 4a to 4c are arranged behind the display device 7 (transmissive LCD), and the LCD on the front part of the rotating reel is controlled to be in a transparent state as necessary (FIG. 12 (f)). Then, at the timing the player to stop operation, a position below the transmission-type LCD 7, while controlling the front portion of the rotating reel 4a~4c in the transmission state, and displaying a demonstration video on its upper side (See FIG. 12A).

  After that, after the player finishes the stop operation, the effect animation is reproduced using the entire screen of the transmissive LCD 7 including the front portions of the rotating reels 4a to 4c, thereby realizing a large-screen image effect. ing.

  However, when the player looks at the rotating reels 4a to 4c through the transmissive LCD 7, the vividness is caused by the reflection of the torso backlight at the rear portion of the LCD and the attenuation of the torso backlight inside the LCD. But will be somewhat impaired. Here, the brightness of the backlight of the rotating body can be increased, but the countermeasure has a problem that power consumption is wasted. Furthermore, in this countermeasure, the reflected light on the LCD rear part is also increased by the amount corresponding to the enhancement of the backlight of the rotating body, and the reflected light on the rear surface of the LCD is reflected again on the surface of the rotating reel and transmitted through the LCD. There is a possibility that a noise image having a strange feeling such as a ghost image may be displayed.

  In view of the above, the inventor has repeatedly conducted various experiments and studies on the configuration of the rotating body backlight. As a result, the human visibility (the degree of brightness perceived by the eyes with respect to light energy) is not uniform with respect to wavelength but exhibits a bell-shaped characteristic centered around 550 nm (see FIG. 12 (e)). ). Therefore, it is not always necessary to enhance the strength of the reel backlight, blue (B) and the wavelength region 450～495Nm, led think may be supplemented with red (R) wavelength region 620～750Nm.

Next, it is conceivable to reinforce blue and red, or reinforce one of blue and / or red. However, in consideration of the reflected light from the LCD back surface, the refractive indices are N0 (air ≒ 1) and N1. The reflectance R at the interface between the two substances depends on the refractive indices N0 and N1 with respect to the vertically incident light (Equation 1), and since the refractive index has wavelength dependence, it is necessary to reinforce red. I thought it was suitable. ^{R = (N1-N0) 2} / (N1 + N0) 2 ··· ( Equation 1)

  That is, the refractive index N1 of glass or plastic is about 1.5, but each has a wavelength dependence in which the refractive index N1 drops with respect to the wavelength (see FIG. 12C), and the reflectance for red is It seems that it is advantageous to reinforce red because it is less reflective than blue.

  Moreover, the light energy E is a Planck's constant h, relative to the speed of light c, is related to E = hc / lambda, it is inversely proportional to the wavelength lambda, than to reinforce the blue (450～495Nm), red (620 (750 nm) is considered to be more advantageous in terms of energy consumption (power consumption).

  Therefore, in the present embodiment, the backlight units BL1 to BL3 are arranged in an aligned manner in which red LED lamps are added to the LED lamps arranged on the circuit board BD at the bottom of the lamp box. That is, the circuit board BD of each lamp box BX, while placing the three high-intensity white LED lamp LPw vertically two rows, between the upper and lower two rows, the red LED lamp LPr parallel vertically column 2 It was placed into individual center. As a result, it was possible to enhance the function of the backlight unit without significantly increasing power consumption. In addition, the effect that the symbols on the rotating reels 4a to 4c are more vividly illuminated by mixing the red with the white was also confirmed.

  The white LED lamp LPw uses the same elements as those in FIG. 11, and the luminous intensity at a driving current of 80 mA is, for example, about 11 cd (Candela), and the forward voltage drop VF is about 3 V. The protective element PT to clamp reverse overvoltage is connected in parallel. The drive current of the white LED lamp LPw is set to 70 mA by appropriately setting the current limiting resistor r1 (r1 = 45Ω). Therefore, with simple calculation, the white light emission luminance of one lamp box BX is approximately the same as the case of the configuration of FIG. 11 (66 cd).

  Incidentally, FIG. 12 (d) shows the spectral characteristics of the white lamp LPW, a red phosphor and a green phosphor disposed around the blue LED, is irradiated with light emission by the blue LED into red and green phosphors This realizes white with high color rendering properties.

  On the other hand, the red LED lamp LPr has a luminous intensity at a drive current of 20 mA, for example, about 220 mcd, and a forward voltage drop VF is about 2 V. By appropriately setting the current limiting resistor r2 (r2 = 280Ω), the driving current of the red LED lamp LPr is set to 30 mA. Therefore, with simple calculation, the emission luminance of red light in one lamp box BX is about 440 mcd.

  As described above, the light emission luminances of white and red are greatly different, but as described above, the symbols on the rotating reels 4a to 4c are more vividly illuminated only by adding a little red to white. Further, it was felt that the light passing through the transmissive LCD was considerably increased. It should be noted that the power consumption that increases due to the addition of the red color is about 360 mW per lamp box BX at most, which is not a problem.

  Next, the lamp driver DR functions in the open drain mode in the circuit configuration of FIG. 12 (h). After connecting two adjacent output terminals to each other, the eight lamp drivers DR arranged in the lamp box BX are connected. LED lamp is being driven. As described above, the white LED lamp is driven at 70 mA, and the red LED lamp is driven at 30 mA, for a total of 170 mA. Since this 170 mA is shared by two output terminals, each output terminal The current flowing into the lamp driver DR is suppressed to 85 mA, so that an excessive load is not applied to the internal circuit of the lamp driver DR. In the lamp driver DR of the embodiment, the maximum rating of the inflow current is about 100 mA, and there is a 15% current margin.

  12 (h) is used in the transmissive LCD (display device) 7, so that the timing at which the rotating reels 4a to 4c should be hidden, that is, the display device 7 is displayed in full screen. At the same time, the light is turned off. When the light is turned off, the duty ratio in the PWM control is 0%, and otherwise, it is 100%.

  Figure 13 is arranged to effect control board 60 control processor GEPR, and an image processor VDP, a display device 7 constituted by a transmission LCD, the connection relationship between the lamp driver DR which is arranged on a backlight substrate 26 Is illustrated. As described above, the lamp driver DR drives and controls the backlight units BL1 to BL3 having the circuit configuration of FIG. 12H in the open drain mode for each lamp box BX.

  Then, corresponding to the presence of nine lamp boxes BX (see FIG. 12G), the lamp driver DR as a whole includes 6 × 9 white LED lamps LPw and 2 × 9 red LEDs. Driving the lamp. Note that these backlight units BL1 to BL3 are arranged in a rotating reel area on the back side of the display device 7 configured by a transmissive LCD.

  In this embodiment, the image processor VDP operates intermittently every 1/30 second, and receives a display list for specifying a display content for one screen (frame) of the display device 7 from the control processor GEPR. Image data for one screen is generated in the frame buffer FB. Then, the generated image data is output to the display device 7 together with the horizontal / vertical synchronization signals HSYC / VSYC at the next operation timing.

  The image data output to the display device 7, and if the effect image on the entire display screen plus reels region and effect region is drawn, only the effect region, there is a case where the effect image is drawn. When the spinning reels 4a to 4c are rotating, the latter operating state is set, and the spinning reel area is controlled to be transparent to the spinning reels 4a to 4c.

  As described above, the circuit configuration and the circuit operation of the effect control unit 22 have been mainly described. Subsequently, the control operation of the CPU core of the main control board 50 (hereinafter, referred to as the main control unit 50) will be described with reference to FIG. The control operation of the CPU of the effect control board 60 (hereinafter, referred to as effect control unit 60) for image-controlling the transmissive LCD will be described with reference to FIGS.

  First, the process of the main control unit 50 includes a main process (FIG. 14A) executed in an infinite loop after turning on the power, a timer interrupt process repeatedly started every 1 ms (FIG. 14A), It is divided into Then, when the medal insertion (ST4), after an internal lottery based on the random number value (ST6), the reel start (ST7), when the reel is stopped (ST8), the winning determination time (ST9), and, when the medal payout (ST10 ), the control command CMD is generated to identify each operation content and operating result.

  At the processing timing (STi) shown in parentheses, the control command to be created includes an insertion command (ST4), a game start command (ST6), a rotation start command (ST7), a stop acceptance command and a stop result command (ST8), The winning command (ST9) and the payout command (ST10). Then, the generated control command CMD is transmitted to the effect control unit 60 in the command output process (ST22) of the timer interrupt process. The game start command specifies the lottery result of the internal lottery process (ST6), and the stop result command specifies that the third rotating reel has stopped (final stop of the rotating reel).

  The effect control unit 60 executes an image effect, a sound effect, and a lamp effect based on the control command received from the main control unit 50 in the procedure shown in FIG. As shown in the drawing, the operation of the effect control unit 60 is intermittently repeated every 1/30 second. In the command analysis process (ST33), as shown in FIG. 15B, the type of the control command CMD is determined. When a game start command is received (ST41: Yes), the display device 7 composed of a transmissive LCD is set to a reduction mode (MD = 1), and image effects, sound effects, and lamp effects to be started from now on. Is specified (ST42). The image effects and others correspond to the lottery results of the internal lottery process (ST6), and are advance announcement effects for informing the result of the success / failure indefinitely.

  Then, when receiving a stop command results to identify the final stop of the rotating reel (ST43: Yes), the display device 7 constituted by a transmission type LCD back to maximum mode (MD = 0), should start from now image effects, sound effect, and to identify the lamp effect (ST44). At this timing, since the stop mode of the rotating reels 4a to 4c is determined, an image effect or the like corresponding to the stop mode is started.

  In the scenario progression process (ST34) executed following the command analysis process (ST33) including the above process, a new production operation (image production, audio production, and lamp production) is newly performed, even if it is newly specified. The started or running effect scenario is updated in accordance with the effect progress (ST34).

  Subsequently, VDP control processing for issuing a display list to the image processor VDP is executed (ST35). As shown in FIG. 15C, in the VDP control processing, first, the display mode MD is determined (ST50), and if the maximum mode using the entire screen (MD = 0) is updated by the scenario progress processing (ST34). based on has been directed scenario, creating a display list for drawing an effect image in the frame buffer FB (ST51). Here, the frame buffer FB (Frame Buffer) is a work area built in the image processor VDP, and means a storage area in which image data to be output to the display device 7 is written.

  On the other hand, in the reduction mode (MD = 1) in which the lower part of the screen is not used, an effect image which is a little small as a whole and which renders the lower part of the screen transparent, and a display list for drawing the effect image in the frame buffer FB are displayed. to create (ST51). Then, the display list created in any of the processes (ST51 / ST52) is issued to the image processor VDP (ST53).

  The image processor VDP operates intermittently every 1/30 second in synchronization with the effect control unit 60. However, the image processor VDP receiving the display list outputs the image data of the effect image as instructed in the display list. Is constructed and written in the frame buffer FB. Figure 15 (d) and FIG. 15 (e) is, in the case where the transmission type LCD to function in the reduction mode (MD = 1), illustrates the case of functioning with up mode (MD = 0). In the reduction mode (MD = 1), it has been clarified that the bottom of the display area, based on the illumination of the backlight unit BL1 to BL3, reels 4a~4c is vividly appear after passing through the transmissive LCD.

  When the VDP control process (ST35) as described above is completed, next, a lamp control operation (ST36) of serially transmitting lamp drive data to the lamp driver DR mounted on the LED board 25 or the backlight board 26 is executed. . As shown in FIG. 16A, the lamp control process is always repeated every 1/30 second, regardless of whether the lamp effect is to be advanced (that is, whether the lighting state of the LED lamp LP is to be changed). Therefore, even if the set value of the built-in register Rij of the lamp driver DR may be garbled due to the influence of noise or the like, the abnormality is recovered after 1/30, which is a practical problem. do not become.

  To describe based on the above, first, to identify a set of drive data to be transmitted, to identify a reference position of the lamp drive table TBL shown in FIG. 18 (b) (ST61). The lamp drive table TBL describes a series of data illustrated in FIG. 8C for each of the lamp drivers DR1 to DRn (see FIG. 7A). For example, for the lamp driver DR to drive the 24 LED lamps in the appropriate compartments of the lamp driving table TBL, slave address and the first register address +30 pieces of setting data (= total 32 bytes) is stored.

  On the other hand, for the lamp driver DR that drives less than 24 M LED lamps, a slave address + a start register address + M setting data (= 2 + M bytes in total) are stored in the corresponding section of the lamp drive table TBL. . Incidentally, for convenience of drawing, in the circuit example of FIG. 11, a small output terminal of pin number (LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2) are illustrated so as not to use, in fact, the terminal numbers By starting use from the small output terminal and disabling the output terminals with large terminal numbers (... LEDR8, LEDG8, LEDB8), a series of setting data (2 + M bytes) starting from 00h of the register number there.

  In the case of using the lamp driver DR shown in Figure 8, regardless of the number of LED lamps to be driven, the setting data of the built-in register R00~R05 is a fixed value. When the configuration shown in FIG. 11 in which a pair of adjacent output terminals is multiplex-connected is employed, as described above, the set values for the pair of internal registers Ri and Rj corresponding to the pair of output terminals are common. is there.

  In any case, after the reference position (the head of the corresponding section) of the lamp drive table TBL is specified (ST61), the operation permission signal OE is set to the H level (ST62) and stored in the corresponding section of the lamp drive table TBL. The required number of series of lamp drive data is serially transmitted from the serial output port So1 (ST63).

  When all serial transmissions have been completed for one lamp driver DR, the operation permission signal OE is returned to the L level (ST64), and the same processing is repeated for the next one lamp driver DR (ST61). To ST64). As described above, the setting data of the built-in registers R00 to R05, which are always fixed values, are repeatedly serially transmitted every 1/30 seconds, so that the RESET signal is not transmitted. is the noise measures corresponding to the bit garbled.

  When the serial transmission process for the LED substrate 25 is completed as described above, the lamp drive data is serially transmitted to the backlight substrate 26 next. Specifically, after setting the operation permission signal OE to the H level (ST67), the display mode MD of the transmissive LCD is determined.

  Then, the lamp driving data corresponding to the display mode (reduced / maximum) is serially transmitted from the serial output port So2 to the lamp driver DR of the backlight board 26 (ST51, ST52), and the operation is performed when all the serial transmissions are completed. The permission signal OE is returned to the L level (ST70).

  Specifically, in the embodiment shown in FIG. 13, for the lamp driver DR, 18 setting data (= 18) corresponding to the slave address (00001h) + the starting register address (00h) + the 18 small terminal numbers. (Total 20 bytes) is transmitted.

  In the maximum mode, setting data with a duty ratio of 0% is transmitted to the 18 built-in registers R06 to R23 in order to turn off all the LED lamps. On the other hand, in the case of the reduction mode, setting data with a duty ratio = 100% is transmitted to the 18 built-in registers R06 to R23 in order to turn on all the LED lamps.

  Above, in FIG. 18, has been described three-wire transmission method that requires an operation permission signal OE, can also take the two-wire transmission scheme shown in FIG. 9, in this case, the processing in step ST62, ST64, ST65 Is unnecessary, and the serial transmission processing can be executed at a stretch to the plurality of lamp drivers DR1 to DRn mounted on the LED substrate 25. Also in the serial transmission to the backlight substrate 26, is not required the process of step ST67, ST70.

  As mentioned above, although the Example of this invention was described in detail, the specific description does not specifically limit this invention. For example, when it is desired to emit only a predetermined LED lamp with high luminance by using the open drain mode or the mixed mode, it is also possible to drive one LED lamp through the multiple connection shown in FIGS. It is suitable.

  That is, as shown in FIG. 9C, a plurality of output terminals of the lamp driver DR mounted on the LED board 25 may be multiplex-connected to each other, and then a specific one or a plurality of series LED lamps LP may be driven. . In the illustrated example, the drive current of the specific LED lamp LP is 100 mA, but the inflow value into the two output terminals of the lamp driver DR is only 50 mA, and even if the maximum rating of the inflow current is 100 mA. A sufficient current margin is secured.

  In the above description, the slot machine has been described as an example. However, in each embodiment, the present invention can be suitably applied to other game machines such as a ball game machine.

50 main control means 60 effect control means GEPR control processor DR lamp driver

Claims (12)

Main control means and the main control and presentation control means for executing effect operation including the ramp effect based on instructions from the unit, a has been constructed gaming machine executes a lottery processing based on a predetermined switch signal And
The lamp effect is realized by a computer circuit constituting an effect control means, by transmitting a group of serial data at an appropriate timing to a built-in register of a lamp driver for driving and controlling the effect lamp,
The computer circuit controls a predetermined plurality of output terminals of a predetermined lamp driver to output drive data of the same logic level, while controlling the predetermined plurality of output terminals to be connected to each other and transmitting the drive data based on the drive data. A gaming machine configured to drive a predetermined effect lamp. The operation modes of the lamp driver include:
An open mode in which a current flowing into the output terminal is defined by a resistance value of an external resistor;
2. The gaming machine according to claim 1, wherein a current flowing into the output terminal includes a constant current mode that can be set based on a value set in a built-in register. The plurality of output terminals of a given lamp driver are:
As a part of the output terminal, the functions in the constant current mode, the remaining output terminals, the gaming machine of claim 2, functioning in the open mode.   It said predetermined plurality of current of the total current value and the same value which flows into the output terminal, a game according to claim 1 flowing to a particular one of the effect lamp or a plurality of series-connected director lamps, Machine.   The gaming machine according to any one of claims 1 to 3, wherein a current obtained by distributing a total current value flowing into the predetermined plurality of output terminals flows to a specific one effect lamp or a plurality of effect lamps connected in series. .   The slot machine according to claim 1, wherein the effect lamp is a white lamp and a red lamp disposed between the white lamps.   The gaming machine according to claim 6, wherein the plurality of white lamps are arranged and arranged, and the number of the red lamps is smaller than the number of the white lamps, and is arranged between the white lamps.   The gaming machine according to claim 6, wherein the effect lamp is arranged so as to be located on a rear side of a display device through which a display screen can be transmitted, and emits light toward the display screen. The logic level of the drive data output by the driver is determined based on a duty ratio of PWM control,
The gaming machine according to any one of claims 1 to 8, wherein the computer circuit is configured to change the light emission state of the effect lamp by appropriately setting the duty ratio. The lamp driver has a built-in power supply circuit for generating a reference level internal power supply voltage by lowering a supply voltage,
The gaming machine according to any one of claims 1 to 9, wherein the operation mode is settable based on the internal power supply voltage output from the lamp driver.   The game according to claim 10, wherein an external element is connected to the internal power supply voltage output from the lamp driver, and a power reset operation of the lamp driver is realized based on the voltage of the external element. Machine.   The lamp driver defines a maximum current value in a constant current mode based on an externally connected resistance value, and a constant current value in a constant current mode based on a set value in a built-in register of the lamp driver. The gaming machine according to any one of claims 1 to 11, wherein the gaming machine is configured to be defined within a range not exceeding a current value.

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