JP6559731B2 - Game machine - Google Patents

Description

  The present invention relates to an electronic game machine with a built-in computer device, and is particularly preferably applied to a spinning game machine.

  In a spinning machine such as a slot machine, when a player inserts a medal into a medal slot and operates a start lever, the rotation of the rotating reel is started accordingly. When the player presses the stop button to stop the rotating reel, when the symbols are aligned on an effective stop line (hereinafter referred to as an effective line), a payout medal corresponding to the symbol is paid out.

  However, in reality, the success / failure state of each game is determined in advance by an internal lottery process in the main control unit before the player starts the stop operation, and the symbol won by the lottery process is determined by the player. The payout medal is paid out by aligning on the active line.

  Of the winning symbols, the combination of big bonus (BB) symbols is particularly valuable. When the player wins the BB role internally and the player aligns the BB symbol on the active line, a big bonus game is started. After that, the winning probability of the small role symbol is maintained extremely high. The number of dividend medals can be expected.

JP-A-2015-198715 JP 2006-063865 A

  By the way, since a lot of this type of gaming machines are densely arranged in the gaming hall, if high-level high-frequency noise is emitted, not only is it concerned about the malfunctioning of the own machine, but also the surrounding gaming machines Will also have an adverse effect.

  Therefore, the applicant has proposed various noise countermeasures such as a configuration in which a power factor correction circuit is provided on a power supply substrate (Patent Document 1) and a configuration in which a ferrite core and a varistor are provided in speaker wiring (Patent Document 2).

  However, when the commercial power supply (AC 100V) is used as it is without being stepped down by the power transformer, further measures are required. That is, radiation noise and propagation noise via the power line of the commercial power supply are legally problematic, and it is necessary to completely clear the regulations of Chapter 5 of the Electrical Appliance and Material Safety Law.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine with improved noise countermeasures.

In order to achieve the above object, the present invention executes a lottery process based on a predetermined switch signal, and controls the game operation based on the lottery result, and a main control unit A gaming machine configured to include an effect control unit that executes an effect operation based on an instruction, and a power source unit that receives an AC voltage and generates a DC voltage used by the main control unit and the effect control unit. The effect control means accesses the sound memory based on an instruction from the control processor, the sound memory that stores basic data for sound effects, and the sound processor, An audio processor that generates a digital audio signal for use, a digital amplifier that receives and amplifies the digital audio signal generated by the audio processor, and is positioned between the digital amplifier and the speaker, An LC filter that smoothes the output signal from the digital amplifier, and the LC filter includes a pair of coil input terminals connected to a pair of signal output terminals of the digital amplifier, and a pair of coil input terminals. A choke coil having first and second coil windings connected internally, and a magnetic core for electromagnetically coupling the first and second coil windings, and an internal connection to each of the first and second coil windings Of the first and second coil output terminals that have been made, the first coil output terminal, a first capacitor disposed between the ground, a second coil output terminal, and a second capacitor disposed between the ground, A third capacitor disposed between the first and second coil output terminals, and the choke coil has a winding direction of two coil windings wound around the magnetic core. , reverse direction der each other It, the capacitance of the first capacitor and the second capacitor, while the same notarized value, the capacitance of the third capacitor is a two to three times the capacitance of the first capacitor and a second capacitor It is characterized by.

  According to the present invention described above, a gaming machine with improved noise countermeasures can be realized.

It is a front view of the slot machine which concerns on an Example. FIG. 2 is a right side view (a) and a plan view (b) of the slot machine of FIG. 1. It is the figure which illustrated the front panel of the slot machine from the back. It is an internal front view of the main body case of the slot machine. FIG. 2 is a block diagram showing a circuit configuration of the slot machine of FIG. 1. It is a block diagram which shows the circuit structure of a main control board. It is a block diagram which shows the circuit structure of a power supply board. It is a circuit diagram which shows the circuit structure of a 1st power supply board | substrate. It is drawing explaining the PFC circuit of the 1st power supply board. It is a block diagram which shows the internal structure of the LLC electric current resonance control circuit of a 1st power supply board | substrate. It is drawing explaining operation | movement of a LLC current resonance control circuit. It is a block diagram showing a circuit configuration of the production interface board. It is drawing explaining the internal structure and operation | movement of audio | voice ROM. 2 is a diagram illustrating an internal configuration and operation of a speech synthesis circuit. It is a block diagram which shows the internal structure of a speech synthesis circuit in detail. It is drawing explaining the wiring of the internal structure of a 1st digital amplifier, and an upper side speaker. It is drawing explaining the wiring of the internal structure of a 2nd digital amplifier, and a lower speaker. 2 is a diagram illustrating the operation of a digital amplifier.

  Hereinafter, the present invention will be described in more detail based on examples. 1 to 4 illustrate a slot machine SL according to an embodiment. In this slot machine SL, a rectangular box-shaped main body case 1 and a front panel 2 fitted with various game members are connected via a hinge 3 so that the front panel 2 can be opened and closed with respect to the main body case 1. (FIG. 2). 1 is a front view of the front panel 2, FIG. 2 is a right side view (a) and a plan view (b) of the slot machine SL, FIG. 3 is a rear view of the front panel 2, and FIG. A front view is shown.

  As shown in FIG. 4, a symbol rotating unit 4 including three rotating reels 4 a to 4 c is disposed in the approximate center of the main body case 1, and a medal payout device 5 is disposed below the symbol rotating unit 4. On each of the rotating reels 4a to 4c, a BB symbol, an RB symbol, various fruit symbols, a replay symbol, and the like are drawn. The medal payout device 5 is provided with a medal hopper 5a for storing medals, a payout motor M, a medal payout control board ME, a payout relay board PAY, a payout sensor (not shown), and the like. Here, the medal is derived from the payout opening 5b toward the front of the drawing based on the rotation of the payout motor M. Note that medals stored exceeding the limit amount are configured to fall into the auxiliary tank 6 through the overflow portion 5c.

  The power supply boards 62A and 62B are arranged adjacent to the medal payout device 5, the main control board 50 is arranged above the symbol rotating unit 4, and the rotary setting board SET is adjacent to the main control board 50. Has been placed. In addition, inside the symbol rotating unit 4, a rotating LED drive substrate DR 1 and a rotating relay substrate IM 2 are provided, and an external concentrated terminal plate OUT is disposed adjacent to the symbol rotating unit 4.

  As shown in FIG. 1, a display device (LCD unit) 7 is disposed on the upper portion of the front panel 2. Then, various characters are displayed on the display device 7 to effectively excite the game action. In addition, three display windows 8a to 8c corresponding to the rotating reels 4a to 4c are arranged at the lower portion of the display device 7. Through the display windows 8a to 8c, about 3 symbols can be seen in the rotational direction of each of the rotating reels 4a to 4c, and a total of 9 symbols in the horizontal direction and 2 in the diagonal direction. Becomes a virtual stop line.

  On the left side of the display window 8a, an LED group 9 indicating a gaming state is provided. Below that, a payout display unit 10 for displaying the number of medals to be paid out as a gaming result, and the number of medals in a credit state are displayed. The storage number display part 11 to display is provided.

  The payout display unit 10 is configured by connecting two 7-segment LEDs, and specifies the number of payout medals, and also functions as an error indicator that displays abnormal contents when an abnormal situation occurs. .

  In the center of the front panel 2 in the vertical direction, a medal insertion slot 12 for inserting medals is provided, and adjacent thereto, a return button 13 for returning medals filled in the medal insertion slot 12 is provided. Also, a credit check button 14 for paying out a credit medal, an insertion button 15 for artificially inserting one credit medal in place of inserting a medal into the medal slot 12, and a credit medal in a pseudo manner A maximum loading button 16 for loading three sheets is provided.

  Below these game members, a start lever 17 for starting the rotation of the rotating reels 4a to 4c and stop buttons 18a to 18c for stopping the rotating reels 4a to 4c are provided.

  In the present embodiment, the internal lottery process is executed due to the operation of the start lever 17, and it is determined whether or not the internal winning state for the BB symbol or the small role symbol is present. Normally, the three rotating reels 4a to 4c start normal rotation in the forward direction, but all or part of the rotating reels 4a to 4c rotate irregularly as a notice effect for notifying the internal winning state. After that, normal rotation may start. The notice effect means an effect that informs the lottery result of the internal lottery process indefinitely.

  At the time of such a notice effect, all or a part of the image effect on the display device 7, the lamp effect for blinking the LED lamp, and the sound effect for driving the speaker are appropriately selected and executed.

  As shown in FIG. 1, a horizontally long tray 19 for storing medals and a medal outlet 20 communicating with the payout port 5 b of the payout device 5 are provided below the front panel 2. In addition, left and right lower speakers SPbL and SPbR for bass are arranged on the left and right of the medal outlet 20, and upper speakers SPtL and SPtR are also arranged on the left and right of the display device 7, respectively. Here, the lower speakers SPbL and SPbR are large speakers emphasizing deep bass, and output monaural background music (BGM) and the like at the same volume on the left and right.

  On the other hand, the upper speakers SPtL and SPtR output stereophonic music and effect sounds when necessary. Here, the music includes a background sound output as a stereo sound. Further, the notice effect by the effect sound includes operations such as sound output of only one speaker, sound movement in the horizontal direction, and sound reciprocation movement in the left and right direction for the upper speakers SPtL and SPtR.

  As shown in FIG. 3, on the back side of the front panel 2, a medal selection device 21 that selects medals inserted into the medal insertion port 12, and medals that are determined to be inappropriate by the medal selection device 21, A return passage 22 that guides the vehicle 20 is provided. In addition, a substrate case 23 that accommodates the effect control substrate 60, the effect interface substrate 61, and the like is disposed on the upper back side of the front panel 2. A game relay board IM1 for relaying signals between the various game members and the main control board 50 shown in FIG.

  FIG. 5 is a block diagram illustrating a circuit configuration of the slot machine SL according to the embodiment. As illustrated, the slot machine SL performs various presentation operations based on a main control board 50 that controls the operation of various game members including the rotating reels 4a to 4c and a control command CMD received from the main control board 50. The production control board 60 to be realized, and the power supply board 62 (62A, 62B) that receives the commercial power supply (100V), converts it to a DC voltage (5V, 12V, 18V, 24V, 36V) and supplies it to each part of the apparatus. It is configured.

  As shown in the lower center of FIG. 5, the power supply board 62 of the present embodiment receives a first power supply board 62A that directly receives commercial power (100V), and receives AC 24V and DC 24V from the first power supply board 62A to reset the power supply. And a second power supply board 62B that outputs a signal RES and a power interruption signal ABN1, ABN2.

  Here, the power reset signal RES is transmitted to each part of the apparatus including the main control board 50 and the rendering interface board 61 when the AC power is turned on. On the other hand, the power interruption signals ABN1 and ABN2 are output in synchronization with the interruption of the AC power supply, the power interruption signal ABN1 is transmitted to the main control board 50, and the power interruption signal ABN2 is transmitted to the effect interface board 61. .

  As shown in the upper center of FIG. 5, the effect interface board 61 receives various levels of DC voltages (5VB, 12VB, 18V, 36V) and a power reset signal from the power boards 62A and 61B via an appropriate relay board. RES and power interruption signal ABN2 are received (FIGS. 5 and 7).

  The effect interface board 61 receives a control command CMD and a strobe signal STB from the main control board 50 via an appropriate relay board. Various control signals (CMD, STB, ABN2) received by the production interface board 61 are transferred to the production control board 60 together with the DC voltage (5 VB, 3.3 V).

  The direct-current voltage 3.3V is generated in the converter circuit DC / DC of the effect interface board 61 based on the DC voltage 5VB received from the second power supply board 62B. In the effect interface board 61, the audio processor SDPR and the audio This is the power supply voltage of the memory SDROM (see FIG. 12).

  By the way, as shown by the broken line in the upper center of FIG. 5, the effect control board 60 and the effect interface board 61 are integrated by connector connection. The computer circuit GEPR of the effect control board 60 controls the image effect on the display device 7, the sound effect by the speakers SPt and SPb, and the lamp effect by the LED lamp or the like.

  That is, the effect control board 60 includes a control processor (computer circuit) GEPR realized by a general-purpose one-chip microcomputer, and an image processor VDP (Video Display Processor) that realizes an image effect in the display device 7 based on the control of the control processor GEPR. ), A watchdog timer WDT that outputs an abnormal reset signal RST when a program runaway of the computer circuit GEPR, a control memory PROM that stores a control program of the control processor GEPR, and an image memory that stores basic image data of the image processor VDP CGROM is installed.

  On the other hand, the effect interface board 61 includes an audio processor (speech synthesizer) SDPR that realizes an audio effect based on control of the control processor GEPR, an audio memory SDRAM that stores sound source data of the audio processor SDPR, and an audio processor SDPR. The first and second digital amplifiers AMP1 and AMP2 that amplify and output the audio signal output from the computer, and receive the DC voltage 3.3V and the power reset signal RES to receive the audio memory SDRAM, the image processor VDP, and the control processor GEPR. A first reset circuit RST1 for resetting the power, a second reset circuit RST2 for abnormally resetting the voice processor SDPR in response to the direct-current voltage 3.3V and the abnormal reset signal ERST, a converter circuit DC / DC for level-converting the direct-current voltage, Is installed Figure 12).

  As illustrated, the first digital amplifier AMP1 drives the upper speakers SPtL and SPtR, and the second digital amplifier AMP2 drives the lower speakers SPbL and SPbR.

  The production interface board 61 is connected to a rotating LED drive board DR1, an LED board DR1, and an inverter board DR2. An LED group and a cold cathode ray tube discharge tube are connected to each board DR1 to DR3. Has been. As described above, the effect control board 60 and the effect interface board 61 are integrated by connector connection, and the control processor GEPR of the effect control board 60 uses an LED lamp or a cold cathode ray tube discharge tube. The lamp effect is executed at an appropriate timing together with the image effect and the sound effect.

  Next, the main control board 50 will be described. The main control board 50 is connected to various game members of the slot machine through the game relay board IM1. Specifically, a start switch for the start lever 17, a stop switch for the stop buttons 18a to 18c, a closing switch for the closing buttons 15 and 16, a clearing switch for the clearing button 14, a door sensor for recognizing opening / closing of the front panel 2, an upstream sensor Lever detection sensor constituting S0, photointerrupters PH1, PH2 constituting medal passage sensors S1, S2, blocker solenoid SL for ON / OFF control of a blocker for preventing passage of illegal medals, various LED elements 9-11, etc. It is connected to the.

  The medal sorting device 21 according to the present embodiment includes an upstream sensor S0 (lever detection sensor), medal passage sensors S1 and S2 (photo interrupters PH1 and PH2), and a blocker solenoid SL. An upstream sensor S0 is arranged at the most upstream position adjacent to the medal slot 12, and a pair of medal passage sensors S1, S2 are arranged close to the downstream position via a blocker.

  Specifically, the upstream sensor S0 is configured to include a lever LV that swings when pressed by the medal surface, and a photointerrupter PH that performs ON / OFF operation in response to the swing of the lever LV. Yes. The upstream sensor S0 is configured to be in the ON state when the medal surface passes the medal when the lever LV is pressed, and is returned to the OFF state after the medal passes.

  The blocker is arranged at the downstream position of the upstream sensor S0 described above, and is in an introduction posture that allows passage of medals when the blocker solenoid SL is energized, and in a return posture that refuses passage of medals when not energized.

  As shown in FIG. 5, the main control board 50 detects the three stepping motors that rotate the rotating reels 4 a to 4 c and the reference positions of the rotating reels 4 a to 4 c via the rotating relay board IM2. Connected to the index sensor. Then, by rotating or stopping the stepping motor, the rotating operation of the rotating reels 4a to 4c and the stopping operation at the target position are realized.

  The main control board 50 is also connected to the medal payout device 5 through the payout relay board PAY. The medal payout device 5 is provided with a medal payout control board ME, a medal full sensor, a medal payout sensor, and a payout motor M. The medal payout control board ME receives a control command from the main control board 50. Based on this, the payout motor M is rotated to pay out a predetermined amount of medals.

  The medal full sensor detects an overflow error when the auxiliary storage is full of medals, and the medal payout sensor detects a shortage error that the number of payout medals is insufficient or an abnormal payout that is not accompanied by a payout operation by a gaming machine. ing. In addition, the main control board 50 is also connected to the external concentration terminal board OUT and the rotary setting board SET. The external concentrated terminal board OUT is connected to, for example, the hall computer HC, and the main control board 50 outputs the number of inserted medals and the number of paid out medals through the external concentrated terminal board OUT.

  Further, the rotating drum setting board SET outputs a setting key signal indicating a setting value set by a staff using a setting key. Here, the set value defines the winning probability of the lottery process executed on the gaming machine in six stages from setting 1 to setting 6, and is appropriately set based on the sales strategy of the gaming hall. . For example, a gaming machine set to the highest rank is most advantageous to the player because the expected value of the number of medals to be paid out is the highest level.

  FIG. 6 illustrates the circuit configuration of the main control board 50. As shown, the main control board 50 includes a one-chip microcomputer 64, an I / O port circuit 65 for inputting / outputting 8-bit parallel data, a counter circuit 66 for generating random values in hardware, an effect control board 60, and the like. The interface circuit with the external board is mainly configured. Here, the one-chip microcomputer 64 incorporates a CTC (Counter / Timer Circuit) 64b, an interrupt controller 64c, and the like in addition to a Z80 equivalent CPU core 64a, ROM, RAM, and the like.

  The CTC 64b is a circuit in which an 8-bit counter and a timer are integrated, and adds a periodic interrupt, a pulse output creation function (bit rate generator) and a time measurement function to the Z80 system. Therefore, in this embodiment, a timer interrupt is generated in the Z80 CPU 64a at a time interval τ of 1.5 mS using the CTC 64b.

  As the interface circuit, an interface circuit 67 with the power supply circuit, an interface circuit 68 with the game relay board IM1, a drum motor driving circuit 69, an interface circuit 70 with the effect control board 60, and the like are provided. Yes. When the power is shut off (at the time of power interruption), a voltage drop interrupt is applied to the Z80 CPU 64a through the interface circuit 67.

  The interface circuit 70 is an 8-bit parallel port for outputting a control command to the effect control board 60, and the rotating motor driving circuit 69 is a circuit that generates a driving signal for the stepping motors of the rotating reels 4a to 4c. . Each of the three stepping motors that rotate the rotating reels 4a to 4c is a two-phase motor having two sets of drive windings, and is driven by 1-2 phase excitation that repeats one-phase excitation and two-phase excitation. Yes.

  As shown in FIG. 6, the interface circuit 68 of the main control board 50 is connected to the medal sorting device 21 via the game relay board IM1. The sensor signal S0 of the upstream sensor S0 is input to the input circuit IN0, and the sensor signals S1 and S2 of the medal passage sensor S1 and the medal passage sensor S2 are input to the input circuits IN1 and IN2. The energization state of the blocker solenoid SL is controlled by the output circuit.

  FIG. 7 illustrates the internal configuration of the first power supply board 62A, the second power supply board 62B, and the effect interface board 61 mainly with respect to the power supply lines. FIG. 8 is a circuit diagram showing a part of the first power supply board 62A.

  First, the first power supply board 62A includes a filter circuit including an input resistor R0 and an input capacitor C0, an overvoltage countermeasure circuit PRT in which varistor groups VR1, VR1, and VR2 are arranged, a common mode choke coil LL, and capacitor arrays C1, C1, C2 is provided.

  Here, the common mode choke coil refers to a choke coil in which the winding directions of two coil windings wound around a magnetic core are opposite to each other. Therefore, common mode noise current flows in each winding, and the direction of the magnetic flux generated by each noise current is the same direction, and the back electromotive force generated in each winding is strengthened, thereby suppressing the noise current. Will increase.

  The capacitor rows C1, C1, and C2 include a pair of capacitors C1 and C1 disposed between the frame ground FG and the AC power supply line, and a capacitor C2 disposed between the AC power supply lines. . The capacitors C1 and C1 absorb common mode noise, and the capacitor C2 and the filter circuits C0 and R0 absorb normal mode noise.

  The overvoltage countermeasure circuit PRT functions so that surge voltage and other overvoltages do not reach the downstream side because the electrical resistance of each of the varistors VR1 and VR2 rapidly decreases at the time of overvoltage. In addition, since the three varistors VR1, VR1, and VR2 are arranged in the same manner as the capacitor rows C1, C1, and C2, the varistor functions as a capacitance element when the varistor is not energized, and the common mode and the normal mode. It also functions as a noise countermeasure.

  Since such noise countermeasures are taken at the input portion of the first power supply board, the propagation noise to the commercial power supply line (100V) is effectively suppressed. A step-down transformer is disposed downstream of the capacitor rows C1, C1, and C2, and is stepped down from AC100V to AC24V and distributed to the second power supply board 62B. Based on this AC 24V, the power reset signal RES and the power interruption signals ABN1, ABN2 are generated.

  On the other hand, AC100V is rectified by the full-wave rectification circuit RECT, and then the power factor is improved in the power factor improvement circuit 24 via the overcurrent prevention circuit RUSH. Thereafter, DC voltages 36 V, 18 V, 24 VA, and 12 VB are generated by two LLC current resonance type DC / DC converters 25 and 26. In the present specification, symbols A and B attached to the voltage values indicate the circuit board of the distribution destination, and the DC voltage attached with the attached symbol A is distributed to the main control board 50, and the attached symbol The DC voltage marked with B is distributed to the production interface board 61.

  FIG. 8 is a circuit diagram illustrating an overcurrent prevention circuit RUSH, a power factor correction circuit 24, and LLC current resonance type DC / DC converters (hereinafter abbreviated as DC converters) 25 and 26. The LLC current resonance type DC converter 25 and the DC converter 26 have the same circuit configuration. One output voltage is 36V and 18V, whereas the other output voltage is 24VB and 12VB. Details of the DC converter 26 are not shown in FIG. 8 because they are only different (see FIG. 7).

  First, the overcurrent prevention circuit RUSH is configured around a current limiting resistor R0, a switching transistor Tr0, and a half-wave rectifier circuit. The half-wave rectifier circuit rectifies high-frequency voltages from the DC transformer 25 and the sense transformers T2 and T2 ′ electromagnetically coupled to the high-frequency transformers TF1 and TF2 of the DC converter 26, and controls the ON / OFF state of the switching transistor Tr0. doing.

  That is, since the output level of the half-wave rectifier circuit is low immediately after the power is turned on, the switching transistor Tr0 is in the OFF state, and the output current of the full-wave rectifier circuit RECT flows through the current limiting resistor R0. The rush current is suppressed. After that, the output level of the half-wave rectifier circuit quickly rises, so that the switching transistor Tr0 is turned on, and all the output current of the full-wave rectifier circuit RECT flows through the switching transistor Tr0. Therefore, power consumption in the current limiting resistor R0 is not continued.

  As shown in FIG. 9, the power factor correction circuit 24 has a dedicated electronic element (IC) PFC, a choke coil L1, a switching transistor Tr1, current detection resistors RS1 and RS2, and a rectified voltage detection resistor. RV1 and RV2, a snubber circuit in which a resistor R1 and a capacitor C1 are connected in series, a smoothing circuit including a diode D1 and a capacitor C2, and output voltage detection resistors RO1 and RO2, are configured as shown in FIG. ) As shown in FIG.

  The electronic element PFC includes a current detection unit (IL Dect), a multiplier, a sawtooth wave generation unit (Saw tooth OSC) with a switching frequency of about 60 kHz, a comparator (PWM Com) that outputs a PWM wave, a driver A portion Dr. The PWM having a switching frequency of about 60 kHz is based on the rectified voltage specified by the detection resistors RV1 and RV2, the rectified current specified by the detection resistors RV1 and RV2, and the output voltage specified by the detection resistors RO1 and RO2. A wave is output.

  As a result, the switching transistor Tr1 is turned on / off in an appropriate conduction time, and the ON current of the transistor Tr1 is smoothed by the choke coil L1, thereby improving the power factor as shown in FIG. 9B. Coil current. Further, since the spike-like energization current does not flow to the rectifier diode as in the case of the full-wave rectifier circuit alone, the harmonics of the spike-like energization current do not become a noise source of the power supply circuit.

  However, by providing the power factor correction circuit 24, an ON current having a switching frequency flows in the transistor Tr1 (see the drain potential in FIG. 9B), and this ON current (PWM wave) may become a noise source. There is also. Therefore, in this embodiment, a snubber circuit including a resistor R1 and a capacitor C1 is provided between the drain and source of the transistor, thereby effectively suppressing the generation of high frequency noise.

  Next, the LLC current resonance type DC converters 25 and 26 will be described. Here, the LLC current resonance type DC converter is a DC converter in which a series resonance circuit is formed by the excitation inductance Lm and leakage inductance Lr (see FIG. 11) of the high frequency transformers TF1 and TF2 and the resonance capacitor Cr. is there. A switching transistor arranged in a half-bridge type or a full-bridge type is optimally turned on / off by an LLC resonance circuit, and a DC voltage is obtained from a rectifier circuit provided on the output side of the high-frequency transformers TF1 and TF2.

  A specific circuit configuration of the DC converter 25 is as shown in FIG. 8, and the illustrated DC converter 25 includes a dedicated electronic element (IC) LLC and switching transistors Tr2 and Tr3 arranged in an asymmetric half-bridge type. And the primary side T1 and the secondary sides T5 and T6 of the high-frequency transformer TF1 and two rectifier circuits. The internal configuration of the dedicated IC (LLC) is as shown in FIG.

  The rectifier circuit includes a first full-wave rectifier circuit including rectifier diodes D10, D11, D12, and D13 that receive a high-frequency voltage generated on the secondary sides T5 and T6 of the high-frequency transformer TF1, and a secondary side T5 and T6 of the high-frequency transformer TF1. The second full-wave rectifier circuit is divided into rectifier diodes D12 and D13 that receive the generated high-frequency voltage. The bridge-type first full-wave rectifier circuit is configured to output DC36V, and the second full-wave rectifier circuit is configured to output DC18V.

  The contents of the operation are as shown in FIGS. 11A to 11J with respect to the principle diagram. As shown in the figure, the high-frequency transformer TF1 is an equivalent circuit in which a leakage inductance Lr and an excitation inductance Lm are connected in series, and on the secondary side of the ideal transformer corresponding to the primary currents I2 and I3 on the primary side of the ideal transformer. , A secondary current (load current) Io corresponding to the turn ratio N2 flows.

  As shown in the figure, in the operation states of FIGS. 11A and 11J where Tr2 = ON and Tr3 = OFF, the LC resonance current I2 flows through the primary circuit, and the secondary current Io corresponding to the turn ratio N2 is generated. It flows to the secondary circuit. Further, in the operation states of FIGS. 11 (e) and 11 (f) where Tr2 = OFF and Tr3 = ON, the LC resonance current I3 flows through the primary circuit, and the secondary current Io corresponding to the turn ratio N2 is secondary. It flows in the circuit. In each operation state, the full-wave rectifier circuit functions to generate a DC voltage of a predetermined level.

  The DC converters 25 and 26 of the first power supply board 62A shown in FIG. 7 have been described above. Next, the second power supply board 62B will be described with reference to FIG. As illustrated, the second power supply board 62B receives DC 24V from the first power supply board and generates DC voltages 12VA, 5VA, and 5VB at various levels, and the DC / DC converters 27A to 27C. A voltage drop detection unit 28 that receives a detection voltage corresponding to an output voltage of 27C and detects an abnormality in any output voltage, and an AC monitor that receives power 24V from the first power supply board 29A to detect power-on and power-off. The circuit 29 includes a detection circuit 30 in a power-on state, and a detection circuit 31 in a current interruption state.

  The AC monitoring circuit 29 includes a rectifier circuit that receives the AC 24 and a photocoupler, and a DC output of the rectifier circuit turns on the photodiode. Therefore, when the power is turned on, the phototransistor quickly turns on, and when the power is turned off, the phototransistor quickly turns off. The detection circuit 30 outputs a power reset signal RES corresponding to the ON transition operation of the phototransistor, and the detection circuit 31 outputs the power interruption signals ABN1 and ABN2 corresponding to the OFF transition operation of the phototransistor. .

  At the bottom of FIG. 7, a part of the production interface board 61 is described. As shown in the figure, the production interface board 61 receives the power interruption signal ANB2, the power reset signal RES, and the DC voltage 5VB from the second power supply board 62B, and receives the DC voltages 12VB, 18V, and 5VB from the first power supply board 62A. It is configured as follows.

  FIG. 12A is a circuit diagram for explaining the function of the effect interface board 61. As shown in FIG. 12A, the effect interface board 61 receives DC5VB received from the second power supply board 62B, generates DC 3.3V and DC1.0V, and the first DC / DC converters 32A and 32B. A reset circuit RST1, a second reset circuit RST2, a speech processor (speech synthesis circuit) SDPR that realizes speech production based on the control of the control processor GEPR, and a speech memory SDRAM that stores sound source data of the speech processor SDPR are shown. Has been.

  In the voice memory SDRAM, as a sound source data, a series of background music (BGM) and a group of effect sounds such as a group of warning sounds are stored as phrase compression data corresponding to the phrase numbers. ing.

  The first reset circuit RST1 receives the DC voltage 3.3V and the power reset signal RES, and resets the power of the sound memory SDRAM, the image processor VDP, and the control processor GEPR (see FIG. 5). The second reset circuit RST2 receives the DC voltage 3.3V and the abnormal reset signal ERST and abnormally resets the sound processor SDPR. As described above, the abnormal reset signal ERST is an output signal from the watchdog timer WDT indicating that the control processor GEPR has run out of program.

  The first and second reset circuits RST1 and RST2 are the same circuit except for the capacitors Cd1 and Cd2. The voltage dividing resistors R10 and R11 that divide the DC voltage VDD, the comparator CMP, the delay circuit Dely, and the delay time Capacitors Cd1 and Cd2 that define (reset periods T1 and T2) and complementary-connected output transistors CMOS are configured.

  In the case of the first reset circuit RST1, the power reset signal RES received from the second power supply board 62B is supplied to the delay circuit Dely. Then, as shown in the time chart of FIG. 12B, after the power reset signal RES transitions from the L level to the H level, the reset period T1 defined by the capacitor Cd1 and the reset signal RESET1 that maintains the L level are output. The

  Also, when the DC voltage VDD exceeds the specified level, the reset signal RESET1 having the same reset period T1 is output. In the present embodiment, the timing at which the DC voltage VDD exceeds the specified level and the timing at which the power supply reset signal RES transitions to the H level are close to each other, so from any later timing to the predetermined reset period T1 The reset signal RESET1 that maintains the L level is output.

  In this embodiment, the DC voltage VDD = 3.3 V is the power supply voltage of the audio processor SDPR and the audio memory SDROM, and the reset period T1 of the reset signal RESET1 is about 1 to 5 μS. Therefore, after the normal level power supply voltage 3.3V is supplied to the audio memory SDROM, the audio memory SDRAM enters the start-up state after a reset period T1 of about 1 to 5 μS.

  Next, when the DC voltage VDD = 3.3 V exceeds a specified level, the second reset circuit RST2 outputs a reset signal RESET2 having a predetermined reset period T2. The reset period T2 is set to three times or more of the reset period T1, and is preferably about 7 to 15 μS.

  In this embodiment, the power supply voltage of the voice processor SDPR is 3.3V and 1.0V. However, since the two DC voltages reach the specified level at close timing, the power supply voltage of the voice processor SDPR is 3.3V. , 1.0V reaches the specified level, and then the voice processor SDPR is activated after the voice memory SDROM reaches the activation start state. Therefore, no trouble occurs even if the activated voice processor SDPR immediately accesses the voice memory SDROM thereafter.

  Further, the abnormal reset signal ERST received from the effect control board 60 is supplied to the delay circuit Dely of the second reset circuit RST2. Accordingly, when the control processor GEPR runs out of program, the audio processor SDPR is also abnormally reset together with the control processor GEPR and the image processor VDP based on the abnormal reset signal ERS. Therefore, the image effect, the lamp effect, and the sound effect by the control processor GEPR are returned to the initial state in synchronization, and the unnatural effect is not continued.

  FIG. 13 is an internal configuration (FIG. 13A) of a sequential access type audio memory SDRAM and a time chart (FIG. 13B) when the audio processor SDPR accesses (memory reads) the audio memory SDRAM. . Here, the sequential access means an operation of reading a series of data following the head address at a time after transmitting the head address to the voice memory SDRAM at the time of memory read.

  As shown in FIG. 12, the audio processor SDPR and the audio memory SDROM have a 16-bit I / O bus, a command latch enable signal CLE, a chip enable signal CE, a write enable signal WE, and an address latch. The enable signal ALE, the read enable signal RE, and the ready / busy signal RB are connected.

  The I / O bus is used for transmitting address information and transmitting / receiving 16-bit data. In the memory read operation, the voice processor SDPR first outputs command data (for example, 0000H) in synchronization with the command latch enable signal CLE, and then in synchronization with the write enable signal WE across a predetermined interval. Then, the head address of the audio data read operation is sequentially output 16 bits at a time (Address Write cycle).

  Next, the audio processor SDPR sequentially accesses the audio data after the head address by repeating the output operation of the read enable signal RE at a predetermined time interval. In the case of the present embodiment, the voice memory SDROM constitutes one page with N * 16 bit length, and constitutes one block with M pages.

  By repeating the output operation of the read enable signal RE, the memory read operation for one block can be realized at most. In this embodiment, one block has a length of M * N * 16 bits, and there is an advantage that a large amount of audio data can be acquired at once without transmitting address information. Therefore, it is possible to quickly acquire a long-duration effect sound.

  FIG. 14A illustrates a schematic internal configuration of the audio processor SDPR and a connection relationship among the control processor GEPR (host CPU), the audio memory SDROM, and the digital amplifier AMP. FIG. 15 shows the internal configuration of the speech synthesis circuit in more detail.

  As shown in FIG. 14 (a), the audio processor SDPR includes a number of audio control registers 51 (RGi, RSj) accessed from the control processor GEPR, a sound control module 52 that controls the audio reproduction operation in an integrated manner, The main generator 53 for decoding the phrase compressed data read from the memory SDRAM and mixing the decoded data of the plurality of phrase reproduction channels CH0 to CH15 at an appropriate volume ratio, and a desired frequency characteristic by digital filter processing The effector 54 that realizes the equalizer function that realizes the output and the compressor function that changes the input / output gain characteristics, the total volume TV that defines the final volume, and four types of signals SCLK, LRCLK, SDO0, and SDO1 for serial transmission are generated A digital IF section 55, includes a is configured that.

  The voice control register 51 performs a read process by the control processor GEPR in order to grasp the operation state of the write register RGi to which the control processor GEPR performs a write process and the voice processor SDPR in order to make the voice processor SDPR function as intended. And read register RSj.

  Each voice control register 51 is given a 1-byte register address, a 1-byte operation parameter (setting value) can be written to the write register RGi, and a 1-byte register from the read register RSj. Status information can be acquired. When the control processor GEPR performs read access to the write register RGi, a 2-byte voice command SND of register address + operation parameter is transmitted from the control processor GEPR to the voice processor SDPR.

  The write data (setting value) to the write register RGi includes (1) a phrase number for specifying a BGM sound or effect sound to be reproduced, (2) a volume (V1, V2) instruction of the reproduced sound, (3 ) Loop instruction that defines the number of playbacks, (4) Operation instruction such as playback start and pause, (5) Panpot instruction that is the volume balance of the upper and lower speakers and left and right speakers, (6) Final volume (TV) Instructions are included.

  As shown in FIG. 14, the audio processor SDPR functions with power supply voltages of 3.3 V and 1.0 V, and is reset to an initial state upon receiving a reset signal RESET2 of the reset period T2 from the reset circuit RST2. As described above, since the reset circuit RST2 functions based on the power supply voltage 3.3V and the abnormal reset signal ERST, the voice processor SDPR is not only when the power is turned on, but also when the control processor GEPR is abnormal, Reset in synchronization with GEPR.

  Next, returning to FIG. 12, the connection relationship between the control processor GEPR and the audio processor SDPR will be described. As shown in FIG. 12, the control processor GEPR and the voice processor SDPR have parallel signal lines (data buses) CD0 to CD7 capable of transmitting and receiving 1-byte data, and a 2-bit length operation management data line (transmitting operation management data). The address buses A0 to A1, the control signal lines WR and RD having a 2-bit length capable of controlling read / write operations, and the chip select signal line CS for selecting the audio processor SDPR are connected.

  The parallel signal lines CD0 to CD7 are realized by the data bus of the control processor GEPR, and the operation management data lines A0 to A1 are realized by the address bus of the control processor GEPR. The voice processor SDPR is provided with three port numbers PORT having the upper 6 bits in common and the lower 2 bits of 00, 01, 10, and the control processor GEPR has assigned I to these port numbers PORT. When the / OREAD instruction or the I / OWRITE instruction is executed, the circuit is configured so that the chip select signal CS becomes an active level in any case.

  The data output to the lower 2 bits A0 to A1 of the address bus when the I / OREAD instruction or the I / OWRITE instruction is executed becomes the operation management data A0 to A1 for the voice processor SDPR. Based on this, it is specified whether the 1-byte data of the data buses CD0 to CD7 at that time is a register address, or write data or read data.

  That is, if the address data A0-A1 is [00], the data bus data CD0-CD7 at that timing is evaluated as a register address, while if the address data A0-A1 is [01], The data CD0 to CD7 on the timing data bus become write data or read data. The read data is executed when the I / OREAD instruction is executed, and the write data is executed when the I / OWRITE instruction is executed.

  Therefore, the transmission operation (write operation) of the voice command SND for writing the predetermined set value in the predetermined voice control register RGi is as shown in the time chart of FIG. 12C, and the port number PORT of the voice processor SDPR is set. This is realized by continuously executing the I / OWRITE instruction while shifting the lower two bits A0 and A1. Specifically, the lower 2 bits A0 to A1 of the address data are changed from [00] → [01], while 1-byte data of the data bus is changed to [register address of the voice control register RGi] → [voice control]. By shifting the write data to the register RGi], the transmission operation of the predetermined voice command SND is realized.

  As in the case of transmitting a SAC number (13 bits), a sequence code number (13 bits), and accompanying control data (such as standby information and loop information), the write data has a length of multiple bytes and is controlled. If the register addresses of the register are consecutive, the operation management data A0 to A1 of [01] are repeated in the order of [00] → [01] → [01] → [01], and a plurality of bytes of write data is transmitted. .

  The voice command transmitted in this manner is subsequently validated within the voice processor SDPR as long as there is no communication abnormality. However, if a communication error is recognized, such as data having a plurality of bytes inconsistent with each other, the voice command SND is not activated. Then, the error flag of the voice control register RSj is set. This error flag (status information STS) changes the operation management data A0 to A1 of the address bus from [01 = 1] to [10 = 2]. The I / OREAD instruction can be received (see FIG. 12E).

  As described above, in this embodiment, error information (abnormality of a plurality of bits) is obtained in the final cycle in which the operation management data A0 to A1 are changed from [00] → [01] →... [01] → [10]. FFH) can be obtained. Then, by retransmitting the voice command SND that could not be properly transmitted in parallel, the voice effect can be appropriately advanced. Therefore, according to the configuration of the present embodiment, it is possible to reliably eliminate the unnaturalness that the sound effect suddenly stops.

  On the other hand, the data reading operation by the I / OREAD operation is as shown in the time chart of FIG. 12D, and the lower 2 bits A0 and A1 of the port number PORT of the voice processor SDPR are changed and the I / OWRITE instruction is changed. This is realized by continuously executing the I / OREAD instruction. Here, the upper 6 bits of the port number PORT generate a chip select signal of the audio processor SDPR, and enable an I / OWRITE instruction and I / OREAD for the audio processor SDPR.

  Specifically, first, as the I / OWRITE operation, for the port number PORT in which the lower 2 bits A0 to A1 of the address data are [00], [the register address of the voice control register RSj that stores the operation status and the like. (1 byte length)] is output. Next, if the I / OREAD instruction is executed for the port number PORT in which the lower 2 bits A0 to A1 of the address data are [01], necessary data such as operation status is obtained from a predetermined voice control register. Can do. When the read data has a length of a plurality of bytes, the I / OREAD instruction is continued for the required number of bytes.

  As shown in FIG. 14, the audio reproduced by the audio processor SDPR having the above configuration is converted into a digital audio signal of the audio processor SDPR in the form of a 4-bit signal (SCLK, LRO, SDO0, SDO1) and the digital amplifier AMP1. , AMP2 and D-class amplified by each digital amplifier and supplied to each speaker as an analog audio signal. Specifically, the amplified output (analog audio signal) of the digital amplifier AMP2 is supplied to the lower speakers SPbL and SPbR for bass, and the amplified output (analog audio signal) of the digital amplifier AMP1 is supplied to the upper speaker SPtL, SPtR is supplied.

  As shown in FIGS. 14A and 15, the main generator 53 includes a decoder 60 divided into 16 phrase reproduction channels (CH0 to CH15) that can be independently decoded, a primary volume V1, and a secondary volume. A volume V2; a channel volume having a panpot section and adjustable sound volume and volume balance; and a channel mix section 61 for mixing the sound of the 16 phrase playback channels (CH0 to CH15). Configured.

  As shown in FIG. 15, the L0 signal, the R0 signal, the R1 signal, and the L1 signal are output for each phrase reproduction channel (CH0 to CH15). These four types (16 × 4 signals in total) are The signals are mixed by the channel mixing unit 61 and output as a mixed L0 signal, a mixed R0 signal, a mixed R1 signal, and a mixed L1 signal.

  Here, the mixed L0 signal is finally supplied to the left upper speaker SPtL, the mixed R0 signal is finally supplied to the right upper speaker SPtR, and the mixed R1 signal and the mixed L1 signal are finally Supplied to the lower speakers SPbL and SPbR. At this stage, each signal (L0, R0, R1, L1) is digital data.

  In this embodiment, (1) phrase number designation, (2) volume (V1 / V2) instruction, (3) loop instruction, (4) operation instruction, (5) voice transition mode instruction, and (6) All the panpot instructions are configured to be performed by designating the phrase reproduction channels CH0 to CH15 of the decoder 60. Therefore, up to 16 types of phrase compressed data corresponding to the phrase reproduction channels CH0 to CH15 are independently reproduced based on the above instructions (1) to (6), and mixed by the channel mixing unit 61. Will be output.

  By the way, the sound control module 52 causes each part of the apparatus to function for each instruction based on the individual instructions from the control processor GEPR written in the control register RGi. In order to simplify the control operation of the control processor GEPR, The voice processor SDPR of this embodiment is provided with a simple access function and a sequencer function.

  Here, the simple access function refers to a group of voice command sequences (register address + set value) registered in advance in an external memory (specifically, voice memory SDROM) and a plurality of control registers RGi corresponding thereto. It is a function to write to. In order to implement the simple access function, the control processor GEPR sends a 2-byte voice command including a SAC number for specifying a group of voice command strings and a register address of a dedicated control register to the voice processor SDPR. It is enough to send to.

  The sequencer function is also the same. A plurality of groups of voice command sequences (register addresses + setting values) registered in advance in the voice memory SDRAM are stored in a plurality of control registers RGi corresponding thereto. It is a function to write every. Then, after writing a group of voice command strings, a plurality of phrase playback and volume / pan functions can be performed by performing an operation such as writing the next group of voice command strings after a waiting time. It becomes possible to execute one after another. Even when this sequencer function is made effective, it is sufficient to transmit a multibyte-length voice command including a sequence code number for specifying a group of voice command strings and a register address of a dedicated control register to the voice processor SDPR.

  As described above, the main generator 53 includes the decoder 60 divided into a plurality of phrase reproduction channels, and a channel volume having a primary volume portion V1 and a secondary volume portion V2 (see FIG. 15). Accordingly, in response to such a configuration, the control processor GEPR of the present embodiment uses the decoders of the phrase reproduction channels CH0 to CH1 for reproducing the BGM sound, and 13 phrases for reproducing the effect sound. Any one of the reproduction channels CH2 to CH14 is used, and the decoder for the phrase reproduction channel CH15 is used for audio notification for notifying the occurrence of a serious abnormal situation.

  Then, an effective sound effect is realized by appropriately setting the volume balance of the primary volume V1 of the phrase reproduction channels CH0 to CH14 for realizing the sound effect. Specifically, when the production sound is output, the volume of the BGM sound is suppressed to prevent the production sound from being overheard. In the present embodiment, the production sound is, for example, a warning sound for notifying with a predetermined reliability (≦ 100%) that there is a possibility of shifting to a big hit state during a series of fluctuating operations, and the phrase reproduction channel CH0. By appropriately setting the volume balance of the primary volume V1 of -CH14, the possibility that the notice sound important for the player is hidden in the high-volume BGM sound is solved.

  In the present embodiment, since the upper and lower panpots can be set for each phrase playback channel, the control processor GEPR has a slightly higher volume for the upper speaker based on the positional relationship between the upper speaker and the lower speaker. The volume balance is set for all phrase playback channels. Specifically, for all phrase playback channels, in order to set the upper and lower panpot settings to an appropriate volume ratio, appropriate operating parameters are written in the upper and lower panpot control registers, and the upper and lower panpot ratios are set, for example, +2 dB: −2 bB is set (FIG. 15).

  In this embodiment, since the left and right panpots can be set for each phrase playback channel, when reproducing stereo sound, a pair of adjacent phrase playback channels CHi, CHi + 1 are used and the phrase playback channel is used. In CHi and CHi + 1, the left and right panpot ratios are set appropriately.

  For example, for the background music, the phrase playback channels CH0 and CH1 are used, and the left and right panpot ratio L0 of the phrase playback channel CH0 in order to supply the CH0 L0 signal (left audio) to the left upper speaker SPtL: R0 is set to 0 dB: −∞ dB. Further, the left / right panpot ratio L0: R0 of the phrase reproduction channel CH1 is set to −∞ dB: 0 dB: in order to supply the CH0 R0 signal (right audio) to the right upper speaker SPtR.

  Since the left and right panpot ratio L1: R1 of CH0 and the left and right panpot ratio L1: R1 of CH1 are equal ratios 0 dB: 0 dB, the left audio reproduced by CH0 and the right audio reproduced by CH1 are In the channel mixing unit 61, the CH1 L1 output and the CH1 L1 output are mixed to obtain the monaural background music L1. Similarly, the left audio reproduced by CH0 and the right audio reproduced by CH1 become the background music R1 of monaural sound by mixing the R1 output of CH0 and the R1 output of CH1 in the channel mixing unit 61. .

  In the present embodiment, since the left and right panpots can be set for each phrase playback channel, the control processor GEPR sometimes uses the L0 signal for the playback sound of the phrase playback channels CH2 to CH14 as part of the notice effect. And the volume balance of the R0 signal are different. In this case, for example, the warning sound heard from the upper left and right speakers can be moved from left to right (panning in the right direction), or conversely, moved from right to left (panning in the left direction).

  As shown in FIG. 15, the output signal (mixed L0, mixed R0, mixed L1, mixed R1) of the channel mix 61 is subjected to digital filter processing based on the operation parameters defined in the control register 51 in the effect unit 54. After that, it is supplied to the total volume unit TV.

  Here, the total volume value TV is defined by an operation parameter written in the corresponding control register 51. In this embodiment, the operation parameter is defined based on a setting switch operated by an attendant in principle. The However, when the player operates the volume switch during the game operation (but during the sound production standby), the total volume TV is defined based on the set value.

  The audio signal (PCM data) mixed L0, mixed R0, mixed L1, and mixed R1 that have passed through the total volume section TV are stored in the output buffer BUF and converted into two types of serial signals SDO0 and SDO1 based on the digital IF section 55. Is done. Here, the serial signal SDO0 is a serial signal that specifies PCM data related to the stereo signals R and L that drive the left and right speakers arranged at the upper part of the gaming machine, and the serial signal SDO1 is a heavy bass that is arranged at the lower part of the gaming machine. It is a serial signal that specifies PCM data related to a monaural signal that drives a speaker.

  These serial signals SDO0 and SDO1 are output from the digital IF unit 55 in synchronization with the bit clock signal BCO. Also, the word clock signal LRO is output from the digital IF unit 55, and it is specified whether the contents of the serial signals SDO0 and SDO1 currently being transmitted are the left signals L0 and L1 or the right signals R0 and R1. It has come to be.

  As shown in FIG. 14B, these signals SDO0, SDO1, BCO, and LRO are transmitted to the digital amplifiers AMP1 and AMP2. For example, if the digital amplifier AMP of YDA171 (YAMAHA) is used, the evaluation is performed. The bit clock signal BCO means the serial clock SCLK, the word clock signal LRO means the channel control signal LRCLK, and the serial signals SDO0 and SDO1 mean SDATA0 and SDATA1.

  The operation of the audio processor SDPR is as shown in FIG. 14B. In the state where the word clock signal LRO (channel control signal LRCLK) is maintained at the L level, the audio signals L0 and L1 of the left channel are transmitted, and the word processor While the clock signal LRO (channel control signal LRCLK) is maintained at the H level, the right channel audio signals R0 and R1 are transmitted. As described above, in this embodiment, four types of audio signals R0, R1, L0, and L1 can be transmitted with four cables, and therefore, signal transmission without noise deterioration due to noise can be performed with the minimum number of cables.

  The serial signals SDO0 and SDO1 are acquired by the digital amplifier AMP in synchronization with the rising edge of the bit clock signal BCO (serial clock signal SCLK). Then, the digital amplifier AMP performs parallel conversion for each predetermined bit length, and after DA conversion, is subjected to class D amplification and supplied to each speaker.

  17 and 18 show the case where YDA171 (YAMAHA) is used as a digital amplifier. As shown in the figure, each of the digital amplifiers AMP1 and AMP2 includes two D-class amplifiers having the same characteristics for the left (L) channel and the right (R) channel.

  The digital amplifier AMP1 shown in FIG. 16 receives the serial clock signal SCLK (BCO), the audio serial signal SDATA0 (SDO0), and the channel control signal LRCLK (LRO), so that the left channel audio signal L0 and the right channel The audio signal R0 of the channel is separated and output separately as an analog signal.

  On the other hand, the digital amplifier AMP2 shown in FIG. 17 receives the serial clock signal SCLK (BCO), the audio serial signals SDATA0 and SDATA1 (both are SDO1), and the channel control signal LRCLK (LRO). The audio signals L0 and L1 and the right channel audio signals R0 and R1 are separated and output separately as analog signals.

  As illustrated, the serial signal SDO1 is supplied as an audio serial signal SDATA0 and an audio serial signal SDATA1. In this embodiment, since the left / right panpot ratio for the L1 signal and the R1 signal is equal to 0 dB: 0 dB in all reproduction channels (see FIG. 15), the mixing L1 after being mixed by the channel mixing unit 61 The signal and the mixed R1 signal are monaural sounds having the same volume on the left and right and the same sound quality on the left and right.

  The mixed L1 and mixed R1 are transmitted as the serial signal SDO1 for the left and right speakers, and are supplied to the digital amplifier AMP2 connected in a circuit as shown in FIG. Therefore, all the signals output from the four internal circuits (L0ch, L1ch, R0ch, R1ch) of the digital amplifier AMP2 are the same sound.

  As shown in FIG. 16, in the digital amplifier AMP1, only the two internal circuits of the four internal circuits (L0ch, L1ch, R0ch, R1ch) function, and the audio signal transmitted to the left upper speaker SPtL The audio signal R0 transmitted to L0 and the right upper speaker SPtR is output from the digital amplifier AMP1.

  On the output side of the digital amplifier AMP1, an LC filter composed of a common mode choke coil CHL1 and capacitor rows C10, C11, C12 is arranged. Until now, the applicant has used a ferrite core and a varistor on the output side of the digital amplifier (Patent Document 2). However, in this configuration, the above configuration was completed as a result of repeating experiments based on the knowledge that the propagation noise to the commercial power line cannot be effectively suppressed.

  Here, the common mode choke coil has a four-terminal structure in which two coil windings are wound around a ferrite core, and the winding direction of the pair of windings is opposite. Therefore, common mode noise current flows in each winding, and the direction of the magnetic flux generated by each noise current is the same direction, and the back electromotive force generated in each winding is strengthened, thereby suppressing the noise current. (See FIG. 16B).

  On the other hand, for the differential current in the differential direction, the direction of the magnetic flux generated by the differential current in each winding is reversed, so the counter electromotive force generated in each winding is canceled and does not function as an inductor. Does not disturb the differential current. That is, the choke coil CHL1 according to the embodiment not only smoothes the output signal from the digital amplifier AMP1 in cooperation with the capacitor arrays C10, C11, and C12, but also suppresses common mode noise to the commercial power supply line. The propagation noise is effectively suppressed.

  Hereinafter, an LC filter that smoothes an output signal from the digital amplifier AMP1 will be described with reference to FIGS. As shown in FIG. 16C, on the output side of the digital amplifier AMP, transistor groups Q1 and Q2 constituting a CMOS structure are arranged in a pair on the upper and lower sides. In FIG. 16C, the common mode choke coil CHL1 is connected between the connection point OUTPL0 of the upper transistor groups Q1 and Q2 and the connection point OUTML0 of the lower transistor groups Q1 and Q2.

  In addition, the capacitor C10 is disposed between the two output terminals of the common mode choke coil CHL1, and the capacitors C11 and C12 are disposed between the two output terminals of the choke coil CHL1 and the ground, respectively. Is realized. The circuit constant of each element is individually set based on the switching frequency Fs (250 KHz to 1.5 MHz) that defines the internal operation of the digital amplifier. Typically, the common mode choke coil of 10 to 30 μH is used. It is concluded that it is preferable to use CHL1, 0.05 to 0.2 μF capacitors C11 and C12 (C11 = C12), and a capacitor C10 having a capacitance about two to three times that of the capacitors C11 and C12. doing.

  Hereinafter, in the digital amplifiers AMP1 and AMP2, the duty ratio τ of the PWM wave changes based on the digital audio signals L0 and R0 received from the audio processor SDPR. Based on the PWM wave, the upper transistor group Q1, Q2 and each transistor in the lower transistor group Q1, Q2 are driven ON / OFF.

  FIG. 16C shows a case where the duty ratio τ of the PWM wave with the frequency Fs is 50%. When the PWM wave is at the H level (left side), the transistor Q2 of the upper transistor group and the lower transistor The group transistor Q1 is turned on. Therefore, when the capacitor C11 is charged, the potential difference between the capacitor C11 and the ground tends to increase. On the other hand, when the capacitor C12 is discharged, the potential difference between the capacitor C12 and the ground tends to decrease.

  Next, when the PWM wave is at the L level (right side), the transistor Q1 of the upper transistor group and the transistor Q2 of the lower transistor group are turned on. Therefore, when the capacitor C12 is charged, the potential difference between the capacitor C12 and the ground tends to increase. On the other hand, when the capacitor C11 is discharged, the potential difference between the capacitor C11 and the ground tends to decrease.

  When the duty ratio τ of the PWM wave is 50%, the operation time on the left side of FIG. 16C and the operation time on the right side of FIG. 16C are the same. The potential difference between the capacitor C12 and the ground is the same, the voltage across the capacitor C10 is 0 V, and no audio current flows through the speaker. Even if there is a common mode noise current that has passed through the common mode choke coil CHL1, the common mode current charges the capacitors C11 and C12 having the same capacitance. Is not superimposed on the audio current going to the speaker.

  Next, the operation when the duty ratio τ of the PWM wave is higher than 50% will be described based on FIG. In this case, since the operation time on the left side of FIG. 18 (a) is longer than the operation time on the right side of FIG. 18 (a), on average, the potential of the capacitor C11 is higher than the potential of the capacitor C12. Thus, the voltage across the capacitor C10 is such that the upper terminal of the capacitor C10 is lower than the lower terminal, and the illustrated audio current flows.

  On the other hand, when the duty ratio τ of the PWM wave is smaller than 50%, the operation time on the right side in FIG. 18 (b) is longer than the operation time on the left side in FIG. 18 (b). The potential of the capacitor C12 is higher than the potential of the capacitor C11, and the voltage across the capacitor C10 has a relationship in which the upper terminal of the capacitor C10 is higher than the lower terminal, and the illustrated audio current flows.

  As described above, in the present embodiment, the choke coil CHL1 as the LC filter includes the capacitor rows C10, C11, and C12. Therefore, the capacitor C10 absorbs the normal mode noise while preventing the common mode noise. High-quality sound output is realized on the upper left speaker SPtL. The same applies to the upper right speaker SPtR. As described above, the stereo can be output from the left and right speakers.

  On the other hand, since the monaural sound is always supplied to the lower speakers SPbL and SPbR, a common audio serial signal (L1 + R1) is supplied to the SDATA0 terminal and the SDATA1 terminal of the digital amplifier AMP2, and the choke coil CHL1 on the upper side of the figure is also shown. In addition, the L0ch output and the R0ch output are supplied redundantly to drive the lower left speaker SPbL.

  In addition, the lower right speaker SPbR is driven by supplying the L1ch output and the R1ch output redundantly to the lower choke coil CHL1 shown in the figure.

  By adopting such a driving method, the output power of the lower speakers SPbL and SPbR that output monaural sound is increased. Note that the upper and lower panpot ratios shown in FIG. 15 are set to +0.2 dB on the upper side and −0.2 dB on the lower side, based on the circuit configuration of FIG.

  As mentioned above, although the Example of this invention was described in detail, the concrete description content does not specifically limit this invention. For example, in the embodiment, the slot machine has been described, but the present invention can be suitably applied to other gaming machines such as a ball game machine.

50 Main control means 60 Production control means 62 Power supply means GEPR Control processor SDROM Audio memory SDPR Audio processor AMP1, AMP2 Digital amplifier CHL1 Choke coil C11 First capacitor C12 Second capacitor C10 Third capacitor

Claims (1)

Main control means for executing a lottery process based on a predetermined switch signal, and comprehensively controlling a gaming operation based on the lottery result, and an effect control means for executing an effect action based on an instruction from the main control means And a power supply unit that receives an AC voltage and generates a DC voltage used by the main control unit and the effect control unit,
The production control means is configured to control the production operation in a centralized manner, a voice memory for storing basic data for voice production, and access to the voice memory based on an instruction from the control processor. An audio processor that generates a digital audio signal, a digital amplifier that receives and amplifies the digital audio signal generated by the audio processor, and an LC filter that is positioned between the digital amplifier and the speaker and smoothes the output signal from the digital amplifier And configured with
The LC filter is
A pair of coil input terminals connected to a pair of signal output terminals of the digital amplifier, first and second coil windings internally connected to the pair of coil input terminals, and first and second coil windings A choke coil having a magnetic core to be electromagnetically coupled;
Of the first and second coil output terminals internally connected to the first and second coil windings, respectively, a first coil output terminal and a first capacitor disposed between the ground,
A second coil output terminal, a second capacitor disposed between the grounds,
A third capacitor disposed between the first and second coil output terminals,
The choke coil, winding directions of the two coil windings wound around the magnetic core, Ri reverse der each other,
The capacitance of the first capacitor and the second capacitor is the same as the notarized value, while the capacitance of the third capacitor is 2 to 3 times the capacitance of the first capacitor and the second capacitor. A featured gaming machine.

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