JP2020004772A - Printed circuit board with jumper portion - Google Patents

Printed circuit board with jumper portion Download PDF

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Publication number
JP2020004772A
JP2020004772A JP2018120006A JP2018120006A JP2020004772A JP 2020004772 A JP2020004772 A JP 2020004772A JP 2018120006 A JP2018120006 A JP 2018120006A JP 2018120006 A JP2018120006 A JP 2018120006A JP 2020004772 A JP2020004772 A JP 2020004772A
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jumper
board
sub
main board
printed
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博志 橋本
Hiroshi Hashimoto
博志 橋本
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RB Controls Co Ltd
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RB Controls Co Ltd
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Abstract

To solve a problem in which, when a printed wiring board is designed, as the size of the printed wiring board is reduced, it is necessary to form a jumper portion that blocks a part of a printed pattern and solder a chip jumper and the like to make the jumper portion conductive later, and as the size of the printed wiring board is reduced, the number of such jumper portions increases, and therefore, the number of steps for soldering the chip jumpers also increases.SOLUTION: A printed circuit board on which an electronic component is mounted is used as a main board, and a sub-board is provided separately from the main board, and a printed pattern for a jumper portion that connects the jumper portions to each other is formed on the sub-board, and the jumper portions are made to conduct with each other by soldering the sub-board to the main board.SELECTED DRAWING: Figure 1

Description

本発明は、主基板の表面に導体からなるプリントパターンを備え、このプリントパターンに、電気的に遮断されたジャンパ部を有するプリント配線基板に関する。   The present invention relates to a printed wiring board having a printed pattern made of a conductor on the surface of a main board, and having a jumper portion that is electrically interrupted on the printed pattern.

回路設計が行われると、その設計された回路に基づいて基板の表面に導電性を有する銅箔などによるプリントパターンが設計される。基板の大きさに制限がない場合には、プリントパターンを自由に設計することができるが、基板の大きさを小さくするに伴ってプリントパターンの設計に対する制限が増える。その結果、2系統のパターンを交差させなければならない場合が発生する。   When a circuit is designed, a printed pattern made of a conductive copper foil or the like is designed on the surface of the substrate based on the designed circuit. If the size of the substrate is not limited, the printed pattern can be freely designed, but as the size of the substrate is reduced, the restriction on the design of the printed pattern increases. As a result, a case may occur in which two systems of patterns must intersect.

このような場合には、交差する2系統のうちの一方を遮断しジャンパ部を形成し、チップジャンパなどの別部材を用いて、この遮断されたジャンパ部を電気的に接続することによって、交差する2系統を短絡させることなく交差させる場合がある(例えば、特許文献1参照)。   In such a case, one of the two intersecting systems is cut off to form a jumper portion, and another member such as a chip jumper is used to electrically connect the cut off jumper portion to thereby form a crossover. There is a case where two systems cross each other without short-circuiting (for example, see Patent Document 1).

特開2013−120894号公報(図3〜図6図)JP 2013-120894 A (FIGS. 3 to 6)

ジャンパ部の個数が少ない場合には、各ジャンパ部ごとにチップジャンパをハンダ付けする工数は少ないが、ジャンパ部の個数が増加するに伴ってチップジャンパなどをハンダ付けする工数が多くなり、基板の作成コストが増加する。   When the number of jumpers is small, the number of steps for soldering chip jumpers for each jumper is small, but as the number of jumpers increases, the number of steps for soldering chip jumpers etc. increases, and Creation costs increase.

そこで本発明は、上記の問題点に鑑み、ジャンパ部の個数が多くても各ジャンパ部を電気的に接続する工数が少なくなるジャンパ部を有するプリント配線基板を提供することを課題とする。   In view of the above problems, it is an object of the present invention to provide a printed wiring board having a jumper section in which the number of steps for electrically connecting each jumper section is reduced even if the number of jumper sections is large.

上記課題を解決するために本発明によるジャンパ部を有するプリント配線基板は、主基板の表面に導体からなるプリントパターンを備え、このプリントパターンに、電気的に遮断されたジャンパ部と、このジャンパ部を電気的に導通させるジャンパ部材とを有するプリント配線基板において、上記主基板のプリントパターンには複数のジャンパ部が設けられており、これら複数のジャンパ部の各々を導通させるジャンパ用プリントパターンを表面に被着させた1枚の副基板を上記ジャンパ部材として形成し、この1枚の副基板を上記主基板に対してハンダ付けすることによって主基板のプリントパターンの複数のジャンパ部を導通させることを特徴とする。   In order to solve the above-mentioned problems, a printed wiring board having a jumper according to the present invention includes a printed pattern made of a conductor on the surface of a main board. And a jumper member for electrically connecting the plurality of jumper portions to the printed pattern of the main board. Forming one sub-substrate adhered to the above as a jumper member, and soldering the one sub-substrate to the main substrate to conduct a plurality of jumpers of the printed pattern of the main substrate. It is characterized by.

上記構成によれば、複数個所のジャンパ部を1枚の副基板によって電気的に接続することができる。   According to the above configuration, a plurality of jumpers can be electrically connected by one sub-board.

なお、主基板上には各種の電子部品が実装されており、副基板を主基板にハンダ付けすると、実装されている電磁部品に副基板が干渉する場合が生じる。この場合には、上記副基板には、上記主基板の表面に実装された電子部品を回避する切除部を形成すればよい。   Various electronic components are mounted on the main board, and when the sub-board is soldered to the main board, the sub-board may interfere with the mounted electromagnetic components. In this case, a cutout for avoiding an electronic component mounted on the surface of the main board may be formed in the sub-board.

ところで、主基板と副基板とが異なる材料で形成されていると、両者の線膨張係数が相違するため、加熱および冷却が繰り返されるとハンダ付け部分にストレスが作用して、ハンダ付け部分が剥離するおそれが生じる。このような不具合が生じないようにするため、上記主基板および副基板は共に同一の材料で形成されていることが望ましい。   By the way, if the main substrate and the sub-substrate are formed of different materials, the coefficients of linear expansion of the two are different. Therefore, when heating and cooling are repeated, stress acts on the soldered portion, and the soldered portion peels off. May occur. In order to prevent such a problem from occurring, it is desirable that both the main substrate and the sub-substrate are formed of the same material.

以上の説明から明らかなように、本発明は、複数個所のジャンパ部を1枚の副基板によって電気的に接続することができるので、ジャンパ部の個数が多くても各ジャンパ部を電気的に接続するための工数が多くなることがない。   As is apparent from the above description, according to the present invention, since a plurality of jumpers can be electrically connected by one sub-board, even if the number of jumpers is large, each jumper can be electrically connected. Man-hours for connection do not increase.

本発明の一実施の形態の構成を示す図FIG. 1 is a diagram showing a configuration of an embodiment of the present invention. ハンダ付け部分の構造を示す部分断面図Partial sectional view showing the structure of the soldered portion

図1を参照して、1は主基板であり、表面には複数の電子部品12が実装されている。これら複数の電子部品12を電気的に接続して回路を形成するために、銅箔からなるパターンが形成されている。このパターンには本来接続されるべきであるが遮断されている複数のジャンパ部11が設けられている。これらジャンパ部11は後述する副基板2をハンダ付けすることによって相互に導通され、電子回路が完成するように構成されている。   Referring to FIG. 1, reference numeral 1 denotes a main board, on which a plurality of electronic components 12 are mounted. In order to electrically connect the plurality of electronic components 12 to form a circuit, a pattern made of copper foil is formed. This pattern is provided with a plurality of jumpers 11 which should be connected but are interrupted. These jumpers 11 are electrically connected to each other by soldering a sub-substrate 2 to be described later, so that an electronic circuit is completed.

副基板2には上記主基板1に設けられているジャンパ部11を相互に導通させるためのジャンパ用のプリントパターン3が設けられている。本実施の形態では、副基板2に3個のプリントパターン3を設けた。   The sub-board 2 is provided with a printed pattern 3 for jumpers for electrically connecting the jumpers 11 provided on the main board 1 to each other. In the present embodiment, three printed patterns 3 are provided on the sub-board 2.

各プリントパターン3は両端のハンダ付け部31と両ハンダ付け部31をつなぐ導通部32とから構成されている。そして、この副基板2を主基板1にハンダ付けする際に、ハンダ付け部31と上記ジャンパ部11とを相互にハンダ付けすることによって、一対のジャンパ部11が導通部32を介して導通することになる。   Each print pattern 3 includes soldering portions 31 at both ends and a conductive portion 32 connecting both soldering portions 31. When the sub-board 2 is soldered to the main board 1, the soldering portion 31 and the jumper portion 11 are soldered to each other, so that the pair of jumper portions 11 conduct through the conduction portion 32. Will be.

なお、副基板2には、上記電子部品12との干渉を避けるために、切除部である窓穴21が形成されている。また、副基板2を主基板1にハンダ付けする際に、両者の間に所定の隙間が形成されるように、スペーサ22を取り付けた。   In addition, a window hole 21 which is a cutout portion is formed in the sub-board 2 in order to avoid interference with the electronic component 12. When soldering the sub-substrate 2 to the main substrate 1, the spacers 22 were attached so that a predetermined gap was formed between them.

本実施の形態では、上記電子部品12を主基板1にハンダ付けする際に、主基板1の表面にハンダペーストを塗布し、その塗布したハンダペースト上に電子部品12を載置し、その状態で加熱することによってハンダペーストを溶融させ、その後冷却することによって各電子部品12を主基板1に実装する。   In the present embodiment, when the electronic component 12 is soldered to the main substrate 1, a solder paste is applied to the surface of the main substrate 1, and the electronic component 12 is placed on the applied solder paste. The electronic components 12 are mounted on the main substrate 1 by heating the solder paste to melt the solder paste, and then cooling the solder paste.

副基板2は電子部品12を主基板1に実装する際に同時にハンダ付けする。図2を参照して、上述のように、ハンダ付け部31を主基板1側のジャンパ部11にハンダ付けする。そのため、ハンダ付け部31に予め複数の小さなボール状のハンダ球4を付着させ、その状態でハンダ付け部31とジャンパ部11とを合わせて加熱することによって、ハンダ球4を溶融させて両者を相互にハンダ付けすることにした。なおこの際、上記スペーサ22によって主基板1と副基板2との間に所定の隙間が確保されるので、溶融したハンダが周囲にはみ出すことがない。   The sub-board 2 is soldered at the same time that the electronic component 12 is mounted on the main board 1. Referring to FIG. 2, as described above, soldering section 31 is soldered to jumper section 11 on main board 1 side. Therefore, a plurality of small ball-shaped solder balls 4 are attached to the soldering portion 31 in advance, and the soldering portion 31 and the jumper portion 11 are combined and heated in this state, so that the solder balls 4 are melted and both are melted. We decided to solder each other. At this time, since a predetermined gap is secured between the main substrate 1 and the sub-substrate 2 by the spacer 22, the molten solder does not protrude to the periphery.

このように、主基板1に対して複数箇所において副基板2がハンダ付けされると、その後加熱冷却された際に、主基板1と副基板2との線膨張係数が異なると、膨張収縮量が相違し、ハンダ付けした部分にストレスが作用する。そこで、主基板1と副基板2とは同じ材料を用い、線膨張係数が同じになるようにした。   As described above, when the sub-substrate 2 is soldered to the main substrate 1 at a plurality of locations, if the linear expansion coefficients of the main substrate 1 and the sub-substrate 2 are different after heating and cooling, the expansion and contraction amount However, stress acts on the soldered portion. Therefore, the same material is used for the main substrate 1 and the sub-substrate 2 so that the linear expansion coefficients are the same.

なお、本発明は上記した形態に限定されるものではなく、本発明の要旨を逸脱しない範囲内において種々の変更を加えてもかまわない。   The present invention is not limited to the above-described embodiment, and various changes may be made without departing from the gist of the present invention.

1 主基板
2 副基板
3 (ジャンパ用)プリントパターン
4 ハンダ球
22 スペーサ
DESCRIPTION OF SYMBOLS 1 Main board 2 Sub-board 3 Print pattern (for jumper) 4 Solder ball 22 Spacer

Claims (3)

主基板の表面に導体からなるプリントパターンを備え、このプリントパターンに、電気的に遮断されたジャンパ部と、このジャンパ部を電気的に導通させるジャンパ部材とを有するプリント配線基板において、上記主基板のプリントパターンには複数のジャンパ部が設けられており、これら複数のジャンパ部の各々を導通させるジャンパ用プリントパターンを表面に被着させた1枚の副基板を上記ジャンパ部材として形成し、この1枚の副基板を上記主基板に対してハンダ付けすることによって主基板のプリントパターンの複数のジャンパ部を導通させることを特徴とするジャンパ部を有するプリント配線基板。   A printed wiring board comprising a printed pattern made of a conductor on the surface of the main board, the printed pattern having a jumper portion electrically interrupted and a jumper member for electrically conducting the jumper portion. The printed pattern is provided with a plurality of jumpers, and one sub-substrate having a surface on which a jumper printed pattern for conducting each of the plurality of jumpers is formed as the jumper member. A printed wiring board having a jumper section, wherein a plurality of jumper sections of a printed pattern of the main board are electrically connected by soldering one sub-board to the main board. 上記副基板には、上記主基板の表面に実装された電子部品を回避する切除部が形成されていることを特徴とする請求項1に記載のジャンパ部を有するプリント配線基板。   The printed wiring board having a jumper according to claim 1, wherein the sub-board is formed with a cutout for avoiding an electronic component mounted on a surface of the main board. 上記主基板および副基板は共に同一の材料で形成されていることを特徴とする請求項1または請求項2に記載のジャンパ部を有するプリント配線基板   3. The printed wiring board having a jumper according to claim 1, wherein the main board and the sub board are formed of the same material.
JP2018120006A 2018-06-25 2018-06-25 Printed circuit board with jumper portion Pending JP2020004772A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63299293A (en) * 1987-05-29 1988-12-06 Toshiba Corp Printed wiring substrate
JPS6412595A (en) * 1987-07-07 1989-01-17 Tokyo Keiki Kk Mounting structure of printed board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63299293A (en) * 1987-05-29 1988-12-06 Toshiba Corp Printed wiring substrate
JPS6412595A (en) * 1987-07-07 1989-01-17 Tokyo Keiki Kk Mounting structure of printed board

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