JP2019092925A - Game machine - Google Patents

Abstract

To provide a game machine capable of reducing possibility in which unintended access is made to a specific storage area.SOLUTION: An address of a storage area is specified using data stored in a Q register, and an LDQ instruction to read the data from the storage area of the specified address is executed. A predetermined value capable of specifying the upper address "F0" of a game RAM area is stored in the Q register until timing T0 in which stop of power supply to a game machine is detected, and a specific value capable of specifying the upper address "F5" of an internal function register which is different from the game RAM area is stored when stop of power supply to a game machine is detected.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a gaming machine capable of playing a game.

  As a gaming machine, a predetermined bet number is set, and based on the start operation being performed, a slot machine in which variable display of a plurality of types of identification information is performed, a game medium such as a game ball, etc. There is a pachinko gaming machine or the like in which variable display of a plurality of types of identification information is performed when a game medium has won in a starting area such as a winning opening provided in the game area.

  As this type of game machine, there has been proposed a game machine that specifies an address of a storage area and executes a specific instruction to read data by accessing the storage area of the specified address (see, for example, Patent Document 1).

JP, 2014-83327, A

  In the gaming machine described in Patent Document 1, there is a risk that an unintended access may be made to the specific storage area if the specific instruction has been issued due to a malfunction when the specific storage area is to be protected. The

  The present invention has been made in view of such problems, and an object of the present invention is to provide a gaming machine capable of reducing the possibility of unintended access to a specific storage area.

(1) A gaming machine capable of playing a game,
Based on a program, a specific instruction (for example, an LDQ instruction) for specifying an address of a storage area using data stored in a predetermined storage area (for example, Q register) and reading data from the storage area of the specified address Instruction execution means (for example, the main control unit 41) to execute;
In order to restore the control state based on the data stored in the specific storage area (for example, the game RAM area) when the power supply to the gaming machine is detected (for example, the process of Sa16 to Sa26 in FIG. 5) Stop the power supply (for example, the process of supplying backup power to the game RAM area, the process of evacuating the register shown in Sk1 to the game RAM area, the process of evacuating the stack pointer to the game RAM area of Sk2 etc.) Processing execution means (for example, the main control unit 41) to be executed (in the power interruption process of FIG. 6) when
In the predetermined storage area (for example, Q register),
Predetermined value data used to specify the address of the specific storage area (for example, a predetermined value capable of specifying the upper address “F0” of the game RAM area) until the stop of the power supply to the game machine is detected Are stored (for example, as shown in FIG. 7, the predetermined value is stored in the Q register until the timing T0 at which the power-off process is performed).
Specific value data (for example, an internal function register which is an area different from the game RAM area) used to specify an address of an area different from the specific storage area when a stop of power supply to the game machine is detected A specific value capable of specifying the upper address "F5" is stored.

  According to such a configuration, when the stop of the power supply is detected is an unstable state from the viewpoint of the power supply, and a specific instruction is erroneously executed in such an unstable state. Even in this case, the possibility of unintended access to an important specific storage area in which data for restoring the control state when power supply is stopped can be reduced.

  In addition, the address of the storage area (including a specific storage area and an area different from the specific storage area) includes the first information (for example, the upper address of the address) and the second information (for example, the lower address of the address) For example, it is preferable to store the first information in a predetermined storage area (for example, a Q register). Then, in the specific instruction, an address is specified from the first information and the second information, and data is read out from the storage area of the specified address. At the time of this reading, an address is specified from the first information stored in the predetermined storage area and the second information specified by the specific command. According to such a configuration, the program capacity of the specific instruction can be reduced as compared with the configuration in which both the first information and the second information are specified in the specific instruction to specify the address.

(2) In the gaming machine of (1),
The specific value data is data used to specify the address of the area to be initialized when the power supply to the gaming machine is started (for example, the specific value is executed before the start process). The upper address of the internal function register that is initialized in the startup setting process can be specified).

  According to such a configuration, even if a specific instruction is erroneously executed in an unstable state, an area to be initialized when power supply is started is accessed, but such an area Even when accessed, it is possible to reduce the occurrence of particular problems.

(3) In the gaming machine of (1) or (2),
Generation of confirmation data (for example, RAM corruption diagnostic fixed data shown in Sk 4 and RAM parity adjustment data shown in Sk 7 shown in FIG. 6) for confirming whether the data stored in the storage area is normal or not The confirmation data generation process (for example, the process of Sk4 and Sk7 in FIG. 6) to be stored in the specific storage area is executed (for example, in the power-off process) when the stop of the power supply is detected. Further comprising data generation processing execution means,
The specific value data is stored in the predetermined storage area (for example, the Q register) after the confirmation data generation process is performed (for example, as illustrated in FIG. 6, the processes of Sk4 and Sk7 are performed). (Sk 8 sets a specific value in the Q register).

  According to such a configuration, even if the specific instruction is erroneously executed after the confirmation data is stored in the specific storage area, the confirmation data is stored in the specific storage area in which the confirmation data is stored. The possibility of access can be reduced.

(4) (1) to (3) In any of the gaming machines,
After the specific value data is stored in the predetermined storage area (for example, after the processing of Sk 8) when the stop of the power supply to the gaming machine is detected (for example, in the power-off processing of FIG. 6) And storing special value data (for example, RAM access prohibition flags shown in Sk9 and Sk10 and power interruption setting flags such as interrupt prohibition flags) corresponding to the stop of the power supply in a special area (for example, internal function register) Further comprising special value storage means for causing
The specific instruction is an instruction for specifying an address of a storage area using data stored in the predetermined storage area, and storing data in the storage area of the specified address based on the program (for example, LDQ) The instruction is also used to execute the process of setting data in the area),
The specific value data is data used to specify a part of the address of the special storage area (for example, a value capable of specifying the upper address “F5” of the internal function register), and the special storage area Data that can specify an address other than the partial address among the addresses is specified by the specific instruction (the lower address of the internal function register is specified by the LDQ instruction).

  According to such a configuration, it is possible to reduce the program capacity of the instruction for storing the special value in the special area when the stop of the power supply is detected.

(5) (1) to (4) In any one of the gaming machines,
The program includes a specific program (for example, a game program) and a non-specific program (for example, a non-game program).
The specific storage area (for example, a game RAM area) is an area in which data used in the specific program is stored,
The address of the specific storage area includes first information (for example, upper address of the address) and second information (for example, lower address of the address)
The first information is stored in the predetermined storage area (for example, Q register),
The specific instruction is an instruction for specifying an address from the first information and the second information specified by the specific instruction, and reading data from the specific storage area of the specified address,
The command execution unit executes the specific command based on the specific program, but does not execute it based on the non-specific command (for example, an LDQ command is used in a game program but an LDQ command in a non-game program) Is not used).

  According to such a configuration, since the specific instruction is not executed based on the non-specific program, the storage area in which the data used in the specific program is stored is accessed by executing the specific instruction in the non-gaming program. Can be reduced. Therefore, it is possible to reduce the possibility of unintended access to a storage area in which data used in a specific program is stored.

(6) In any one of (1) to (5) gaming machines,
The program includes a specific program (for example, a game program) and a non-specific program (for example, a non-game program).
The address of a program storage area (for example, a gaming program area) in which a program used in the specific program is stored is first information (for example, upper address of the address) and second information (for example, lower address of the address) Including) and
The first information is stored in a special storage area (for example, a vector table area),
A special instruction (for example, an RST instruction and a CALLV instruction) specifies an address from the first information and the second information specified by the special instruction, and reads a program from the program storage area of the specified address. It is an instruction,
The instruction execution means executes the special instruction based on the specific program but does not execute it based on the non-specific program (for example, in a game program, an RST instruction and a CALLV instruction are used, but the non-game program Does not use the RST and CALLV instructions).

  According to such a configuration, since the special instruction is not executed based on the non-specific program, the special instruction is executed in the non-gaming program, whereby the storage area storing the program used in the specific program is accessed. Can be reduced. Therefore, it is possible to reduce the possibility of executing an unintended access to the storage area in which the program used in the specific program is stored.

It is a schematic diagram of the slot machine of the embodiment to which the present invention is applied. It is a figure which shows the memory map of ROM which a main control part mounts, and RAM. It is a figure which shows the detail of the memory map of ROM which a main control part mounts, and RAM. It is a flowchart which shows the control content of the starting process which a main control part performs (the 1). It is a flowchart which shows the control content of the starting process which a main control part performs (the 2). It is a flowchart which shows the control content of the power failure process which a main control part performs. It is a figure which shows the timings, such as prohibition of RAM access.

[overall structure]
FIG. 1 is a schematic view showing an example of the overall configuration of a gaming machine. FIG. 1A is a schematic view showing an example of the main appearance configuration of the gaming machine 1. FIG. 1 (b) is a schematic view showing an example of the main internal configuration of the gaming machine 1.

  As shown in FIG. 1A, the gaming machine 1 according to the present embodiment is provided with a liquid crystal display 51, one or more speakers 53 capable of outputting various sounds, as a rendering means for performing rendering. , And one or more lamps 63 capable of emitting light in various modes. The liquid crystal display 51 functions as display means for displaying an image. The speaker 53 functions as a sound output unit that outputs a sound. The lamp 63 functions as a light emitting unit that emits light.

  As shown in FIG. 1 (b), inside the gaming machine 1 is a game control board 40 for controlling the progress of the game and outputting various commands according to the progress of the game, and a predetermined effect according to the command. An effect control board 90 or the like for controlling the image is provided. The game control board 40 includes a main control unit 41 that performs processing related to the progress of the game and controls a configuration mounted or connected to the game control board 40. The effect control board 90 receives a command transmitted from the game control board 40 and performs processing for performing effects, and also includes a sub control unit 91 that controls the configuration mounted or connected to the effect control board 90.

  In addition, the main control unit 41 includes a central processing unit (CPU) 41 a, a read only memory (ROM) 41 b, and a random access memory (RAM) 41 c. The sub control unit 91 further includes a CPU 91a, a ROM 91b, and a RAM 91c.

  Also, the main control unit 41 includes a plurality of input ports and a plurality of output ports. Each of the plurality of output ports outputs various signals (control signals for controlling various motors, lights, display units, etc.). Various signals (an operation detection signal from the writing operation unit, a power failure detection signal described later, and the like) are input to each of the plurality of input ports. In the following, although the gaming machine 1 is described as a slot machine, the following concept can be applied to other gaming machines (for example, pachinko gaming machines).

  When playing a game in the slot machine, first, a specified number of bets is set by inserting a medal into the medal insertion portion or operating the MAX BET switch. As a result, the pay line is activated, the operation to the start switch is activated, and the game can be started. If a medal is inserted with the number of bets set, that amount is increased to credits.

  When the start switch is operated in a state where the number of bets for which one game can be started is set (the state where the game can be started), a plurality of (for example, three) reels are rotated to display symbols in a fluctuating manner. The rotation of the corresponding reel is stopped by operating the stop switches respectively corresponding to the reels. Then, three symbols are derived and displayed as a display result on the upper, middle, and lower portions of the see-through window. When a winning is generated by stopping the combination of winning symbols on the winning line LN, a predetermined number of medals are awarded to the player according to the winning.

  In addition, the target combination to be drawn by the internal drawing is called a selection object combination or a winning combination. In order for the part to be won, the part must be won by the internal lottery.

[About memory area and program of main control unit]
FIG. 2 is an address map of a memory area used by the main control unit 41. As shown in FIG. 2, the memory area used by the main control unit 41 includes memory areas (0000H to 7FFFH) allocated to the ROM 41b and memory areas (F000H to FFFFH) allocated to the RAM 41c.

  The memory area of the ROM 41b includes a program / data area (0000H to 26FFH) in which programs and fixed data are stored, a ROM comment area (2700H to 277FH) in which arbitrary data such as program title and version can be set, and The vector table area (2780H to 27A7H) in which the upper address of the subroutine of the CALLV instruction to be executed and the start address of the timer interrupt processing (main) are set, and the parameters for setting the internal function of the main control unit 41 as hardware Is set, and an unused area (2800H to 7FFFH) in which access is prohibited.

  The parameters set in the HW parameter area in the ROM 41b include the final address (HPRGEND) of the ROM area used in the program / data area, the start address (HRAMSTAT) of the RAM area to be accessed and the final address (HRAMEND).

  The memory area of the RAM 41c is an internal function register area (F500H to F500H to which a usable area (F000H to F400H) usable as a work and a register group for controlling each function mounted on the main control unit 41 are stored. F6FFH) and unused areas (F401H to F4FFH, F700H to FFFFH) in which access is prohibited. Although not particularly shown in FIG. 2, the memory area of the RAM 41c includes a signal area to be described later. Similar to the internal function register, the upper address of the signal area is assumed to be "F5".

  FIG. 3 is an address map of a program / data area in the ROM 41 b of the main control unit 41 and an available area in the RAM 41 c.

  As shown in FIG. 3A, the program / data area in the ROM 41b is a game program area in which a game program related to the progress of the game is stored, a game data area in which game data used by the game program is stored, and It includes a use area 1, a non-play program area where a non-play program not related to the progress of a game is stored, a non-play data area where non-play data used by the non-play program is stored, and an unused area 2. .

  In addition, the progress of the game is to advance a series of processes constituting the game, and in the case of a slot machine, set the number of bets and enable the start of the game, start the game and rotate the reels. The step of stopping the reel and the step of deriving the display result, and the step of imparting a value such as a medal according to the display result are advanced.

  A game program area related to the progress of the game and a non-game program not related to the progress of the game are separately allocated, and are allocated backward in the storage area of the ROM 41b of the game program area and the non-program area. Since the area before the non-program area is allocated the unused area 1 of at least 16 bytes or more, a storage area is a game program area related to the progress of the game and a non-game program not related to the progress of the game. Can be easily identified according to the difference between

  Also, while the game program area and the game data area, the non-game program area and the non-game data area are respectively allocated to continuous areas, the game program area and the game data area related to the progress of the game and the non-regardless of the progress of the game Because the game program and the non-game data area are allocated to the non-continuous area across the unused area 1 of at least 16 bytes or more, the game program area and the game data area pertaining to the progress of the game, and the progress of the game Non-play programs and non-play data areas that are not involved can be easily identified according to the difference in storage area.

  In the above description, the front and back of the storage area refers to the magnitude relationship of the address values assigned to the storage area. The smaller the address is the front and the larger the address is the rear. Therefore, a storage area allocated later than one storage area corresponds to a storage area whose address value is larger than that of one storage area, and a storage area allocated ahead of one storage area. A storage area whose address value is smaller than that of one storage area corresponds to this.

  In addition, the game program may be allocated behind the non-game program area, and the unused area may be allocated in front of the game program allocated behind the non-game program area. A game program area related to the progress of the game and a non-game program not related to the progress of the game can be easily specified according to the difference in the storage area.

  In addition, the game program area and the non-game program area may be allocated to the adjacent areas across the unused area 1, and even with such a structure, the game program area related to the progress of the game It is possible to easily identify non-game programs that are not involved in the progress of the game according to the difference in storage area.

  In addition, since 0 values are stored in all areas in the unused areas 1 and 2 of the program / data area of the ROM 41b, the game program area and the game data area, the non-game program area and the non-game data, The unused areas 1 and 2 can be easily distinguished from each other, and the unauthorized areas 1 and 2 can be easily detected even when illegal data is stored.

  Note that 1 may be stored in all areas in the unused areas 1 and 2 of the program / data area of the ROM 41b, and even in such a structure, the game program area and the game data area, and the non-game area The program area and the non-play data can be easily distinguished from the unused areas 1 and 2 and can be easily found out even if the unused areas 1 and 2 store illegal data. .

  In addition, as long as the game program area and the non-game program area are allocated to separate areas, the game program area and the non-game program area may be applied to the area adjacent to each other. Even with such a configuration, it is possible to easily identify the game program area related to the progress of the game and the non-game program not involved in the progress of the game according to the difference in the storage area.

  The game program area and the non-game program area both start from an address (0H) of 0 having the same lower four digits when the address is expressed in binary, and the program / data area of the ROM 41b Among them, the game program area related to the progress of the game and the non-game program area not related to the progress of the game can be easily distinguished from the other areas.

  In addition, in both the gaming program area and the non-game program area, when the address is expressed in binary notation, not only the lower 4 digits start from the same address of 0, but also in hexadecimal expression, the lower 1 digit value. Since it starts from the same address of 0 (0H), the game program area and the non-game program area can be easily distinguished from other areas not only when the address is expressed in binary but also when expressed in hexadecimal. can do.

  In addition, regardless of whether the game program area and the non-game program area both represent addresses in binary notation or hexadecimal notation, the lower N (N is a natural number of 1 or more) digits start from an address having the same value. It is possible to easily distinguish the game program area and the non-game program area from other areas. For example, the value of the lower N (N is a natural number of 1 or more) digits are the same 1 The same effect can be obtained with the configuration starting from the address of.

  As shown in FIG. 3B, the usable area of the RAM 41c includes a game RAM area used as a work by a game program, a non-game RAM area used as a work by a non-game program, and an unused area 4. The game RAM area includes the special work, the important work, the general work, the unused area 3, and the game stack area where the game program saves data. The non-game RAM area includes the game. An area to which the program can refer, an area to which the game program can not refer, and a non-game stack area to which the non-game program saves data are included. In the present embodiment, the game stack area and the non-game stack area are individually provided in different areas, but may be configured to include one stack area shared by the game program and the non-game program.

  The special work is a work in which data for transmitting a command to the sub control unit 91, various software random numbers, etc. are stored data which is initialized only before the start of setting.

  The important work is a work in which data for display of various displays and LEDs, input / output data of I / O port, clock counter of game time, etc. are stored.

  The general work is a work in which a stop control table, a stop symbol, the number of medals paid out, and the like are stored.

  The game stack area (in use) is an area in which data saved from the register of the CPU 41a is stored. Also, the unused stack area (unused) is initialized in the activation process, but the game stack area (in use) is not initialized because the program continues.

  Also, the start address of the game RAM area is "F000H". Further, in this embodiment, the upper addresses of the start address of the special work, the start address of the important work, and the start address of a part of the general work are assumed to be “F0”.

  The unused area 3 is an area in which neither a game program nor a non-game program is used, and is an area which is surplus with respect to a game RAM area of a predetermined capacity.

  In addition, the unused area 4 is an area of 16 bytes or more in which neither a game program nor a non-game program is used. Since the game RAM area and the non-game RAM area are allocated to the non-consecutive areas across the unused area 4, the game RAM area used by the game program related to the progress of the game and the non-system regardless of the progress of the game The non-play RAM area used by the game program can be easily identified according to the difference in storage area.

  In the following, the game program area, the game data area and the game RAM area may be collectively referred to as a game area, and the non game program area, the non game data area and the non game RAM area may be collectively referred to as a non game area. . In addition, the unused area 1 and the unused area 2, the unused area 3 and the unused area 4 may be collectively referred to as an unused area.

  The main control unit 41 permits access to the available area of the RAM 41c when there is access to the area to which access is inhibited in the program / data area of the ROM 41b based on the parameters set in the HW parameter area. When there is an access to an area not set in (1), an access to an area other than the program / data area in the ROM 41b, or an access to an area other than the usable area in the RAM 41c. In other words, in the normal operation, an illegal access reset is generated when there is an access to a memory area that is not accessed, so that the disabling process for disabling the progress of the game is executed, so the unused area of the ROM 41b Or an area not related to the operation, an unused area of the RAM 41c, etc. Even when grams is stored, it is possible to prevent the illegal program from being executed.

  In this embodiment, when the RAM access is prohibited (see, for example, Sk9 in FIG. 6), the disabling process is executed when the game RAM area is accessed. On the other hand, when the RAM access is prohibited, the disabling process is not executed even if the internal function register is accessed. As a modification, when the RAM access is prohibited, the disabling process may be executed when the internal function register is accessed.

  In the present embodiment, in particular, the gaming program area and the non-gaming program area are allocated to the program / data area of the ROM 41b to which access is permitted by the program, and before the non-gaming program area behind the gaming program area. Unused area 1 is allocated to the area, and a group of areas including the head address of the gaming program area to the final address of the non-gaming program in the program / data area based on the parameters set in the HW parameter area While the access to the area (the area from the game program area to the non-game data area) is collectively set to permission, the game program or game data in the other areas, that is, the program / data area, the non-game program, Non-play data is not stored Because it is forbidden access to the area later than the game data, it is possible to prevent conducted unintended control by malware or illegal data.

  Further, in the program / data area of the ROM 41b where access is permitted by the program, the game area is allocated behind the non-game program area, and an unused area in the area before the game program area behind the non-game program area. Is allocated, and based on the parameters set in the HW parameter area, batch access to a group of areas including the area from the top address of the non-gaming program area to the final address of the gaming program in the program / data area Even if the access to the other area is prohibited, it is possible to prevent the unintended control by the illegal program or the illegal data.

  A game program area and a non-game program area are allocated to the program / data area, and an unused area 1 is allocated to an area in front of the non-game program area behind the game program area. Of the areas, one area including game program area (area from game program area to game data area), one area including non game program (area from non game program area to non game data area) It is also possible to set access to each permission and prohibit access to other areas, and even in such a configuration, to the area where game programs and non-game programs are not stored among program / data areas. Unauthorized access to the program, and unauthorized programs and data The control does not will take place can be prevented. Further, in the program / data area of the ROM 41b where access is permitted by the program, the game area is allocated behind the non-game program area, and an unused area in the area before the game program area behind the non-game program area. Of the program / data area including the gaming program area (the area from the gaming program area to the gaming data area) and the one area including the non-game program (non-gaming program area) Access to the area to the data area may be set to permit, and access to other areas may be prohibited. Even in such a configuration, a game program or non-game in the program / data area may be set. Access to the area where the program is not stored Because There is inhibited, it is possible to prevent conducted unintended control by malware or illegal data.

  Also, in the above description, although the area itself for permitting access in the program / data area is set, the area for indirectly permitting access is set by setting the area for prohibiting access in the program / data area. It is good also as composition which is done.

  When the user program is executed in an area other than the designated area for permitting program travel based on the parameters set in the HW parameter area, that is, the main control section 41 executes the user program in a normal operation. When the user program is executed in the non-region, the IAT circuit (Illegal Address Trap: not shown) outputs an IAT generation signal to disable the progress of the game, so the unused region or the operation of the ROM 41b Even if an illegal program is stored in an area not related to the above, an unused area of the RAM 41c, or the like, it is possible to prevent an illegal program from being executed.

  In the present embodiment, in particular, the gaming program area and the non-gaming program area are allocated to the program / data area of the ROM 41b to which access is permitted by the program, and before the non-gaming program area behind the gaming program area. Designating that the IAT circuit permits program travel for each of the gaming program area and the non-gaming program area in the program / data area based on the parameters set in the HW parameter area while the unused area 1 is allocated to the area While setting as an area, program running is prohibited in other areas, that is, areas where game programs and non-gaming programs are not stored among program / data areas, and thus unintended control by an illegal program or illegal data Is done Mau it can be prevented.

  Further, in the program / data area of the ROM 41b where access is permitted by the program, the game area is allocated behind the non-game program area, and an unused area in the area before the game program area behind the non-game program area. Is set, and based on the parameters set in the HW parameter area, the IAT circuit sets the designated area for permitting program travel for each of the game program area and the non-game program area in the program / data area. Even if program running in other areas is prohibited, it is possible to prevent the unintended control due to the illegal program or the illegal data being performed.

  A game program area and a non game program area are allocated to the program / data area, and an unused area 1 is allocated to an area in front of the non game program area behind the game program area, and an HW parameter area Of the program / data area including the area from the top address of the gaming program area to the final address of the non-gaming program based on the parameters set in (area from the gaming program area to the non-gaming data area) , The IAT circuit may be collectively set as a designated area for permitting program travel, and program travel in other areas may be prohibited. Even in such a configuration, among the program / data areas No gaming programs or non-gaming programs are stored Since the program running in the range is inhibited, it is possible to prevent conducted unintended control by malware or illegal data. Further, in the program / data area of the ROM 41b where access is permitted by the program, the game area is allocated behind the non-game program area, and an unused area in the area before the game program area behind the non-game program area. Of the program / data area including the area from the top address of the non-gaming program area to the final address of the gaming program based on the parameters set in the HW parameter area (from the gaming program area Even if the IAT circuit collectively sets a designated area for permitting program travel with respect to the area to the non-gaming data area) and program travel in other areas is prohibited, the intention due to the illegal program or illegal data Do not have control Ukoto can be prevented.

  In the above description, although the program / data area is configured to set the area for permitting program travel itself, program travel is indirectly permitted by setting the area for prohibiting program travel in the program / data area. An area may be set.

[About the instruction which the program uses]
The program executed by the main control unit 41 includes a main routine that controls the progress of the entire program, and a subroutine that is called during the execution of another program.

  Also, a CALL instruction is included as an instruction to cause the main control unit 41 to execute the program stored in the program / data area.

  The CALL instruction is an instruction to call and execute a subroutine stored at an address designated in the main routine or subroutine. When calling a subroutine by the CALL instruction, the main control unit 41 stores the address of the caller in the stack area, and calls and executes the subroutine stored at the designated address. Then, after the subroutine ends, the address of the caller stored in the stack area, that is, the program of the main routine or subroutine of the caller that executed the CALL instruction is restored.

  In addition, the CALL instruction includes a normal CALL instruction and a special CALL instruction CALLV instruction. Whereas a normal CALL instruction is an instruction that specifies an address by specifying an upper address and a lower address by specifying both the upper address and the lower address and calls a subroutine, the CALLV instruction only has the lower address. By specifying, it is an instruction to specify the address by the upper address preset in the vector table area of the ROM 41b and the specified lower address, and to call the subroutine. A program (subroutine) used in the game program is stored in the storage area of the specified address. Therefore, with the CALLV command, it is possible to call a program (subroutine) used in the game program with a smaller amount of data compared to a normal CALL command.

  The RST instruction executes and calls a subroutine stored at a specific address corresponding to a specified value by specifying a value (a capacity is smaller than the specific address) corresponding to a plurality of predetermined specific addresses. It is an instruction to In the storage area of the specific address, a program (subroutine) used in the game program is stored. Therefore, it is possible to call a program (subroutine) used in the game program with a smaller amount of data compared to the above-mentioned ordinary CALL instruction or CALLV instruction by the RST instruction. When calling a subroutine by the RST instruction, the main control unit 41 stores the address of the caller in the stack area, and calls and executes the subroutine stored at the specific address corresponding to the designated value. After completion of the subroutine, the process returns to the address of the caller stored in the stack area, that is, the main routine or subroutine of the caller that executed the RST instruction.

  The main control unit 41 identifies the address by the upper address set in the vector table area by the CALLV instruction and the lower address designated by the CALLV instruction, and is used in the game program stored in the identified address. Call a program (subroutine) and execute it. For this reason, the high-order address which constitutes a part of the address used when calling the particularly frequently used subroutine among the game programs is set in advance in the vector table, and the address is based on the high-order address set in the vector table. Since it is specified, it is possible to call a subroutine with a smaller amount of data compared to a normal CALL instruction which designates both the upper address and the lower address and calls the subroutine. When calling these subroutines, the address is specified You can reduce the waste of your program.

  In addition, since the capacity of the value (value corresponding to a plurality of predetermined addresses) specified by the RST instruction is smaller than the capacity of the address, the data amount of the RST instruction is smaller than that of the normal CALL instruction. Since it is possible to call a program (subroutine) used in the game program, the data capacity of the game program can be reduced by using the RST command in the game program.

  The main control unit 41 includes an LD instruction as an instruction to read data stored in the program / data area. The LD instruction is an instruction for reading out the data stored at the address designated in the main routine or subroutine into the designated register. The main control unit 41 reads the data stored at the address specified by the LD instruction, and stores the read data in a register (for example, an internal function register) specified by the LD instruction.

  The LD instruction also includes a normal LD instruction and a special LD instruction LDQ instruction. The normal LD instruction is an instruction to read out the data stored in the area of the ROM 41b or the RAM 41c by the upper address and the lower address specified by specifying both the upper address and the lower address. The LDQ instruction specifies the address by the upper address preset in the special register (Q register) in the above-mentioned internal function register area of the RAM 41c and the specified lower address by specifying only the lower address, and the ROM 41b or It is an instruction to read the data stored in the area of the RAM 41c and store the read data in the specified register, and store the predetermined data in the predetermined register with a smaller amount of data compared to the normal LD instruction. Is possible.

  When reading data stored in the area of the ROM 41b or RAM 41c in the main routine or subroutine, all addresses (upper and lower parts) indicating the area are specified by using the LDQ instruction which is a special LD instruction. It is possible to read out the data of the area by specifying only the lower part of the address. By using the LDQ instruction, it is possible to read data with a smaller amount of data compared to a normal LD instruction that specifies data by specifying both the upper address and the lower address, and specify an address when reading data. You can reduce the waste of your program.

  In addition, LD instructions (normal LD instructions, LDQ instructions, etc.) are also used for other processes using storage areas. The other processing includes processing of referring to data stored in the storage area (for example, processing of Sa1 in FIG. 4 described later, etc.), processing of setting data in the storage area, and storage processing. It includes a process of erasing (clearing) the set data (for example, a process of Sa 16 in FIG. 5 described later) and the like.

  The game program is a program related to the progress of a game, and is a program for executing a process that hinders the progress of the game if the process based on the program is not executed. On the other hand, a non-game program is a program that does not relate to the progress of a game, and even if it is called from the game program and the process based on the program is not executed, the game can be progressed It is a program for executing processing.

  In other words, the non-game program is a program that executes a process different from the process related to the progress of the game. The “process different from the process related to the progress of the game” is, for example, a process of initializing a non-gaming RAM area in a non-gaming RAM area initialization process, a medal sensor check process in a medal sensor process, and a data processing for duty ratio monitor Each state count processing, sensor monitoring processing in non-game related processing, test signal output processing, medal passing time timer update processing, combination ratio monitor display data selection processing and the like are included. Further, as shown in FIG. 3A, the game program area and the non-game program area are separately configured. Therefore, for example, even if the capacity of the game program area is determined, there is no need to consider the capacity of the non-game program area. Therefore, the degree of freedom in the design of the game program area can be improved.

  In the game program, any command including the special CALL command CALLV command, RST command, special LD command LDQ command may be used for the above-mentioned CALL command or LD command, and the special CALL command may be used. It is also possible to use a specific address to call a subroutine or to use a special LD command to read out specific game data and non-game data in the ROM 41b and RAM 41c.

  In the non-gaming program, the usual CALL instruction is used for the above-mentioned CALL instruction, but the special CALL instruction CALLV instruction is not used. Therefore, while a subroutine may be called by specifying an address using a normal CALL instruction, a subroutine may not be called using a special CALL instruction. Therefore, it is possible to prevent the game program area in the ROM 41b from being inadvertently accessed by the non-game program.

  Further, in the non-game program, a normal LD command can be used for the above-mentioned LD command. As a result, in the non-game program, it is possible to specify an address using a normal LD command and read out predetermined data. On the other hand, in non-gaming programs, the LDQ command is not used. Therefore, it is possible to prevent the process of reading data by the LDQ instruction from being performed carelessly.

  The control contents of various processes performed by the main control unit 41 executing the game program and the non-game program will be described based on FIGS. 4 to 6. 4 to 6 show control contents when the gaming machine is a slot machine.

[About the process when starting the main control unit 41 and the starting process]
The startup process performed by the main control unit 41 will be described based on FIGS. 4 and 5. The start-up process is a subroutine included in the game program.

  When the predetermined start condition is satisfied, the main control unit 41 is activated in a state where the timer interrupt is set to be inhibited by the occurrence of the reset, and performs various processes according to the program stored in the ROM 41 b. After startup, first, start-up setting processing included in the game program is performed to initialize all output ports, and internal registers (including internal function registers) included in the main control unit 41 are stored in a predetermined area of the ROM 41b in advance. The initialization processing included in the game program, which is initialized based on the set internal register initialization table, is performed. Thus, in the present embodiment, initialization of the internal function register is performed when power supply is started. In addition, the predetermined start condition is a condition established by the start of the power supply to the gaming machine 1 (the detection of the power supply to the gaming machine 1) and the system reset with respect to the gaming machine 1 And the condition established by Also, the execution conditions of the system reset include, for example, when a reset operation is performed by the user, when a timeout signal from the watchdog timer is generated, and when an IAT signal from the IAT circuit is generated.

  Note that, as a modification, initialization processing of internal registers (including internal function registers) included in main control unit 41 is not performed by a program, but hardware (for example, initialization circuit (not particularly shown)) May be configured to execute.

  As shown in FIG. 4, first, in Sa1A, the main control unit 41 sets specific value data in the Q register. Hereinafter, "specific value data" is simply referred to as "specific value". Here, specific values will be described. In the present embodiment, when power is restored (when power supply is started, that is, when the activation process is performed), power is generated based on data in the game RAM area or the like (power Return to the control state) when the supply is stopped. Therefore, the game RAM area is an important area in terms of returning to the control state.

  As shown in FIG. 2, the upper address of the game RAM area is "F0". Here, the specific value is an area in which the upper address of the area different from the game RAM area can be specified. In this embodiment, the different areas are the "internal function register" and the "signal area". That is, the specific value is a value that can specify "F5" which is the upper address of the internal function register. In other words, the specific value is a value used to specify "F5" which is the upper address of the internal function register. The specific value is also a value that can specify the upper address "F5" of the signal area.

  When the process of Sa1B ends, various setting processes are executed. In the various setting processes, a plurality of (N, where N is an integer of 2 or more) setting processes are executed. The N setting processes include, for example, random number start setting, serial communication circuit setting, and reset / interrupt controller setting. By the N setting processes, N set values (hereinafter also referred to as “start-up set values”) corresponding to the N sets are stored in each of the N areas in the internal function register. Ru.

  Here, storage of the N start setting values in the internal function register is also executed by the LDQ instruction. Specifically, based on the specific value (upper address is F5) stored in the Q register in Sa1A and the value (lower address) specified for each of the N in the LDQ instruction, the N settings are made. The value is stored in each of N regions in the internal function register.

  After the processing of Sa1B ends, the process proceeds to Sa1. In Sa1, a process of referring to the signal area of the input port is performed. When the power supply to the gaming machine 1 is stopped (when a power failure occurs), a power failure detection circuit (not shown) transmits a power failure detection signal to the main control unit 41. The power failure detection signal is a signal indicating that a power failure has occurred (voltage drop). Further, information (for example, a power failure detection signal flag) related to the power failure detection signal is stored in the signal area. The power failure detection signal flag is stored in the signal area when the power failure detection signal is output from the power failure detection circuit (ON state), and the power failure detection signal flag is in the signal region when the power failure detection signal is not output from the power failure detection circuit. It will not be stored in (OFF state).

  In this embodiment, the address of this signal area is “F 560”. As a modification, the signal area may be any address as long as the upper address is “F5”.

  That is, the lower address (60) of the signal area is designated by the LDQ instruction in Sa1, and the lower address and the specific value (the upper address F5 of the signal area) stored in the Q register are used. To identify the address of the signal area. In Sa1, a signal area (signal area of input port) which is an area of the specified address is referred to.

  In Sa2, it is determined whether the power failure detection signal output from the power failure detection circuit (not shown) is in the ON state (whether or not the power failure detection signal flag is stored in the signal region) (Sa2) . When the power failure detection signal is in the ON state, the process waits until the power failure detection signal is in the OFF state (YES in Sa1). Thereafter, after the power supply voltage of the slot machine 1 becomes normal and the power failure detection signal is turned off (NO at Sa1), the process proceeds to Sa3A.

  In Sa3A, the permission process for permitting access to the available area of the RAM 41c is executed by the LDQ instruction. Specifically, the permission process is performed by setting the permission flag in the RAM access area in the internal function register. In this embodiment, the address of the RAM access area is assumed to be "F550".

  That is, in Sa3A, the lower address (50) of the RAM access area is specified by the LDQ instruction, and the lower address and the specific value (F5 which is the upper address of the RAM access area) stored in the Q register. Based on the address of the RAM access area. In Sa3A, the permission flag is set by the LDQ instruction to the RAM access area which is the area of the specified address.

Next, in Sa3B, the specific value (specific value data) is erased in the Q register in which the specific value has been set, and predetermined value data is set. Hereinafter, "predetermined value data" is simply referred to as "predetermined value". Here, the predetermined value is data that can specify the upper address "F0" of the game RAM area. In other words, the predetermined value is data used to specify the upper address "F0" of the game RAM area. That is, by executing the process of Sa3B, the specific value (the value that can specify F5) is changed to the predetermined value (the value that can specify F0).
In this manner, in a period in which a specific value is set in the Q register (a period from Sa1A to Sa3B, and a period from Sk8 to the end of the power-off process in the power-off process of FIG. In the case of executing the process using (1), the LDQ instruction executes the process of using the function setting register). Therefore, the program capacity can be reduced as compared with the configuration in which the function setting register is processed by the LD instruction in a period in which the specific value is set in the Q register.
In addition, in a period in which a predetermined value is set in the Q register (for example, a period from when the process of Sa3B is performed to when the process of Sk8 of the power interruption process (see FIG. 6 described later) is performed), When the process using the game RAM area is executed, the process using the game RAM area is executed by the LDQ command. Therefore, in a period in which a predetermined value is set in the Q register, the program capacity can be reduced as compared with the configuration in which the game RAM area is processed by the LD command.

  Next, the parity of a predetermined area of the RAM 41c is calculated (Sa3), and a predetermined initial address is set in the stack pointer (Sa4). Then, it is determined whether or not the parity calculated in the step of Sa3 is normal (Sa5). This determination is performed using the RAM parity adjustment data calculated at Sk6 described later. If the parity is normal, the RAM destruction diagnostic fixed data set in the predetermined area of the RAM 41c in Sk7 of the power-off process described later is obtained (Sa6), and the RAM 41c is acquired based on the RAM destruction diagnostic fixed data. It is diagnosed whether or not the memory contents are destroyed (Sa7).

  If it is determined in step Sa5 that the parity is normal, and if the storage content of the RAM 41c is diagnosed in step Sa7, the RAM 41c is based on the parity of the RAM calculated in step Sa3 and the result of the diagnosis in Sa7. It is determined whether there is an abnormality (Sa8). The case where there is an abnormality in the RAM 41c means the case where the parity is not normal or the case where it is diagnosed that the parity is normal but the memory content is abnormal.

  Then, if there is an abnormality in the RAM 41c, the value of the flag register in which the operation result is stored among the registers included in the main control unit 41 is saved by storing it in the game stack area of the game RAM area in a predetermined order. After (Sa9), the non-gaming RAM area initialization processing included in the non-gaming program is called and performed (Sa10). Then, in the non-game RAM area initialization process, after initializing the non-game RAM area of the RAM 41c, the process returns to the start process. Then, when returning to the activation process, the values of the flag register evacuated to the game stack area in the step of Sa9 are sequentially read out from the game stack area in the reverse order to the evacuation and set in the flag register. The flag register is restored to the state before the RAM area initialization process (Sa11).

  In the non-gaming RAM area initialization process, first, the value of the current address of the gaming stack area indicated by the stack pointer SP used by the calling party's gaming program is stored in a predetermined area of the non-gaming RAM area and saved. Let Thereafter, a predetermined value of the non-gaming stack area (a value stored in a predetermined area of the non-gaming RAM area as an address indicated by the stack pointer SP at the end of the previous non-gaming program) is set as the value of the stack pointer SP. Thus, the stack pointer SP is set for the non-gaming program. Then, the values of all the registers provided in the main control unit 41 including the flag register described above are saved by storing them in the non-play stack area of the non-play RAM area specified by the stack pointer SP in a predetermined order. After that, the start address (first address of unused area 4) and end address (last address of non-play RAM area) of the initialization target RAM are specified, and the data of the specified address is used as the initial value of the specified address. Is cleared until the specified address becomes the end address, the process from the start address of the initialization target RAM to the end address (in this embodiment, The area from the beginning of the unused area 4 to the end of the non-play RAM area is initialized. Then, when the non-gaming RAM area initialization processing is started, the values of the registers stored and evacuated in the non-gaming stack area are sequentially read out from the non-gaming stack area in the reverse order to that for evacuation. By setting the registers corresponding to, all the registers are restored to the state when the non-play RAM area initialization process was started. After that, when the non-play RAM area initialization process is started, the non-play RAM area initialization process is started by setting the value of the stack pointer SP evacuated to the predetermined area of the non-play RAM area as the stack pointer SP. The stack pointer SP is returned to the state at the time when the non-gaming RAM area initialization processing is ended.

  In the non-gaming RAM area initialization process, the capacity of the initialization object RAM is calculated by specifying the start address and the end address of the initialization object RAM, and the RAM area corresponding to the capacity is the initialization object RAM. The area from the start address to the end address of the initialization target RAM may be initialized by sequentially clearing from the start address.

  If it is determined in the step Sa8 that the RAM 41c is not abnormal, or if the register is restored in the step Sa11, the RAM destruction diagnostic fixed data set in the RAM 41c is cleared (Sa12), and the RAM 41c is abnormal. When there is a RAM destruction initialization address for specifying the address of the game RAM area to be subjected to initialization processing is set (Sa13). Thereafter, it is determined whether or not the setting key switch is in the ON state with reference to the input port (Sa14).

  If it is determined in step Sa14 that the setting key switch is in the ON state, setting change processing is performed. In the setting change process, control is performed in a setting change state in which the set value can be changed by a store clerk or the like of the game arcade. The setting value is a value indicating the degree of advantage to the player.

  If it is determined in step Sa14 that the setting key switch is not in the ON state, it is determined whether there is an abnormality in the RAM 41c based on the parity of the RAM calculated in step Sa3 and the diagnosis result in Sa7 (Sa15) If it is determined that the RAM 41c is not abnormal, the output buffer for outputting the external output signal is cleared (Sa16). The output buffer is provided in a predetermined area of the game RAM area of the RAM 41c. Further, a reel error counter which is set in a predetermined area of the RAM 41c and which counts the number of times the reel rotation error is detected is cleared (Sa17). The reel error counter is provided in a predetermined area of the game RAM area of the RAM 41c. Thereafter, the stack pointer SP is restored to the power-off state by setting the address at power-off to the stack pointer SP based on the stored contents of the RAM 41c (Sa18), and the port input process is performed twice continuously (Sa19) , Sa 20).

  Port input processing is input state data related to input states such as detection signals of various switches input to the parallel input port 511 (input data indicating current input states of various switches, same state as previous and current input data) And the edge data indicating that the finalized data has changed since the previous time. In a predetermined area of the game RAM area of the RAM 41c, port input buffers 0 to 2 for storing input state data of various switches are provided, and the input state data of various switches updated by the port input processing is It is stored in predetermined bits of the port input buffer predetermined for each type. In the port input processing, detection states (ON state or OFF state) of various switches to be input ports 0 to 2 of the parallel input port 511 are stored as input data in predetermined bits of the port input buffer. Also, compare the detection states (ON state or OFF state) in the previous and current port input processing, and if the current input data and the previous input data are in the same state, indicate the current input data detection state. If the current input data and the previous input data are in different states, the previous input data is maintained. Also, when the final data is compared with the current and previous data, and the final data changes from the OFF state to the ON state, the ON edge data indicating that the final data changes from the OFF state to the ON state is input to the port input buffer 0 When the finalized data is stored in a predetermined bit of 2 to 2 and the finalized data changes from ON to OFF, the OFF edge data indicating that the finalized data has changed from ON to OFF is stored in the port input buffers 0 to 2 Store in bits. Input data, decision data, and edge data of various switches stored in the port input buffer can be referenced from the game program and the non-game program.

  Further, in the activation process, by performing the port input process twice in succession, when the port input process is subsequently performed, the input state of various switches after the activation process is performed, that is, the power to the gaming machine Since input state data regarding input states such as detection signals of various switches are created based on input states of various switches after supply is resumed, it is possible to prevent an unintended input situation from being identified. It is supposed to be. Further, in the port input process, the configuration may be such that the finalized data is created based on the input data (for example, the current, the previous time, and the previous second time input data) acquired by the three or more port input processes. In such a configuration, after the start processing is performed, the port input processing is continuously performed in the start processing a number of times smaller than the number of the port input processing required to create the definite data. When port input processing is performed, input state data can be created based on input states of various switches after the start processing is performed.

  After performing port input processing in the steps of Sa19 and Sa20, reference is made to a predetermined input port (Sa21) to determine whether the reset / setting switch is ON (Sa22), and the reset / setting switch Is in the ON state, status data indicating that the reset / setting switch is in the ON state is set in a predetermined area of the RAM 41c (Sa23).

  The reset / setting switch functions as a reset switch for releasing an error state or a suspension state when it is in a state different from the setting change state, and for changing the setting value in the setting change state. Act as a switch.

  If it is determined in the step Sa22 that the reset / setting switch is not in the ON state, and after the status data is set in the step Sa23, a return command indicating that the control state before power interruption is restored is sent to the sub control unit 91. After transmission (Sa24), in the command transmission processing of the timer interrupt processing (main), a door command transmission flag indicating that a door command indicating the detection state of the door opening detection switch 25 is transmitted is set in a predetermined area of the RAM 41c ( Sa 25). In the command transmission process, normally, the door command is transmitted when the detection state of the door open detection switch 25 changes, but when the door command transmission flag is set in a predetermined area of the RAM 41 c, the door open detection switch 25 The door command indicating the detection state of the door opening detection switch 25 is transmitted regardless of whether or not the detection state of has changed.

  Then, after setting the door command transmission flag in the step of Sa25, restore all the registers to the state before power interruption stored in the RAM 41c (Sa26), and set the timer interrupt to permission (Sa27), After ending the start processing and shifting to the timer interrupt processing (main), the processing returns to the main processing that was being executed before the power supply to the slot machine 1 was stopped.

  On the other hand, if it is determined in the step Sa15 that the RAM 41c is abnormal, the game RAM initialization processing is performed (Sa28), and the RAM destruction start initialization address set in the step Sa13 starts the game RAM area of the RAM 41c. Initialize the area to the end of. After that, after evacuating the value of the flag register in which the flag is set in the register to the game stack area of the game RAM area (Sa29) as in the process to the steps of Sa9 to Sa11, (Sa29) After calling up the game RAM area initialization process (Sa30) and initializing all non-game RAM areas of the RAM 41c, the process returns to the calling source and restores the register saved in the step of Sa29 (Sa31).

  After restoring the register in step Sa31, set the door command transmission flag (Sa32), set the timer interrupt to be enabled (Sa33), and use the RAM error code (E8) to indicate that the RAM 41c has an error. The predetermined register is prepared (Sa34), the start process is ended, and the process shifts to the error process.

  In the error processing, control is made to an error state in which the progress of the game is disabled. Further, an error command capable of specifying an error code (E8) prepared in a predetermined register is transmitted to the sub control unit 91, and the error code (E8) can be referred to a predetermined area of the RAM 41c by other processing. Set as an error flag. Further, control is made to display the error code (E8) on a game assist indicator (not shown). Thereafter, the control of the error state is performed until it is specified that the release condition of the error state corresponding to the error code (E8) prepared in the predetermined register is satisfied. When the RAM abnormal error code (E8) is prepared in a predetermined register and it shifts to the error state, it shifts to the setting change state by turning on the power to the gaming machine with the setting key switch ON. By initializing all the game RAM areas, it is possible to reliably eliminate the abnormality of the data of the RAM 41 c and release the error state. On the other hand, when the power switch is turned on without turning on the setting key switch, the abnormality of the RAM 41c is detected again, and an error state occurs again.

  As described above, after the power supply to the slot machine 1 is started, the main control unit 41 performs the start process first, and in the start process, the power supply to the slot machine 1 is started. Depending on the state of the main control unit 41 at the time, the timer interrupt process (main), the setting change process, or the error process is transferred. Then, when shifting to these processes, a command capable of specifying the type of processing to be shifted is transmitted to the sub control unit 91, and when shifting to timer interrupt processing (main), that is, the game When returning to the control state before the power supply to the machine is stopped, a return command is sent to the sub control unit 91, and when setting change processing is started and the setting change state is entered, When a setting command (start) is sent to the sub control unit 91 and error processing is started due to an abnormality in the RAM 41 c to shift to an error state, an error command is sent to the sub control unit 91.

  After the main control unit 41 shifts from the activation process to the setting change process, it passes through the setting change state and returns to a state in which the game can be progressed, and the state in which the game can be progressed When returning to the sub-control unit 91, the setting command (end) capable of specifying that the setting change state is to be ended is transmitted to the sub control unit 91, but the return command is not transmitted. Further, after transitioning to the error processing due to the abnormality of the RAM 41c, the transition to the setting change processing is made as described above, and the error state is canceled, thereby returning to the state where the game can be progressed. Even when the error processing is ended and the game can return to the state where the progress of the game is possible, the return command is not transmitted to the sub control unit 91.

  As described above, the main control unit 41 of the present embodiment is activated when the power supply to the gaming machine is started, and performs the activation setting process included in the game program, and all the outputs are performed by the activation setting process. It is supposed to initialize the port.

  In addition, after performing the startup setting process, the main control unit 41 calls up the non-play RAM area initialization process included in the non-game program when it is determined that the RAM 41 c is abnormal in the startup process. The predetermined area of the non-game RAM area is initialized. Further, in the start-up process, the RAM initialization process included in the game program is called to initialize a predetermined area of the game RAM area of the RAM 41c, and the game RAM area is initialized by the game program. The area is configured to be initialized by the non-game program.

  Next, the control contents of the power interruption process (main) performed by the main control unit 41 will be described based on FIG. The power interruption process (main) is a subroutine included in the game program.

  The main control unit 41 executes the power-off process (main) when it is determined in the above-described timer interrupt process (main) that the voltage drop state has continued for a predetermined time. That is, when the main control unit 41 detects the stop of the power supply to the gaming machine, it executes the power-off process.

  As shown in FIG. 6, in the power-off process (main), first, the values of all the registers provided in the main control unit 41 are saved by storing them in the game stack area of the game RAM area in a predetermined order (Sk 1 And) storing the current address of the game stack area indicated by the stack pointer SP in a predetermined area of the game RAM area (Sk2). In addition, the predetermined area of the game RAM area including the game stack area of the game RAM area in which the main control unit 41 stores the value of the register and the predetermined area of the game RAM area in which the value of the address indicated by the stack pointer SP is stored Even if power supply to the slot machine 1 is stopped, the stored contents of the game RAM area are stored as long as power is supplied by the backup power supply.

  Next, all of the plurality of output ports are initialized (Sk3). Thereby, the output of the signal output from the plurality of output ports is stopped.

  Next, the main control unit 41 sets destruction diagnostic data in a predetermined area of the RAM 41 c (Sk 4). In the present embodiment, it is assumed that the predetermined area of the RAM 41 c in which the destruction diagnostic data is set is a game RAM area. As a modification, the predetermined area of the RAM 41 c in which the destruction diagnostic data is set may be an area different from the game RAM area.

  Next, the parity adjustment data set in the predetermined area of the RAM 41c is cleared (Sk5). Next, the main control unit 41 calculates parity adjustment data based on all the storage areas (including the unused area and the unused stack area) of the RAM 41c. In the present embodiment, the main control unit 41 calculates parity adjustment data of the new RAM 41 c so that the exclusive OR of all the storage areas (including the unused area and the unused stack area) of the RAM 41 c becomes 0. Do. Next, the main control unit 41 sets the parity adjustment data in a predetermined area of the RAM 41 c (Sk 7). In this embodiment, it is assumed that the predetermined area of the RAM 41c in which the parity adjustment data is set is a game RAM area. As a modification, the predetermined area of the RAM 41 c in which the parity adjustment data is set may be an area different from the game RAM area.

  Next, the main control unit 41 sets a specific value in the Q register. As described above, the specific value is information that can specify the upper address (F5) of the "internal function register" which is an area different from the game RAM area.

  A predetermined value is set in the Q register after the power-off process is performed until the process of Sk8 is performed (see FIG. 7 described later). For example, the identification of the region A where the destruction diagnostic data is set in Sk4, the identification of the region B where the RAM parity adjustment data is set in Sk5, the identification of the region C where the data for RAM parity adjustment of Sk7 is set, etc. It is executed using the LDQ instruction. In Sk4, the address of the area A is specified based on the predetermined value set in the Q register and the value specified by the LDQ instruction. Further, in Sk5, the address of the area B is identified based on the predetermined value set in the Q register and the value designated by the LDQ instruction. Further, in Sk7, the address of the area C is specified based on the predetermined value set in the Q register and the value specified by the LDQ instruction.

  Next, in Sk9, the prohibition of the access to the RAM 41c is set. The prohibition process of Sk9 will be described. The prohibition process is executed using a specific instruction. Specifically, the prohibition process is executed by setting the access prohibition flag in the RAM access area (the address is "F550" as described above) in the internal function register.

  That is, the lower address (50) of the RAM access area is designated by the LDQ instruction in Sk9, and the lower address and the specific value (the upper address F5 of the RAM access area) stored in the Q register. Based on the address of the RAM access area. In Sk9, an access prohibition flag is set by the LDQ instruction to the RAM access area which is the area of the specified address.

  Next, in Sk10, the timer interrupt is inhibited. The prohibition process of Sk10 will be described. The prohibition process is executed using the LDQ instruction. Specifically, the prohibition process is executed by setting a timer interruption prohibition flag in a timer interruption area (address is set to "F560") in the internal function register.

  That is, the lower address (60) of the timer interrupt area is specified by the LDQ instruction in Sk10, and the lower address and the specific value stored in the Q register (F5 which is the upper address of the timer interrupt area) And the address of the timer interrupt area is specified. In Sk10, the timer interrupt prohibition flag is set by the LDQ instruction to the timer interrupt region which is the region of the specified address. Hereinafter, the RAM access prohibition flag described in Sk9 and Sk10 and the interrupt prohibition flag are also referred to as “power-off set value”. The power-off set value can also be referred to as “a value according to the stop of the power supply”.

  After the process of Sk10 is completed, the loop process is started. In loop processing, it waits while monitoring the output condition of the voltage drop signal. In this state, when the voltage drop signal is not input, it is determined that the voltage is restored, and the program is started from the start process (main). On the other hand, if the voltage drops while the voltage drop signal is input, the operation is internally stopped.

  When the power supply of AC 100 V from the outside is stopped by the above processing, the power-off process (main) is executed, and the value of the register before the power-off is saved in the game stack area of the game RAM area. Since the content of the predetermined area of the game RAM area of the RAM 41c including the game stack area is also held by the backup power supply, the start process (when the power supply to the slot machine 1 is resumed) ( In the main), it is possible to restore the control state before power interruption.

[About setting timing of specific value and setting timing of predetermined value]
Next, the setting timing of the specific value to the Q register and the setting timing of the predetermined value to the Q register will be described with reference to FIG. Each timing shown in FIG. 7 is merely an example, and the period between each timing may be another period.

  It is assumed that the power-off process is started at timing T0. It is assumed that a specific value is set in the Q register at timing T1 in the power-off process (see FIG. 6) (Sk 8 in FIG. 6). A predetermined value is set in the Q register in the period up to the timing T1. Further, after timing T1, a specific value is set in the Q register. Further, at timing T2 after timing T1, access to the RAM 41c is set to be inhibited (Sk9). Then, at timing T3, it is assumed that the power-off process has ended. In the example of FIG. 7, when a specific value is set in the Q register, access to the RAM 41 c is prohibited, but after the specific value is set in the Q register, other processing is performed. After execution, access to the RAM 41 c may be prohibited.

  Further, it is assumed that the activation process (FIGS. 4 and 5) is started at timing T4. When this start-up process is executed, a specific value is set in the Q register (see Sa1A in FIG. 4). As a result, a specific value is set in the Q register. Thereafter, at timing T5, access to the RAM 41c is permitted (see Sa3A). A predetermined value is set in the Q register at timing T6 after timing T5 (see Sa3B). As a result, the specific value is not set in the Q register, and the predetermined value is set. Thereafter, it is assumed that the start-up process ends at timing T7.

[About the effect of this embodiment]
Next, the effects of the present embodiment will be described.

  (1-1) As described above, the game includes the game stack area of the game RAM area in which the main control unit 41 stores the value of the register and the predetermined area of the game RAM area in which the value of the address indicated by the stack pointer SP is stored. A predetermined area of the RAM area is backed up by a backup power supply, and in the power-off process, a process of evacuating the register indicated by Sk1 in the game RAM area, a process of evacuating the stack pointer of Sk2 in the game RAM area, etc. . Further, in the activation process, the control state (the control state at the time of the power-off process) is restored based on the data stored in the game RAM area. Therefore, the game RAM area is an important area.

  The power interruption process is performed when it is determined that the voltage drop state has continued for a predetermined time. Therefore, the case where the power interruption process is performed is an unstable state in terms of power supply. In such an unstable state, the LDQ instruction may be executed due to a malfunction or the like.

  If a predetermined value (value indicating the upper address “F0” in the game RAM area) is stored in the Q register in the power-off process, if the LDQ instruction is executed due to a malfunction or the like, the important area Access to a certain gaming RAM area (access not intended by the designer of the gaming machine) will be executed.

  Therefore, in the present embodiment, the specific value is stored in the Q register at a predetermined timing of the power-off process (the timing T1 in the example of FIG. 7). The specific value is a value capable of specifying the upper address "F5" of an area different from the game RAM area (in this embodiment, the internal function register). Therefore, in the power interruption process executed when the system is in an unstable state from the viewpoint of power supply, even if the LDQ instruction is executed due to a malfunction or the like, the game RAM area is not accessed (access to internal function register Will be Therefore, it is possible to reduce the possibility that access not intended by the designer will be performed.

  The start-up process is a process executed immediately after the supply of power is started. Therefore, the case where the start-up process is performed is an unstable state in terms of power supply. In such an unstable state, the LDQ instruction may be executed due to a malfunction or the like.

  If a predetermined value (value indicating the upper address “F0” in the game RAM area) is stored in the Q register in the activation process, it is an important area if the LDQ instruction is executed due to a malfunction or the like. Access to the game RAM area (access not intended by the designer) will be executed.

  Therefore, in the present embodiment, a specific value is stored in the Q register at a predetermined timing (in the example of FIG. 7, timing T4) of the activation process. The specific value is a value capable of specifying the upper address "F5" of an area different from the game RAM area (in this embodiment, the internal function register). Therefore, even if the LDQ instruction is executed due to a malfunction or the like in the activation process executed when the system is in an unstable state from the viewpoint of power supply, the game RAM area is not accessed (the internal function register is accessed ). Therefore, it is possible to reduce the possibility that access not intended by the designer will be performed.

  In addition, the address of the storage area (including the game RAM area and the internal function register) includes the first information (for example, the upper address of the address) and the second information (for example, the lower address of the address) Preferably, the first information is stored in a predetermined storage area (for example, a Q register). Then, in the specific instruction (for example, the LDQ instruction), the address is specified from the first information and the second information, and the data is read from the storage area of the specified address. At the time of this reading, an address is specified from the first information stored in the predetermined storage area and the second information specified by the specific command. According to such a configuration, the program capacity of the specific instruction can be reduced as compared with the configuration in which both the first information and the second information are specified in the specific instruction to specify the address.

  Also, in the power-off process and the start-up process, when a predetermined value is set in the Q register, a process (for example, data from the game RAM area) using a game RAM area (an area that can specify an address from the predetermined value) To execute the process of reading out data or the process of writing data in the game RAM area, etc. is executed by the LDQ command. Therefore, the program capacity of the LDQ instruction in the processing using the game RAM area can be reduced.

  Also, in the power-off process and start-up process, when a specific value is set in the Q register, a process using an internal function register (an area where an address can be specified from the specific value) (for example, data in the internal function register) In the case of executing writing processing etc., it is executed by the LDQ instruction. Therefore, the program capacity of the LDQ instruction in the processing using the internal function register can be reduced.

  (1-2) Further, when the power supply to the slot machine 1 is started, the startup setting process is executed prior to the power-off process. In this startup setting process, the internal function register is initialized. As described above, even if the LDQ instruction is executed due to a malfunction or the like in the power-off process after the specific value is set in the power-off process, the LDQ instruction performs the initial setting process at startup. The internal function registers to be integrated will be accessed. Therefore, the possibility of particular problems occurring can be reduced.

  (1-3) In addition, confirmation data (for example, RAM destruction diagnosis shown in Sk4 in FIG. 6) for confirming whether or not the data stored in the storage area (for example, game RAM area) is normal. In the confirmation data generation process (for example, the process of Sk4 and Sk7 in FIG. 6) of generating fixed data and RAM parity adjustment data shown in Sk7 and storing the same in the specific storage area, stop of power supply is detected When (for example, in the power-off process). Further, a specific value is set in the Q register after the confirmation data generation process is executed (for example, as shown in FIG. 6, after the processes of Sk4 and Sk7 are executed, the Sk register Specific value is input to

  Therefore, even if the specific instruction is mistakenly executed after the confirmation data is stored in the specific storage area, the possibility of accessing the specific storage area in which the confirmation data is stored is reduced. it can.

  (1-4) Also, storage of the power-off set value (Sk9 and Sk10 in FIG. 6) in the internal function register is also executed by the LDQ instruction. Specifically, based on the specific value (upper address is F5) stored in the Q register in Sk8 and the value (lower address) specified by the LDQ instruction in each of Sk9 and Sk10, RAM destruction diagnostic fixed data The data for RAM parity adjustment are stored in the internal function register. Therefore, according to such a configuration, it is possible to reduce the program capacity of the LDQ instruction as compared with the configuration in which all the addresses of the internal function register are specified to specify the address in the LDQ instruction.

(1-5) Also, as shown in FIG. 3, the upper address of the game RAM area is “F0”, and the game RAM area stores data used in the game program. On the other hand, the upper address of the non-game RAM area in which the data used in the non-game program is stored is "F3". Further, as shown in FIG. 7 and the like, “F0” is set in the Q register in the period from the time when the start-up process is performed to the time when the power-off process is performed. Temporarily, when the LDQ command is used in a non-gaming program, the upper address is actually "F3", but the gaming RAM area whose upper address is "F0" while the non-gaming RAM area should be accessed. It will be accessed by As a result, access to the game RAM area, which is an important area (access not intended by the designer of the game machine) is performed.
Therefore, while the LDQ command is used in the game program, the LDQ command is not used in the non-game program. Therefore, it is possible to reduce that the designer of the gaming machine does not intend to access the gaming RAM area whose upper address is "F0".

  (1-6) Also, as shown in FIG. 3, the upper address of the gaming program area is "00", and the gaming program area stores a program (subroutine) used in the gaming program. On the other hand, the upper address of the non-game program area in which the program (subroutine) used in the non-game program is stored is "20". Also, in the vector table area, a value (for example, "00") capable of specifying the upper address of the game program area is stored. If a special command (CALLV command) is used in a non-gaming program, the upper address is "00" while the non-gaming program area whose upper address is "20" should actually be accessed. A certain gaming program area (a storage area in which a program (subroutine) used in the gaming program is stored) is accessed. Then, in the non-gaming program, access to the gaming program area (access not intended by the designer of the gaming machine) is performed.

Further, a program (subroutine) used in the game program is stored in the storage area of the specific address corresponding to the value designated by the RST instruction. If a special command (RST command) is used in a non-gaming program, the non-gaming program area is actually to be accessed, but a game (a subroutine) used in the gaming program is stored. The program area is accessed. Then, in the non-gaming program, access to the gaming program area (access not intended by the designer of the gaming machine) is performed.
Therefore, while special instructions are used in game programs, special instructions are not used in non-game programs. Therefore, it is possible to reduce the possibility that the designer of the gaming machine will not perform an access to the gaming program area.

  (2-1) In addition, the Q register is different from the game RAM area until the access to the game RAM area is permitted (for example, until the RAM access shown at timing T5 in FIG. 7 is permitted). A specific value that can specify the address of the internal function register that is an area (for example, a specific value that can specify the upper address “F5” of the internal function register) is stored. Further, after the access to the game RAM area is permitted (for example, after the RAM access shown at timing T6 in FIG. 7 is permitted), a predetermined value (for example, of the game RAM area) which can specify the address of the game RAM area A predetermined value capable of specifying upper address "F0" is stored.

  Further, in a period until access to the game RAM area is permitted (that is, a period in which access to the game RAM area is prohibited), it can be said that the game RAM area is an important area.

  Temporarily, during a period until RAM access is permitted (that is, a period during which RAM access is prohibited, for example, a period from timing T4 to T5), a predetermined value (upper address “F0 of the game RAM area”) is stored in the Q register. In the case where a value indicating “1” is stored, the LDQ instruction may be executed due to a malfunction or the like. In this case, access to the game RAM area (important area) where access is prohibited is performed (access not intended by the designer). In this embodiment, when the game RAM area to which access is prohibited is accessed, the legal access reset is generated to disable the progress of the game. Therefore, if the LDQ command is executed due to a malfunction or the like, the progress of the game is inadvertently disabled.

  Therefore, in the present embodiment, a specific value (a value capable of specifying the upper address of the internal function register) is stored until RAM access is permitted. Therefore, even if the LDQ command is executed due to a malfunction etc. until the RAM access is permitted, the game RAM area is not accessed, so there is a possibility that the progress of the game is carelessly made. It can be reduced.

  It should be noted that as a modification, when RAM access is prohibited, even if the game RAM area is accessed, the configuration that does not execute "disabling processing to disable the progress of the game" (hereinafter referred to as "disabling processing non-execution configuration "It is good." In such a configuration, when the game RAM area is accessed by executing the LDQ command due to a malfunction or the like when the RAM access is prohibited, the data stored in the game RAM area is It may be changed.

  On the other hand, in the present embodiment, when RAM access is prohibited, a specific value is set in the Q register. Therefore, in the gaming machine in which the disabling process non-execution configuration is adopted, the possibility that the game RAM area is accessed can be reduced even if the LDQ instruction is executed due to a malfunction or the like.

  (2-2) Further, information (for example, a power failure detection signal flag) related to the power failure detection signal output from the power failure detection circuit (not shown) is stored in the signal region. The main control unit 41 executes the activation process based on the power failure detection signal (for example, refer to Sa1 and Sa2 in FIG. 4). When referring to the signal area of the input port of Sa1, the specific value (upper address of the signal area) set in the Q register in Sa1A and the value specified by the LDQ instruction in Sa1A (lower order of the signal area) The address of the signal area is specified based on the address). In Sa1, a signal area (signal area of input port) which is an area of the specified address is referred to. Therefore, the program capacity of the LDQ instruction in the process of Sa1 can be reduced as compared with the configuration in which all the addresses in the signal area are specified to specify the address in the LDQ instruction.

  (2-3) Further, in the start-up process of FIG. 4, a determination process of determining whether the data is normal or not is performed using the data stored in the storage area. In the present embodiment, as shown in Sa5 to Sa7 of FIG. 4, this determination process is a process of diagnosing the RAM 41c using the fixed data for RAM destruction diagnosis and the data for RAM parity adjustment. Further, the specific value is stored in the Q register until the determination process is performed (for example, in the example of FIG. 4, the specific value is set until the process of Sa7 is performed). Therefore, even if the LDQ instruction is erroneously executed before the determination process is executed, for example, the possibility of accessing the game RAM area can be reduced.

  Further, in the present embodiment, the determination data (fixed data for RAM destruction diagnosis and data for RAM parity adjustment) used in the determination process is stored in the game RAM area. Therefore, until the determination process is executed, that is, when the determination data stored in the game RAM area is stored, the determination data is changed by unintentionally accessing the game RAM area. It is possible to reduce the possibility of being

  (2-4) Further, the storage of the setting value at startup (Sa1B in FIG. 4) in the internal function register is also executed by the LDQ instruction. Specifically, based on the specific value (upper address is F5) stored in the Q register in Sa1A and the value (lower address) specified for each of the N in the LDQ instruction, the N settings are made. The value is stored in each of N regions in the internal function register. Therefore, according to such a configuration, it is possible to reduce the program capacity of the LDQ instruction as compared with the configuration in which all the addresses of the internal function register are specified to specify the address in the LDQ instruction.

  (3-1) In addition, until the access to the game RAM area is prohibited (for example, until the RAM access shown at timing T2 in FIG. 7 is prohibited), the address of the game RAM area is stored in the Q register. A specifiable predetermined value (for example, a predetermined value capable of specifying the upper address "F0" of the game RAM area) is stored. Further, after the access to the game RAM area is prohibited (for example, after the RAM access shown at timing T2 in FIG. 7 is prohibited), the address of the internal function register which is an area different from the game RAM area can be specified A specific value (for example, a value capable of specifying the upper address "F5" of the internal function register) is stored.

  Also, after access to the game RAM area is prohibited, it can be said that the game RAM area is an important area.

  If a predetermined value (a value indicating the upper address “F0” of the gaming RAM area) is stored in the Q register during a period (for example, a period from timing T2 to T3) after RAM access is prohibited. In some cases, the LDQ instruction may be executed due to a malfunction or the like. In this case, access to the game RAM area (important area) where access is prohibited is performed (access not intended by the designer). In the present embodiment, when the game RAM area to which access is prohibited is accessed, the progress of the game is disabled. Therefore, if the LDQ command is executed due to a malfunction or the like, the progress of the game is inadvertently disabled.

  Therefore, in the present embodiment, after RAM access is prohibited, a specific value (a value capable of specifying the upper address of the internal function register) is stored. Therefore, after the RAM access is prohibited, even if the LDQ command is executed due to a malfunction or the like, the game RAM area is not accessed, so there is a possibility that the progress of the game is carelessly made. It can be reduced.

  In addition, when RAM access is prohibited, even if the game RAM area is accessed, a configuration that does not execute "disabling processing to disable the progress of the game" (hereinafter referred to as "disabling processing non-execution configuration"). It may be In such a configuration, when the game RAM area is accessed by executing the LDQ command due to a malfunction or the like when the RAM access is prohibited, the data stored in the game RAM area is It may be changed.

  On the other hand, in the present embodiment, when RAM access is prohibited, a specific value is set in the Q register. Therefore, in the gaming machine in which the disabling process non-execution configuration is adopted, the possibility that the game RAM area is accessed can be reduced even if the LDQ instruction is executed due to a malfunction or the like.

[Modification]
As mentioned above, although the main embodiment in this invention was described, this invention is not limited to said embodiment, A various deformation | transformation and application are possible. Hereinafter, modified examples of the above-described embodiment applicable to the present invention will be described.

  (1) In the present embodiment, as shown in the power interruption process of FIG. 6, setting of the specific value of Sk8 in the Q register is described as being performed before setting of the RAM access prohibition flag of Sk9. However, the process of Sk8 may be performed after the process of Sk9. Alternatively, the process of Sk8 and the process of Sk9 may be performed simultaneously. That is, the process of Sk8 is a process that is executed when access to the RAM 41c is prohibited (when access to the RAM 41c is prohibited). Even with such a configuration, the same effect as that of the present embodiment can be obtained.

  (2) In the present embodiment, as a method of returning to the control state (at the time of power failure detection) in the power failure process in the startup process (during power failure recovery), backup power is supplied to the game RAM area In addition, as described in Sk1 and Sk2 of FIG. 6, it has been described that the register and the stack pointer are saved. However, another method may be adopted as a method of returning to the control state at the time of the power interruption detection.

  For example, a configuration may be adopted in which at least a part of data indicating the control state when the power failure is detected is saved in the backup area. When such a configuration is adopted, it can be said that the backup area is an important area. Therefore, for example, a configuration may be adopted in which the predetermined value is a value that can identify the upper address of the backup area, and the specific value is a value that can identify the upper address of an area different from the backup area. Even with such a configuration, the same effect as that of the present embodiment can be obtained.

  (3) Further, in FIG. 4, a period from when a specific value is set in the Q register by the process of Sa1A to when a predetermined value is set in the Q register by the process of Sa3B (hereinafter, referred to as a first period. In addition to the processing described in FIG. 4 based on the LDQ instruction as processing using the function setting register), or the processing described in FIG. It may be executed in place of In this case, M (M is an integer of 2 or more) processing is executed based on the LDQ instruction (an instruction specifying only the lower address of the function setting register) as the process using the function setting register in the first period. The configuration can reduce the program capacity more than the configuration in which the M processes are executed based on an instruction specifying both the upper address and the lower address of the function setting register.

  Further, in FIG. 6, based on the LDQ instruction, as processing using the function setting register in a period from when a specific value is set in the Q register by Sk8 to when it enters a loop (hereinafter referred to as a second period). 6 may be executed in addition to the process described in FIG. 6 or may be executed in place of the process described in FIG. In this case, L (L is an integer of 2 or more) processing is executed based on the LDQ instruction (an instruction specifying only the lower address of the function setting register) as the process using the function setting register in the second period. The configuration can reduce the program capacity more than the configuration in which the L pieces of processing are executed based on an instruction specifying both the upper address and the lower address of the function setting register.

  (4) In the example of the power-off process in FIG. 7, the RAM access is prohibited at the timing T2 at which the specific value of the Q register is set. However, the RAM access may be inhibited after other processing is performed at the timing when the specific value of the Q register is set. Further, in the example of the start-up process of FIG. 7, it has been described that the predetermined value is set in the Q register at the timing T6 at which the RAM access is permitted. However, a predetermined value may be set in the Q register after other processing is performed at the timing when the RAM access is permitted. According to these configurations, the same effect as the present embodiment can be obtained while performing other processing.

  (5) In the present embodiment, the upper address of the game RAM area is "F0", and the upper address of the internal function register is "F5". However, if the upper addresses of the game RAM area and the upper addresses of the internal function register are different from each other in the upper addresses of both areas, the upper addresses of at least one of the two areas may be different from this embodiment. For example, the upper address of the game RAM area may be "F1" and the upper address of the internal function register may be "FE". Even with such a configuration, the same effect as that of the present embodiment can be obtained.

  (6) In the activation process of the present embodiment, processing (see Sa1 and Sa2 in FIG. 4) using the power failure detection signal (signal indicating that the power supply has been stopped) is executed in Sa1 and Sa2 in the activation process. I explained that. However, instead of the power failure detection signal indicating that power supply has been stopped, the start processing is performed using a signal indicating that power supply has been started (hereinafter referred to as "power supply signal"). It is also good.

  In the configuration using the power supply signal, in Sa1 of FIG. 4, data (power supply) indicating that the power supply signal is input to the signal region (region in the internal function register) of the input port Supply signal flag) is set. Then, in Sa2, it is determined whether or not the power supply signal flag is stored in the signal area, and if it is determined YES in Sa2, the process proceeds to Sa3A. Even with such a configuration, the same effect as that of the present embodiment can be obtained.

  (7) In the present embodiment, the upper address of each of the start address of the special work, the start address of the important work, and the start address of the part of the general work has been described as “F0”. However, the area where the upper address is "F0" may be another area. For example, this other area may be an area (specific storage area) in which data is read or data is written according to the progress of the game. In addition, this other area may be an area (specific storage area) for saving (backing up) at least a part of control data at the time of the power failure when the power is disconnected. In this case, upon power failure recovery, control data at the time of power failure may be restored based on the saved data.

  It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is indicated not by the above description but by claims, and is intended to include all modifications within the meaning and scope equivalent to claims.

  1 slot machine, 6 MAX BET switch, 7 start switch, 41 main control unit, 91 sub control unit.

Claims (1)

A gaming machine capable of playing a game,
An instruction execution unit that specifies an address of a storage area using data stored in a predetermined storage area, and executes a specific instruction that reads data from the storage area of the specified address based on a program;
A process for executing a process for restoring the control state based on the data stored in the specific storage area when the power supply to the gaming machine is detected, when the stop of the power supply is detected Equipped with
In the predetermined storage area,
The predetermined value data used to specify the address of the specific storage area is stored until the stop of the power supply to the gaming machine is detected.
A gaming machine, wherein specific value data used to specify an address of an area different from the specific storage area is stored when a stop of power supply to the gaming machine is detected.

Images