JP2023158039A - Game machine - Google Patents

Abstract

To reduce a program capacity in a game machine.SOLUTION: A game machine includes control means for performing control pertaining to progress of a game. The control means includes an accessible memory address space, and at least one register group including multiple general-purpose registers, and multiple upper-level value registers as registers for storing high-level values of a memory address space to be handled by partial instructions. The high-level value registers include a first type high-level value register and a second type high-level value register, and is configured so as to store a first high-level value in the first type high-level value register and a second high-level value differing from the first high-level value in the second type high-level value register, and refers to the first high-level value in the first type high-level value register in execution of a first instruction and refers to the second high-level value in the second type high-level value register in execution of a second instruction differing from the first instruction.SELECTED DRAWING: Figure 26

Description

The present invention relates to a gaming machine, and particularly relates to details of a program executed by the gaming machine.

For example, in gaming machines such as pinball gaming machines such as pachinko gaming machines and reel-type gaming machines such as slot machines, an arithmetic processing unit such as a CPU (Central Processing Unit) is installed as a control means for controlling the progress of the game. The arithmetic processing unit performs processing according to instructions written in the program, thereby realizing various operations of the gaming machine.

Note that the following Patent Document 1 can be cited as a related prior art.

JP 2019-141675 Publication

Here , in recent years, the processes executed by gaming machines have become diverse, and it has become difficult to store the program of the control means in a memory with limited capacity.

Therefore, an object of the present invention is to reduce the program capacity of a gaming machine.

A gaming machine according to the present invention includes a control means for controlling a game, and the control means has an accessible memory address space, a general-purpose register, and an address of the memory address space handled in some instructions. It has at least one register group each containing a plurality of upper value registers that are registers that store upper values, and the upper value registers include a first type upper value register and a second type upper value register. , the first type upper value register is configured to store a first upper value, and the second type upper value register is configured to store a second upper value different from the first upper value; When executing an instruction, refer to the first upper value of the first type upper value register, and when executing a second instruction different from the first instruction, refer to the second upper value of the second type upper value register. It refers to a value .

Note that the gaming machine may be configured as follows.
That is, it includes a first register group and a second register group each including a plurality of general-purpose registers, a first interrupt management register, and a second interrupt management register, and the first interrupt management register and the second register group are provided. a first instruction to write a permission value to the second interrupt management register; a second instruction to write a prohibition value to the first interrupt management register and the second interrupt management register; There is a third instruction used, and a fourth instruction used when returning from the out-of-area program to the in-area program, and the third instruction, before calling the out-of-area program, It is possible to execute processing for writing the prohibited value in the first interrupt management register and switching the register group to be used from the first register group to the second register group, and the fourth instruction is executed by the program in the area. Before returning to , execute processing for overwriting the value of the second interrupt management register in the first interrupt management register and switching the register group to be used from the second register group to the first register group. This is possible, and in the program within the area, the third instruction is executed after the second instruction is executed but before the first instruction is executed.
When executing a program outside the area, it is necessary to disable interrupts. Therefore, if the first instruction is executed before the third instruction is executed, the interrupt disabled state and interrupt enabled state will be frequently switched. On the other hand, if the third instruction is executed after the second instruction is executed but before the first instruction as described above, the interrupt-disabled state is maintained and the out-of-area program is executed. Since the call and return to the program within the area are performed, the number of times the interrupt control state is switched can be reduced.

Furthermore, in the gaming machine described above, the first register group has a first stack pointer that stores a stack pointer, and the second register group has a second stack pointer that stores a stack pointer. , causing the first stack pointer to store address information of the stack memory used by the program within the area, storing address information of the stack memory used by the program outside the area into the second stack pointer, and storing address information of the stack memory used by the program outside the area, In a program, when executing the third instruction and calling the out-of-area program, there are cases in which the out-of-area program is called by specifying a first address thereof, and in which it is called by specifying a second address. In the out-of-area program, a fifth controller for storing common stack memory address information in the second stack pointer both when the first address is called and when the second address is called. It is possible to have a configuration that executes instructions.

This makes it possible to reset the value of the stack pointer used by the out-of-area program each time the out-of-area program is called.

Furthermore, in the gaming machine described above, the first register group has a first stack pointer that stores a stack pointer, and the second register group has a second stack pointer that stores a stack pointer. , causing the first stack pointer to store address information of the stack memory used by the program within the area, storing address information of the stack memory used by the program outside the area into the second stack pointer, and storing address information of the stack memory used by the program outside the area, In a program, when executing the third instruction and calling the out-of-area program, the first address of the out-of-area program is specified and called, and the second address is specified and called at a later timing. In some cases, the out-of-area program executes a sixth instruction for storing predetermined stack memory address information in the second stack pointer only when the first address is called. Is possible.

The stack memory address information that should be set for the second stack pointer at the start of processing of an out-of-area program is fixed address information, so as an out-of-area program, the second address is set after the program at the first address is executed. When a program is executed, it is sufficient to store address information in the second stack pointer only in the program at the first address, which is the program to be executed first.

According to the present invention, it is possible to reduce the program capacity in a gaming machine.

FIG. 1 is a front perspective view showing the appearance of a gaming machine as an embodiment of the present invention. It is a diagram showing the configuration of a game board of a game machine as an embodiment. It is a block diagram showing a control configuration of a gaming machine as an embodiment. FIG. 3 is an explanatory diagram of an example of a prefetch preview performance in the embodiment. It is a flow chart showing main processing on the main control side of the embodiment. 6 is a flowchart showing the initial setting process in FIG. 5. FIG. 7 is a flowchart showing power abnormality check processing according to the embodiment. FIG. 7 is a diagram showing the correspondence between the operational judgment conditions for transitioning to setting change processing, RAM clearing processing, setting confirmation processing, and backup restoration processing and the values of the W register. 6 is a flowchart showing main loop processing in FIG. 5. FIG. 6 is a flowchart showing the setting change process in FIG. 5. FIG. 11 is a flowchart showing the output management process in FIG. 10. It is a figure showing an example of a 7 segment decoding table. FIG. 3 is a diagram illustrating a relationship between a segment configuration and a segment display pattern on a setting value display. 6 is a flowchart showing RAM clear processing in FIG. 5. FIG. 6 is a flowchart showing the setting confirmation process in FIG. 5. FIG. FIG. 3 is a diagram showing an example of a set value offset conversion table. 6 is a flowchart showing main loop pre-processing in FIG. 5. FIG. 3 is a flowchart showing main control side timer interrupt processing according to the embodiment. 19 is a flowchart showing the power check/backup process in FIG. 18. 19 is a flowchart showing the setting abnormality check process in FIG. 18. FIG. 3 is an explanatory diagram of areas set in the memory of the main control unit. FIG. 3 is an explanatory diagram of regulations set for each area. FIG. 3 is a diagram showing a register configuration in a prior example. 9 is a diagram illustrating a program of a portion mainly corresponding to the main loop processing (FIG. 9) in the main control side main processing (FIG. 5). FIG. FIG. 3 is a diagram illustrating a program related to performance display monitor total division processing (S304). FIG. 2 is a diagram showing a register configuration in an embodiment. It is an explanatory diagram about the update rule of the interrupt control flag in an embodiment. FIG. 3 is a diagram illustrating an example of an intra-area program when a process transfer method according to an embodiment is applied. FIG. 3 is a diagram illustrating an example of an out-of-area program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram illustrating another example of an intra-region program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an out-of-area program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an intra-region program when the process transfer method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an out-of-area program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an intra-region program when the process transfer method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an out-of-area program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an intra-region program when the process transfer method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an out-of-area program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an intra-region program when the process transfer method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an out-of-area program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an intra-region program when the process transfer method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an out-of-area program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an intra-region program when the process transfer method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an out-of-area program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an intra-region program when the process transfer method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an out-of-area program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an intra-region program when the process transfer method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an out-of-area program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an intra-region program when the process transfer method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an out-of-area program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an intra-region program when the process transfer method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an out-of-area program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an intra-region program when the process transfer method according to the embodiment is applied. FIG. 7 is a diagram showing another example of an out-of-area program when the process migration method according to the embodiment is applied. FIG. 7 is a diagram showing a modification of an intra-area program related to a register bank switching instruction. FIG. 7 is a diagram showing a modification of an out-of-area program related to a register bank switching instruction. FIG. 7 is a diagram showing a modification of an intra-area program related to a register bank switching instruction. FIG. 7 is a diagram showing a modification of an out-of-area program related to a register bank switching instruction. FIG. 7 is a diagram showing a modification of an intra-area program related to a register bank switching instruction. FIG. 7 is a diagram showing a modification of an out-of-area program related to a register bank switching instruction. FIG. 7 is a diagram showing a modification of an intra-area program related to a register bank switching instruction. It is. FIG. 7 is a diagram showing a modification of an out-of-area program related to a register bank switching instruction. FIG. 7 is a diagram showing an example of an intra-area program when using "CALL" and "RET" instructions. FIG. 7 is a diagram showing an example of an out-of-area program when using "CALL" and "RET" instructions. FIG. 3 is a diagram showing a memory map of the main control unit in the embodiment.

Hereinafter, embodiments of the present invention will be described in the following order with reference to the accompanying drawings.

<1. Structure of gaming machine>
<2. Control configuration of gaming machine>
[2-1. Main control section]
(About changing settings)
(About performance display)
(Production control command)
[2-2. Performance control section]
<3. Overview of operation>
[3-1. Symbol fluctuation display game]
(Special symbol fluctuation display game)
(Decorative pattern variable display game)
(Normal symbol fluctuation display game)
(About suspension)
[3-2. Game state]
[3-3. About the hit]
[3-4. About the production]
(Production mode)
(Preview performance)
(Direction means)
<4. Main control unit processing>
[4-1. Main control side main processing]
(Initial setting process)
(Processing after initial settings)
(main loop processing)
(Setting change processing)
(RAM clear processing)
(Setting confirmation process)
(main loop preprocessing)
(Advantages of data table for setting value display and setting value conversion table)
[4-2. Main control side timer interrupt processing]
(Power check/backup processing)
(Processing for error management and game progress, etc.)
<5. About processing transition between in-area processing and out-of-area processing>
[5-1. Regarding used area and unused area]
[5-2. Processing transfer method in precedent example]
[5-3. Processing migration method as an embodiment]
[5-4. Another example of a program]
[5-5. Program modification example]
[5-6. Other variations]
<6. About Q register and U register>
<7. Summary of embodiments>

<1. Structure of gaming machine>

The structure of a pachinko gaming machine 1 as an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a perspective view of the front side showing the external appearance of the pachinko game machine 1, and FIG. 2 is a view showing the front side of the game board 3 included in the pachinko game machine 1.

A pachinko gaming machine 1 (hereinafter sometimes abbreviated as "gaming machine 1") shown in FIG. A game board 3 (see FIG. 2) is installed in an attached game board storage frame (not shown), and a game area 3a formed on the surface of the game board 3 is exposed to the opening of the front frame 2. have A glass door 6 supporting transparent glass is provided on the front side of this gaming area 3a. Further, on the back side of the game board 3, various control boards (see FIG. 3) for controlling game operations are arranged.

A key cylinder (not shown) for unlocking the door is provided on the front side of the glass door 6, and by inserting a key into this key cylinder and operating it to one side, the locked state of the glass door 6 with respect to the front frame 2 can be changed. , by operating the front frame 2 to the other side, the locked state of the front frame 2 relative to the outer frame 4 can be released and opened to the front side.

A front operation panel 7 is disposed below the glass door 6 and is pivotally supported to the front frame 2 by a hinge (not shown) so as to be openable and closable. The front operation panel 7 is provided with an upper tray unit 8, and the upper tray unit 8 is formed with an upper tray 9 for storing ejected game balls.

The upper tray unit 8 also includes a ball extraction button 14 for pulling out the game balls stored in the upper tray 9 to the bottom of the gaming machine 1, and a ball removal button 14 for discharging game balls to a game ball lending device (not shown). A ball lending button 11 for making a request and a card return button 12 for requesting the return of the valuable medium inserted into the game ball lending device are provided. Further, the upper tray unit 8 is provided with a performance button 13 (operating means) configured to be operable by the player. This production button 13 becomes operable (input accepted) when the built-in lamp (button LED 75) is lit during a predetermined input reception period, and a predetermined operation (pressing, repeated pressing, long pressing, etc.) is performed while the built-in lamp is lit. By doing so, it is possible to bring about changes in the performance.
Although not shown in FIG. 1, the front operation panel 7 includes a cross key 15a for users such as players and hall staff to select various items and give directions, and selection items. Operators such as a decision button 15b are provided for instructing the decision to be made.

Further, on the right end side of the front operation panel 7, a firing operation handle 15 is provided for operating the firing device 32 (see FIG. 3).

Further, on both sides of the upper part of the front frame 2 and above the firing operation handle 15, speakers 46 are provided to produce a sound production effect (sound effect) by sound. In addition, a plurality of decorative lamps 45 (for example, full-color LEDs for light production, etc.) are provided at appropriate locations on the glass door 6 to provide a light production effect through light decoration. A plurality of full-color LEDs (LEDs for light production) serving as the decorative lamps 45 are provided around the pachinko game machine, that is, around the front frame of the glass door 6 in the circumferential direction.

The configuration of the game board 3 will be explained with reference to FIG. 2. On the illustrated game board 3, a ball guide rail 5 that guides the launched game balls is attached in an annular manner as a board partitioning member, and a generally circular area surrounded by the ball guide rail 5 is a game area 3a, The four corners are non-gaming areas.

Approximately in the center of the gaming area 3a, for example, three (left, middle, right) display areas (symbol variation display areas) independently display a plurality of types of decorative patterns (for example, numbers, characters, symbols, etc.). A liquid crystal display (LCD) 36 is equipped with a liquid crystal display device (LCD) 36 that is capable of variable display operation (fluctuating display and stop display) of the left symbol (compatible with the left display area), middle symbol (compatible with the middle display area), and right symbol (compatible with the right display area). It is provided. In the following description, a plurality of types of decorative symbols that are variably displayed on the left, middle, and right symbols may be referred to as a "symbol group." That is, for example, the symbol stopped and displayed in the left display area is one of the symbol groups that constitute the left symbol.
The liquid crystal display device 36 displays various effects in the form of images in addition to the variable display operation of decorative symbols under the control of the effect control section 24 to be described later.

In addition, a center decoration 48 is provided in the game area 3a in a form that extends far around the display surface of the liquid crystal display device 36. The center decoration 48 is provided along the front side of the game board 3, and protects the display surface of the liquid crystal display device 36 from surrounding game balls. It acts as a channel distribution means that allows channels to be divided into left and right. In this embodiment, the center decoration 48 is arranged approximately at the center of the game area 3a so that the presence of the center decoration 48 forms a flow path for the game ball on both upper sides (left and right sides) of the game area 3a. ing. The game ball shot into the upper side of the game area 3a by the firing device 32 is distributed to the left and right on the upper side of the armor frame 48b, and is divided into the left downstream path 3b on the left side of the center decoration 48 and the right downstream path 3c on the right side. flow down either.

In addition, the non-gaming area near the upper right edge (upper right corner) of the game board 3 serves as a display area for various functions, and the 7-segment display (with dots) is connected to the upper starting port 34 (for the first special symbol) and the lower starting port 34 (for the first special symbol). A special symbol display device 38a (first special symbol display means) and a special symbol display device 38b (second special symbol display means) are arranged side by side in correspondence with the mouth 35 (for the second special symbol). is provided. In the special symbol display devices 38a and 38b, a special symbol variable display game is executed by a variable display operation of a "special symbol" expressed by a 7-segment display. Then, the liquid crystal display device 36 displays a decorative pattern in the form of an image in a variable manner in synchronization with the variable display of special symbols by the special symbol display devices 38a and 38b, and displays the decorative pattern along with various preview effects (effect images). Symbol variation display games are to be executed (details regarding these symbol variation display games will be explained later).

Further, in the various function display sections, a composite display device (LED display for pending composite display) 38c consisting of a 7-segment display (with dots) is arranged next to the special symbol display devices 38a and 38b. What is called "compound" is the five functions: special symbols 1 and 2, display of the number of pending balls for normal symbol operation, and status notification when the variable time reduction function is activated (time saving mode) and high probability state (high accuracy mode). This is because it is a holding/time-saving/high-accuracy composite display device (hereinafter simply referred to as a "compound display device") having a display function.

Further, in the various function display section, a normal symbol display device 39a (normal symbol display means) formed by arranging a plurality of (two in this embodiment) LEDs is provided next to the composite display device 38c. In this normal symbol display device 39a, a normal symbol variable display game is executed by a variable display operation of normal symbols expressed by two LEDs. For example, as a fluctuating display operation, the normal symbols by LEDs alternately turn on and off like a seesaw, and by stopping with either side lit, it becomes clear whether the normal symbol fluctuating display game is correct or not. There is. Further, a round number display device 39b is provided adjacent to the normal symbol display device 39a, which is formed by arranging three LEDs (first to third round display LEDs). This round number display device 39b notifies the specified number of rounds (maximum number of rounds) related to the jackpot based on the combination of the lighting and non-lighting states of the three LEDs.

Below the center decoration 48, an upper starting port 34 (first special symbol starting port: first starting means) and a lower starting port 35 (second special symbol starting port: second starting means) are provided. A normal variable prize winning device 41 is provided above and below, and detection sensors 34a and 35a (upper starting hole sensor 34a, lower starting hole sensor 35a: see FIG. 3) for detecting passage of a game ball are formed inside each. ing.

The upper starting opening 34, which is the first special symbol starting opening, is the first special symbol in the special symbol display device 38a (hereinafter, the first special symbol will be referred to as "special symbol 1", and in some cases may be referred to as "special symbol 1"). This is a winning opening related to the starting conditions for the variable display operation of the ``starting hole'' (hereinafter referred to as ``starting hole opening/closing means''), and is configured as a winning rate fixed type winning device that does not have a starting opening/closing means (means that allows the starting opening to be opened or enlarged). In this embodiment, due to the action of a game ball fall direction changing member (for example, a game nail (not shown), a windmill 44, a center decoration 48, etc.) in the game area 3a, the left flow downward path 3b is caused to reach the upper starting port 34. The game ball that has flown down the right flow path 3c has a configuration that allows the ball to enter (win) easily, whereas the game ball that has flown down the right flow path 3c has a configuration that makes it difficult or impossible for the ball to enter.

The normal variable winning device 41 is configured as a winning rate variable winning device in which the winning rate of game balls in the starting hole can be varied by the starting hole opening/closing means. In this embodiment, the starting opening/closing means includes a pair of left and right movable wings (movable members) 47 that enable the lower starting opening 35, which is the second special symbol starting opening, to be opened or expanded. It is configured as a "type" winning device.

The lower starting port 35 of the normal variable winning device 41 is connected to the second special symbol in the special symbol display device 38b (hereinafter, the second special symbol will be referred to as "special symbol 2", and may be abbreviated as "special symbol 2" in some cases). ), and the winning area of the lower starting port 35 is in the open state ( It is converted into a closed state (difficult to win state) which makes it more difficult or impossible to win than the open state. In this embodiment, when the movable wing piece 47 is inactive, it maintains a closed state (a winning impossible state) in which winning to the lower starting port 35 is impossible.

In addition, on both sides of the normal variable winning device 41, there are four general winning holes 43, three on the left side and one on the right side, and inside each one is a general winning hole that detects the passing of a game ball. A mouth sensor 43a (see FIG. 3) is formed. Furthermore, within the area of the game board, a movable accessory (not shown) that provides a visual presentation effect is arranged at a position that does not obstruct the flow of the game ball.

Further, on the diagonally upper right side of the normal variable winning device 41, that is, on the upper side of the middle part of the right downstream path 3c, there is a normal symbol starting port 37 (third starting port) consisting of a passing gate (specific passing area) through which a game ball can pass. means) are provided. This normal symbol starting opening 37 is a winning opening related to the normal symbol fluctuating display operation in the normal symbol display device 39a, and inside thereof is a normal symbol starting opening sensor 37a (see FIG. 3) that detects a passing game ball. is formed. In addition, in this embodiment, the normal symbol starting port 37 is formed only on the right downstream path 3c side, and is not formed on the left downstream path 3b side. However, the present invention is not limited to this, and may be formed only in the left downstream path 3b, or may be formed in both downstream paths, respectively.

In the middle of the route from the normal symbol start opening 37 to the normal variable winning device 41 in the right downstream route 3c, there is a special variable winning hole configured to allow the large winning hole 50 to be opened or enlarged by a retractable opening door 52b. A device 52 (special electric accessory) is provided, and a big winning hole sensor 52a (see FIG. 3) for detecting a game ball that enters the big winning hole 50 is formed inside the device 52 (special electric accessory).

The area around the big prize opening 50 is a bulge (decorative member) 55 that bulges out from the surface of the game board 3, and the upper side 55a of this bulge 55 forms the downstream guide part of the right downstream path 3c. There is. When the big winning opening 50 is closed by the open door 52b (big winning opening closed state), by forming a surface continuous with the upper side 55a of this bulging part 55, the downstream guide part of the right downstream path 3c ( It forms part of the upper side 55a). In addition, in the downstream area of the right downstream path 3c, in the area above the upper side 55a of the bulging part 55, or more precisely, in the gaming area above the big prize opening 50, there is a flow path correction plate approximately parallel to the downstream direction of the game ball. 51d is provided in a protruding manner, and serves to draw the game balls flowing down toward the big prize opening 50.

The process of entering the game ball into the grand prize opening 50 is as follows.
The game ball that has passed through the floating area between the top surface of the center decoration 48 and the ball guiding rail 5 is placed on the top surface (upper side) 55a of the bulge portion 55 that protrudes from the game board 3 and functions as a guide for the game ball. It flows down along the river. Then, the game ball comes into contact with the right end of the flow path correction plate 51d protruding from the surface of the game board 3, whereby the flowing direction of the game ball is corrected in the direction of the big prize opening 50 (downward). At this time, if the grand prize opening 50 is covered by the push-in type open door 52b (grand prize opening closed state), the game ball rolls on this, and a predetermined array (not shown) is formed. The game nail guides the player in the direction of the tulip-type normal variable winning device 41 (lower starting port 35). At this time, if the lower starting port 35 is in a winning state (starting port open state), a game ball can be won in the lower starting port 35. On the other hand, if the open door 52b is retracted into the game board surface and the grand prize opening 50 is open (grand prize opening state), the game ball is guided into the grand prize opening 50.

In the gaming machine 1 of this embodiment, when the player aims the firing position toward the special variable prize winning device 52 side (when the player aims so that the game ball passes through the right downstream path 3c), the upper starting port The game ball is configured to be difficult or not guided to the 34 side. Therefore, in the "big winning opening closed state", unless the movable wing piece 47 of the normal variable winning device 41 is operated, it is difficult or impossible to win a prize at each starting opening 34, 35. The movable wing pieces 47 are designed to operate in an opening/closing pattern that is more advantageous than in the normal state when the game state is brought about with the electric support state described later.

In the case of this embodiment, the way the player plays to create an advantageous situation changes depending on the gaming state. Specifically, in a gaming state that involves the "state without electric support" described below, it is considered advantageous to "hit to the left" in which the game ball is aimed so that it passes through the left downstream path 3b; If the game state is accompanied by a "presence state", it is considered advantageous to "hit right" in which the game ball is aimed so that it passes through the right downstream path 3c.

In the gaming machine 1 of the present embodiment, when there is a winning in a winning opening other than the normal symbol start opening 37 among the various winning openings provided in the gaming area 3a, a promise is made for each winning opening. The number of prize balls per winning ball (for example, 3 for the upper starting hole 34 or lower starting hole 35, 13 for the big winning hole 50, and 10 for the general winning hole 43) is determined by the game ball payout device 19 (FIG. 3). (see). The game balls that do not enter into each of the above-mentioned winning holes are discharged from the gaming area 3a through the out hole 49.
Here, "winning" refers to a winning opening that takes a game ball into its interior, or a winning opening that is not a structure that takes a gaming ball inside but is a pass-through type gate (for example, the normal symbol starting opening 37). If it is, it means that a game ball passes through that gate, and in reality, if a game ball is detected by each winning detection switch formed for each winning hole, a "winning" will occur in that winning hole. be treated as such. The game balls related to this winning are also referred to as "winning balls." In addition, if a game ball enters the winning hole, that game ball will be detected by the winning detection switch, so unless otherwise specified in this specification, it does not matter whether the gaming ball is detected by the winning detection switch or not. Regardless, the term "winning" may include the case where a game ball enters the winning opening.

<2. Control configuration of gaming machine>

A configuration (control configuration) for realizing gaming operation control of the gaming machine 1 will be explained with reference to the block diagram in FIG. 3.
The gaming machine 1 of the present embodiment includes a main control board (main control means) 20 (hereinafter referred to as "main control section 20") that controls overall control of gaming operations (gaming operation control), and a main control section. A production control board (production control means) 24 (hereinafter referred to as "production control unit 24") which receives production control commands from the production means 20 and centrally controls production execution control (appearance control) by production means, and a prize ball. a payout control board (payout control means) 29 that performs payout control; a power supply board (power supply control means (not shown)) that generates and supplies the necessary power to the gaming machine 1 from an external power supply (not shown); It is composed of
Note that in FIG. 3, power supply routes to each part are omitted.

[2-1. Main control section]

The main control unit 20 is equipped with a microprocessor with a built-in CPU (Central Processing Unit) 20a (main control CPU), and also stores various data necessary for controlling the gaming operations in addition to a control program that describes the gaming operation control procedure. It is equipped with a ROM (Read Only Memory) 20b (main control ROM) for storage, and a RAM (Random Access Memory) 20c (main control RAM) that functions as a work area and buffer memory, making up a microcomputer as a whole. .

Although not shown, the main control unit 20 includes a CTC (Counter Timer Circuit) and a CPU 20a for realizing periodic interrupts, constant cycle pulse output generation functions (bit rate generator), and time measurement functions. An interrupt controller circuit that provides an interrupt enable/disable function such as a timer interrupt that provides an interrupt signal, and can output a system reset signal to reset the CPU 20a by detecting power-on, power-off, power abnormality, etc. a reset circuit, a watchdog timer (WDT) circuit that monitors abnormal operation of the control program, and a travel prohibition outside designated area (IAT) circuit that monitors whether the program is being executed correctly within a preset address range. , and a counter circuit for generating random numbers within a certain range using hardware.

The counter circuit includes a random number generation circuit that generates random numbers and a sampling circuit that samples random numbers from the random number generation circuit at predetermined timing, and works as a 16-bit counter as a whole. The CPU 20a acquires the numerical value indicated by the random number generation circuit as an internal lottery random number (random number for jackpot determination (random number size: 65536)) by sending an instruction to the sampling circuit according to the processing state. , and use that random number for the jackpot lottery. Note that the internal lottery random number is obtained by adding a soft random number generated by appropriate software processing and a hard random number in order to prevent cheating such as trying to win.

Further, the CPU 20a includes a plurality of registers for storing various values. Note that details of the registers included in the CPU 20a in the embodiment will be described later.

The main control unit 20 includes an upper starting hole sensor 34a that detects winning (ball entering) into the upper starting hole 34, a lower starting hole sensor 35a that detects winning into the lower starting hole 35, and a normal symbol starting hole 37. A normal symbol starting hole sensor 37a that detects the passage of the symbol, a big winning hole sensor 52a that detects winning to the big winning hole 50, a general winning hole sensor 43a that detects winning to the general winning hole 43, and an out hole 49. An OUT monitoring switch 49a is connected to detect game balls (out balls) ejected from the main controller 20, and the main control unit 20 can receive detection signals output from these. The main control unit 20 is able to grasp which winning hole the game ball has entered based on the detection signals from each sensor.

In addition, the main control unit 20 includes a normal electric accessory solenoid 41c for controlling the opening and closing of the movable wing piece 47 of the lower starting port 35, and a large winning opening solenoid 52c for controlling opening and closing of the opening door 52b of the large winning opening 50. are connected, and the main control unit 20 can transmit control signals for controlling these.

Further, a special symbol display device 38a and a special symbol display device 38b are connected to the main control section 20, and the main control section 20 is capable of transmitting a control signal for controlling the display of the special symbols 1 and 2. . Furthermore, a normal symbol display device 39a is connected to the main control unit 20, and is capable of transmitting a control signal for displaying and controlling the normal symbols.

Further, a composite display device 38c and a round number display device 39b are connected to the main controller 20, and the main controller 20 outputs control signals for display-controlling various information displayed on the composite display device 38c, round number display device 39b, etc. It is possible to transmit a control signal for controlling the display of the prescribed round number of jackpots displayed on the number display device 39b.

Further, an external centralized terminal board 21 for the frame is connected to the main control unit 20, and the main control unit 20 controls the hall computer HC provided outside the gaming machine via the external centralized terminal board 21 for the frame. It is possible to transmit game information (for example, jackpot information, prize ball number information, symbol variation execution information, etc.).
The hall computer HC is an information processing device (computer device) for monitoring gaming information from the main control unit 20 and comprehensively managing the operating status of the gaming machines in the pachinko hall.

Furthermore, a payout control board (payout control unit) 29 is connected to the main control unit 20, and when it is necessary to pay out prize balls, a control command regarding payout (number of prize balls) is sent to the payout control board 29. It is possible to send a payout control command that specifies a payout control command.

A launch control board (launch control unit) 28 that controls the launch device 32 and a game ball payout device (game ball payout means) 19 that pays out game balls are connected to the payout control board 29. The main roles of this payout control board 29 include receiving payout control commands from the main control unit 20, controlling the prize ball payout of the game ball payout device 19 based on the payout control commands, and transmitting status signals to the main control unit 20. It is.

The game ball payout device 19 is provided with an out-of-supply detection sensor 19a that detects a lack of supply of game balls, and a ball count sensor 19b that detects the game balls (prize balls) to be paid out. It is possible to receive each detection signal. Further, the game ball payout device 19 is provided with a payout motor 19c that drives a ball payout mechanism (not shown) for paying out game balls, and a payout control board 29 is configured to control the payout motor 19c. control signals can be transmitted.

Further, the payout control board 29 includes a full detection sensor 60 that detects when the upper tray 9 is full of game balls (in this embodiment, a detection sensor that detects the stored state of game balls stored in the upper tray 9). , a front door open sensor 61 (in this embodiment, a detection sensor that detects at least the open state of the front frame 2) is connected.

The payout control board 29 is capable of transmitting various status signals to the main control unit 20 based on detection signals from the full detection sensor 60, the front door open sensor 61, the out-of-supply detection sensor 19a, and the ball counting sensor 19b. It becomes. The status signals include a ball jam signal indicating a full state, a door open signal indicating that at least the front frame 2 is open, an out-of-supply signal indicating an insufficient supply of game balls from the game ball payout device 19, and a prize ball signal. It is configured to be able to transmit various status signals, including a counting error signal indicating insufficient dispensing of balls or an abnormality occurring in the ball counting sensor 19b, and a dispensing completion signal indicating that dispensing operation has been completed. Based on these status signals, the main control unit 20 determines the open state of the front frame 2 (door open error), whether the payout operation of the game ball payout device 19 is normal (out of supply error), and whether the upper tray 9 is open or not. Monitor the full state (ball clogging error), etc.

Furthermore, a firing control board 28 is connected to the payout control board 29, and is capable of transmitting a permission signal for permitting firing to the firing control board 28. The firing control board 28 controls the energization of a firing solenoid (not shown) provided in the firing device 32 based on the output of the permission signal from the dispensing control board 29, and controls the operation of the firing operation handle 15. This realizes the firing action of the game ball. Specifically, the firing permission signal is output from the payout control board 29 (fire permission signal ON state), and the touch sensor (not shown) provided on the firing operation handle 15 indicates that the player touches the handle. The firing operation of the game ball is permitted on the condition that the firing operation handle 15 is detected as being in the position of the ball, and that the firing stop switch (not shown) provided on the firing operation handle 15 is not operated. Therefore, when the firing permission signal is not output (firing permission signal OFF state), no firing operation is performed even if the firing operation handle 15 is operated, and the game ball is not fired. Further, the strength with which the game ball is launched can be changed according to the amount of operation of the firing operation handle 15.
Note that when the payout control board 29 detects the ball clogging error, it transmits a ball clogging signal to the main control unit 20 and stops outputting the firing permission signal to the firing control board 28 (firing permission signal OFF), and the upper tray 9 Control is performed to stop the launch operation until the full state is resolved.
Further, the payout control board 29 outputs a firing permission signal to the firing control board 28 on the condition that firing permission is instructed by the main control unit 20.

Here, the main control section 20 is connected to a setting key switch 94 and a RAM clear switch 98, and is capable of receiving detection signals from these switches.

The RAM clear switch 98 is, for example, a push button type switch for inputting an instruction to initialize a predetermined area of the RAM 20c.
The setting key switch 94 is a key switch for switching to a setting change mode (when an ON operation is performed) by inserting a setting key owned by a hall staff and operating the ON/OFF operation when the power is turned on.
Here, the setting change mode is a mode in which the setting value Ve can be changed. The set value Ve is a value representing the level of probability of winning a game state advantageous to the player.

The RAM clear switch 98 is turned on/off in response to the operation of a RAM clear button that is operable with the front frame 2 open. Further, the setting key switch 98 is provided with a corresponding key cylinder into which the above-mentioned setting key can be inserted and removed, and is turned on and off when the setting key inserted into the key cylinder is rotated in the forward direction. It is turned OFF by being rotated in the opposite direction from the ON state. The key cylinder is provided so that it can be operated by inserting a setting key when the front frame 2 is open. Note that the key cylinder functions as an operator that can be operated by inserting a setting key.

In this example, the above-mentioned RAM clear button is also used for changing the set value Ve. Specifically, the RAM clear button also functions as an operator for sequentially advancing the set value Ve.

The RAM clear switch 98 and the setting key switch 94 are provided at appropriate locations inside the gaming machine 1. For example, it is placed on the main control board 20.

Further, a setting/performance display device 97 is connected to the main control section 20 .
The setting/performance display 97 is configured with, for example, a 7-segment display, and functions as a display means capable of displaying a setting value Ve and performance information (described later). The setting/performance display 97 is mounted, for example, on the main control unit (main control board) 20 at an easily visible position.
The main control unit 20 is capable of transmitting a control signal for displaying the setting value Ve and performance information to the setting/performance display 97.

Here, the setting value Ve mainly defines the lottery probability (winning probability) of at least a jackpot (a winning type that causes a condition device described below to operate) in stages (for example, six stages of settings 1 to 6). The higher the setting value Ve, the higher the winning probability (setting 1 is the lowest winning probability, and from then on, the winning probability increases in ascending order of the setting value), which works in the player's favor. There is. In other words, the higher the set value Ve is, the higher the so-called "machine discount (ball payout rate, payout rate)" becomes, which is advantageous to the player.
In this way, the set value Ve is a value that defines the probability of winning a jackpot, a machine discount, etc., and it means a value for a grade related to the likelihood of occurrence of a specific event such as a profit state that affects the player. , in this embodiment, the advantage of the game is defined according to each set value Ve.

In this example, it is assumed that there are six stages (stages of advantageousness) of the setting value Ve that can be used according to the rules. Specifically, it is assumed that the legally usable range of the set value Ve (hereinafter referred to as "usable range Re") is in the range of "1" to "6".
Under this premise, the pachinko gaming machine 1 of this example uses only some of the setting values Ve that can be used according to the rules. Specifically, the pachinko game machine 1 of this example uses only three values, for example, "1", "2", and "6" among the set values Ve within the usable range Re, "1" to "6". do. In other words, the specification limits the probability of winning to three stages instead of six, which is the maximum according to the rules.
Below, the range of setting values Ve actually used in the pachinko game machine 1, specifically the range of setting values Ve actually used among the setting values Ve within the usable range Re (in the above example, "1 ”, “2”, and “6”) is expressed as “usage range Ru”.

The set value Ve is set exclusively by hall staff such as hall clerks based on the business strategy of the hall (gaming parlor). In addition, when there are multiple types of jackpots, the winning probability of which jackpot is changed according to the set value Ve, and the type of jackpot to be targeted can be determined as appropriate. For example, if there are three types of jackpots, jackpots 1 to 3, the higher the set value Ve is, the higher the winning probability for all jackpots 1 to 3 may be. The total winning probability may be increased. Furthermore, the probability of winning some jackpots may be increased. For example, only the probability of winning for jackpots 1 and 2 may be increased, and the probability of winning for jackpot 3 may be set to a constant value with all set values Ve.

(About changing settings)

In order to change the set value Ve, in this example, with the power of the gaming machine 1 turned off and the front frame 2 released, the setting key switch 94 is turned on (operated to the setting change mode side), and While the RAM clear button is pressed (RAM clear switch 98 is ON), power is turned on to the gaming machine 1. Then, the current set value Ve is displayed on the setting/performance display 97, and a transition is made to the "setting change mode" in which the set value Ve (1, 2, 6 in this example) can be changed.

In this example, the determination as to whether or not to shift to the setting change mode is made in the main control side main processing described later (see step S104 in FIG. 5). When the above operating conditions for transitioning to the setting change mode are satisfied, processing for changing the settings is executed accordingly.

After transitioning to the setting change mode, when the RAM clear button that functions as a change operator for the setting value Ve is turned on, the current display value of the setting/performance display 97 changes from 1→2→6→1→ 2→6→...'' within the usage range Ru. When the setting key switch 94 is turned off when the desired setting value Ve is reached, the setting value Ve is determined, and information about the determined setting value Ve is stored (memorized) in a predetermined area of the RAM 20c.
Furthermore, when the setting key switch 94 is turned off, the setting change mode is ended and the display on the setting/performance display 97 is cleared.
When the setting change mode ends, the state shifts to a state where game progress is allowed.

(About performance display)

The main control unit 20 is capable of transmitting a control signal for displaying predetermined performance information on the setting/performance display 97.
Performance information is information that pachinko halls and related agencies want to confirm, and typical examples include information regarding the presence or absence of fraudulent prize balls such as excessive prize balls for gaming machine 1, and the original ball output performance of gaming machine 1. It is. Therefore, the performance information itself is information that is not directly related to the progress of the game itself when the player plays the game, unlike preview effects and the like.

Therefore, the settings/performance display 97 is connected to the inside of the gaming machine 1, for example, the main control section (main control board) 20, the payout control board 29, the firing control board 28, the relay board, the production control section (production control board (liquid crystal The display information is provided at a position where the display information can be viewed when the front frame 2 is in an open state, such as on the control board (including the control board) 24 or the board case (a protective cover that protects the board).

Here, the following information can be specifically adopted as the performance information.

(1) The total number of balls paid out due to winnings during a specific state (total number of prize balls during a specific state: Information (specific ratio information) based on the value (α/β) divided by the number of pieces (β pieces) can be employed as the performance information.
The above-mentioned "total number of paid out balls" refers to the total value of game balls (prize balls) that are paid out when winning in the winning openings (upper starting opening 34, lower opening opening 35, general winning opening 43, big winning opening 50). It is. In the case of this embodiment, there are three upper starting holes 34 or lower starting holes 35, 13 big winning holes 50, and 10 general winning holes 43.
Further, which state to adopt as the specific state can be determined as appropriate depending on the state under which performance information is desired to be grasped. In the case of this embodiment, any state among the normal state, potential state, time saving state, variable probability state, and jackpot game can be adopted. Furthermore, multiple types of states may be measured. For example, the normal state, variable probability state, all gaming states except during winning games, etc., and the types to be measured can be determined as appropriate.
Further, as the period in the specific state, a period in which the jackpot lottery probability is either low probability state or high probability state may be adopted.
Alternatively, the total number of payouts may be determined by excluding one or more specific winning holes from the measurement target (total number of payouts excluding specific winning holes). For example, the total number of payouts may be determined by excluding the big winning hole 50 from the measurement target among the winning holes.

(2) Alternatively, only one of the total number of paid out balls, the total number of paid out balls excluding specific winning holes, and the total number of out pitches may be measured, and the measurement result may be used as performance information.

In this embodiment, the total number of pitches put out during the normal state (number of pitches put out at normal time) and the total number of out pitches during the normal state (number of pitches out at normal time) are measured in real time, and the number of pitches put out at normal time is calculated as the number of pitches out at normal time. The value obtained by multiplying the value divided by 100 by 100 (the value calculated as the number of pieces paid out during normal times÷ the number of pieces out during normal times×100) is displayed as performance information (hereinafter referred to as "normal time ratio information"). Note that the displayed value at this time is a value rounded off to the first decimal place.
Therefore, each data of the number of balls paid out during normal time, the number of out balls during normal time, and the normal time ratio information is stored in the corresponding areas of the RAM 20c (the storage area for the total number of prize balls during the specified period, the storage area for the number of out balls during the specified period, and the storage area for the specified ratio information), respectively. It is designed to be stored (memorized). However, rather than simply permanently measuring and displaying performance information, the measurement is temporarily terminated when the total number of out pitches reaches a predetermined prescribed number (for example, 60,000). This prescribed number is not the total number of out pitches in the normal state, but the total number of out pitches during all game states (including during winning games) (hereinafter referred to as "all state out number"). This total state out number is also measured in real time and stored in the corresponding area (all state out number storage area) of the RAM 20c. Hereinafter, for convenience of explanation, the storage area for the total number of awarded pitches during the specific period, the storage area for the number of outs during the specific period, the specific ratio information storage area, and the storage area for the number of outs in all states will be abbreviated as the "measurement information storage area."

Then, the normal time ratio information at the time of completion is stored in a predetermined area (performance display storage area) of the RAM 20c (the current normal time ratio information is stored), and then the measurement information storage area (normal time payout number, normal time out number and the number of out pitches in all states), then start counting again (start measuring the number of pitches paid out in normal times, the number of out pitches in normal times, the normal time ratio information, and the number of out pitches in all states). The setting/performance display 97 displays the previous normal time ratio information (measurement history information) and the normal time ratio information currently being measured. In addition, it is possible to display not only the previous information but also the history of the time before the last time or the time before that (three times ago), and it is possible to appropriately determine how many times before the information is to be displayed.

Here, in the case of this example, the setting value Ve and performance information are alternatively displayed on the setting/performance display 97. Specifically, in this example, setting changes and setting confirmation are performed only at startup when the power is turned on, so settings and settings are changed in response to the transition to the setting change mode or setting confirmation mode after the power is turned on. The setting value Ve is displayed on the performance display 97, and after setting changes and setting confirmations are completed, performance information is displayed.
Note that the configuration is not limited to displaying the setting value Ve and the performance information on a common display, but a configuration in which the set value Ve and performance information are displayed on separate displays may also be adopted. In that case, the setting value Ve and performance information may be displayed in parallel.

(Production control command)

The main control unit 20 is capable of transmitting various performance control commands including information regarding the special symbol variation display game, information regarding errors, etc. to the performance control unit 24 depending on the processing state. However, in order to prevent fraud such as cheating, the main control section 20 only transmits signals to the production control section 24, and has a one-way communication configuration in which it is not possible to receive signals from the production control section 24. It has become.

Here, the production control command defines the function with a 2-byte structure consisting of a 1-byte length mode (MODE) and a 1-byte length event (EVENT), and in order to distinguish between MODE and EVENT, Bit 7 is ON, and Bit 7 of EVENT is OFF. When transmitting this information as valid information, a strobe signal is output corresponding to each of the mode (MODE) and event (EVENT). That is, when there is a command to be transmitted, the CPU 20a (main control CPU) sets and outputs mode (MODE) information for transmitting the command to the production control unit 24, and after a predetermined period of time has elapsed from this setting, the CPU 20a (main control CPU) transmits the command for the first time. The strobe signal is transmitted. Furthermore, event information is set and output after a predetermined time has elapsed since the strobe signal was transmitted, and a second strobe signal is transmitted after a predetermined time has elapsed from this setting. The strobe signal is controlled to be active by the CPU 20a for a predetermined period to ensure that the CPU 24a (performance control CPU) can receive commands.

[2-2. Performance control section]

The performance control unit 24 is equipped with a microprocessor with a built-in CPU 24a (performance control CPU), a ROM 24b (performance control ROM) that stores performance data required for performance control processing, and a RAM 24c (functioning as a work area and buffer memory). It is mainly composed of a microcomputer equipped with a production control RAM), and is also equipped with an audio control section (sound source IC), an RTC (Real Time Clock) function section, a counter circuit, an interrupt controller circuit, a reset circuit, a WDT circuit, etc. and controls the overall production operations.

The performance control CPU 24a performs arithmetic processing for various performance operations and controls each performance means based on the performance control program and the performance control commands received from the main control unit 50. In the case of the pachinko game machine 1 of this embodiment, the presentation means include the liquid crystal display device 36 (main liquid crystal display device 36M, sub liquid crystal display device 36S), optical display device 45a, sound generator 46a, and a movable device not shown in the drawings. It becomes a physical object.

The production control ROM 24b stores a control program for production operations by the production control CPU 24a and various data necessary for production operation control.
The performance control RAM 24c is used as a work area used by the performance control CPU 24a for various calculation processes, a table data area, a buffer area for various input/output data, processing data, and the like.
Note that the arithmetic control section 24 may have a configuration in which a 1-chip microcomputer and its peripheral circuits are mounted, but various configurations of the production control section 24 are possible. For example, in addition to the microcomputer, an interface circuit with each part, a random number generation circuit that generates random numbers for lottery for performances, a CTC for various time counting, a watchdog timer (WDT) circuit, and an interrupt signal to the performance control CPU 24a. In some cases, an interrupt controller circuit or the like is provided.

The main roles of the production control unit 24 are receiving production control commands from the main control unit 20, selecting and deciding production based on the production control commands, controlling the display of the liquid crystal display device 36 (supplying display data), and controlling the sound generation device 46a. This includes audio output control of the optical display device 45a (LED), operation control of the movable accessory (drive control of the movable accessory motor 80c), and the like.

Since this production control section 24 also has a function as a control device for the liquid crystal display device 36, the production control section 24 also has functions as a so-called VDP (Video Display Processor), image ROM, and VRAM (Video RAM). The production control CPU 24a also functions as a liquid crystal control section.
VDP refers to a function that controls overall video output processing such as image development processing and image drawing.
The image ROM refers to a memory in which image data (effect image data) on which the VDP performs image development processing is stored.
The VRAM is an image memory area that temporarily stores image data developed by the VDP.

With these configurations, the production control section 24 generates various image data based on commands from the main control section 20, and outputs it to the main liquid crystal display device 36M and the sub liquid crystal display device 36S. As a result, various effects images are displayed on the main liquid crystal display device 36M and the sub liquid crystal display device 36S.

Further, the production control section 24 has a sound control section (sound controller: sound source IC) for the sound generation device 46a including the speaker 46, and the sound signal outputted by the sound control section is amplified by the amplifier section 46d and outputted from the speaker 46. is supplied to
The production control unit 24 also includes a lamp driver unit 45d that functions as a light display control unit for a light display device 45a including a decorative lamp 45 and various LEDs, and a movable object motor that operates a movable body (not shown). A motor driver section 80d (motor drive circuit) functioning as a drive control section for 80c is connected. The effect control section 24 instructs the lamp driver section 45d and the motor driver section 80d to control the light display operation by the optical display device 45a and the operation of the movable object motor 80c.

The production control unit 24 is also connected to an origin switch 81 and a position detection sensor 82 for monitoring the operation of the movable accessory.
The origin switch 81 is composed of, for example, a photo interrupter, and detects whether or not the movable accessory motor 80c is at the origin position. The origin position is, for example, a position where the movable body is not normally exposed on the board surface in FIG. 2. The performance control unit 24 is capable of determining whether or not the movable accessory motor 80c is at the origin position based on the detection information of the origin switch 81.
Furthermore, the performance control unit 24 controls the operation mode of the movable accessory while monitoring the current operation position (for example, the amount of movement from the origin position) based on the detection information from the position detection sensor 82. Further, the performance control section 24 monitors malfunctions in the operation of the movable accessory based on the detection information from the position detection sensor 82, and if any malfunctions occur, they are detected as errors.

Further, to the production control unit 24, switches for the production button 13, the cross key 15a, and the decision button 15b shown as the operation unit 17 in the figure, that is, the operation detection switches for the production button 13, the cross key 15a, and the decision button 15b are connected, The performance control unit 24 is capable of receiving operation detection signals from the performance button 13, cross key 15a, and determination button 15b, respectively.

Furthermore, the performance control unit 24 is provided with a handle sensor 83 (touch sensor) for detecting whether or not the operation handle 15 shown in FIG. 1 is being touched by a user such as a player. The performance control unit 24 is able to determine whether or not the operating handle 15 is touched by the user based on the detection information of the handle sensor 83.

Based on the performance control command sent from the main control unit 20, the performance control unit 24 selects (determines) a performance pattern by lottery or uniquely from a plurality of types of performance patterns prepared in advance, and Various presentation means are controlled at the right timing to bring out the desired presentation. As a result, it is possible to display a performance image on the liquid crystal display device 36 corresponding to the performance pattern, play sound from the speaker 46, and drive the decorative lamps 45 and LEDs to turn on and off. A ``performance scenario'' in a broad sense is realized by chronologically unfolding the preview performances, etc.).

Here, regarding the production control command, the production control unit 24 (CPU 24a) generates an interrupt process based on the input of the above-mentioned strobe signal transmitted by the main control unit 20 (CPU 20a), and receives and analyzes the command. Specifically, the CPU 24a executes a control program for command reception interrupt processing based on the input of the strobe signal described above, and in the interrupt processing realized thereby, acquires a production control command and analyzes the command contents. conduct.
At this time, if an interrupt occurs based on the input of the strobe signal, the CPU 24a performs the processing even if an interrupt process based on another interrupt (timer interrupt process executed periodically) is being executed. The command reception interrupt processing is performed by interrupting the command reception interrupt, and even if other interrupts occur at the same time, the command reception interrupt processing is performed with priority.

<3. Overview of operation>
[3-1. Symbol fluctuation display game]

Next, an overview of the gaming operation of the gaming machine 1 realized by the control configuration as described above (FIG. 3) will be explained.
First, the symbol variation display game will be explained.

(Special symbol fluctuation display game)

In the gaming machine 1 of the present embodiment, the main control unit 20 operates based on a predetermined starting condition, specifically, the game ball enters the upper starting port 34 or the lower starting port 35 (winning). A "jackpot lottery" will be held by random number lottery. The main control unit 20 causes the special symbol display devices 38a and 38b to variably display special symbol 1 and special symbol 2 based on the lottery result to start a special symbol variation display game, and after a predetermined period of time has elapsed, The symbols are derived and displayed on the symbol display device, thereby ending the special symbol variation display game.

Here, in this embodiment, the jackpot lottery based on winnings in the upper starting slot 34 and the jackpot lottery based on winnings in the lower starting slot 35 are performed separately and independently. Therefore, the jackpot lottery result regarding the upper starting opening 34 is derived on the special symbol display device 38a side, and the jackpot lottery result regarding the lower starting opening 35 is derived on the special symbol displaying device 38b side. Specifically, on the special symbol display device 38a side, on the condition that a game ball enters the upper starting port 34, a first special symbol variable display game is started by displaying the special symbol 1 in a variable manner, On the other hand, on the special symbol display device 38b side, on the condition that the game ball enters the lower starting port 35, the special symbol 2 is displayed in a variable manner and a second special symbol variable display game is started. ing. Then, when the special symbol variation display game on the special symbol display device 38a or the special symbol display device 38b is started, after a predetermined variation display time has elapsed, if the jackpot lottery result is "jackpot", a predetermined "jackpot" is displayed. In other cases, the special symbol being displayed in a variable manner is stopped and displayed in a predetermined "miss" manner, thereby deriving the game result (jackpot lottery result).

In this specification, for convenience of explanation, the first special symbol variation display game on the special symbol display device 38a side is referred to as "special symbol variation display game 1", and the second special symbol on the special symbol display device 38b side is referred to as "special symbol variation display game 1". The variable display game will be referred to as "special symbol variable display game 2." In addition, unless otherwise necessary, "Special Symbol 1" and "Special Symbol 2" will simply be referred to as "Special Symbol" (sometimes abbreviated as "Special Symbol"), and "Special Symbol Variation Display Game 1" and ""Special symbol variation display game 2" is simply referred to as "special symbol variation display game."

(Decorative pattern variable display game)

Further, when the above-mentioned special symbol variable display game is started, the decorative symbol variable display game is started by variably displaying decorative symbols (ornamental game symbols) on the main liquid crystal display device 36M. Various performances will be held in conjunction with the event. When the special symbol variable display game ends, the decorative symbol variable display game also ends, a predetermined special symbol indicating the jackpot lottery result is displayed on the special symbol display device, and the jackpot lottery result is reflected on the main liquid crystal display device 36M. The decorative patterns that have been created are now derived and displayed. That is, the result of the special symbol variation display game is reflected and displayed by a decorative symbol variation display game that includes a decorative symbol variation display operation.

Therefore, for example, when the result of the special symbol variation display game is a "jackpot" (when the jackpot lottery result is a "jackpot"), an effect that reflects the result is developed in the decorative symbol variation display game. Then, in the special symbol display device, when the special symbol is stopped and displayed in a display mode indicating a jackpot (for example, 7 segments is displayed as "7"), "left", "middle", " In each display area of ``Right'', the decorative pattern reflects the ``jackpot'' (for example, in each display area of ``Left'', ``Middle'', and ``Right'', 3 decorative patterns are displayed as ``7'', ``7'', and ``7''). 7" display state).

When this "jackpot" occurs, specifically, the special symbol variation display game ends, the decorative symbol variation display game ends accordingly, and as a result, the "jackpot" symbol mode is derived and displayed. After that, the big winning hole solenoid 52c of the special variable winning device 52 is activated and the opening door 52b opens and closes in a predetermined pattern, thereby opening and closing the big winning hole 50, which is more advantageous to the player than in the normal gaming state. A special game state (jackpot game) occurs. In this jackpot game, the opening door 52b allows the jackpot to be opened until a predetermined time (maximum opening time: for example, 29.8 seconds) has elapsed or the number of game balls that have entered the jackpot (big jack 50 winning balls) is a predetermined number (maximum number of winning balls: the upper limit of the number of winning balls allowed for a winning opening whose entrance is opened or expanded by one activation of the accessory: for example, 9) A "round game" in which the winning area is opened or expanded until the winning area is reached, and the big winning opening is closed when any of these conditions is met, is played for a predetermined number of rounds (for example, up to 16 rounds). round) repeated.

When the jackpot game starts, an opening performance is first performed to notify that the jackpot has started, and after the opening performance ends, a round game is performed a plurality of times up to a predetermined number of rounds as an upper limit. After the specified number of rounds is completed, an ending effect is performed to notify that the jackpot has ended, thereby ending the jackpot game.

Regarding the information necessary to execute the above-mentioned decorative symbol variation display game, first, the main control unit 20 specifically determines the information based on the fact that a game ball has entered the upper starting hole 34 or the lower starting hole 35 (winning). , on the condition that the game ball is detected by the upper starting port sensor 34a or the lower starting port sensor 35a and the starting condition (starting condition regarding special symbols) is met, a lottery is performed to determine whether it is a "jackpot" or "miss". 'Win/Low Lottery (Win Type Lottery)' and 'Symbol Lottery (Win Type (Win Type) Lottery)' where the jackpot type is drawn if it is a 'jackpot', and the losing type if it is a 'loss'. )' (If there is only one type of loss, it is not necessary to perform a type lottery for the loss, so that lottery may be omitted), and based on the lottery result information, the fluctuation pattern of the special symbol Also, a special symbol to be finally stopped and displayed (hereinafter referred to as "special stop symbol") is determined according to the winning type.
Then, the main control unit 20 sends a "variation pattern designation command" that includes at least special symbol variation pattern information (for example, information regarding the jackpot lottery result and special symbol variation time, etc.) as a performance control command that specifies the processing state. It is transmitted to the production control section 24 side. As a result, basic information required for the decorative symbol variation display game is sent to the performance control section 24. In this embodiment, in order to provide a rich variety of performances, a "decorative symbol designation command" including information on special stop symbols (symbol lottery result information (information regarding hit type)) is also transmitted to the production control unit 24. It looks like this.

The above-mentioned special symbol variation pattern information can include information specifying whether or not a specific advance notice effect (for example, a "reach effect" or a "pseudo-continuous effect" to be described later) will occur. To be more specific, the special symbol variation patterns are roughly divided into a "winning variation pattern" in the case of a hit and a "loss variation pattern" in the case of a loss, depending on the jackpot lottery result. These fluctuation patterns include, for example, a 'reach fluctuation pattern' that specifies the occurrence of a reach effect, which will be described later, a 'normal fluctuation pattern' that does not specify the occurrence of a reach effect, and the occurrence (overlapping occurrence) of a pseudo-continuous effect and a reach effect. A plurality of types of variation patterns are included, such as a ``reach variation pattern with pseudo-coupling'' that specifies, and a ``normal variation pattern with pseudo-coupling'' that specifies the occurrence of a pseudo-coupling effect but not specifying the occurrence of a reach effect. In addition, in order to secure the production time for the ready-to-reach effect and the pseudo-continuous effect, the variation time is usually set longer for the variation pattern that specifies the ready-to-reach effect or the pseudo-continuous effect than for the normal variation pattern.

The production control unit 24 performs time-series display during the decorative pattern variation display game based on information included in the production control commands (here, the variation pattern specification command and the decorative pattern specification command) sent from the main control unit 20. The content of the performance to be developed (performance scenario such as a preview performance) and the decorative pattern to be finally displayed (decorative stop pattern) are determined, and the decorative pattern is displayed in a variable manner according to the time schedule based on the variation pattern of the special symbol. A symbol variation display game is executed. As a result, the decorative symbols on the main liquid crystal display device 36M are displayed in a variable manner in synchronization with the variable display of the special symbols on the special symbol display devices 38a and 38b, and the period of the special symbol variable display game and the decorative symbol variable display game are changed. The middle period has substantially the same time width. In addition, the performance control unit 24 controls the main liquid crystal display device 36M, the optical display device 45a, or the sound generator 46a, respectively, so as to correspond to the performance scenario, and develops various performances in the decorative symbol variation display game. Thereby, the reproduction of images (image production) on the main liquid crystal display device 36M, the reproduction of sound effects (sound production), and the lighting and blinking driving of the decorative lamps 45, LEDs, etc. (light production) are realized.

In this way, the special symbol variation display game and the decorative symbol variation display game have an inseparable relationship, and the display results of the special symbol variation display game are reflected in the decorative symbol variation display game. , these two symbol variation display games may be regarded as equivalent symbol games. In this specification, the above two symbol variation display games may be simply referred to as "symbol variation display games" unless otherwise necessary.

(Normal symbol fluctuation display game)

Furthermore, in the gaming machine 1, based on the fact that a game ball has passed through the normal symbol starting port 37 (winning), the main control unit 20 performs an "assistance winning lottery" by random number lottery. Based on this lottery result, a normal symbol fluctuation display game is started by variably displaying the normal symbols expressed by the LED on the normal symbol display device 39a, and after a certain period of time has passed, the result is changed to a combination of LED lighting and non-lighting. It is designed to stop and display. For example, when the result of the normal symbol fluctuation display game is "assistance hit", the display section of the normal symbol display device 39a is set to a specific lighting state (for example, all two LEDs 39 are lit, or "○" and " Among the LEDs representing "×", the LED on the "○" side is displayed in a stopped state (in a lit state).

When this "assistance hit" occurs, the normal electric accessory solenoid 41c (see Fig. 3) is activated, which causes the movable blade 47 to open in an inverted "C" shape and the lower starting port 35 to open. Alternatively, the game ball is enlarged and enters a state where it is easy to enter (starting mouth open state), and an auxiliary game state (hereinafter referred to as "normal power open game") that is more advantageous to the player than the normal game state occurs. In this normal power open game, the movable wing piece 47 of the normal variable prize winning device 41 is used to open the lower starting port 35 until a predetermined time (for example, 0.2 seconds) elapses, or the game in which the lower starting port 35 wins The winning area is opened or expanded until the number of balls reaches a predetermined number (for example, 4 balls), and when any of these conditions is met, the lower starting port 35 is closed. (twice) is repeated.

(About suspension)

Here, in this embodiment, during the special/decorative symbol variation display game, the normal symbol variation display game, the jackpot game, the normal power release game, etc., the upper starting port 34, the lower starting port 35, or the normal symbol starting port 37 is used. When a winning occurs, that is, when a detection signal is input from the upper starting opening sensor 34a, the lower starting opening sensor 35a, or the normal symbol starting opening sensor 37a, and the corresponding starting condition (symbol game starting condition) is satisfied, This data is stored as data related to the right to start the variable display game, except for data related to the variable display, up to a predetermined upper limit, which is the maximum number of pending memories (for example, a maximum of 4). The pending pending data that has not been subjected to this symbol variation display operation, or the game ball related to the pending data, is also referred to as an "operation pending ball." In order to make it clear to the player the number of balls on hold, a dedicated hold display (not shown) provided at a suitable location on the gaming machine 1 or a liquid crystal display device 36 (main liquid crystal display device 36M or sub-liquid crystal display device 36S) lights up the hold indicator provided as an icon image on the screen.

Further, in this embodiment, up to four operation hold balls related to the special symbol 1, the special symbol 2, and the normal symbol are each stored in the corresponding storage area of the RAM 20c, and are reserved as the number of confirmed fluctuations of the special symbol or the normal symbol. In addition, the maximum number of stored balls (maximum number of reserved balls) regarding the special symbol 1, special symbol 2, and normal symbol is not particularly limited. Further, all or a part of the maximum number of reserved storage numbers for each symbol may be different, and the number can be determined as appropriate depending on the gaming nature.

[3-2. Game state]

The gaming machine 1 according to the present embodiment is configured to be able to generate a plurality of types of gaming states in addition to the above-mentioned jackpot, which is a special gaming state. In order to facilitate understanding of this embodiment, various game states will first be explained.

The gaming machine 1 of this embodiment is configured to be able to execute and control at least four types of gaming states: a normal state, a time saving state, a potential state, and a variable probability state. These game states are distinguished by the jackpot lottery probability state (low probability state, high probability state), the presence or absence of the electric chew support state (bonus game) (with electric support, without electric support), etc.

"Electric Chew Support State" means that the opening operation period of the movable wing piece 47 of the normal variable prize winning device 41 in the normal electricity open game (at least one of the opening time of the movable wing piece 47 and the number of openings thereof) is in the normal state. Refers to the ``open extension state'' that is extended beyond the . When the open extension state occurs, the opening operation period of the movable blade 47 is extended from, for example, 0.2 seconds in the normal time (under the non-open extension state) to 1.7 seconds, and the number of opening and closing operations is increased, for example, This will be extended from the usual one time to two or three times.
In the case of this embodiment, under the electric chew support state, the lottery probability of winning the support changes from a low probability (for example, 1/256) to a high probability (for example, 255/256) of the predetermined probability (normal probability). At the same time, a 'normal symbol time reduction state' occurs that shortens the average time required for one normal symbol variable display game (normal symbol variable display operation time) (for example, from 10 seconds (reduced to 1 second). Therefore, when the electric chew support state occurs, the normal power release game occurs frequently, resulting in an operation rate improved state (high base state) in which the operation rate of the movable wing piece 47 per unit time is higher than in the normal state. Hereinafter, the state under electric support support will be abbreviated as "with electric support", and the case without electric support will be abbreviated as "without electric support".

In this embodiment, the "normal state" means that the jackpot lottery probability is a low probability (for example, 1/399) of the predetermined probability (normal probability), and the gaming state without electric support (low probability + no electric support). To tell.

"Time-saving state" means that the jackpot lottery probability is as low as in the normal state, but the average time required for one special symbol fluctuation display game (special symbol fluctuation display operation time) is longer than the normal state. It refers to a gaming state in which a 'special symbol time saving state' in which the time is shortened also occurs and the electric chew support state occurs. In other words, during the time saving state, it becomes "low probability + electric support available + special symbol time saving state".

"Potential probability state" is a 'special symbol probability variable state' in which the jackpot lottery probability has changed to a high probability (for example, 1 in 39.9) that is higher than the low probability mentioned above, and a gaming state without electric support (high probability state). probability + no electric support).

The "variable probability state" refers to a gaming state in which the jackpot lottery probability is as high as the probability state, but a special symbol time saving state and an electric chew support state occur. In other words, during the probability change state, it becomes "high probability + electric support available + special symbol time saving state".

Regarding the gaming state, if we focus on the jackpot lottery probability, if the gaming state is "normal state" or "time saving state", at least the jackpot lottery probability will be "low probability state", and if the gaming state is "potential state" or "probable variable state" If the state is 'state', at least the jackpot lottery probability is 'high probability state'. During the jackpot, a jackpot game in which the jackpot is opened and closed occurs, but the jackpot lottery probability and the presence or absence of electric support are the same as the normal state, with a low probability and no electric support.

[3-3. About the hit]

Next, "winning" in the gaming machine 1 will be explained.
In the gaming machine 1 of this embodiment, a jackpot lottery (win lottery) is performed for a plurality of types of wins. In the case of this example, the winning types include each jackpot belonging to the jackpot types, such as "normal 4R", "normal 6R", "probable variable 6R", and "probable variable 10R".
Note that the above notation "R" means the specified number of rounds (maximum number of rounds).

The jackpot type is a hit that triggers the operation of the conditional device. Here, the "condition device" is a device whose operation is a necessary condition for the operation of the accessory continuous operation device for playing a round game, and a specific combination of special symbols is displayed or a game ball is displayed. This refers to something that activates when passing through a specific area within the grand prize opening.

The above probability variable state ends the high probability state and shifts to a low probability state when the special symbol variation display game has been executed a predetermined number of times (for example, 70 times: the specified ST number) without winning the jackpot type. This is a so-called "time-limiting definite change machine (ST machine)", and when the specified ST number ends, the game returns to the normal state from the next game. However, it may also be a "general probability changing machine" that continues until the next jackpot is won.
The number of executions of the special symbol variation display game may be the total number of executions of the special symbol variation display game 1 and the special symbol variation display game 2 (the total number of variations of the special symbol 1 and special symbol 2), It may be the number of executions of either one (for example, the number of executions of the special symbol variation display game 2). Furthermore, the number of time-saving states is not limited to 60 or 100, but can be determined as appropriate depending on the gameplay. Furthermore, there is no particular restriction on what kind of hit to provide, and it can be determined as appropriate.

Here, in this example, there are a plurality of types of "losses" as well as jackpot types. Specifically, three types of deviations are provided: "missing 1", "missing 2", and "missing 3".
As described above, if the result of the winning/losing lottery is "losing", a lottery of the losing type is performed in the symbol lottery.

[3-4. About the production]
(Production mode)

Next, the performance mode (performance state) will be explained. The gaming machine 1 of this embodiment is provided with a plurality of types of performance modes for presenting performances related to the gaming state, and is configured to be able to switch between the performance modes. Specifically, a normal performance mode, a time-saving performance mode, a probability performance mode, and a probability variable performance mode are provided, each corresponding to a normal state, a time-saving state, a probability state, and a probability-variable state. In each production mode, the background display as the background of the fluctuating display screen of decorative symbols is displayed with a different background effect, so that the player can understand what kind of gaming state he or she is currently in. It has become.

The performance control unit 24 (CPU 24a) has a functional unit (performance state transition control means) that controls transition between multiple types of performance modes. The production control unit 24 (CPU 24a) responds to a specific production control command sent from the main control unit 20 (CPU 20a), specifically, a production control command that includes gaming state information managed on the main control unit 20 side. Based on this, the current gaming state is grasped in a manner that maintains consistency with the gaming state managed by the main control unit 20 side, and the system is configured to be able to control transition between a plurality of types of performance modes. Examples of the above-mentioned specific performance control commands include a variation pattern designation command, a decorative symbol designation command, and a game state designation command sent when a change occurs in the game state.

(Preview performance)

Next, the preview performance will be explained. The performance control unit 24 performs various operations related to the current performance mode and the jackpot lottery result based on the content of the performance control command from the main control unit 20, specifically, at least the fluctuation pattern information included in the fluctuation pattern designation command. It is configured to be able to control the appearance of "notice effects". This kind of preview performance is used as a "stimulation performance" to suggest (notice) the level of expectation as to whether or not the winning type has been won (hereinafter referred to as "win expectation level"), and to arouse the player's expectation of winning. work. Typical preview performances include "reach performance,""pseudo-continuationperformance," and even "pre-reading preview performance." The performance control unit 24 functions as a preview performance control means that can control the execution (appearance) of these performances.

"Reach effect" refers to a performance mode that involves a reach state (fluctuating display mode that involves a reach state: reach variation pattern), and specifically, a method that derives and displays the final game result via a reach state. It refers to the style of production. The reach effects include multiple types of reach effects associated with the degree of expectation of winning. For example, there are cases where the expectation of winning is relatively higher than when a normal reach effect appears. This kind of reach performance is called ``super reach performance.'' Many of these "super reaches" have a relatively longer production time (fluctuating time) than normal reaches in order to stimulate expectations of winning. In addition, normal reach and super reach include multiple types of reach effects. In this example, Super Reach includes multiple types of reach effects such as Super Reach 1, 2, 3, and 4, and the winning expectation of Super Reach 1 to 4 is expressed as "Super Reach 1 < Super Reach 2 < Super Reach". The relationship is “Reach 3 < Super Reach 4”.

"Pseudo-continuous performance" refers to a performance mode that involves a pseudo continuous variation display state (pseudo-continuous variation) of decorative symbols. It refers to a variable display mode in which a display operation is repeated one or more times, in which a part or all of a decorative pattern is temporarily stopped, and then the decorative pattern is re-variably displayed from the temporarily stopped state. In this respect, it is different from the later-described "pre-read preview performance (continuous preview performance)" which is developed over multiple symbol change display games. Basically, the occurrence rate (appearance rate) of such "pseudo-links" is determined so that the higher the number of pseudo fluctuations, the higher the expectation of winning.For example, depending on the number of pseudo fluctuations, It is made easier to select performances to arouse expectations such as reach.

"Pre-reading notice effect" (hereinafter sometimes abbreviated as "pre-reading notice" or "pre-reading effect") is, based on the result of pre-reading judgment, before the fluctuation display of the target symbol is performed. It means an effect that alerts you to the possibility of being controlled in an advantageous state. Note that "advantageous state" means a state advantageous to the player.
Specifically, the look-ahead performance in this example mainly displays pending balls (unexploited pending balls) that have not yet been used for the execution of the symbol variation display game (variable display operation of special symbols). It is performed in a presentation manner that can notify the winning expectation in advance before the operation pending ball is used in the symbol variation display game, using the pattern and background effects of the symbol variation display game to be executed first. . In addition, in the symbol variation display game, in addition to the above-mentioned "reach effect", there are various effects such as the so-called "SU (step up) notice effect", "timer notice effect", "resurrection effect", and "premier notice effect". It occurs and is designed to liven up the game content.

Here, with reference to FIG. 4, the "suspended change notice performance" as an example of the above-mentioned pre-read notice performance will be described.
In the case of the gaming machine 1 of this embodiment, the upper display area of the screen of the main liquid crystal display device 36M includes a display area for displaying a decorative symbol variation display game (a display area for displaying a decorative symbol variation display effect and a preview effect). In addition, the display area on the lower side of the screen includes a hold display area 76 (hold display areas a1 to d1) that displays the number of active hold balls on the special symbol 1 side and a special hold display area 76 (hold display areas a1 to d1). A reservation display area 77 (reservation display parts a2 to d2) that displays the number of activated reservation balls on the symbol 2 side is provided. Regarding the presence or absence of an operation pending ball, this fact is notified by a predetermined pending display mode. In Figure 4, the presence or absence of an operation-holding bulb is shown in a lit state (with an operation-holding bulb: "○ (white circle mark)" in the figure) or in an off state (no operation-holding bulb: a broken line circle in the figure). An example is shown in which information regarding the number of pending pitches is reported.

Displays regarding the presence or absence of pending action balls (pending display) are displayed in order of occurrence (order of winning), and in each pending display area 76, 77, the leftmost action pending ball indicates that all actions in the pending display are displayed. It is displayed as the activated suspended ball that occurred first (that is, the oldest) among the suspended balls on the time axis. Further, on the left side of the holding display areas 76 and 77, a fluctuating display area 78 is provided to show the activated holding balls that are currently being used in the special symbol changing display game. In the case of the present embodiment, the changing display area 78 is configured so that an image in which an icon of a game currently being played pending K is displayed on top of the icon of the catch J. That is, when the variable display of the special symbol 1 or the special symbol 2 is started, the icon (icon image) of the oldest pending a1 or a2 displayed in the pending display areas 76 and 77 is changed to the icon (icon image) of the oldest pending K during game execution. As an icon, it moves onto the icon of the catch J in the changing display area 78, and this state is maintained for a predetermined display time.

When a pending ball occurs, the main control unit 20 sends the pre-read judgment information related to the jackpot lottery result and the number of pending balls at the time of the pre-read judgment (the number of pending balls that currently exist, including the currently-occurred pending ball). A "pending addition command" specifying this is sent to the production control unit 24 (see steps S1309 to S1312 in FIG. 28).
In the case of this embodiment, the pending addition command is composed of 2 bytes, and the pending addition command includes data on the upper byte side that makes it possible to specify the number of active pending balls at the time of look-ahead judgment, and the look-ahead judgment information. It consists of lower byte side data.

Here, as understood from the above description, in the present embodiment, based on the occurrence of a winning in the upper starting hole 34 or the lower starting hole 35 and a new held ball, a pre-reading of the held ball is performed. As a determination, a jackpot lottery is performed for the symbol variation display game related to the reserved ball. As will be described later, the main control unit 20 holds and stores information representing the result of the jackpot lottery conducted as such a pre-read determination in the corresponding storage area of the RAM 20c.
The information on the jackpot lottery result obtained during the pre-reading determination is used to select (lottery) a symbol variation pattern in the symbol variation display game, and can be referred to as "variation pattern selection information". Therefore, it can be said that the main control unit 20 performs a pre-read determination and stores the resulting "variation pattern selection information" in a predetermined area of the RAM 20c.

When the effect control unit 24 receives the above-mentioned pending addition command transmitted by the main control unit 20, based on the pre-read determination information included therein, the effect control unit 24 performs a “pre-read preview effect” as part of the display control process related to the above-mentioned pending display. Performs production control processing related to. Specifically, a "pre-read preview lottery" is held to determine whether or not the pre-read preview performance can be executed, and if the lottery is won, the pre-read preview performance is made to appear.

Here, the look-ahead determination information specifically refers to the jackpot lottery result (the jackpot lottery result at the start of fluctuation) executed when the operation-reserved ball is used in the symbol fluctuation display game in the main control unit 20; This is game information obtained by pre-reading and determining the fluctuation pattern at the start of fluctuation. In other words, this information includes at least information that pre-reads and determines the winning/losing lottery results at the start of fluctuation (pre-read winning/losing information), and also includes information that pre-reads and determines the symbol lottery results (pre-read symbol information) and fluctuations at the start of fluctuation. It is possible to include information on which a pattern has been pre-read and determined (pre-read variation pattern information). What kind of information to send the pending addition command to the production control unit 24 can be determined as appropriate depending on the content to be notified in the pre-read notice.
In this example, it is assumed that the pending addition command includes pre-read win/loss information, pre-read symbol information, and pre-read variation pattern information.

In addition, the "pre-read fluctuation pattern" obtained by the pre-read judgment when the action-holding ball occurs does not necessarily have to be the "fluctuation pattern at the start of fluctuation" obtained when the action-holding ball is actually subjected to the fluctuation display operation. There isn't. For example, to describe a typical case where the fluctuation pattern at the start of the fluctuation is a fluctuation pattern that specifies "Super Reach 1", in this case, the content specified by the look-ahead fluctuation pattern is "Super Reach 1". Rather than specifying the type of reach performance itself, it is possible to specify the essential "super reach type".

In the case of the present embodiment, if you win the pre-read preview lottery, the pending icon that is the target of the pre-read preview among the pending icons in the pending display areas a1 to d1 and a2 to d2 will be displayed as a normal hold display, for example. "Pending display change" that can change from white (normal pending display mode) to a pending display (special pending display mode) with blue, green, red, and danger patterns (or special colors and patterns such as rainbow colors) for advance notice. A look-ahead preview performance (also referred to as a "pending change notice") of "Kei" will be performed.
FIG. 4 shows an example in which the hatched operation reservation sphere of the reservation display section b1 has changed to a special reservation display. Here, the display of the pending icon in blue, green, red, and danger pattern means that the expectation of winning is high in this order.In particular, the display of the pending icon with the danger pattern indicates that the expectation of winning the jackpot is extremely high. It is said to be a premium hold icon that will be displayed.

(Direction means)

Various effects on the game machine 1 are produced by effect means provided in the game machine 1. This presentation means may be any stimulus transmission means that can produce a presentation effect by appealing to human senses such as visual, auditory, and tactile senses, and may be a light generating means such as a decorative lamp 45 or an LED device (light display device 45a: light production means), sound generation devices such as the speaker 46 (sound production device 46a: sound production means), production display devices (display means) such as the main liquid crystal display device 36M and the sub liquid crystal display device 36S, and contact with the operator's body. Typical examples include a pressure device that transmits pressure, a wind pressure device that applies wind pressure to the player's body, and a movable accessory that produces a visual performance effect by its operation. Here, the effect display device is a visually appealing display device like the image display device, but differs from the image display device in that it also includes devices that do not rely on images (for example, a 7-segment display). When referred to as an image display device, it mainly refers to a type that displays effects by displaying images, and devices that express effects by other than images, such as a 7-segment display, are included in the concept of effect display device.

<4. Main control unit processing>

Next, the processing performed by the main control unit 20 of this embodiment will be explained. The main control unit 20 processes mainly a predetermined main process (main process on the main control side: FIG. 8) and a timer interrupt process activated by a scheduled interrupt from the CTC (timer interrupt process on the main control side: FIG. 20). It consists of:

[4-1. Main control side main processing]

FIG. 5 is a flowchart showing main control side main processing.
Main processing on the main control side is started when a system reset occurs due to a system reset signal from the power supply board when recovering from a power outage or power failure, or when the watchdog timer function is activated due to a control program running out of control. WDT) is activated and the CPU 20a is forcibly reset (WDT reset). In either case, when the main processing is started, the main control section 20 (CPU 20a) first executes the initial setting processing necessary for starting the gaming operation, such as initializing the values of the registers of each section including the CPU 20a. (Step S101).

(Initial setting process)

FIG. 6 is a flowchart showing the initial setting process in step S101.
In FIG. 6, when the above system reset or WDT reset occurs, the CPU 20a sets itself to an interrupt disabled state in step S201, and then stores the value of the stack pointer in the RAM 20c in the stack area as a stack pointer setting process in step S202. Execute the process to set according to the final address of . Then, in the subsequent step S203, processing is performed to invalidate the RAM protection and invalidate the prohibited area in the function of prohibiting running outside the specified area of the RAM 20c.

Next, in step S204, the CPU 20a executes processing for turning off the security signal, setting value display, and firing permission signal. Here, the security signal is a signal output to the hall computer HC through the frame external centralized terminal board 21, and functions as a signal for notifying the hall computer HC of a status such as a setting change. Setting value display OFF means turning off the display of the setting value Ve on the setting/performance display 97.
The firing permission signal is a signal outputted from the payout control board 29 to the firing control board 28 as described above, and the CPU 20a instructs the payout control board 29 to turn off the firing permission signal.
Here, turning off the security signal and turning off the setting value display are countermeasures against turning on and off the power while changing settings. That is, since there is a possibility that the power was turned off while displaying the set value Ve in the setting change process, the set value display and the security signal are temporarily turned off.

In step S205 following step S204, the CPU 20a executes a power abnormality check process.
As shown in FIG. 7, in the power abnormality check process, the WDT timer is cleared (step S11), and it is determined whether the power abnormality signal is ON (step S12). The power abnormality signal is a signal output from the power supply board, and represents that the power abnormality signal OFF is at a normal level, and represents that the power abnormality signal ON is not at a normal level (that is, abnormal). If the power abnormality signal is ON, the CPU 20a returns to step S101 shown in FIG. 5, and starts the main control side main processing from the beginning. That is, if an abnormality is found in the power supply, the main control side main processing is reset.
If the power supply abnormality signal is not ON, no abnormality is recognized in the power supply, and the CPU 20a ends the power supply abnormality check process.

Returning to FIG. 6, in response to the completion of the power abnormality check process in step S205, the CPU 20a performs various setting processes at the time of startup in step S206. In the setting process in step S206, for example, an interrupt mode setting process for setting a predetermined interrupt mode, an internal hardware random number setting process for activating an internal hardware random number circuit, etc. are executed. Further, in the setting process of step S206, a process of setting an initial value to a predetermined register among the various registers included in the CPU 20a is also performed.

In step S207 following step S206, the CPU 20a sets the activation waiting time of the sub-control board (effect control unit 24). Then, through the processing of steps S208 to S210, it waits for the set activation waiting time to elapse. Specifically, the set startup wait time is subtracted by 1 (step S208), the power supply abnormality check process (step S209) is executed, and if the startup wait time is not zero (step S210:≠0), step S208 Return to processing. The activation of the effect control section 24 is completed by the standby process based on such activation waiting time.

In step S210, if the above-mentioned startup waiting time has elapsed (waiting time = 0), the CPU 20a proceeds to step S211 and transmits a standby screen display command to the effect control section 24.
In response to this standby screen display command, the production control unit 24 displays a predetermined screen display on the liquid crystal display device 36 corresponding to the startup, such as a screen on which characters such as "Please Wait..." are displayed. Performs control for execution.

In response to executing the transmission process in step S211, the CPU 20a advances the process to step S212, and through the processes in step S212 and step S213, performs payout control while executing the power abnormality check process (S212: see FIG. 7). It waits for a power-on signal to be sent from the board 29. This power-on signal is a signal that is output when the payout control board 29 starts up normally, and the CPU 20a waits until the payout control board 29 starts up normally. As a result, if the payout control board 29 is not functioning properly due to some trouble, the processing of steps S212 and S213 is simply repeated and no gaming operation is started. Therefore, payout abnormalities such as prize balls not being paid out do not occur, and it is possible to prevent players from feeling distrustful.
If the CPU 20a receives the above-mentioned power-on signal (step S213: ON), the CPU 20a finishes the initialization process in step S101.

(Processing after initial settings)

Upon completion of the above initial setting process, the CPU 20a proceeds to step S102 shown in FIG. 5.
In step S102, the CPU 20a acquires information on input port n (ie, a predetermined input port) and copies it to the W register.
Here, input port n is a 1-byte (8-bit) port, and in this example, the following signals are input. Note that "b0" to "b7" shown below represent bit positions.

b0: Setting key (input signal from setting key switch 94)
b1: Out of supply detection signal b2: Counting error signal b3: Disconnection detection signal 1
b4: Disconnection detection signal 2
b5: Door open signal (detection signal of front door open sensor 61)
b6: RAM clear button (input signal from RAM clear switch 98)
b7: Power-on signal and payout communication confirmation signal

Here, for the setting key b0, "0" means that the setting key switch 94 is OFF, and "1" means that the setting key switch 94 is ON. Regarding the door open signal b5, "0" means the door is closed (front frame 2 is closed), and "1" means the door is open. Furthermore, regarding the RAM clear button b6, "0" means RAM clear switch 98 = OFF (button non-operation state), and "1" means RAM clear switch 98 = ON (button operation state).

In step S103 following step S102, the CPU 20a masks the value of the W register. Specifically, the values required to perform the transition determination of the setting change processing (S115), RAM clear processing (at least S117 and S118), setting confirmation processing (S109), and backup restoration processing (S111) described below. A process is performed to mask values other than the setting key (b0), RAM clear button (b6), and door open signal (b5).
As can be understood from the above explanation, the condition for transitioning to the setting change process is that both the setting key and the RAM clear button are in the operating state with the front frame 2 open at the time of startup. ing.
Furthermore, in this example, the conditions for transitioning to the RAM clearing process are that, in terms of operation, the setting key is in an inoperable state and the RAM clear button is in an operating state at the time of startup.
In terms of operation, the conditions for transitioning to the setting confirmation process are that the front frame 2 is open, the setting key is in an operating state, and the RAM clear button is in an inoperable state.
Furthermore, in terms of operation, the condition for transitioning to the backup restoration process is that both the setting key and the RAM clear button are in a non-operating state at the time of startup.

FIG. 8 shows the correspondence between the operational judgment conditions for transitioning to the setting change process, RAM clear process, setting confirmation process, and backup recovery process and the value of the W register.
FIG. 8 shows the order of setting change processing, RAM clearing processing, setting confirmation processing, and determination of transition to backup restoration processing.
As shown in the figure, the judgment conditions for transition to the first setting change process are set key: ON (setting key switch 94: ON), door open: ON (front door open sensor 61: ON), and RAM clear switch 98. : ON, and therefore, the values of the W register must be 0th bit: 1, 5th bit: 1, and 6th bit: 1.
The determination condition for transition to the second RAM clearing process is that the RAM clear switch 98 is ON, and it is determined whether the value of the W register is 6th bit: 1 or not. Here, in this example, the determination to proceed to the RAM clearing process is executed when the transition condition for the setting change process is not satisfied. In addition, the RAM clear switch 98 must be OFF before proceeding to the setting confirmation process and backup recovery process. From these points, if the conditions for transition to the setting change process are not satisfied and the RAM clear switch 98 is ON, it can be estimated that the transition to the RAM clear process is being performed. Therefore, in this example, in the determination of transition to RAM clear processing as described above, in terms of operation, only whether the RAM clear switch 98 is ON or not (6th bit: 1 or not) is determined. It is said that

The judgment conditions for moving to the third setting confirmation process are setting key: ON, door open: ON, and RAM clear switch 98: OFF.Therefore, the value of the W register is 0th bit: 1st bit, 5th bit. :1st and 6th bits: 0 is the condition.
Furthermore, the judgment conditions for transition to the fourth backup recovery process are set key: OFF and RAM clear switch 98: OFF, so the values of the W register are 0 bit: 0, 6th bit: 0. It is considered a condition.

Here, regarding the backup restoration process, the transition conditions for only performing the backup restoration process without going through the setting confirmation process are written as setting key: OFF and RAM clear switch 98: OFF on the operation surface as described above. However, regardless of whether or not the setting confirmation process is executed, the condition for simply transitioning to the state in which the backup restoration process is performed is that the backup flag described later is ON (step S106). ).

The explanation returns to FIG. 5.
In response to performing the masking process in step S103, the CPU 20a executes a setting change condition satisfaction determination process in step S104. Specifically, in order to determine whether to shift to the setting change mode, it is determined whether the value (3 bits) after masking in step S103 is "111".
If the value after masking is "111" and a positive result is obtained that the setting change condition is met, the CPU 20a executes the setting change process in step S115. That is, processing for newly setting the setting value Ve is performed in response to the operation of the RAM clear button or setting key.
Note that details of the setting change process in step S115 will be explained later.

Here, as described above, in this embodiment, the detection signals from the setting key switch 94, the front door open sensor 61, and the RAM clear switch 98, in other words, each detection signal used in determining the transition to the setting change mode. The signals are input to the same input port of the main control unit 20, and it is determined all at once whether the values of each input detection signal satisfy a predetermined condition.
As a result, the number of determination processes can be reduced compared to the case where it is determined individually whether or not the value of each detection signal satisfies a predetermined condition regarding the determination of transition to the setting change mode.

In response to executing the setting change process in step S115, the CPU 20a executes RAM clearing process in step S116. This RAM clearing process includes a process for initializing values in a predetermined area (used area) including a work area in the RAM 20c, and a setting for notifying the production control unit 24 side of the end of the setting change process executed in step S115. This includes a process for sending a change end command, the details of which will be described later.

Subsequently, in the previous step S104, if the value after masking in step S103 is not "111" and a negative result is obtained that the setting change condition is not satisfied, the CPU 20a proceeds to step S105 and detects the RAM abnormality. Determine whether or not. Specifically, it is at least determined whether the "setting value" stored in the work area of the RAM 20c is a value outside the usage range Ru (in this example, outside the range of "1", "2", and "6"). do.
Here, the value handled by the CPU 20a regarding the setting value Ve is the setting value Vd. The setting value Vd is a value corresponding to the setting value Ve, and in this example, it is a 1-byte value, and is set to 00H so that at least three stages corresponding to the above-mentioned usage range Ru can be expressed. Values from (0) to 02H(3) are determined. Note that "H" means a hexadecimal number (the same applies hereinafter). In this example, the set value Vd = 00H represents the set value Ve = "1", the set value Vd = 01H represents the set value Ve = "2", and the set value Vd = 02H represents the set value Ve = "6". be taken as a thing. In the main control unit 20, the setting value Vd is mainly handled as the “setting value”, and this setting value Vd is stored in the “setting value” storage area in the work area of the RAM 20c of the main control unit 20. .
In the determination process of step S105, it is determined whether the set value Vd stored in the work area is a value in the range of 00H to 02H.

In step S105, if it is determined that the set value is outside the above usage range Ru (that is, outside the normal range) and that the RAM is abnormal, the CPU 20a performs processing to wait for the power to be turned on again following step S112. From then on.
Specifically, in step S112, the CPU 20a sends an effect control command (setting A process of transmitting a change waiting command) to the production control unit 24 is performed. If a RAM abnormality is detected at startup, the system is forced to enter a setting change mode and accepts changes (settings) to the setting value Ve. Therefore, in step S112, the CPU 20a first notifies the production control unit 24 of the transition to the setting change mode using a setting change wait command.
Upon receiving the setting change wait command, the production control unit 24 causes the liquid crystal display device 36 to display a screen to prompt a setting change operation, such as a screen containing text such as "Please open the door and change the settings". let At this time, the effect control section 24 may perform control to display a corresponding light effect (for example, lighting all the LEDs in the light display device 45a) and sound effect together with the screen display.

In step S113 following step S112, the CPU 20a sets the backup flag to 00H (ie, OFF), and then repeats the error display process in step S114. In the error display process of step S114, a process for causing the setting/performance display 97 to display an error is performed. This error display process is repeated until the power to the pachinko game machine 1 is turned off, and when the power is turned on again, the processes from step S101 onwards are executed again as the main control side main process. At this time, if an operation to shift to the setting change mode has been performed in accordance with the screen display, etc., the shift to the setting change mode is performed, and the abnormal state of the RAM is resolved.

In step S105 described above, if it is determined that the set value is not outside the usage range Ru and that there is no RAM abnormality, the CPU 20a proceeds to step S106 and checks whether the backup flag is in the ON state (in this example, the backup flag = 5AH). is ON).
In the gaming machine 1, when the power is cut off, processing for backing up the information stored in the RAM 20c is performed by the power check/backup processing (step S901, see FIG. 19), which will be described later, in the main control side timer interrupt processing. If the backup process is properly performed when the power is cut off, the backup flag is turned on (see step S1010 in FIG. 19). Therefore, in step S106 described above, the backup flag is checked to determine whether or not backup recovery is possible. Specifically, in step S106, it is determined whether the backup flag stored in a predetermined area of the RAM 20c is in the ON state (5AH).

If it is determined in step S106 that the backup flag is not ON, the CPU 20a advances the process to step S112 described above. As a result, if the backup restoration conditions are not met, the transition to the setting change mode is forcibly performed, similar to the case where the RAM abnormality described above is recognized.

Here, as described above, the determination process in step S106 corresponds to the process of determining whether or not the transition to the state in which the backup restoration process is performed is possible, regardless of whether or not the setting confirmation process is executed.

On the other hand, if it is determined in step S106 that the backup flag is ON, the CPU 20a determines in step S107 whether a RAM clear condition (condition for transition to RAM clear processing) is satisfied. Specifically, it is determined whether the value of the 6th bit of the W register is "1".
If the value of the 6th bit of the W register is "1" and an affirmative result is obtained that the RAM clear condition is satisfied, the CPU 20a advances the process to step S116 described above. As a result, the RAM clearing process described above is executed.

Here, as can be seen by referring to the route from step S107 to step S116 described above, in the gaming machine 1 of this embodiment, it is possible to clear the RAM without changing settings. This makes it possible to deal with the case where it is desired to clear data other than the data related to the set value Ve, such as data related to payout in the RAM 20c.

Further, in step S107, if the value of the 6th bit of the W register is not "1" and a negative result is obtained that the RAM clear condition is not satisfied, the CPU 20a proceeds to step S108 and the setting confirmation condition ( It is determined whether the following conditions (conditions for transition to setting confirmation processing) are satisfied. That is, it is determined whether the value of the W register after masking in step S103 is "110".
If the value of the W register after masking is "110" and a positive result is obtained that the setting confirmation condition is satisfied, the CPU 20a executes the setting confirmation process in step S109, and advances the process to step S110. That is, the process shifts to backup restoration processing.
Note that details of the setting confirmation process in step S109 will be explained later.

On the other hand, if the value of the W register after masking is not "110" and a negative result is obtained that the setting confirmation condition is not satisfied, the CPU 20a passes the setting confirmation process in step S109 and proceeds to step S110. .

In step S110, the CPU 20a performs a process of transmitting a predetermined production control command corresponding to the backup recovery to the production control unit 24 as a command transmission process at the backup recovery.

In step S111 following step S110, the CPU 20a performs backup restoration processing.
The backup restoration process is a process of restoring the operation to the state before the power was cut off after the power was turned on, based on the stored contents of the RAM 20c backed up at the time of the power cut. Specifically, the CPU 20a performs processing for restoring the stack pointer that was before the power was shut off and starting the gaming operation from the processing state at the time of the power shutoff.
In addition, in the backup recovery process, a power failure recovery display command (OB03H) for instructing information display corresponding to the case of backup recovery is sent to the production control unit 24 in the main loop preprocessing of step S119, which will be described later. Therefore, a process is executed to store the lower byte data of the power failure recovery display command in a register.

When the backup restoration process in step S111 is executed, or when the RAM clear process in step S116 described above is executed (that is, when both the setting change process and the RAM clear process are executed, or when only the RAM clear process is executed) , the CPU 20a proceeds to step S117.

In step S117, the CPU 20a sets the CTC to periodically generate a timer interrupt every predetermined time, such as 4 ms.
By performing the setting process in step S117, an interrupt request signal to the interrupt controller is periodically output from then on, and the main control side timer interrupt process is executed.

In the following step S118, the CPU 20a performs a process of transmitting a production control command for instructing the start of the game to the production control unit 24, and then advances the process to step S119, executes main loop preprocessing, and then executes a process in step S120. Executes main loop processing.
Note that the main loop preprocessing in step S119 will be explained later.

(main loop processing)

FIG. 9 is a flowchart showing the main loop processing of step S120.
In the main loop process of FIG. 9, the CPU 20a sets itself to an interrupt disabled state in step S601, and executes random number update processing in the subsequent step S602. In this random number update process, various random numbers used in special symbol variation display games and normal symbol variation display games (random numbers related to jackpot lottery that circulate within a predetermined numerical range by increment processing (special symbol determination used in symbol lottery) Random numbers used to change the initial value (start value) of random numbers related to the auxiliary winning lottery (random numbers for determining auxiliary winnings used in the auxiliary winning lottery) , the initial value random number for assistance hit determination) and the random number for the variation pattern used for selecting the variation pattern.

The RAM 20c of this embodiment includes a counter for generating the initial value of a random number counter for special symbol determination, and a counter for generating the initial value of a random number counter for special symbol determination, as various random number counters used for symbol lottery related to jackpot lottery, auxiliary hit lottery, variable pattern lottery, etc. A random number counter for determining a supplementary hit, a counter for generating an initial value of a random number counter for determining a supplementary hit, a random number counter for determining a supplementary hit, a random number counter for a fluctuating pattern, and the like are provided. These counters serve as a random number generation means that generates random numbers using software. In the random number update process of step S602, the two initial value generation counters that generate the initial values of the special symbol determination random number counter and the supplementary hit determination random number counter, the fluctuation pattern random number counter, etc. are updated, and the various Generate soft random numbers. For example, if the numerical range that can be taken as a random number counter for a variation pattern is "0 to 238", a value is obtained from the count value storage area for generating a random number value for a variation pattern in the RAM 20c, and the obtained value is After adding "1", it is stored in the original count value storage area. At this time, if the result of adding "1" to the obtained value is "239", "0" is stored in the original random number counter storage area. Other initial value generation random number counters are updated in the same way.

After completing the random number update processing in step S602, the CPU 20a performs processing to save the values of all registers in step S603, and then performs performance display monitor total division processing in step S604.
This performance display monitor total division process is a process for calculating the value as the performance information described above (here, for example, the value as the "normal duty ratio information" described above). As mentioned above, the value of the normal time ratio information is calculated using the total number of balls to be paid out and the total number of out balls. It is calculated based on the result of counting the number of game balls that entered the lower starting hole 35, the general winning hole 43, and the big winning hole 50), and for the total number of out balls, the number of game balls ejected from the out hole 49 is calculated. Find it by counting.
Counting the number of winning pitches and counting the number of out pitches is performed in the input management process (see step S904 in FIG. 18), which will be described later, in the main control side timer interrupt process. The CPU 20a calculates a value as the normal time ratio information in step S604 based on the count values obtained by counting the number of winning pitches and counting the number of out pitches performed on the timer interrupt processing side in this way. As described above, the calculated value as the normal duty ratio information is stored in a predetermined area (measurement information storage area) of the RAM 20c.
The value of the normal duty ratio information calculated in this way is displayed on the setting/performance display 97 by a performance display monitor display process (see step S916 in FIG. 18), which will be described later, in the main control side timer interrupt process.

In step S605 following step S604, the CPU 20a performs all register restoration processing, and in subsequent step S606 sets itself to an interrupt enabled state, and then returns to step S601.

In this way, in the main loop process of step S123, the processes of steps S601 to S606 are repeated in an infinite loop. The CPU 20a repeatedly executes the processes of steps S601 to S606, except while performing the timer interrupt process, which is executed intermittently.

(Setting change processing)

FIG. 10 is a flowchart showing the setting change process in step S115.
In this setting change process, a process for setting the setting value Ve based on the operation, and a production control command for notifying that the setting is being changed or that the setting change has been completed are sent to the production control unit 24. Processing for sending is performed.

In FIG. 10, the CPU 20a first executes a process of transmitting a setting changing command (BA76H) to the production control unit 24 in step S401.
Upon receiving this settings changing command, the production control unit 24 displays a screen display on the liquid crystal display device 36 to notify that the settings are being changed, such as a screen displaying text such as "Settings are being changed." Processing is performed so that the corresponding sound is output from the speaker 46 during the setting change. Furthermore, at this time, the effect control section 24 may cause predetermined LEDs (for example, all LEDs) in the light generating means (light display device 45a) described above to light up in a predetermined lighting pattern.

In the following step S402, the CPU 20a sets the backup flag to 00H (ie, OFF state), and then sets the system operation status to 2 in step S403. This system operation status is information for at least identifying whether or not the setting change process of step S115 has been passed at the time of startup, and "2" indicates that the setting change process has been passed; A value (for example, "0") indicates that the setting change process has not been performed.
As can be seen with reference to FIG. 5, in this example, the RAM Although the clear processing (program) is assumed to be shared, by using the above system operation status, it is possible to share the RAM clear processing program and execute the processing differently in the former case and the latter case. .

In step S404 following step S403, the CPU 20a executes processing to obtain a set value. Specifically, the setting value Vd (in this example, any one of 00H to 02H) stored in the work area of the RAM 20c is obtained.

The processing from step S405 following step S404 is to update the displayed value on the setting/performance display 97 in response to the sequential advance operation of the setting value Ve (operation of the RAM clear button), or the operation to complete the setting change (operation of the setting key). This is a process for setting the setting value Ve in accordance with the operation).
First, in step S405, the CPU 20a decrements the acquired setting value Vd by 1 ("setting value - 1"), and in the subsequent step S406, determines whether the setting value Vd is larger than 1 (setting value>1"). ). In this example, since the maximum value of the set value Vd is 02H, it will not be determined that the set value>1 in step S406, which is executed for the first time after the start of the setting change process.
If the set value Vd is not greater than 1 in step S406, the CPU 20a sets the carry flag in step S407 (turns it ON), and increments the set value Vd by 1 ("set value + 1") in step S408. ), and in step S409 it is determined whether the carry flag is ON. If the carry flag is ON, the CPU 20a executes a setting change command acquisition process in step S411, and transmits the setting change command to the effect control unit 24 through command processing in the subsequent step S412.
Note that the setting change command will be described later.
Then, in response to executing the command transmission process in step S412, the CPU 20a executes the output management process in step S413. Through this output management process, the setting value Ve corresponding to the current setting value Vd is displayed on the setting/performance display 97. Note that details of the output management process in step S413 will be described later.

In step S414 following step S413, the CPU 20a determines whether the setting key is OFF, that is, whether the setting key switch 94 is OFF, and if the setting key is not OFF, in step S415, the CPU 20a switches the change switch 94 to It is determined whether the RAM clear switch 98 is ON. If the RAM clear switch 98 is not ON, the CPU 20a re-executes the output management process in step S413.
Through the processing in steps S413 to S415, the CPU 20a waits until either the setting key or the change switch is turned on, and during the standby, displays the current setting value Ve on the setting/performance display 97 through the processing in step S413. Repeat the process for

If the change switch is ON in step S415, the CPU 20a returns to step S406.
Here, if the setting value Vd acquired at the start of the setting change process in step S115 (the setting value Vd that was being set until then) is 02H, the change switch is determined to be ON in step S415. In the process of step S406, which is executed accordingly, a determination result is obtained that "setting value>1" (because it is incremented by -1 in step S405 but +1 in step S408). In response to a change operation (forward operation) performed when the set value Vd is 02H, the set value Vd should be returned to 00H. Therefore, if it is determined in step S406 that "set value>1", the carry flag setting process in step S407 is passed and the process proceeds to step S408. As a result, the carry flag is determined to be OFF in step S409, so the process proceeds to step S410, and the set value Vd is returned to 00H ("set value←0").
In response to returning the set value Vd to 00H in step S410, the CPU 20a advances the process to step S413 via the processes of steps S411 and S412. That is, in this case, the setting value Ve (“1” in this example) corresponding to the setting value Vd=00H is displayed on the setting/performance display 97.

Through the above processing, during the setting change, the setting value Vd is changed in a cyclical manner within the range of 00H to 02H (within the usage range Ru) according to the changing operation, and the setting value Vd corresponding to the changed setting value Vd is changed. The set value Ve is displayed on the setting/performance display 97.

Further, the setting change command transmitted in step S412 is a command for notifying the production control unit 24 of the setting value Ve corresponding to the currently selected setting value Vd during the setting change process, and is a command for notifying the production control unit 24 of the setting value Ve corresponding to the currently selected setting value Vd. This is a command in which information representing Ve is stored.
Through the series of processes from steps S406 to S415 described above, each time the currently selected setting value Ve is switched by the setting value forwarding operation, a setting change command that reflects the switched setting value Ve is sent to the effect control unit 24. That will happen.
In addition, although the explanation by illustration is omitted in FIG. 10, when acquiring the setting value Ve corresponding to the setting value Vd, the CPU 20a uses a setting value offset conversion table to be described later (see FIG. 16).

If it is determined in step S415 that the setting key is OFF, the CPU 20a proceeds to step S416 and executes processing to save the setting value Vd. That is, a process is executed to store the set value Vd in a predetermined area in the work area of the RAM 20c.
The CPU 20a finishes the setting change process in step S115 in response to executing the save process in step S416.

FIG. 11 is a flowchart of the output management process in step S413.
First, in step S501, the CPU 20a executes security signal output processing. Specifically, processing is performed to output a security signal to the hall computer HC through the frame external centralized terminal board 21.
In the following step S502, the CPU 20a executes a process of outputting 0 to the LED common port, that is, the common port of the LED as the setting/performance indicator 97, and then acquires display data from the 7-segment decoding table in step S503. Execute processing. That is, this is a process of acquiring display data of the set value Ve ("1", "2", "6") based on the set value Vd.
Note that if 0 is output to the LED common port in step S502, the setting/performance display 97 will be in a display OFF state (no display state), the significance of which will be described later.

FIG. 12 shows an example of a 7-segment decoding table, and FIG. 13 is a diagram illustrating the relationship between the segment configuration and the segment display pattern on the setting/performance display 97.
The 7-segment decoding table is stored in the ROM 20b of the main control unit 20.

In this example, the seven segments on the setting/performance display 97 are numbered from 0 to 6 as shown in FIG. 13A. In addition to these seven segments 0 to 6, the setting/performance display 97 is also provided with a DP (dot point) display section (light emitting section), and the DP display section is numbered "7". ing.
A total of 10 7-segment display data are prepared, from display data "SEG_0" representing the numerical value "0" to display data "SEG_9" representing the numerical value "9". The display data is 1 byte (8 bits) data, and if the lowest bit position is the 1st bit position, the 1st bit position is the display/non-display (light emission/non-light emission) of segment "0". represents. Thereafter, similarly, the second bit position is segment "1", the third bit position is segment "2", the fourth bit position is segment "3", the fifth bit position is segment "4", and the sixth bit position is segment "3". The bit position represents display/non-display of segment "5" and the seventh bit position represents segment "6", respectively.
Furthermore, in the display data in this example, the eighth bit position represents display/non-display of DP ("7").

The 7-segment decoding table shown in FIG. 12 is configured so that the corresponding display data, specifically, the display data of SEG_1, SEG_2, and SEG_6, are obtained from the setting values Vd=00H, 01H, and 02H. It is configured.
Specifically, in the 7-segment decode table of this example, an area is secured to store display data for each setting value Vd at least from 00H to 05H, such as the address area "6203" to "6208" in the figure. The display data SEG_1 ("06" in the figure) corresponding to the setting value Vd=00H is placed in the top layer area (the area with the address with the lowest number) in this area, and the setting value is placed in the second area. Display data SEG_2 ("5B" in the figure) corresponding to Vd=01H is stored in the third area, and display data SEG_6 ("7D" in the figure) corresponding to the set value Vd=02H is stored.
In this example, the fourth area corresponding to the setting value Vd=03H, the fifth area corresponding to the setting value Vd=04H, and the sixth area corresponding to the setting value Vd=05H are used for display purposes. Although "00" is stored as data, its significance will be explained again.
In addition, in the 7-segment decoding table of this example, display data SEG_E ("79") for displaying "E" representing a setting value error is stored in the seventh area. In response to the case where the set value Vd shows an abnormal value such as the set value Vd being outside the usage range Ru, it is possible to notify a set value error through the setting/performance indicator 97. .

The explanation returns to FIG. 11.
The CPU 20a performs a process of outputting the display data acquired from the 7-segment decoding table in the process of step S503 to the setting/performance display 97 in step S504.
The subsequent processing in steps S505 to S508 is a process for dynamically lighting (intermittent lighting) the LED for displaying the setting value Ve on the setting/performance display 97. Specifically, in step S505, the CPU 20a increments the LED counter by 1, and in the subsequent step S506, determines whether the 0th and 1st bits (lower two bits) of the LED counter are "11". Here, the lower two bits of the LED counter become "11" when the increment process in step S505 is performed a multiple of four times.
In step S506, if the 1st and 0th bits of the LED counter are "11", the CPU 20a proceeds to step S507, outputs data specifying the segment for setting value display to the LED common port, and Execute timer count processing. By executing the output process in step S507, the setting value Ve is displayed on the setting/performance display 97 based on the display data output in step S504. This display state is continued for the time set by the display timer in step S508 (4 ms in this example).

The output management process shown in FIG. 11 ends in accordance with the execution of the process in step S509 following the timer count process in step S508, and the process proceeds to step S414 shown in FIG. If the change switch is ON, the output management process in step S413 is repeated. As described above, in step S502, 0 is output to the LED common port, so the lighting state of the LED for displaying the set value started in the process of step S507 is canceled by executing step S502. Then, in step S505, the LED counter is incremented by 1, so in step S506 it is determined that the 0th and 1st bits of the LED counter are not "11", the output process in step S507 is passed, and the timer count process in step S508 is executed. executed. In other words, after the process of step S507 is executed and the LED for displaying the setting value is turned on for at least 4ms, the period until the 0th and 1st bits of the LED counter become "11" again, that is, in this example, The LED is turned off for at least 4ms×3=12ms.
In this way, dynamic lighting is realized in which the LED for displaying the set value is lit intermittently at a predetermined cycle.

In FIG. 11, the CPU 20a executes an input data creation process in step S509 in response to executing the timer count process in step S508.
This input data creation process is executed by calling, for example, the same process of step S902 in the main control side timer interrupt process (FIG. 18). As will be described later, the input data created in the input data creation process includes input data of the RAM clear switch 98 indicating whether or not there is an operation for sequentially advancing the setting value Ve, and setting key switch input data indicating whether or not there is an operation to complete the setting change. It contains 94 input data.
As can be seen with reference to FIG. 10, the determination of the presence or absence of a setting change completion operation (S414) and the determination of the presence or absence of a sequential advance operation of the setting value Ve (S415) are executed after the output management process of step S413. By executing the input data creation process in step S509, the data required for these determination processes can be obtained in advance.

(RAM clear processing)

FIG. 14 is a flowchart of the RAM clearing process (S116) shown in FIG.
First, in step S601, the CPU 20a executes intra-area RAM initialization processing. The initialization process in step S601 is a process for initializing (clearing) values in a predetermined area (used area) including the work area in the RAM 20c. However, in the initialization process at step S601, the storage area for the set value Vd in the work area is not subject to initialization.

Note that the above-mentioned performance information is stored in an area outside the used area of the RAM 20c (details will be described later with reference to FIG. 21), and therefore is not cleared in the initialization process of step S601.
What is to be cleared in the RAM clearing process is data in the RAM area (normal data storage area) such as various flags, timers, counters, etc. necessary for normal game progress. Examples of this data include: In other words, data related to gaming state designation (gaming state flag that specifies the current gaming state such as normal state, variable probability state, time saving state, potential state, etc.), a flag specifying whether or not a winning game is in progress (condition device operation flag), various data related to the execution of winning games (current number of rounds, maximum number of rounds, etc.), data related to jackpot lottery results (jackpot determination flag: winning/losing lottery result information, special symbol determination data: symbol lottery result information) , manage pending data regarding pending balls (number of pending balls, various random numbers used for jackpot drawings, various random numbers used for supplementary winning drawings, random numbers for variable patterns), special symbol operation status, and game progress. Timer (special symbol accessory operation timer), input/output data related to switches and sensors, various winning counters that count the number of winning balls in the winning opening, a flag that specifies the presence or absence of electric support status (open extension flag), electric Electric support counter that counts the remaining number of supports, counter that counts the remaining number of high probability states (special pattern probability variable number counter, general pattern probability variable number counter), various error flags (excluding RAM error flag), and payout related data etc. In any case, when the RAM clearing process is executed, all data other than specific data (setting value Vd and performance information) are set to the initial state.

Here, as understood from the description of FIG. 5 above, if the setting change process (S115) is executed, the process advances to step S116 and RAM clear process is executed.
In the setting change process, the setting value Vd may be changed. When the set value Vd is changed, the values stored in the work area of the RAM 20c other than the set value Vd may become inconsistent with the changed set value Vd. Therefore, when the setting change process is performed, the area other than the setting value Vd in the work area is cleared (initialized) by executing the RAM clear process.

In response to the execution of the initialization process in step S601, the CPU 20a sets the RAM clear notification timer to 30 s in step S602, and executes a process for setting a missed mark on this special drawing. The RAM clear notification timer is a timer for setting the time for RAM clear notification executed by the production control unit 24 in response to a RAM clear command transmitted in the process of step S803 in FIG. 17, which will be described later, and is 30 seconds in this example. Set. Moreover, the special map mentioned here means, for example, the above-mentioned special map 1 and special map 2.

In step S603 following step S602, the CPU 20a determines whether the system operation status described above is "2". That is, it is determined whether or not the setting change process of step S115 has been performed after startup.
If the system operation status is "2", the CPU 20a executes the process corresponding to the case where the setting change process is passed through steps S604 to S612.
If the system operation status is not "2", the CPU 20a advances the process to step S613, stores the lower byte data of the RAM clear command in the register, and ends the RAM clear process in step S116.
Note that the operation of storing the lower byte data of the command in the register as described above functions as an operation of specifying the type of command to be transmitted in step S804 of the main loop pre-processing (FIG. 17), which will be described later.

In the case of going through the setting change process, the CPU 20a first resets the system operation status to "0" in step S604, executes the process of acquiring the setting change end command (BA77H) in step S605, and then executes the process of acquiring the setting change end command (BA77H) in step S606. A setting change end command is transmitted to the production control section 24 through the transmission process.

The processes in steps S607 to S612 following step S606 are processes related to displaying the set value Ve on the setting/performance display 97.
First, in step S607, the CPU 20a outputs data specifying a segment for setting value display to the LED common port, and in subsequent step S608, the CPU 20a outputs display data corresponding to the setting value Vd from the 7-seg decoding table (see FIG. 13). After executing the process of adding DP to the display data in step S609, that is, the process of setting the value of the seventh bit position of the display data to "1", the display data is output by the output process of step S610. Output to setting/performance display 97.

The processes of steps S612 and S613 following step S611 are processes for continuing the display state of the set values Ve and DP on the setting/performance display 97 for a predetermined period of time (1 s in this example). Specifically, the CPU 20a repeatedly executes the display timer count process in step S612 (for example, the 4 ms cycle timer count process similar to the previous step S508 (see FIG. 11)) until it is determined in step S612 that 1 s has elapsed. do.

If it is determined in step S612 that 1 s has elapsed, the CPU 20a executes the storage process in step S613, and finishes the RAM clear process in step S116.

As can be understood from the above explanation, when the setting change process in step S115 is executed and the setting change completion operation is performed (step S412: Y in FIG. 10), in the RAM clear process in step S116, A setting change end command is sent to the production control unit 24 (S605, S606), and a notification that the setting change has ended is issued.
In the case of this example, the setting change end command notifies the production control unit 24 that the setting change has ended, but does not provide a function to notify the setting value Ve set in the setting change process. .
In this example, the setting value Ve set in the setting change process is notified to the production control unit 24 by a setting value command transmitted in the process of step S808 in FIG. 17 (main loop preprocessing) described later.

(Setting confirmation process)

FIG. 15 is a flowchart showing the setting confirmation process in step S109.
The setting confirmation process is a process for confirming and displaying the setting value Ve that is being set.
In FIG. 15, the CPU 20a first sets a fraud information timer to 30 seconds in step S701. The unauthorized information timer is a timer for managing the output time of the security signal mentioned above to the hall computer HC.
In the following step S702, processing for acquiring current setting value information is performed. That is, the setting value Vd stored in the work area of the RAM is acquired.

In step S703 following step S702, the CPU 20a executes processing to obtain setting value data from the setting value offset conversion table.

FIG. 16 shows an example of a set value offset conversion table stored in the ROM 20b of the main control unit 20.
The set value offset conversion table converts the set value Vd (00H to 02H) into the set value Ve (“1
, ``2,''``6'') into identification data (``SETNUM1'' to ``SETNUM6'').
In this example, the setting value offset conversion table has at least an area for storing identification data of the setting value Ve for each setting value Vd from 00H to 05H, such as the address area "6215" to "6220" in the figure. The identification data of the set value Ve "1"("00" in the figure) corresponding to the set value Vd = 00H is secured in the uppermost region of this region, and the identification data of the set value Ve "1"("00" in the figure) corresponding to the set value Vd = 00H is secured in the second region. The identification data of the corresponding setting value Ve “2” (“01” in the figure) is in the third area, and the identification data of the setting value Ve “6” (“05” in the figure) corresponding to the setting value Vd=02H is in the third area. Stored.
In this example, the fourth area corresponding to the setting value Vd=03H, the fifth area corresponding to the setting value Vd=04H, and the sixth area corresponding to the setting value Vd=05H have the setting value "00" is stored as the identification data of Ve, and its significance will be explained again.

In FIG. 15, the CPU 20a acquires the above identification data as "setting value data" through the acquisition process in step S703.

In response to executing the acquisition process in step S703, the CPU 20a executes the acquisition process for the setting confirmation command (BA6xH) in step S704, and sends the setting confirmation command to the production control unit 24 through the command transmission process in step S705. Send.
In the acquisition process of step S704, the CPU 20a performs a process of including the setting value data acquired in step S703, that is, identification data for identifying the setting value Ve currently being set, in the setting confirmation command.
Thereby, by executing the command transmission process of step S705, the effect that the setting is being confirmed and the current setting value Ve are notified to the production control unit 24.

Processing in steps S706 and S707 following step S705 is processing for displaying the current setting value Ve on the setting/performance display 97.
Specifically, in step S706, the CPU 20a first executes a process of acquiring data of setting values and DP. That is, a process is executed to obtain the current setting value Vd stored in the work area of the RAM 20c and the DP data (“1”) on the setting/performance display 97. Then, the output management process of step S707 is executed. The output management process in step S707 is the same as the output management process in step S413 shown in FIG. As a result, the setting/performance display 97 in this case displays a value representing the current setting value Ve and DP.

In step S708 following step S707, the CPU 20a determines whether or not the setting key is OFF (the setting key switch 94 is OFF), that is, whether an operation to instruct the end of the setting confirmation display has been performed, and determines whether the setting key is OFF. For example, the output management process in step S707 is executed again. As a result, after the settings confirmation command is sent in step S705, the process waits until an instruction to end the settings confirmation display is performed in the process of step S708, and during the standby, the settings and performance The process of displaying the current set values Ve and DP on the display 97 is continued.

If it is determined in step S708 that the setting key is OFF, the CPU 20a executes the acquisition process of the setting confirmation end command (BA67H) in step S709, and sends the setting confirmation end command to the production control unit 24 through the command transmission process of the subsequent step S710. The setting confirmation process in step S109 is completed.

(main loop preprocessing)

FIG. 17 is a flowchart of the main loop preprocessing in step S119.
In the main loop pre-processing, the CPU 20a first executes initialization command acquisition processing in step S801, and then transmits the initialization command to the effect control unit 24 through the command transmission processing in step S802. The initialize command is a command for instructing to initialize (return to origin) the movable accessory motor 80c that operates the movable object as an accessory.

In step S803 following step S802, the CPU 20a performs a process of acquiring transmission command data from the acquired lower byte command, and transmits the acquired command data to the effect control unit 24 through the command transmission process of step S804.
Here, in the acquisition process in step S803, data of a command whose lower byte data is stored in a register in the process of processing after startup is acquired. Specifically, when the RAM clear process in step S116 is performed (when both the setting change process and the RAM clear process are performed, or when the setting change process is not performed and only the RAM clear process is performed), The data of the RAM clear command (BA02H) is acquired. On the other hand, if the backup restoration process in step S111 is performed (if both the settings confirmation process and the backup restoration process are performed, or if the settings confirmation process is not performed and only the backup restoration process is performed), the power outage is restored. The data of the display command (OB03H) is acquired.
Thereby, the effect control unit 24 is configured to execute different processes depending on whether the RAM clear process is performed or the backup restoration process is performed.

In step S805 following step S804, the CPU 20a executes processing for transmitting the number of reserved pieces of special figures 1 and 2. Here, in the process of step S805, when the backup restoration process of step S111 is performed, the pending numbers of special figures 1 and 2 are sent to the production control unit 24, and the RAM clear process of step S116 is performed. In this case, the pending number is not transmitted (because the information on the pending number has been cleared).

The processing of steps S806 to S808 following step S805 is processing for notifying the current setting value Ve to the production control unit 24 by a setting value command.
First, in step S806, the CPU 20a performs processing to obtain the setting value Vd stored in the work area of the RAM 20c as a process for obtaining current setting value information, and in subsequent step S807, the CPU 20a performs processing to obtain the setting value Vd stored in the work area of the RAM 20c. The process of acquiring setting value data from FIG. 16) is executed. Specifically, the identification data of the setting value Ve (“1”, “2”, “5”) corresponding to the setting value Vd (00H to 02H) obtained in step S806 is obtained.
Then, the CPU 20a performs the acquisition process of the set value command (F6xxH) in the subsequent step S808, and transmits the set value command to the effect control unit 24 by the command transmission process of step S809.
In the acquisition process in step S808, a setting value command including the identification data acquired in step S807 is acquired. With such a setting value command, the current setting value Ve can be notified to the production control section 24.

In response to executing the command transmission process in step S809, the CPU 20a executes internal function register setting process in step S810, that is, register setting process for initializing various functions such as a hardware random number counting function, and In S811, processing is executed to set the performance display monitor lighting timer to 5 seconds. The performance display monitor lighting timer is a timer for managing the operation time of the operation confirmation lighting operation (flashing operation for 5 seconds in this example) when the setting/performance display 97 is activated.

Further, in step S812 following step S811, the CPU 20a resets the system operation status to "0", and in step S813 turns on the firing permission signal to the payout control board 29. In response, the payout control board 29 determines that the firing is permitted, outputs the permission signal to the firing control board 28, and allows the firing device 32 to fire the game balls. This allows the game ball to be fired using the firing operation handle 15.
Here, the configuration is such that the payout control board 29 receives a firing permission signal from the main control unit 20 and allows the firing operation, that is, the instruction information for firing permission from the main control unit 20 is indirectly transmitted through the payout control board 29. Although the configuration in which the launch permission signal is sent to the launch control board 28 is illustrated as an example, the present invention is not limited to this, and for example, the launch permission signal from the main control unit 20 may be configured to be output directly to the launch control board 28. .
In response to executing the process in step S813, the CPU 20a finishes the main loop preprocessing in step S119.

(Advantages of data table for setting value display and setting value conversion table)

Here, in this embodiment, like the setting value offset conversion table shown in FIG. is stored.
This data table contains setting value related information that is selected when the main control unit 20 refers to settable setting values Vd (“00H” to “02H”) through the setting change process (see FIG. 10). It includes certain first setting value related information and second setting value related information that is setting value related information selected when the main control unit 20 refers to a setting value that cannot be set by the setting change process. Specifically, the first set value related information corresponds to "00", "01", and "05" stored in addresses "6215", "6216", and "6217", respectively, in the set value offset conversion table shown in FIG. , the second setting value related information corresponds to "00", "00", and "00" stored in addresses "6218", "6219", and "6220", respectively.
Further, in the data table, at least specific information regarding the setting value Ve representing the stage with the lowest winning probability (that is, "00" at the address "6215") is stored as the first setting value related information, and the second setting value related information is stored as the first setting value related information. The same information as the specific information is stored as the value-related information.

When the setting value Vd is a value that cannot be set, it is possible to rewrite the setting value Vd stored in the RAM 20c to a value representing the lowest level.
However, if it is tampered with after being rewritten, there is a risk that the corresponding information will be acquired from the data table based on the unsettable setting value Vd, and an operation according to the unsettable setting value will be realized.
According to the above configuration, since it is impossible to obtain information corresponding to the setting value Vd that cannot be set from the data table, it is possible to prevent fraudulent acts from being established, and to ensure the fairness of the game. can be increased.

Furthermore, in this embodiment, 0 is stored as the above-mentioned specific information.
This makes it possible to prevent fraudulent acts due to falsification of setting values by a simple method of writing specific information=0 in the setting value related information. That is, the fairness of the game can be improved by a simple method.

In addition, in this embodiment, regarding the 7-segment decoding table shown in FIG. Setting value related information (addresses “6203” to “6205”) and second setting value related information, which is setting value related information selected when the main control unit 20 refers to a setting value that cannot be set by the setting change process. (addresses "6206" to "6208") are included. In the 7-segment decoding table, 0 is stored as the second setting value related information.
As a result, even if the data table is referenced by a setting value Vd that cannot be set in the setting change process due to fraudulent activity or some kind of malfunction, the setting value display means (in this example, the setting/performance display 97) will be set. It is possible to prevent the value from being displayed. Specifically, in this example, data of "00", that is, "00000000" is acquired as display data, so all segments "0" to "6" in the 7 segments for displaying setting values are hidden. As a result, numerical values will not be displayed.
Therefore, it is possible to prevent incorrect display of set values.

[4-2. Main control side timer interrupt processing]

The main control side timer interrupt processing will be described with reference to the flowchart in FIG.
The main control side timer interrupt process is activated by an interrupt from the CTC at regular intervals (about 4 ms), and is executed by interrupting the execution of the main control side main process.

In FIG. 18, when a timer interrupt occurs, the CPU 20a first executes a power check/backup process in step S901. This power check/backup process mainly monitors the power level supplied from the power supply board, and if an abnormality such as a power outage occurs, the Backup processing and the like are performed to store predetermined gaming information in the RAM 20c.

(Power check/backup processing)

FIG. 19 is a flowchart showing the power check/backup process in step S901.
In the power check/backup process, the CPU 20a reads the power abnormality signal output from the power supply board twice in step S1001, and determines whether the two read values match in step S1002. If both values do not match, the process returns to step S1001 and the power supply abnormality signal is read twice again.

If both values match in step S1002, the CPU 20a determines in step S1003 whether the power abnormality signal is at a normal level (the power abnormality signal is OFF = normal level, ON = not normal level).
If the power abnormality signal is at a normal level (step S1003: OFF), the CPU 20a turns off the backup flag in step S1004, clears the power abnormality confirmation counter in the subsequent step S1005, and ends the power abnormality check process in step S901. That is, if it is confirmed that the power supply abnormality signal is at a normal level, the backup process described below is not performed and the timer interrupt process continues.

On the other hand, if the power abnormality signal is not at the normal level in step S1003 (step S1003: ON), the CPU 20a increments the value of the power abnormality confirmation counter by 1 in step S1006, and then increments the value of the power abnormality confirmation counter in step S1007. It is determined whether or not the value is equal to or greater than a predetermined threshold value (threshold value = a natural number greater than or equal to 2: for example, "2").
If the value of the power abnormality confirmation counter is not equal to or greater than the threshold value, the CPU 20a ends the power abnormality check process in step S901. That is, if a state in which the power supply abnormality signal is not at the normal level is detected but is not continuously detected, the backup process is not performed and the timer interrupt process continues.

On the other hand, if the value of the power abnormality confirmation counter is equal to or greater than the threshold value, the CPU 20a performs backup processing shown as steps S1008 to S1011.
Specifically, the CPU 20a first clears the value of the power supply abnormality confirmation counter (S1108), turns off the launch permission signal (S1009), and turns on the backup flag (S1010).
Further, the CPU 20a transmits a power-off command to the production control unit 24 (S1011), and advances the process to step S1012.

In step S1012, the CPU 20a performs processing to enable RAM protection and disable the prohibited area.
The RAM protect is a function to prevent rewriting of the RAM 20c due to malfunction or operation. By enabling RAM protection, only data reading from the RAM 20c is possible, and data writing is disabled.
Further, the prohibited area is an area corresponding to a designated area in the IAT (travel prohibition outside designated area) function, and by setting the prohibited area to be invalid, IAT reset will not occur thereafter.

In step S1013 following step S1012, the CPU 20a clears the value of the output port, and in the subsequent step S1014, stops the timer interrupt processing, sets itself to an interrupt disabled state, and shifts to infinite loop processing.
During this infinite loop, the CPU 20a is reset by the WDT, and due to loss of operating power, the CPU 20a transitions to a stopped state.

The explanation returns to FIG. 18.
In FIG. 18, after completing the power check/backup process in step S901, the CPU 20a executes input data creation process in step S902. Specifically, input data is created based on input information (ON/OFF signals, rising states (ON edge, OFF edge)) from various sensors and switches.
The input information here is, for example, from the winning detection switches such as the upper starting opening sensor 34a, the lower starting opening sensor 35a, the normal symbol starting opening sensor 37a, the big winning opening sensor 52a, the general winning opening sensor 43a, and the OUT monitoring switch 49a. ON/OFF information (win detection information) of the output switch signal, ON/OFF information (operation detection information) of the switch signal output from switches related to the setting operation of the setting value Ve, such as the setting key switch 94 and the RAM clear switch 98. information), and status signals from the payout control board 29 (ON/OFF information of the front door open sensor 61 and full detection sensor 60). Thereby, whether or not a game ball is detected in the out hole or each winning hole is monitored for each interruption.

After completing the input data creation process in step S902, the CPU 20a executes timer management process in step S903 to manage a timer used for controlling gaming operations. Here, the values of various timers used to control the gaming operations of the gaming machine 1 are updated (subtracted).

Next, the CPU 20a performs input management processing in step S904. In this input management process, the values of the winning counter, the OUT ball monitoring counter, etc. are updated based on the input data created in the input data creation process (S902). The "winning counter" is a counter that is provided corresponding to each winning hole and counts the number of winning game balls (number of winning balls). The OUT ball monitoring counter is a counter that counts game balls (out balls) discharged from the out port 49.
The input management process in step S904 functions as an input management means that manages input signals (detection signals) from various winning a prize opening sensors.

In step S905 following step S904, the CPU 20a executes a setting abnormality check process.

FIG. 20 is a flowchart showing the setting abnormality check process in step S905.
In FIG. 20, the CPU 20a checks the set value error flag in step S1101. The set value error flag is a flag that is set (turned ON) by the process of step S1103 described below when an abnormality in the set value Vd is recognized, and in this example, "5AH" means the ON state. .

In step S1101, if the setting value error flag is "5AH" (ON state), the CPU 20a ends the setting abnormality check process in step S905. That is, the fact that the setting value error flag is determined to be ON in step S1101 means that the transmission of the setting value abnormality command (command that instructs the production control unit 24 to execute the setting error notification) has already been executed in step S1104, which will be described later. Therefore, the setting abnormality check process ends without transmitting the setting value error flag again.

On the other hand, if it is confirmed in step S1101 that the set value error flag is not "5AH" (OFF), the CPU 20a determines whether the set value Vd is within the normal range (within the range of 0 to 2) in step S1102. Determine whether or not. Specifically, the setting value Vd stored in the work area of the RAM 20c is obtained, and it is determined whether the value is within the range of "00H" to "02H".

If the setting value Vd is within the normal range, the CPU 20a ends the setting abnormality check process in step S905.
If the set value Vd is not within the normal range, the CPU 20a proceeds to step S1103 and sets a set value error flag (ON state), and in the subsequent step S1104 sets a value to indicate that an abnormality has occurred in the set value Vd. A value abnormality command is sent to the production control section 24, and the setting abnormality check process is completed.
Here, the setting value error flag is used in step S1308 in FIG. 25 (setting error determination at the time of winning), which will be described later, as well as in step S1501 in FIG. It is used in step S1701 in FIG. 30 (setting error determination when performing fluctuation pattern lottery at the start of fluctuation).

Here, upon receiving the above set value abnormality command, the effect control unit 24 performs a process for notifying the data abnormality of the set value Ve. For example, processing is performed to display on the liquid crystal display device 36 an image including a message such as "RAM abnormality. Please call the attendant."
In the gaming machine 1, a setting error (setting value error) can be canceled by performing a setting change operation.

The explanation returns to FIG. 18.
After completing the setting abnormality check process in step S905, the CPU 20a executes error management process in step S906. In this error management process, the presence or absence of an error is monitored based on input data related to various sensors and status signals from the payout control board 29.
When an error occurs, the CPU 20a performs error processing, and if the type of error requires transmission of an error command, the CPU 20a transmits the corresponding command to the effect control section 24. When the production control unit 24 receives this error command, it executes error notification according to the error type. Further, when the error that is occurring is resolved, the CPU 20a transmits an error cancellation command to the production control section 24. When the production control section 24 receives this error cancellation command, it terminates the error notification that is being executed.

Next, in step S907, the CPU 20a executes a timer interrupt random number management process that periodically updates the random numbers related to each variable display game. Here, in order to make the count value of the random number counter random, we update the random number (+1 is added for each interrupt) for the random number for special symbol determination, the random number for assistance hit determination, etc., and every time the random number counter goes around. Next, a process is performed to change the start value of the random number counter. Note that the internal lottery random numbers (jackpot determination random numbers) are generated by the random number generation circuit, so they are not updated here.

In step S908 following step S907, the CPU 20a executes prize ball management processing. In this prize ball management process, the above-mentioned prize winning counter is checked, and if there is a prize winning, a payout control command specifying the number of prize balls is transmitted to the payout control board 29. When receiving the payout control command, the payout control board 29 controls the game ball payout device 19 based on the prize ball number information included in the payout control command, and causes the game ball payout device 19 to perform a payout operation for the specified number of prize balls.

Next, the CPU 20a executes normal symbol management processing in step S909. In this normal symbol management process, necessary processing is performed to execute the normal symbol variation display game. Here, it is monitored whether or not a game ball is detected by the normal symbol starting hole sensor 37a, and when a game ball is detected, predetermined game information (such as a random number for determining a support hit) necessary for the support win lottery is sent. The game information is acquired (random number acquisition processing), and the game information is stored as pending data (operation pending balls related to normal symbols) up to the maximum number of pending balls (suspended storage processing). Then, when a predetermined variable display start condition regarding the ordinary symbol is established, a supplementary winning lottery is performed based on the activated reserved balls, and a variation pattern of the ordinary symbol is selected based on the supplementary winning lottery result, and a stop display mode of the ordinary symbol (normal symbol) is selected. Determine the stop symbol). In addition, here, in order to display the normal symbols in a variable manner, if the symbol is changing, LED display data for the variable display is created, and if it is not changing, LED display data for the stop display is created.

Furthermore, the CPU 20a executes normal electric accessory management processing in step S910. In this normal electric accessory management process, processing necessary for executing the normal electric power open game is performed. Specifically, when the lottery result of the auxiliary winning lottery is a win, a process of setting solenoid control data for the normal electric accessory solenoid 41c is performed. Based on the solenoid control data set here, an excitation signal is output to the normal electric accessory solenoid 41c, thereby controlling the opening/closing operation pattern of the movable blade 47.

Next, the CPU 20a executes special symbol management processing in step S911. In this special symbol management process, a jackpot lottery is mainly performed in the special symbol fluctuation display game, and based on the lottery results, the special symbol fluctuation pattern (pre-read fluctuation pattern and fluctuation pattern at the start of fluctuation) and special stop symbol Processing necessary for the special symbol variation display game, such as determination of , is executed.

Next, the CPU 20a executes special electric accessory management processing in step S912. In this special electric accessory management process, a setting process necessary for controlling the execution of the winning game is performed. Specifically, when the jackpot lottery result is a jackpot, a winning game (jackpot game) corresponding to the winning type is executed and controlled.
Specifically, it sets solenoid control data for the big winning hole solenoid 52c, counts the number of rounds (in the case of a jackpot), monitors the maximum number of wins to the big winning hole 50, and the opening time, etc. Further, when the winning game ends, the game state transition setting is performed based on the game state at the time of winning and the winning type.

Also, here, a plurality of performance control commands are transmitted depending on the progress of the winning game. At the start of the jackpot, the start of a round game, the end of a round game, the maximum number of rounds, etc., the time has come to send the jackpot start command, round start command, round end command, big prize opening command, and jackpot end command, respectively. Send accordingly. The jackpot start command includes the current winning type information, and is used by the performance control section 24 to determine a series of winning performance scenarios to be developed during the winning game. In addition, the jackpot end command includes information regarding the current winning type and the gaming state at the time of winning the winning, that is, information that can specify the gaming state after the winning game ends. It is used when deciding the production mode after the game. Therefore, since this "jackpot end command" can specify the gaming state after the end of the winning game, it plays a role as a gaming state designation command that designates the gaming state.

After completing the processing for proceeding with the game up to step S912, the CPU 20a performs external terminal management processing in step S913. In this external terminal management process, the operating state information of the gaming machine 1 is outputted to external devices such as the hall computer HC and the island lamp through the frame external centralized terminal board 21. The operating state information includes, for example, game information such as winning game occurrence information, symbol variation display game execution start information, number of winnings/prize balls information, and error information.

Next, the CPU 20a executes LED management processing in step S914. In this LED management process, output control of control signals (dynamic lighting data) to LED displays such as the normal symbol display device 39a, the special symbol display devices 38a and 38b, and the setting/performance display device 97 is performed. Control signals based on display data created in the normal symbol management process (step S909), special symbol management process (step S911), etc. are output to the corresponding display device or display device in this LED management process, and display control is performed. It will be done. As a result, a series of variable display operations (variable display and stop display) of special symbols on the special symbol display devices 38a, 38b and normal symbols on the normal symbol display device 39a are realized.

In step S915 following step S914, the CPU 20a saves the values of all registers, and then performs performance display monitor display processing in step S916. That is, this is a process for displaying the value as the normal duty ratio information mentioned above on the setting/performance display 97.
As mentioned earlier, in this example, the value of the normal pitch ratio information is recalculated every time the number of pitches out in all conditions reaches a predetermined value, and the setting/performance indicator 97 shows the current normal pitch ratio information. It is possible to display the working ratio information and the previous normal working ratio information (normal working ratio information whose calculation was completed at the most recent recalculation timing). Therefore, in the display process of step S916 in this case, a process is performed to display these two types of values as normal duty ratio information on the setting/performance display 97.
Note that the current value of the normal duty ratio information is the value calculated in the process of step S604 in the main loop process (FIG. 11) described above, and the previous value of the normal duty ratio information is stored in a predetermined area of the RAM 20c. Then, the CPU 20a reads out the stored value and displays it on the setting/performance display 97.

Next, the CPU 20a restores the values of all registers in step S917, clears the count value of the WDT in step S918, and ends the main control side timer interrupt processing.

When the above timer interrupt processing is completed, the CPU 20a executes the main loop processing (S123) until the next timer interrupt occurs.

<5. About processing transition between in-area processing and out-of-area processing>
[5-1. Regarding used area and unused area]

FIG. 21 is an explanatory diagram of an area (memory area) set in the memory in the main control unit 20. Specifically, it is an explanatory diagram of areas set in the memory that can be accessed by the CPU 20a, as the ROM 20b and the RAM 20c.

A first memory area (hatched area in the figure) and a second memory area (matte area in the figure) are set in the memory that can be accessed by the CPU 20a. The first memory area is defined as an area in which a predetermined program and data used by the CPU 80a in proceeding with the gaming operation (game) are placed. The second memory area is defined as an area for arranging programs and data that are permitted to be placed outside the first memory area.
In this example, the programs and data related to the management and display of the performance information described above are permitted to be placed in the second memory area. Specifically, the program and data related to the performance display monitor aggregation division process (S304) in the main loop process (S120) shown in FIG. 9, and the performance display monitor display process in the main control side timer interrupt process shown in FIG. These are programs, data, etc. related to (S916).

Here, the first memory area is called a "use area" in the sense that it is an area that can be used in game progress processing. On the other hand, the second memory area is called an "outside use area" in the sense that it is an area that can be used for specific processing other than game progress processing.
Note that hereinafter, the area "outside the used area" as the second memory area may also be referred to as the "unused area." Furthermore, in the following description, "within the area" and "outside the area" mean "within the usage area" and "outside the usage area", respectively, unless otherwise specified.

As shown in the figure, each of the first memory area and the second memory area includes a control area for storing a program, a data area for storing data used by the program, and various types of data generated in the process of processing by the program. An R/W area (Read/Write area) is set for storing flags, timer values, etc. in a rewritable manner. The control area and data area correspond to areas within the ROM 20b, and the R/W area corresponds to an area within the RAM 20c.

FIG. 22 is an explanatory diagram of regulations established for the first memory area and the second memory area.
In each of the first and second memory areas, the program in the control area is permitted to refer to and update (record) data in the R/W area within its own area. On the other hand, in each of the first and second memory areas, the program in the control area is only permitted to refer to the data in the R/W area in the other memory area, but is not permitted to update it. For example, a flag recorded by a program in the second memory area in the R/W area in the second memory area can only be referenced by the program in the first memory area and cannot be updated. .
Although not shown, only programs in the same memory area are allowed to reference data in the data area. That is, a program in the first memory area references data in a data area in the second memory area, and a program in the second memory area references data in a data area in the first memory area. Such things are not allowed.

[5-2. Processing transfer method in precedent example]

Here, in the process in which the CPU 20a executes the processes described with reference to FIGS. There is a process of returning to the processing of the program within the area upon completion of the processing. That is, there is a process transition between inside the area and outside the area. As a specific example of such a process transition, in the main loop process (S120) shown in FIG. Examples include a process in which after executing the out-of-area program process, the process returns to the random number update process in step S302.

Here, first, a method as a precedent example will be described with respect to the above-mentioned method of transferring processing between inside the region and outside the region.
FIG. 23 is a diagram showing the register configuration of the CPU 20a in the prior example.
As shown in the figure, the CPU 20a in the prior example includes a PC (program counter) register 100, an I (interrupt) register 101, and an R (refresh) register 102, as well as a front register 103 and a back register 104, each consisting of a plurality of registers. It is equipped with
The table register 103 includes a Q register 105, an A (accumulator) register 106, an F (flag) register 107, a B register 108, a C register 109, a D register 110, an E register 111, an H register 112, an L register 113, and an IX register 114. , an IY register 115, and an SP (stack pointer) register 116.
The back register 104 includes Q' register 105', A' register 106', F' register 107', B' register 108', C' register 109', D' register 110', E' register 111', and H' register. 112', L' register 113', IX' register 114', and IY' register 115'.
Among these various registers, at least the B register 108 to L register 113 and the B' register 108' to L' register 113' are general-purpose registers.

An example of a program related to processing transition between inside the area and outside the area will be described with reference to FIGS. 24 and 25.
FIG. 24 shows an example of a program mainly corresponding to the main loop processing of step S120 (particularly the interrupt waiting part: see FIG. 9) in the main control side main processing (FIG. 5), and FIG. A program related to performance display monitor total division processing (S304) is illustrated as an external program.

For confirmation, we will explain the main commands among the various commands used in the program. The command here refers to a mnemonic command in assembly language.
"DI" is an instruction to disable interrupts, and "EI" is an instruction to enable interrupts.
"PUSH" is an instruction to stack (save) the value of a specified register to the stack area of the memory (RAM 20c), and "POP" is an instruction to take out (write) the value of the stack area to the specified register.
"LD" is a load instruction, which writes the value of the location specified on the right side to the location specified on the left side after "LD" is written. For example, the description "LD R,n" (where R is a value that specifies a register, and n is a value that specifies an address on memory) means that the register specified by R is specified by n. This is an instruction to write the value of the address in memory. Furthermore, the description “LD n,R” is an instruction to write the value of the register specified by R to the address on the memory specified by n.
"CALL" is an instruction to call a program, and "RET" is an instruction to return processing to the caller.

The lower part of FIG. 24 ("ZANYO_1" in the figure) shows a program for interrupt wait processing in the main loop processing (S120). As can be seen with reference to FIG. 9, in the main loop process, random number update process (step S302) and performance display monitor total division process are executed while waiting for this interrupt.
First, in interrupt wait processing, interrupts are disabled by a DI command. The reason why interrupts are prohibited here is to prevent interrupt processing from being executed during the random number update processing executed by the next instruction. It also has the meaning of preventing interrupt processing from being executed during execution of an out-of-area program, which will be described later. If an interrupt processing program as an in-area program is executed while an out-of-area program is being executed, the interrupt processing program accesses the work memory in the used area and updates the memory. In other words, since the area inside the area will be updated while the program outside the area is being executed, interrupt processing is prohibited.

Next, various random number update processes are called and executed by the "CALL M_RNDJOB" command.

The values of the A register 106 and the F register 107 are saved in the memory by the "PUSH AF" command following the "CALL M_RNDJOB" command. The reason why this instruction is executed is because the contents of the F register 107 change when "LD SP,n" is executed in the out-of-area program to be described later, so it is necessary to save the contents of the F register 107.

The command "CALL_SHKSHM" following the above "PUSH AF" calls the performance display monitor aggregation/division process outside the area.

As shown in FIG. 25, in the performance display monitor total division process, first, a stack pointer that specifies an address outside the used area is set by the command "LD SP,_ESTPNT". Then, all registers from the B register 108 to the L register 113 are saved by the commands "LD (_RBCBUF), BC", "LD (_RDEBUF), DE", and "LD (_RHLBUF), HL" in the figure.
Various instructions after "LD (_RHLBUF),HL" perform processing to calculate values as performance information.

In the figure, the "LD BC,(_RBCBUF)", "LD DE,(_RDEBUF)", and "LD HL,(_RHLBUF)" instructions from two lines before the last line to four lines before the last line perform the process of restoring all registers. The stack pointer is restored by the "LD SP,_ISTPNT2" instruction one line before the final line. Then, the "RET" command on the last line returns the process to the caller. That is, the process returns to the program within the area.

In response to the above-mentioned "RET" command, the command "POP AF" after "CALL_SHKSHM" in FIG. 24 is executed. By this "POP AF", the values of the A register 106 and the F register 107 are restored.
Next, "EI" enables interrupt processing, "JR ZANYO_1" returns the processing to the beginning of "ZANYO_1", and loop processing as interrupt wait processing is realized.

Here, in the prior example, since there is one SP (stack pointer) register 116, the SP pointer 116 is shared by the program within the area and the program outside the area. For this reason, it is necessary to perform "PUSH AF" or "POP AF" processing when processing is transferred between inside the area and outside the area. In other words, when an in-area program calls an out-of-area program, these "PUSH AF" and "POP AF" commands must be written.
As mentioned above, the usage area is an area where programs related to the progress of gaming operations are placed, but in recent years, as gaming operations have become more complex, the program capacity and data capacity of the usage area has been increasing. Usage space tends to be squeezed. Therefore, it is required to reduce the program capacity in the used area.

[5-3. Processing migration method as an embodiment]

FIG. 26 is a diagram showing the register configuration of the CPU 20a in the embodiment.
As shown in the figure, the CPU 20a of the embodiment includes a PC register 100, an I register 101, and an R register 102, as well as a first register bank 121, a second register bank 122, and an IFF (interrupt control flag) register 125. There is.
Here, the register bank is a register group consisting of a plurality of registers including general-purpose registers. The first register bank 121 and the second register bank 122 each have a main register 123 and a sub-register 124, and the main register 123 corresponds to the table register 103 shown in FIG. , A register 106, F register 107, B register 108, C register 109, D register 110, E register 111, H register 112, L register 113, IX register 114, IY register 115, and SP register 116. .
The sub-registers 124 correspond to the back register 104 shown in FIG. 23, and include Q' register 105', A' register 106', F' register 107', B' register 108', C' register 109', It has a D' register 110', an E' register 111', an H' register 112', an L' register 113', an IX' register 114', and an IY' register 115'.
Note that the main register 123 has a U register 130, and this U register 130 will be explained later.

The IFF register 125 is a register for storing an interrupt control flag IFF. The interrupt control flag IFF is a flag for managing the permission/prohibition state of interrupt processing, that is, the interrupt control state. In this example, two types of interrupt control flags IFF are handled: "IFF1" and "IFF2." Correspondingly, the IFF register 125 can store interrupt control flags IFF1 and IFF2 individually.
Here, of the interrupt control flags IFF1 and IFF2, only the IFF1 side is used as a reference value for the interrupt control state, and IFF2 is used auxiliary to manage the value of IFF1.

In this embodiment, a first register bank 121 and a second register bank 122 are provided as shown in FIG. Used by the program. That is, when transitioning from processing of an in-area program to processing of an out-of-area program, the register bank to be used is switched from the first register bank 121 to the second register bank 122. Conversely, when transitioning from processing of a program outside the area to processing of a program within the area, the register bank to be used is switched from the second register bank 122 to the first register bank 121.

As described above, the first register bank 121 and the second register bank 122 are provided, and the first register bank 121 is used for inside the area and the second register bank 122 is used for outside the area. It becomes possible to use a dedicated SP register 116 for each external program, and there is no need to execute "PUSH AF" or "POP AF". Therefore, it is possible to reduce the program capacity for programs within the area.

Furthermore, in this embodiment, "CALLEX" and "RETEX" are used as commands that can be substituted for "CALL" and "RET".
"CALLEX" is an instruction that calls a program outside the area from a program within the area. Specifically, it is an instruction to disable interrupt processing (DI), and to switch the register bank to be used (from the first register bank 121 to the second register bank 122). This is a single instruction that aggregates the commands (switch to) and the CALL command of the specified out-of-area program.
“RETEX” is an instruction for returning from an outside-area program to an inside-area program, and specifically, an instruction to switch the register bank to be used (switch from the second register bank 122 to the first register bank 121); This is a single instruction that includes an execution instruction for returning the interrupt control state (enabled/disabled) to the state immediately before execution of the CALLEX instruction, and a RET instruction for returning the processing to the caller.

Here, in order to make it possible to disable interrupts with "CALLEX" and return the interrupt control state to the state immediately before the execution of the CALLEX instruction with "RETEX", we need to use "CALLEX", "RETEX", " When executing DI and EI, it is specified that the interrupt control flag IFF is updated as follows.
FIG. 27 is an explanatory diagram of the update rule for the interrupt control flag IFF.
As shown in the figure, when the "DI" instruction is executed, both interrupt control flags IFF1 and IFF2 are set to "0" (prohibited value) indicating that interrupts are disabled. On the other hand, when executing the "EI" instruction, both interrupt control flags IFF1 and IFF2 are set to "1" (permission value) indicating permission for interrupts.
Further, when executing the "CALLEX" instruction, the interrupt control flag IFF1 is set to "0" which is a prohibited value, and the value of the interrupt control flag IFF2 is maintained (that is, it is not changed). Furthermore, when executing the "RETEX" instruction, the value of the interrupt control flag IFF2 is substituted for the interrupt control flag IFF1. At this time, the value of the interrupt control flag IFF2 is maintained.

By updating the interrupt control flag IFF according to the above rules, execution of the "CALLEX" instruction realizes an interrupt disabled state, and execution of the "RETEX" instruction changes the interrupt control state to immediately before the execution of the CALLEX instruction. will be returned to the state of

FIGS. 28 and 29 show examples of programs in which “CALLEX” and “RETEX” are applied to the programs related to processing transition between the inside and outside of the area illustrated in FIGS. 24 and 25.
Note that, in FIGS. 28 and 29, among the various instructions shown in FIGS. 24 and 25, respectively, instructions that are omitted due to the application of the method of the embodiment are shown grayed out.

As mentioned above, by providing the first register bank 121 and the second register bank 122, the "PUSH AF" required when calling an out-of-area program in an in-area program and the return from an out-of-area program can be easily performed. "POP AF", which was sometimes required, is no longer necessary.
Thereby, it is possible to reduce the program capacity for programs within the area.

Here, since "CALLEX" includes a "DI" instruction, the effect of reducing the number of "DI" instructions (the effect of reducing program capacity) may be obtained in some cases. In the example of FIG. 24, the program configuration is such that random number update processing is performed before calling the out-of-area program, so the "DI" instruction is executed before the random number update processing, and the out-of-area program is called with interrupts disabled. will be held. In such a case, since it is not necessary to execute a "DI" instruction to call a program outside the area, the effect of reducing "DI" instructions by applying "CALLEX" cannot be obtained. However, in the interrupt enabled state, a program configuration may be adopted that calls a program outside the area. In such a case, the "DI" instruction will be executed before the out-of-area program is called by "CALL", so by applying "CALLEX", the number of "DI" instructions can be reduced, and the program The effect of reducing capacity can be obtained.

In the embodiment, by providing the second register bank 122 for use outside the area, there is no need to save or restore register values when transitioning from an in-area program to an out-area program. Therefore, in the out-of-area program (Figure 29), the instructions "LD (_RBCBUF), BC", "LD (_RDEBUF), DE", "LD (_RHLBUF), HL" to save the register value, The "LD BC,(_RBCBUF)", "LD DE,(_RDEBUF)", and "LD HL,(_RHLBUF)" instructions are used to restore the saved values, and the instructions are used to restore the stack pointer value within the area. There is no need to write the "LD SP,_ISTPNT2" command.

Here, as understood with reference to the program illustrated in FIG. 28, in this embodiment, in the area program, after executing the "DI" instruction and before executing the "EI" instruction, Executing the "CALLEX" instruction. This means that if the "EI" command is the "first command", the "DI" command is the "second command", and the "CALLEX" command is the "third command", then the first command is executed after the second command is executed. In other words, the third instruction is executed before the execution.

When executing an out-of-area program, it is necessary to disable interrupts. Based on this premise, if EI (first instruction) is executed before CALLEX (third instruction) is executed, the interrupt disabled state and interrupt enabled state will frequently switch.
Specifically, when performing EI before CALLEX, interrupts are disabled at the first DI in the loop process → execution of random number update processing → interrupts are enabled at EI → interrupts are disabled at CALLEX → interrupts are enabled at RETEX. . In other words, the number of times of switching within the main loop processing is 3 times. On the other hand, in the case of an embodiment in which EI is performed after CALLEX, the interrupt disabled state is maintained continuously from the first DI to the execution of the program outside the area and the return to the program within the area, and then the state is switched to the interrupt enabled state by EI. . That is, the number of times of switching within the main loop processing is 1.
Therefore, if EI is performed before CALLEX, the control state will change frequently and control stability will be impaired, but according to an embodiment in which EI is performed after CALLEX, the number of times the control state changes can be reduced. This makes it possible to improve control stability.

Further, according to the migration method as the embodiment described above, since PUSH and POP processing is not necessary, it is possible to improve the processing speed.

30 and 31 show examples of programs in which CALLEX and RETEX are applied to the calling of an out-of-area program in the timer interrupt processing on the main control side shown in FIG. 18. A program (intra-area program) is illustrated, and FIG. 31 illustrates a program (outer-area program) corresponding to the performance display monitor display process in step S916.
Note that in FIG. 30, for convenience of illustration, instructions corresponding to the WDT clearing process in step S918 are not shown. In addition, in each of the figures including FIGS. 30 and 31, and up to FIG. 63 illustrated below, instructions that are omitted due to the application of CALLEX and RETEX are shown grayed out, similar to the previous FIGS. 28 and 29. ing.

In FIG. 30, if the CALL instruction is used instead of CALLEX to call the performance display monitor display processing, which is an out-of-area program (that is, if the register configuration shown in FIG. 23 is adopted), the necessary instruction is "PUSH AF" → "DI" → "CALL _SHYMT" → "POP AF" → "EI" → "RETI", but when using CALLEX (when adopting the register configuration shown in Figure 26), the necessary instruction is "CALLEX _SHYMT". " → "EI" → "RETI", and by reducing the number of "PUSH AF", "DI", and "POP AF" instructions, it is possible to reduce the program capacity of programs within the area.

In the performance display monitor display processing program shown in FIG. 31, first, a stack pointer that specifies an address outside the used area is set by the command "LD SP,_ESTPNT". In the case of a precedent example that uses CALL or RET, "LD (_RBCBUF),BC", "LD (_RDEBUF),DE", "LD ( _RHLBUF),HL'' were required, but these instructions are omitted in this embodiment.
In the figure, each command from "RWM initial determination" to "initial display timer subtraction process" is a command for realizing the process of displaying the value of performance information on the setting/performance display 97. After these instructions, in the preceding example, the instructions "LD BC,(_RBCBUF)", "LD DE,(_RDEBUF)", and "LD HL,(_RHLBUF)" are used to restore the saved value to the register, and Although the instruction "LD SP,_ISTPNT2" for restoring the stack pointer in the area was required, these instructions are also omitted in this embodiment.
"RETEX" in the last line switches the register bank to be used from the second register bank 122 to the first register bank 121, returns the interrupt control state (in this case, maintains the disabled state), and returns the processing to the caller. A return is made.

Note that the "EI" command one line before the last line in FIG. 30 is not essential. If the interrupt control state immediately before the execution of the CALLEX instruction in FIG. 30 is the "interrupt enabled state", the interrupt control state when returning to the program in the area is changed to the "interrupt enabled state" by executing the RETEX instruction shown in FIG. 31. To become.

Here, in FIGS. 29 and 31, in the first line of the out-of-area program, the instruction "LD SP,_ESTPNT" is executed, that is, the out-of-area program uses the SP register 116 in the second register bank 122. It is assumed that the process of storing the stack memory address value (the stored value of "ESTPNT" on the memory) is executed. This can be rephrased as follows. That is, when calling by specifying the first address of an out-of-area program using the "CALLEX" command in the in-area program ("CALLEX_SHKSHM" in Figure 28), and when calling by specifying the second address ("CALLEX_SHKSHM" in Figure 30). _SHYMT"), and in the out-of-area program, whether the first address is called or the second address is called, the stack memory common to the SP register 116 of the second register bank 122 is This is to execute an instruction (fifth instruction) to store address information (the stored value of "ESTPNT").

This makes it possible to reset the value of the stack pointer used by the out-of-area program each time the out-of-area program is called.
Therefore, even if the stored value of the second stack pointer changes due to some kind of malfunction after the execution of a certain out-of-area program, the correct stack pointer value will be set when another out-of-area program is executed. This can improve the stability of stack processing by out-of-area programs.

Note that the stack pointer value that should be set at the start of out-of-area program processing is a fixed value of "ESTPNT", so "LD SP,_ESTPNT" must be executed every time out-of-area program processing starts. is not required. Specifically, the command "LD SP,_ESTPNT" only needs to be executed at least when the out-of-area program is executed each time the gaming machine is started.
For example, if the out-of-area program in FIG. 29 is executed before the out-of-area program in FIG. 31, the instruction "LD SP,_ESTPNT" only needs to be executed in the out-of-area program in FIG. 29. Or, conversely, if the out-of-area program in FIG. 31 is executed before the out-of-area program in FIG. 29, "LD SP,_ESTPNT" only needs to be executed in the out-of-area program in FIG. 31. .
This can be rephrased as follows. In other words, when an in-area program executes a CALLEX instruction to call an out-of-area program, specifying the first address of the out-of-area program (calling either the out-of-area program in FIG. 29 or 31). ) and later, there are cases in which the second address is specified and called (in which case the other out-of-area program in FIG. 29 or 31 is called), and in the out-of-area program, the first address is Only when called, an instruction (sixth instruction) for storing address information of the common stack memory in the second stack pointer is executed.

As mentioned above, the stack memory address information that should be set at the start of processing of an out-of-area program is fixed address information, so the program at the second address is executed after the program at the first address as an out-of-area program. In this case, it is sufficient that the storage process of address information for the second stack pointer is performed only in the program at the first address that is executed first.
Therefore, processing efficiency can be improved by executing an instruction to store address information of a predetermined stack memory in the second stack pointer only when the first address is called as described above.

[5-4. Another example of a program]

32 and 33 show another example of the program shown in FIGS. 28 and 29 above. Specifically, another example of the program (FIG. 32) corresponding to the part that calls the out-of-area program in the main loop process (S120) and another example of the out-of-area program (FIG. 33) that is called by the process of FIG. 32 are shown. It shows.

34 and 35 show another example of the program shown in FIGS. 30 and 31, that is, another example of the main control side timer interrupt processing program (FIG. 34) and an outside area called in the timer interrupt processing. Another example of the program (FIG. 35) is shown.

In addition, in the out-of-area programs shown in FIGS. 33 and 35, the address on the memory that stores the value to be set in the second stack pointer (SP register 116 in the second register bank 122) is as shown in FIGS. 29 and 31. It is defined as "@RWM2SP" instead of "ESTPNT".
As can be seen by referring to the instruction "LD SP,@RWM2SP" in FIGS. 33 and 35, here, the common address as the storage value of "@RWM2SP" is stored in the second stack pointer every time the out-of-area program is executed. Although an example is given in which information is set, in this case as well, it is also possible to perform storage processing of address information for the second stack pointer only in the out-of-area program that is executed first.

FIGS. 36 to 53 show examples of programs when the process transfer method according to the embodiment is applied to the process of the main control unit in a reel-type gaming machine (slot machine).
36, FIG. 38, FIG. 40, FIG. 42, FIG. 44, FIG. 46, FIG. 48, FIG. 50, and FIG. Examples of programs for various processes including instructions for calling external programs are shown. Specifically, FIG. 36 shows the initial setting process when the power is turned on, FIG. 38 shows the game execution process, FIG. 40 shows the process according to the insertion of game medals and operation of the start lever, and FIG. FIG. 44 shows an example of a program for the role ratio monitor display related information update process, FIG. 46 shows a setting change process, FIG. 48 shows a condition device signal output process, FIG. 50 shows a game medal insertion process, and FIG. 52 shows a game medal insertion error process. ing.
37, FIG. 39, FIG. 41, FIG. 43, FIG. 45, FIG. 47, FIG. 49, FIG. 51, and FIG. Specifically, FIG. 37 shows the outside work area process 3, FIG. 39 shows the replay state identification signal output process, FIG. 41 shows the condition device signal output clear process, FIG. 43 shows the condition device signal output process, and FIG. Examples of programs include the role ratio monitor control process, FIG. 47 shows the outside work area process 1, FIG. 49 shows the condition device signal output monitoring process, FIG. 51 shows the retention check process, and FIG. 53 shows the programs for the outside work area process 2. .

Regarding the program in the area exemplified here, for example, "(DI guarantee)" shown in FIGS. 36, 38, 40, etc. means that the interrupt is disabled at least in the line where the (DI guarantee) is written. This means that it is guaranteed that the DI instruction has been executed in any line before this line.

Among the area programs exemplified here, the area programs shown in FIGS. 38, 40, and 48 execute the “CALLEX” instruction after executing the “DI” instruction and before executing the “EI” instruction. This corresponds to the example of executing .
Thereby, it is possible to prevent the interrupt control state from frequently switching, and it is possible to improve the stability of control.

In particular, in the program shown in Figure 48, two CALLEX instructions are written consecutively, but in this case, if after executing the "DI" instruction and before executing the "EI" instruction, ” instruction is not executed, but instead the “EI” instruction is executed before the “CALLEX” instruction is executed, the number of times the interrupt control state is switched is five. Specifically, a total of 6 times: DI → EI → CALLEX (switch to interrupt disabled state) → RETEX (return to interrupt enabled state) → CALLEX (switch to interrupt disabled state) → RETEX (return to interrupt enabled state) . On the other hand, if a method is adopted in which the "CALLEX" instruction is executed after the "DI" instruction is executed but before the "EI" instruction is executed as in the embodiment, the number of times the interrupt control state is switched is one. This can improve the stability of control.

As can be seen by referring to "LD SP,CMN_STACK" shown in the first line of each figure in FIG. 37, FIG. 39, FIG. 41, FIG. 43, FIG. 45, FIG. The storage address of the stack pointer for the unused area (the value to be set in the SP register 116 in the second register bank 122) in this case is defined as "CMN_STACK".
As can be understood from the fact that the instruction "LD SP,CMN_STACK" is included in each figure such as FIG. An example of setting is given.

In the case of a reel-type gaming machine, there are three or more types of out-of-area programs that are called from in-area programs. In this way, when there are three or more types of out-of-area programs to be called, at least with regard to the relationship between two of them, storage processing of address information for the second stack pointer is performed only in the out-of-area program that is executed first. It is also possible to have it performed. At this time, in order to improve processing efficiency, it is desirable that the storage process of address information for the second stack pointer be executed only in the first out-of-area program to be executed among three or more types of out-of-area programs. .

[5-5. Program modification example]

Next, modified examples of the program will be described with reference to FIGS. 54 to 63.
In the explanation so far, an example has been given in which a register bank switching instruction used in CALLEX or RETEX is included, but the register bank switching instruction can also be defined as an independent instruction. Here, an example will be given in which the register bank switching instruction (mnemonic) is defined as "BANKF," but the specific name of the switching instruction is not limited to "BANKF."

When using an independent register bank switching instruction as "BANKF", one "CALL" instruction, two "BANKF" instructions, and one "RET" command will be used.
54, FIG. 56, FIG. 58, and FIG. 60 show various program examples that can be considered as application examples of the "BANKF" command to the initial setting process at power-on illustrated in FIG. 36 above. FIGS. 55, 57, 59, and 61 show examples of out-of-area programs (out-of-area work area processing 3) called by the in-area programs in FIGS. 54, 56, 58, and 60, respectively. .

In the example shown in the set of FIGS. 54 and 55, the "BANKF" command for switching the register bank from the first register bank 121 for inside the area to the second register bank 122 for outside the area is executed on the outside program side, and This is an example in which a "BANKF" command for switching from the second register bank 122 for external use to the first register bank 121 for intra-area use is executed on the intra-area program side.
In this case, the in-area program switches the register bank from the second register bank 122 to the first register bank 121 following the "CALL" instruction (CALL O_CLRWM3) for calling the target out-of-area program, as shown in FIG. The "BANKF" command is written for this purpose. In addition, in the out-of-area program in this case, as shown in FIG. 55, the "BANKF" instruction for switching the register bank from the first register bank 121 to the second register bank 122 is written in the first line, and "BANKF" is written in the last line. RET” command is written.

Here, in the out-of-area program shown in FIG. 55, the "LD SP,CMN_STACK" instruction (setting the second stack pointer) is written in the second line, but the out-of-area program side When executing the "BANKF" instruction for switching to the second register bank 122, the "BANKF" instruction is executed before executing the "LD SP, CMN_STACK" instruction.

The example shown in the set of FIGS. 56 and 57 includes a "BANKF" command for switching from the first register bank 121 to the second register bank 122, and a "BANKF" command for switching from the second register bank 122 to the first register bank 121. ” This is an example in which both instructions are executed by the program within the area.
In the area program in this case, as shown in FIG. 56, the "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 is written in the line immediately before the "CALL" instruction, and the "CALL" A "BANKF" command for switching from the second register bank 122 to the first register bank 121 is written on the next line of the command.

In the example shown in the set of FIGS. 58 and 59, a "BANKF" command for switching from the first register bank 121 to the second register bank 122 is executed on the area program side, and the switch from the second register bank 122 to the first register bank 122 is This is an example in which the "BANKF" command to switch to is executed on the outside program side.
As shown in FIG. 58, in the in-area program in this case, a "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 is written in the line immediately before the "CALL" instruction, and the out-of-area program As shown in FIG. 59, a "BANKF" command for switching from the second register bank 122 to the first register bank 121 is written in the line immediately before the "RET" command.

The example shown in the set of FIGS. 60 and 61 includes a "BANKF" command for switching from the first register bank 121 to the second register bank 122, and a "BANKF" command for switching from the second register bank 122 to the first register bank 121. This is an example in which both commands are executed on the out-of-area program side. As shown in FIG. 61, in the out-of-area program in this case, the "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 is written on the first line, and the "RET" instruction is written on the line immediately before the "RET" instruction. A “BANKF” instruction for switching from the second register bank 122 to the first register bank 121 is written.

By defining the "BANKF" command as described above, options other than CALLEX and RETEX (CALL and BANKF, or RET and BANKF) are provided as commands to realize processing transition between inside the area and outside the area. This makes it possible to improve the degree of freedom in program creation.

Here, it is not essential to apply CALLEX and RETEX to all processing transitions between within the area and outside the area. For example, in an in-area program, there are situations in which CALL and RET can be used as usual instead of CALLEX and RETEX, depending on the processing content of the program before and after a call instruction for an out-of-area program. For example, in a situation where there is a process to be performed with interrupts disabled after returning to the area by a return instruction to the program in the area, there is no need to execute EI when returning to the area, so CALL, instead of CALLEX, RETEX, Even if RET is used, an appropriate interrupt control state can be achieved.

The combination of FIGS. 62 and 63 shows an example of a program inside the area and outside the area when CALL and RET are used in such a situation.
Note that although FIGS. 62 and 63 show program examples when the second register bank 122 for use outside the area is not used, for example, by using "BUNKF" explained in FIGS. 54 and 55, Omitting instructions for saving and restoring AF ("PUSH AF" and "POP AF") in a program, and omitting instructions for saving and restoring the stack pointer (stack pointer for use within the region) in programs outside the area ("PUSH AF" and "POP AF") LD (W_STKBAK),SP", "LD SP,(W_STKBAK)") and instructions for saving and restoring all registers ("PUSH ALL", "EX AF,AF'", "EXX", "PUSH GPR", "POP GPR") ", "EX AF,AF',""EXX,""POPALL") may be omitted.

[5-6. Other variations]

In addition, in the explanation so far, when calling a program outside the area from a program within the area, after executing DI (second instruction) and before executing EI (first instruction), CALLEX (third instruction) is called. ), but it is also possible to execute CALLEX after executing EI, or in other words, execute EI before CALLEX.
By executing EI before executing CALLEX, the duration of the interrupt disabled state can be shortened. In other words, it is possible to suppress processing delays due to the inability to execute interrupt processing.

Here, in the gaming machine 1 of this example, winning information is updated in the timer interrupt process (see the prize ball management process in S908). Of the various out-of-area programs exemplified, in the performance display monitor total division process shown in FIG. 29 and the like, the value of the performance information is calculated using the winning information updated in the interrupt process. Therefore, if you adopt a method of executing EI before CALLEX when calling such performance display monitor aggregate division processing, the calculation of performance information in the out-of-area program will be performed based on the information updated immediately before. This can be done using winning information, which is preferable.

<6. About Q register and U register>

Next, the Q register (Q register 105 and Q' register 105') and U register 130 will be explained.
First, the memory address space of the CPU 20a in the main control section 20 will be explained with reference to the memory map of FIG.
As shown in the figure, a total of 65,536 bytes of space from address 0000h (h means hexadecimal number) to address FFFFh is prepared as the memory address space of the CPU 20a.
An area of 16384 bytes (16 kbytes) from address 0000h to address 3FFFh is an area of the built-in ROM, and an area of 1024 bytes (1 kbyte) from address F000h to address F3FFh is an area of the built-in RAM.
The area from address 4000h to address EFFFh located between the areas of the built-in ROM and built-in RAM is an unused area.

The area from address F400h to FDFFh is an unused area, the area from address FE00h to FEFFh is an area of built-in register 1, and the area from address FF00h to address FFCFh is an area of built-in register 2.

The area from address FFD0f to address FFFFh is an XCS decoding area.
Here, the CPU 20a of this example employs a memory mapped I/O method as a data input/output management method. As is well known, memory mapped I/O is a method of allocating I/O registers to the same address space as data memory.
In this example, a storage area corresponding to an I/O register is allocated to the XCS decode area. In this sense, the XCS decode area is hereinafter referred to as an "input/output port area (I/O port area)."

As described above with reference to FIG. 21, the memory area accessible by the CPU 20a is divided into a used area as a first memory area and an unused area as a second memory area. FIG. 64 shows the division of the used area and unused area in the built-in RAM area, and as shown in the figure, in the built-in RAM area in this example, an area of 512 bytes from address F000h to address F1FFh is used. An area of 256 bytes from address F200h to address F2FFh is set as an unused area.

Based on the above, the Q register and the "LDQ" instruction, which is an instruction related to the Q register, will be explained.
The Q register 105 and the Q' register 105' are registers that store the upper values of some addresses handled by the "LDQ" instruction. In this example, these Q register 105 and Q' register 105' are 8-bit (1 byte) registers.

The "LDQ" instruction is written, for example, as "LDQ R,m" (R means a value specifying a register, m means a value specifying an address on memory) or "LDQ m,R". It functions as a load instruction similar to the "LD" instruction, and basically writes the value of the location specified on the right side to the location specified on the left side after writing "LDQ". The difference from the "LD" instruction is that only the lower value of the address on memory needs to be written as the value of "m". That is, the "LDQ" instruction is an instruction that accesses an address with the value described as "m" as the lower value and the value stored in the Q register 105 or Q' register 105' as the upper value. Specifically, for "LDQ R,m", for the register specified by "R", the value of "m" is the lower value, and the value stored in the Q register 105 or Q' register 105' is the upper value. This is an instruction to write the value stored at the address in the memory. In addition, in the case of "LDQ m,R", specify by "R" the address on the memory where the value of "m" is the lower value and the value stored in Q register 105 or Q' register 105' is the upper value. This is an instruction to write the value of the specified register.

The Q register is a register provided to implement such an "LDQ" instruction. By providing the Q register, there is no need to write the upper value of the address in the program, and the program capacity can be reduced.

Here, in this example, the above-mentioned "LDQ" command is applied to access to the used area in the built-in RAM area shown in FIG. 64. Therefore, "F0h" and "F1h" are stored in the Q register 105 and Q' register 105', respectively.
As shown in FIG. 64, the used area in the built-in RAM is set as an area from address F000h to address F1FFh. In other words, the used area has a size exceeding 256 bytes, which can be covered by the lower 1 byte (8 bits) of the address value. Therefore, if only one Q register is provided, the above "LDQ" instruction can only be applied to areas where the upper address value in the used area is either "F0h" or "F1h". .
In this example, by providing two Q registers, the Q register 105 and the Q' register 105', the "LDQ" instruction can be applied to any address in the used area of the built-in RAM.

In this example, "F0h" and "F1h" as described above are stored not only in the Q register 105 and Q' register 105' in the first register bank 121, but also in the Q register 105 in the second register bank 122. , Q' register 105'. The storage process of "F0h" and "F1h" in these Q register 105 and Q' register 105' is automatically performed as initial value setting process for Q register 105 and Q' register 105' when the CPU 20a is started after being reset. is executed.
Alternatively, the process of storing "F0h" and "F1h" in these Q register 105 and Q' register 105' may be executed, for example, in "various settings processing at startup" (S206) in "initial setting processing" (S101). You can also do it.

As mentioned above, the second register bank 122 is a group of registers used by out-of-area programs.
As described above, by storing "F0h" and "F1h" in the Q register 105 and Q' register 105' of the second register bank 122, respectively, the out-of-area program can store the used area in the built-in RAM. The "LDQ" command can also be used when referencing data. In other words, the program capacity can be reduced by using the "LDQ" instruction even for programs outside the area.
For confirmation, it is not permitted for an out-of-area program to update the data in the used area, but it is permitted to refer to it (see FIG. 22).

For actual usage examples of the "LDQ" command, please refer to FIGS. 36, 39, 40, 42, 43, 46, 50, etc. Among these, the "LDQ" instruction shown in FIGS. 39 and 43 corresponds to an instruction that accesses the address of the used area when executing an out-of-area program.

In order to properly access and divide the used area of the built-in RAM using the "LDQ" instruction, it is necessary to switch the Q register referenced by the "LDQ" instruction depending on the address to be accessed within the used area. . Specifically, it is necessary to appropriately switch which of the Q register 105 and Q' register 105' to refer to.

In this example, such switching of the Q register is realized by an "EX" instruction. Specifically, this is realized by the command "EX Q,Q'".
In this example, the "EX Q,Q'" instruction is an instruction for toggling the Q register referred to by the "LDQ" instruction between the Q register 105 and the Q' register 105'. That is, in response to the command "EX Q, Q'" in a state where the referenced Q register=Q register 105, the referenced Q register is switched to the Q' register 105'. Further, the Q register to be referred to is switched to the Q register 105 in response to the command "EX Q, Q'" in a state where the Q register to be referred to is the Q' register 105'.

In addition, in the above example, the area to which the "LDQ" instruction is applied (that is, the area used in the built-in RAM in this example) is an area of 256 x 2 = 512 bytes, and two Q registers are provided accordingly. However, the area to which the "LDQ" instruction is applied can be larger than 512 bytes. In that case, by setting the number of Q registers to three or more, the "LDQ" instruction can be used when accessing any address within the target area.

Next, the U register 130 will be explained.
The U register 130 is a register that stores the upper address value of the input/output port area shown in FIG. 64. Specifically, "FFh" is stored in the U register 130 in this example.
By providing this U register 130, when specifying the access destination address of the input/output port area in an input/output instruction ("IN" instruction or "OUT" instruction), it is necessary to write the upper value of the access destination address in the program. It becomes possible to eliminate

Note that although memory mapped I/O is used in this example, commands related to data input/output are the same as when using port mapped I/O, such as "IN" commands and "OUT" commands. (See, for example, FIG. 38, FIG. 40, FIG. 48, etc.).
Specifically, the "IN" instruction in this case is written as "IN r,m", which means that the value written as "m" is lower-ordered for the register specified by "r". This is an instruction to write a value stored in an address in the input/output port area (that is, a virtual input/output register) with the value stored in the U register 130 as the upper value. Furthermore, the "OUT" instruction is written as "OUT m,r", which is an input/output port with the value written as "m" as the lower value and the value stored in the U register 130 as the upper value. This is an instruction to write the value stored in the register specified by "r" to the address within the area.
Furthermore, as understood from the explanation of the "IN" and "OUT" instructions above, when memory mapped I/O is adopted, the "LD" instruction can also be used as an instruction related to data input/output. .

As shown in FIG. 26, in this example, only one U register 130 is provided in each of the first register bank 121 and the second register bank 122. Specifically, in each of the first register bank 121 and the second register bank 122, the U register 130 is provided as one of the main registers 123.
By providing the U register 130 also for the second register bank 122, the input/output port area can be accessed using the upper value of the address stored in the U register 130 even when a program outside the area is executed. is possible. In other words, it is possible to eliminate the need to write the upper value of the access destination address in an "IN" instruction or "OUT" instruction even in an out-of-area program.

As described above, the input/output port area is an area from address FFD0h to address FFFFh, and the area size is 48 bytes. In other words, it is the area size that can be covered by the lower value of the address.
Therefore, in each of the first register bank 121 and the second register bank 122, the number of U registers 130 is singular.

Here, as mentioned above, regarding the Q register, a common value is stored in each of the Q register 105 and the Q' register 105' in the first register bank 121 and the second register bank 122, respectively, but the U register 130 Also, a common value is stored in each of the first register bank 121 and the second register bank 122. Specifically, in this example, "FFh" is stored in each U register 130.
Such a process of storing "FFh" in the U register 130 is automatically executed as an initial value setting process for the U register 130 when the CPU 20a is started after being reset.
Alternatively, the process of storing "FFh" in the U register 130 can also be executed, for example, in the "various setting process at startup" (S206) in the "initial setting process" (S101).

In addition, in the above explanation of the Q register, it was mentioned that the "EX" instruction is used when accessing an area with a different upper address value, but it is not necessary to use the "EX" instruction, and in some cases Access can also be performed by writing the upper value of the access destination address in the program.
For example, when accessing the address of the upper value "F1h" with Q register 105 selected as the Q register to be used, instead of switching the Q register to be used to Q' register 105' with the "EX" instruction. , address information including the upper value "F1h" may be written in the program as access destination address information. Alternatively, when accessing the address of the upper value "F0h" with Q'register 105' selected as the Q register to be used, instead of switching the Q register to be used to Q register 105 with the "EX" instruction. , address information including the upper value "F0h" may be written in the program as information on the access destination address.
Here, in the former case, the Q register is used when accessing the address of the upper value "F0h", but is not used when accessing the address of the upper value "F1h". Furthermore, in the latter case, the Q register is used when accessing the address of the upper value "F1h", but is not used when accessing the address of the upper value "F0h". That is, in these cases, the Q register may or may not be used when the used area on the memory (that is, the target area on the memory) is accessed.
On the other hand, since the U register 130 targets only the area with the upper address value "FFh", it is always used when the target area on the memory is accessed.

<7. Summary of embodiments>

As described above, the first gaming machine as an embodiment includes a first register group (first register bank 121) each including a plurality of general-purpose registers, and a second register group (second register bank 122). ), a first interrupt management register (IFF1 of the IFF register 125), and a second interrupt management register (IFF2 of the IFF register 125).
Additionally, there is a first instruction (``EI'' instruction) that writes enabled values to the first and second interrupt management registers, and a second instruction (``EI'' instruction) that writes prohibited values to the first and second interrupt management registers. DI" instruction), the third instruction ("CALLEX" instruction) used when calling an out-of-area program from an in-area program, and the fourth instruction ("CALLEX" instruction) used when returning from an out-of-area program to an in-area program. "RETEX" command).
The third instruction can execute processing to write a prohibited value to the first interrupt management register and switch the register group used from the first register group to the second register group before calling the out-of-area program. The fourth instruction overwrites the value of the second interrupt management register to the first interrupt management register and changes the register group to be used from the second register group to the first register group before returning to the program in the area. It is possible to execute processing to switch to .
Furthermore, in the intra-area program, after executing the second instruction, but before executing the first instruction, a third instruction is executed.

When executing a program outside the area, it is necessary to disable interrupts. Therefore, if the first instruction is executed before the third instruction is executed, the interrupt disabled state and interrupt enabled state will be frequently switched. On the other hand, if the third instruction is executed after the second instruction is executed but before the first instruction as described above, the interrupt-disabled state is maintained and the out-of-area program is executed. Since the call and return to the program within the area are performed, the number of times the interrupt control state is switched can be reduced.
Therefore, the number of times the control state is switched can be reduced, and the stability of control can be improved.

Further, in the first gaming machine as the embodiment, the first register group has a first stack pointer (SP register 116 of the first register bank 121) that stores a stack pointer, and the second register group has the following: It has a second stack pointer (SP register 116 of the second register bank 122) that stores the stack pointer, the first stack pointer stores the address information of the stack memory used in the program within the area, and the second stack pointer stores the address information of the stack memory used in the program within the area. , when storing the address information of the stack memory used by the out-of-area program, and calling the out-of-area program by specifying the first address of the out-of-area program when executing the third instruction in the in-area program and calling the out-of-area program. , there are cases where a second address is specified and called, and in an out-of-area program, whether the first address is called or the second address is called, the second stack pointer has a common stack. A fifth instruction for storing memory address information is being executed.

This makes it possible to reset the value of the stack pointer used by the out-of-area program each time the out-of-area program is called.
Therefore, even if the stored value of the second stack pointer changes due to some kind of malfunction after the execution of a certain out-of-area program, the correct stack pointer value will be set when another out-of-area program is executed. This can improve the stability of stack processing by out-of-area programs.

Furthermore, in the first gaming machine as an embodiment, the first register group has a first stack pointer that stores a stack pointer, and the second register group has a second stack pointer that stores a stack pointer. The address information of the stack memory used by the program within the area is stored in the first stack pointer, the address information of the stack memory used by the program outside the area is stored in the second stack pointer, and the address information of the stack memory used by the program within the area is stored. When executing the third instruction and calling an out-of-area program, there are cases where the first address of the out-of-area program is specified and called, and there are times when the second address is specified and called at a later timing. , in the out-of-area program, a sixth instruction for storing address information of a predetermined stack memory in the second stack pointer is executed only when the first address is called.

The stack memory address information that should be set for the second stack pointer at the start of processing of an out-of-area program is fixed address information, so as an out-of-area program, the second address is set after the program at the first address is executed. When a program is executed, it is sufficient to store address information in the second stack pointer only in the program at the first address, which is the program to be executed first.
Therefore, processing efficiency can be improved by executing an instruction to store address information of a predetermined stack memory in the second stack pointer only when the first address is called as described above.

A second gaming machine as an embodiment includes a control means for controlling game progress, and the control means has an accessible memory address space, a general-purpose register, and the storage means handled in some instructions. It has at least one register group (register bank) each including a plurality of upper value registers, each of which is a register that stores an upper value of an address.
In the memory address space, there is a first area (internal RAM area) with a predetermined area size, and a second area (internal RAM area) which is different from the first area and whose area size is smaller than the predetermined size. The upper value registers include a type 1 upper value register (Q register) related to the first area and a type 2 upper value register (Q register) that stores the upper value of the address in the second area. There are upper value registers (U registers), and in a register group, the number of first type upper value registers is plural, the number of type two upper value registers is singular, and there are multiple first type upper value registers in a register group. includes a first type 1 upper value register (Q register 105) and a second type 1 upper value register (Q' register 105').

By providing an upper value register, when accessing a required address in the first area or second area, the upper value stored in the upper value register is used to access the program. It becomes possible to eliminate the need to write values. In other words, it is possible to reduce the program capacity. At this time, depending on the number of bytes of the lower address value, it may not be possible to cover the entire area to be accessed. For example, assuming that the size of the area that can be covered by the lower address value is 256 bytes (that is, the lower address value = 1 byte), if the size of the first area exceeds 256 bytes, the lower address The value cannot cover the entire first area. In other words, in this case, it is necessary to use different upper address values for an area within 256 bytes and an area exceeding 256 bytes in the first area. Therefore, the first type upper value register includes a first type first upper value register and a second type first upper value register that stores a value consecutive to the stored value of the first type first upper value register. At least a register is provided. This makes it possible to access any address in the first area using the upper value stored in the upper value register, eliminating the need to write the upper value of the access destination address in the program. It becomes possible to eliminate it. Since the second area is smaller than the predetermined size, it is possible to eliminate the need to write the upper value of the access destination address in the program even if the number of second type upper value registers is singular.
Therefore, the program capacity can be reduced by having a plurality of type 1 upper value registers and a single type 2 upper value register as described above.

Further, in the second gaming machine as the embodiment, the second area is an area to which the input/output register of the control means is allocated.

This makes it possible to employ memory mapped I/O.
With memory-mapped I/O, there is no need to provide an I/O register as hardware, so the internal circuit of the control means can be simplified, and processing speed and cost can be reduced.

Furthermore, in the second gaming machine as an embodiment, the first area includes a used area that is an area made usable by an in-area program, and an unused area that is an area made usable by an outside area program. The used area consists of two areas with consecutive upper address values, and the unused area is an area where the upper address values are different from the used area. The program includes a first register group used in a program, and the first register group includes the first upper value register of the first type and the second upper value register of the first type.

This makes it possible to access any address in the used area using the address upper value stored in the corresponding one of the two first type upper value registers. In other words, it is possible to eliminate the need to write the upper value of the access destination address in the program within the area.
Therefore, it is possible to reduce the program capacity in the used area.

Furthermore, in the second gaming machine as an embodiment, the first area includes a use area that is an area made usable by an in-area program, and a use area that is an area made usable by an outside area program. It has two register groups: a first register group used by the program in the area and a second register group used by the program outside the area. There are a first type upper value register, a second type first upper value register, and a second type upper value register, and in each of the first and second register groups, the first type first upper value register, the second type A common value is stored in each of the first type upper value register and the second type upper value register.

That is, the same values as those in the first register group are stored in the two first type upper value registers and the single second type upper value register in the second register group. As a result, when accessing the first area or the second area when executing an out-of-area program (that is, when using the second register group), the information stored in the first type upper value register or the second type upper value register It becomes possible to use the upper value of the address. In other words, it is possible to eliminate the need to write an address upper value in an instruction for accessing the first area or the second area even for programs outside the area.
Therefore, it is possible to prevent the capacity of the out-of-area program from expanding unnecessarily.

1 Pachinko gaming machine 13 Production button 15a Cross key 15b Decision button 20 Main control board (main control unit)
20a CPU
20b ROM
20c RAM
24 Production control board (production control section)
24a CPU
24b ROM
24c RAM
36M Main liquid crystal display device 36S Sub-liquid crystal display device 38a, 38b Special symbol display device 45 Decorative lamp 45a Optical display device 46 Speaker 46a Sound generator 61 Front door open sensor 83 Handle sensor 94 Setting key switch 97 Setting/performance indicator 98 RAM Clear switch 100 PC (program counter) register 105 Q register 105'Q' register 116 SP (stack pointer) register 121 First register bank 122 Second register bank 125 IFF (interrupt control flag) register 130 U register

Claims (1)

Equipped with a control means for controlling the game,
The control means includes:
has an accessible memory address space, and
It has at least one register group each including a plurality of general-purpose registers and a plurality of upper value registers that are registers that store upper values of addresses in the memory address space handled in some instructions,
The upper value registers include a first type upper value register and a second type upper value register,
The first type upper value register is configured to store a first upper value, and the second type upper value register is configured to store a second upper value different from the first upper value,
When executing a first instruction, the first upper value of the first type upper value register is referred to, and when executing a second instruction different from the first instruction, the first upper value of the second type upper value register is referred to. A gaming machine that refers to the second highest value .

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