JP7282643B2 - game machine - Google Patents

Description

The present invention relates to a game machine, and more particularly to a register configuration of control means in the game machine.

For example, in a game machine such as a pinball game machine as a pachinko game machine or a reel-type game machine as a slot machine, an arithmetic processing device such as a CPU (Central Processing Unit) is provided as a control means for controlling the game progress. Various operations of the gaming machine are realized by the arithmetic processing unit performing processing according to instructions described in the program.

In addition, the following patent document 1 can be mentioned about related prior art.

JP 2019-141675 A

In recent gaming machines, as the number of functions to be implemented increases, the capacity of programs is also increasing, putting pressure on the memory.

Therefore, an object of the present invention is to reduce the program capacity.

A gaming machine according to the present invention comprises control means for controlling the progress of a game, the control means having an accessible memory address space, general-purpose registers, and the memory address space handled by some instructions. at least one register group including a plurality of upper value registers that store upper address values, and the memory address space includes a first area having a predetermined area size, and the first area. and a second region having a region size smaller than the predetermined size, wherein the upper value register includes a first type upper value register associated with the first region and a second region in the second region a second type upper value register for storing an upper value of an address, wherein in the group of registers, the number of the first type upper value registers is plural, the number of the second type upper value registers is singular, and the register The plurality of first type upper value registers in the group includes: a first first type upper value register; A seed high value register is included.

By providing the upper value register, when accessing a desired address in the first area or the second area, the access using the upper value stored in the upper value register enables the program to access the higher address of the address. It is possible to eliminate the need to describe the value. That is, it is possible to reduce the program capacity. At this time, depending on the number of bytes of the address lower value, the entire area to be accessed may not be covered. For example, assuming that the size of the area that can be covered by the lower address value is 256 bytes (that is, the lower address value = 1 byte), if the size of the first area exceeds 256 bytes, the lower address value The value cannot cover the entire first area. In other words, in this case, it is necessary to use different upper address values for the area within 256 bytes and the area exceeding 256 bytes in the first area. For this reason, as the first type upper value register, a first first type upper value register and a second first type upper value register that stores a value consecutive to the stored value of the first first type upper value register At least a register is provided. As a result, any address in the first area can be accessed using the upper value stored in the upper value register, eliminating the need to describe the upper value of the access destination address in the program. It is possible to eliminate it. Since the second area is smaller than the predetermined size, it is possible to eliminate the need to describe the upper value of the access destination address in the program even if there is only one type 2 upper value register.

Further, in the gaming machine according to the present invention described above, the second area may be an area to which the input/output registers of the control means are assigned.

This makes it possible to employ memory mapped I/O.

Further, in the gaming machine according to the present invention described above, the first area includes a use area that is an area made available by the inside-area program, and a non-use area that is an area made available by the outside-area program. The used area is composed of two areas with consecutive upper address values, and the unusable area is an area whose upper address value is different from that of the used area. and a first register group used at least in the intra-region program, wherein the first first class upper value register and the second first class upper value register are provided in the first register group. It is possible to

As a result, when accessing any address in the used area, it is possible to perform access using the address upper value stored in the corresponding one of the two first-class upper value registers. That is, it is possible to eliminate the need to describe the upper value of the access destination address in the intra-area program.

Further, in the gaming machine according to the present invention described above, the first area includes a use area that is an area made available by the inside-area program, and a non-use area that is an area made available by the outside-area program. a first register group used by the program inside the area and a second register group used by the program outside the area as the register groups, and each of the first and second register groups includes The first first class upper value register, the second first class upper value register, and the second class upper value register are provided, and each of the first and second register groups includes the first A common value may be stored in each of the first type upper value register, the second first type upper value register, and the second type upper value register.

That is, the same values as those on the first register group side are stored in the two first type upper value registers and the single second type upper value register in the second register group. As a result, when accessing the first area or second area when executing a program outside the area (that is, when using the second register group), the Address high value can be used. In other words, it is possible to eliminate the need to describe the address high-order value in the instruction for accessing the first area and the second area even for the program outside the area.

According to the present invention, it is possible to reduce the program capacity.

1 is a front perspective view showing the appearance of a gaming machine as an embodiment of the present invention; FIG. It is a diagram showing the configuration of the game board of the game machine as an embodiment. It is a block diagram showing the control configuration of the gaming machine as an embodiment. FIG. 11 is an explanatory diagram of an example of a pre-reading foretelling effect in the embodiment; 4 is a flowchart showing main processing on the main control side of the embodiment; FIG. 6 is a flow chart showing an initial setting process in FIG. 5; FIG. 4 is a flowchart showing power supply abnormality check processing according to the embodiment; FIG. 10 is a diagram showing the correspondence relationship between each determination condition in terms of operation and the value of the W register when transitioning to setting change processing, RAM clear processing, setting confirmation processing, and backup restoration processing; 6 is a flowchart showing main loop processing in FIG. 5; FIG. 6 is a flowchart showing a setting change process in FIG. 5; FIG. 11 is a flowchart showing output management processing in FIG. 10; FIG. 11 is a diagram showing an example of a 7-segment decoding table; FIG. 10 is a diagram illustrating the relationship between the segment configuration and the display pattern of the segments in the setting value indicator; FIG. 6 is a flowchart showing RAM clear processing in FIG. 5; FIG. FIG. 6 is a flowchart showing a setting confirmation process in FIG. 5; FIG. FIG. 10 is a diagram showing an example of a set value offset conversion table; FIG. 6 is a flow chart showing main loop pre-processing in FIG. 5 ; FIG. It is the flowchart which showed the main control side timer interrupt processing of embodiment. FIG. 19 is a flow chart showing power supply check/backup processing in FIG. 18; FIG. FIG. 19 is a flow chart showing a setting abnormality check process in FIG. 18; FIG. FIG. 4 is an explanatory diagram of areas set in a memory of a main control unit; FIG. 4 is an explanatory diagram of regulations set for each area; FIG. 10 is a diagram showing a register configuration in a prior example; FIG. 9 is a diagram exemplifying a program of a portion mainly corresponding to main loop processing (FIG. 9) in main control side main processing (FIG. 5); FIG. 11 is a diagram illustrating a program related to performance display monitor total division processing (S304); It is a diagram showing a register configuration in the embodiment. FIG. 10 is an explanatory diagram of an interrupt control flag update rule in the embodiment; FIG. 10 is a diagram illustrating an intra-area program when a process transition method as an embodiment is applied; FIG. 10 is a diagram illustrating an out-of-area program when a process transition method as an embodiment is applied; FIG. 10 is a diagram showing another example of an intra-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an out-of-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an intra-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an out-of-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an intra-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an out-of-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an intra-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an out-of-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an intra-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an out-of-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an intra-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an out-of-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an intra-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an out-of-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an intra-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an out-of-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an intra-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an out-of-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an intra-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an out-of-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an intra-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an out-of-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an intra-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing another example of an out-of-area program when applying the process transition method as an embodiment; FIG. 10 is a diagram showing a modification of an intra-area program related to a register bank switching instruction; FIG. 10 is a diagram showing a modification of an out-of-area program related to a register bank switching instruction; FIG. 10 is a diagram showing a modification of an intra-area program related to a register bank switching instruction; FIG. 10 is a diagram showing a modification of an out-of-area program related to a register bank switching instruction; FIG. 10 is a diagram showing a modification of an intra-area program related to a register bank switching instruction; FIG. 10 is a diagram showing a modification of an out-of-area program related to a register bank switching instruction; FIG. 10 is a diagram showing a modification of an intra-area program related to a register bank switching instruction; is. FIG. 10 is a diagram showing a modification of an out-of-area program related to a register bank switching instruction; FIG. 10 is a diagram showing an example of an intra-area program when using "CALL" and "RET" instructions; FIG. 10 is a diagram showing an example of an out-of-area program when using "CALL" and "RET" instructions; It is the figure which showed the memory map of the main-control part in embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in the following order with reference to the accompanying drawings.

<1. Game Machine Structure>
<2. Game Machine Control Configuration>
[2-1. Main control part]
(Regarding setting value change operation)
(About performance display)
(Production control command)
[2-2. Production control unit]
<3. Overview of operation>
[3-1. Symbol variation display game]
(Special symbol variation display game)
(Decorative pattern variation display game)
(Normal pattern fluctuation display game)
(About hold)
[3-2. game state]
[3-3. About hit]
[3-4. About production]
(Direction mode)
(Notice production)
(Direction means)
<4. Processing of Main Control Unit>
[4-1. Main control side main processing]
(initial setting processing)
(Processing after initial setting)
(main loop processing)
(setting change processing)
(RAM clear processing)
(Setting confirmation process)
(main loop preprocessing)
(Advantages of the set value display data table and the set value conversion table)
[4-2. Main control side timer interrupt processing]
(power supply check/backup processing)
(Processing for error management and game progress, etc.)
<5. Processing Transition Between In-Region Processing and Out-of-Region Processing>
[5-1. About used area and non-used area]
[5-2. Processing transition method in the preceding example]
[5-3. Process migration method as an embodiment]
[5-4. Another example of the program]
[5-5. Variation of program]
[5-6. Other Modifications]
<6. About Q register and U register>
<7. Summary of Embodiments>

<1. Game Machine Structure>

The structure of a pachinko game machine 1 as an embodiment according to the present invention will be described with reference to FIGS. 1 and 2. FIG. FIG. 1 is a front perspective view showing the appearance of the pachinko game machine 1, and FIG. 2 is a front view of the game board 3 of the pachinko game machine 1.

A pachinko game machine 1 (hereinafter sometimes abbreviated as "game machine 1") shown in FIG. A game board 3 (see FIG. 2) is mounted in an attached game board storage frame (not shown), and a game area 3a formed on the surface of the game board 3 faces the opening of the front frame 2. have. A glass door 6 supporting transparent glass is provided on the front side of the game area 3a. Also, on the back side of the game board 3, various control boards (see FIG. 3) for controlling game operations are arranged.

A key cylinder (not shown) for unlocking the door is provided on the front side of the glass door 6. By inserting a key into this key cylinder and operating it to one side, the locked state of the glass door 6 with respect to the front frame 2 is released. , to release the locked state of the front frame 2 with respect to the outer frame 4 and open to the front side.

Under the glass door 6, a front operation panel 7 is pivotally supported on the front frame 2 by a hinge (not shown) so that it can be opened and closed. An upper tray unit 8 is provided on the front operation panel 7, and the upper tray unit 8 is formed with an upper tray 9 for storing discharged game balls.

The upper tray unit 8 also has a ball ejection button 14 for ejecting the game balls stored in the upper tray 9 to the lower part of the gaming machine 1, and a game ball dispensing device (not shown) for dispensing game balls. A ball lending button 11 for making a request and a card return button 12 for requesting the return of the valuable value medium inserted in the game ball lending device are provided. Also, the upper tray unit 8 is provided with a performance button 13 (operating means) configured to be operable by the player. The effect button 13 can be operated (input can be accepted) when the built-in lamp (button LED 75) is lit during a predetermined input reception period, and a predetermined operation (press, repeated hits, long press, etc.) is performed while the built-in lamp is lit. By doing so, it is possible to bring about changes in the production.
Although not shown in FIG. 1, the front operation panel 7 has a cross key 15a for users such as players and hall staff to select various items and give directions, and a selection item. An operator such as a decision button 15b is provided for instructing the decision of.

A firing operation handle 15 for operating a firing device 32 (see FIG. 3) is provided on the right end side of the front operation panel 7 .

Speakers 46 are provided on both sides of the upper part of the front frame 2 and on the upper side of the shooting operation handle 15 to produce a sound effect (sound effect). In addition, a plurality of decorative lamps 45 (for example, full-color LEDs for light production, etc.) are provided at appropriate locations on the glass door 6 to exhibit a light production effect by light decoration. A plurality of full-color LEDs (light effect LEDs) as the decorative lamps 45 are provided around the pachinko game machine, that is, around the front frame edge of the glass door 6 in the circumferential direction.

The configuration of the game board 3 will be described with reference to FIG. The game board 3 shown in the figure is provided with a ball guide rail 5 that guides the shot game ball in an annular shape as a board surface partitioning member. The four corners are non-game areas.

Approximately in the center of the game area 3a, for example, in three (left, middle, right) display areas (symbol variation display areas), a plurality of types of decorative patterns (for example, numbers, characters, symbols, etc.) are displayed independently. A liquid crystal display (LCD) 36 capable of variable display operation (variable display and stop display) of a left pattern (corresponding to the left display area), a middle pattern (corresponding to the middle display area), and a right pattern (corresponding to the right display area) is provided. is provided. In the following description, a plurality of types of decorative symbols that are variably displayed on the left, middle and right symbols may be referred to as "symbol group". That is, for example, the symbol stopped and displayed in the left display area is one of the symbol group forming the left symbol.
The liquid crystal display device 36, under the control of the effect control section 24, which will be described later, displays various effects in the form of images in addition to the variable display operation of decorative symbols.

In the game area 3a, a center decoration 48 is provided so as to surround the display surface of the liquid crystal display device 36 in a long way. The center decoration 48 is provided along the front side of the game board 3 to protect the display surface of the liquid crystal display device 36 from surrounding game balls, and to control the flow of the game ball depending on the strength or stroke length of the game ball's launch. It works as flow path distribution means that enables distribution of the path to the left and right. In this embodiment, the center decoration 48 is arranged substantially in the center of the game area 3a so that the passage of game balls is formed on both upper sides (left and right sides) of the game area 3a due to the presence of the center decoration 48. ing. The game balls hit by the shooting device 32 on the upper side of the game area 3a are distributed to the left and right on the upper side of the armor frame portion 48b, and are divided into the left flowing path 3b on the left side of the center decoration 48 and the right flowing path 3c on the right side. flow something.

In addition, the non-game area near the upper right edge (upper right corner) of the game board 3 serves as various function display portions, and the 7-segment display (with dots) is an upper starting port 34 (for the first special symbol) and a lower starting port. A special symbol display device 38a (first special symbol display means) and a special symbol display device 38b (second special symbol display means) arranged side by side corresponding to the mouth 35 (for the second special symbol). is provided. In the special symbol display devices 38a and 38b, a special symbol variable display game is executed by a variable display operation of the "special symbol" represented by the 7-segment display. In the liquid crystal display device 36, in time synchronization with the variable display of the special symbols by the special symbol display devices 38a and 38b, the decorative symbols by images are variably displayed, and decorated with various advance notice effects (effect images). A symbol variation display game is executed (details of these symbol variation display games will be described later).

In addition, in the various function display units, next to the special symbol display devices 38a and 38b, a composite display device (holding composite display LED display device) 38c consisting of a 7-segment display device (with dots) is arranged. Composite is called special symbols 1, 2, display of the number of operation pending balls of normal symbols, variable time reduction function in operation (time saving) and high probability state (high probability) state notification, five This is because it is a holding/time-saving/high-precision composite display device (hereinafter simply referred to as "composite display device") having a display function.

Further, the various function display units are provided with a normal symbol display device 39a (normal symbol display means) in which a plurality of (two in this embodiment) LEDs are arranged next to the composite display device 38c. In this normal symbol display device 39a, a normal symbol variation display game is executed by a normal symbol variation display operation represented by two LEDs. For example, as a variable display operation, normal patterns by LEDs alternately turn on and off in a seesaw manner, and by stopping with either side lit up, the propriety of the normal pattern variable display game becomes clear. there is Further, a round number display device 39b having three LEDs (first to third round display LEDs) arranged adjacent to the normal symbol display device 39a is provided. The number-of-rounds display device 39b notifies the specified number of rounds (maximum number of rounds) related to the big hit by a combination of lighting and extinguishing states of the three LEDs.

Below the center decoration 48, an upper starting port 34 (first special symbol starting port: first starting means) and a lower starting port 35 (second special symbol starting port: second starting means) are provided. Detecting sensors 34a, 35a (upper start sensor 34a, lower start sensor 35a: see FIG. 3) for detecting the passage of game balls are formed inside each of them. ing.

The upper starting port 34, which is the first special symbol starting port, is the first special symbol in the special symbol display device 38a (hereinafter, the first special symbol is referred to as "special symbol 1", and in some cases "special symbol 1" (abbreviated as )), and is configured as a fixed winning rate type winning device that does not have starting opening/closing means (means for opening or enlarging the starting opening). In this embodiment, due to the action of the game ball falling direction changing member (eg, game nail (not shown), windmill 44, center decoration 48, etc.) in the game area 3a, the left flow path 3b to the upper start port 34 A game ball that has flowed down the path 3c is configured to easily enter (win a prize), whereas a game ball that has flowed down the right flow path 3c has a configuration that makes it difficult or impossible to enter.

The normal variable winning device 41 is configured as a variable winning rate type winning device capable of varying the winning rate of the game ball at the starting opening by the opening opening/closing means. In this embodiment, as a starting opening opening and closing means, a so-called "electric tulip It is configured as a "type" winning device.

The lower starting port 35 of the normal variable winning device 41 is the second special symbol in the special symbol display device 38b (hereinafter, the second special symbol is referred to as "special symbol 2", and in some cases is abbreviated as "special symbol 2". ), and the winning region of the lower starting port 35 is an open state ( winning easy state) and a closed state (difficult to win state) that makes winning more difficult or impossible than in the open state. In this embodiment, when the movable wing piece 47 is inactive, the closed state (non-winning state) is maintained in which the lower starting port 35 cannot be won.

On both sides of the normal variable prize winning device 41, a total of four general prize winning ports 43 are arranged, three on the left side and one on the right side. A mouth sensor 43a (see FIG. 3) is formed. In addition, a movable accessory (not shown) that exerts a visual performance effect is arranged in the area of the game board at a position that does not interfere with the flow of the game ball.

In addition, diagonally above the normal variable winning device 41, that is, on the upper side of the middle part of the right flow path 3c, there is a normal symbol start port 37 (third start means) are provided. This normal symbol starting port 37 is a prize winning port related to normal symbol fluctuation display operation in the normal symbol display device 39a, and inside thereof, a normal symbol starting port sensor 37a (see FIG. 3) for detecting a passing game ball is provided. is formed. In addition, in this embodiment, the normal symbol starting port 37 is formed only on the right flow path 3c side, and is not formed on the left flow path 3b side. However, the present invention is not limited to this, and may be formed only in the left flow path 3b or may be formed in both flow paths.

In the middle of the route from the normal symbol starting port 37 to the normal variable winning device 41 in the right flow path 3c, there is a special variable winning configured to be able to open or expand the big winning port 50 by a projecting open door 52b. A device 52 (special electric accessory) is provided, and a big winning hole sensor 52a (see FIG. 3) for detecting a game ball entering the big winning hole 50 is formed inside.

A bulging portion (decorative member) 55 bulging out from the surface of the game board 3 is formed around the big winning opening 50, and the upper side 55a of the bulging portion 55 forms a downstream guide portion of the right downstream path 3c. there is When the large winning opening 50 is closed by the open door 52b (large winning opening closed state), the downstream guide portion ( It is adapted to form part of the upper edge 55a). In addition, in the downstream area of the right flow path 3c, in the area above the upper side 55a of the bulging portion 55, more precisely in the game area above the big winning opening 50, a flow path correction plate is provided substantially parallel to the downstream direction of the game ball. 51d is protruded, and functions to attract the falling game balls toward the big winning hole 50.例文帳に追加

The process of entering the game ball into the big winning hole 50 is as follows.
A game ball that has passed through the floating area between the upper surface of the center decoration 48 and the ball guide rail 5 is projected onto the top surface (upper side) 55a of the bulging portion 55 that protrudes from the game board 3 and functions as a guide for the game ball. It flows down along. Then, the game ball touches the right end of the flow path correction plate 51d projecting from the game board 3 surface, thereby correcting the flowing direction of the game ball to the direction of the big winning hole 50 (downward). At this time, if the large winning opening 50 is covered by the retractable open door 52b (closed state of the large winning opening), the game ball rolls on it, and further in a predetermined arrangement (not shown). By the game nail, it is guided in the direction of the tulip-type normal variable winning device 41 (lower starting port 35). At this time, if the lower starting port 35 is in a winning state (starting port open state), a game ball can enter the lower starting port 35 . On the other hand, if the open door 52b is retracted in the game board surface and the large winning opening 50 is open (large winning opening open state), the game ball is guided into the large winning opening 50.例文帳に追加

In the gaming machine 1 of the present embodiment, when the player aims at the launch position on the side of the special variable winning device 52 (when aiming so that the game ball passes through the right flow path 3c), the upper start opening A game ball is difficult or not guided to the 34 side. Therefore, in the "large winning opening closed state", unless the movable wing 47 of the normal variable winning device 41 operates, winning to the starting openings 34 and 35 is difficult or impossible. The movable wing 47 operates in a more advantageous opening/closing pattern than in a normal state when the game state is accompanied by a state with an electric sapo, which will be described later.

In the case of the present embodiment, the manner in which the player should hit to obtain an advantageous situation changes according to the game state. Specifically, if the game state is accompanied by the "state without electric sapo", which will be described later, it is advantageous to hit "left", aiming for the game ball to pass through the left flow path 3b. If it is a game state accompanied by "with state", "right hitting" aiming to make the game ball pass through the right flow path 3c is advantageous.

In the gaming machine 1 of the present embodiment, when there is a winning in a winning opening other than the normal symbol start opening 37 among various winning openings provided in the game area 3a, a promise is made for each winning opening. The number of prize balls per winning ball (for example, 3 for the upper starting port 34 or lower starting port 35, 13 for the big winning port 50, and 10 for the general winning port 43) is determined by the game ball payout device 19 (Fig. 3 See). The game balls that have not won the winning openings are ejected from the game area 3a through the out opening 49. FIG.
Here, "winning" means that the winning opening does not have a structure in which the game ball is taken in, or the winning opening is not a structure in which the game ball is taken in, but is a winning opening made up of a pass-through gate (for example, the normal symbol start opening 37). If it is, it means that the game ball passes through the gate, and in fact, when the game ball is detected by each winning detection switch formed for each winning hole, "winning" occurs in that winning hole treated as if A game ball related to this winning is also called a "winning ball". If a game ball enters the winning hole, it will be detected by the winning detection switch. Irrespective of this, there are cases where the term "winning" includes the case where a game ball enters the winning opening.

<2. Game Machine Control Configuration>

A configuration (control configuration) for realizing game operation control of the gaming machine 1 will be described with reference to the block diagram of FIG.
The gaming machine 1 of the present embodiment includes a main control board (main control means) 20 (hereinafter referred to as "main control unit 20") that controls overall game operation (game operation control), and a main control unit. A production control board (production control means) 24 (hereinafter referred to as "production control unit 24") that receives production control commands from the production means and controls the execution of production (appearance control) by the production means, and a prize ball. A payout control board (payout control means) 29 for performing payout control, a power supply board (power control means (not shown)) for generating and supplying necessary power to the gaming machine 1 from an external power supply (not shown), is configured with
Note that the power supply route to each part is omitted in FIG.

[2-1. Main control part]

The main control unit 20 is equipped with a microprocessor containing a CPU (Central Processing Unit) 20a (main control CPU), and in addition to a control program describing game operation control procedures, various data necessary for game operation control are stored. A ROM (Read Only Memory) 20b (main control ROM) for storing data and a RAM (Random Access Memory) 20c (main control RAM) functioning as a work area and buffer memory are installed, and the microcomputer is configured as a whole. .

Although not shown, the main control unit 20 includes a CTC (Counter Timer Circuit) for realizing periodic interrupts, a constant cycle pulse output generation function (bit rate generator), and a time measurement function, and the CPU 20a. An interrupt controller circuit that enables/disables interrupts, such as a timer interrupt that gives an interrupt signal, and can output a system reset signal to reset the CPU 20a by detecting power on/off and power failure. A reset circuit, a watchdog timer (WDT) circuit that monitors abnormal operation of the control program, and an out-of-designated area travel prohibition (IAT) circuit that monitors whether the program is being executed correctly within a preset address range , and a counter circuit or the like for generating random numbers within a certain range in terms of hardware.

The counter circuit includes a random number generating circuit for generating random numbers and a sampling circuit for sampling random numbers from the random number generating circuit at a predetermined timing, and functions as a 16-bit counter as a whole. The CPU 20a acquires the numerical value indicated by the random number generation circuit as an internal lottery random number (random number for judging a big hit (magnitude of random number: 65536)) by sending an instruction to the sampling circuit according to the processing state. , the random number is used for the jackpot lottery. The internal lottery random number is obtained by adding a soft random number generated by appropriate software processing and a hard random number, in order to prevent cheating such as hitting a winning game.

The CPU 20a also has a plurality of registers for storing various values. The details of the registers included in the CPU 20a in the embodiment will be described later.

The main control unit 20 includes an upper starting hole sensor 34a that detects winning (entering a ball) to the upper starting hole 34, a lower starting hole sensor 35a that detects winning to the lower starting hole 35, and a normal symbol starting hole 37. A normal symbol start opening sensor 37a that detects the passage of the, a large winning opening sensor 52a that detects winning to the big winning opening 50, a general winning opening sensor 43a that detects winning to the general winning opening 43, and an out opening 49 An OUT monitoring switch 49a for detecting a game ball (out ball) discharged from the outlet is connected, and the main control unit 20 can receive detection signals output from these. The main control unit 20 can grasp which winning hole the game ball has entered based on the detection signal from each sensor.

The main control unit 20 also includes a normal electric accessory solenoid 41c for controlling the opening and closing of the movable wing piece 47 of the lower start opening 35, and a large winning opening solenoid 52c for controlling the opening and closing of the open door 52b of the large winning opening 50. are connected, and the main control unit 20 can transmit control signals for controlling them.

Further, the main control unit 20 is connected with a special symbol display device 38a and a special symbol display device 38b, and the main control unit 20 can transmit a control signal for controlling the display of the special symbols 1 and 2. . Furthermore, a normal symbol display device 39a is connected to the main control unit 20, and a control signal for controlling display of normal symbols can be transmitted.

A compound display device 38c and a round number display device 39b are connected to the main control unit 20, and the main control unit 20 outputs control signals for controlling display of various information displayed on the compound display device 38c, It is possible to transmit a control signal for controlling the display of the prescribed number of rounds by the big hit displayed on the number display device 39b.

Further, the main control unit 20 is connected to a frame external centralized terminal board 21, and the main control unit 20 transmits predetermined signals to the hall computer HC provided outside the game machine via the frame external centralized terminal board 21. It is possible to transmit game information (for example, big hit information, prize ball information, symbol variation execution information, etc.).
The hall computer HC is an information processing device (computer device) for monitoring game information from the main control unit 20 and managing the operation status of the game machines of the pachinko hall.

Furthermore, a payout control board (payout control unit) 29 is connected to the main control unit 20, and when it is necessary to pay out prize balls, a control command related to payout (number of prize balls A payout control command that specifies ) can be transmitted.

The payout control board 29 is connected with a launch control board (launch control section) 28 that controls the launcher 32 and a game ball payout device (game ball payout means) 19 that pays out game balls. The main roles of this payout control board 29 are to receive payout control commands from the main control unit 20, to control prize ball payout of the game ball payout device 19 based on the payout control commands, and to transmit status signals to the main control unit 20. is.

The game ball payout device 19 is provided with a supply shortage detection sensor 19a for detecting a shortage of supply of game balls and a ball counting sensor 19b for detecting game balls (prize balls) to be paid out. can receive each detection signal. The game ball payout device 19 is provided with a payout motor 19c for driving a ball payout mechanism (not shown) for putting out game balls. of control signals can be transmitted.

Further, the payout control board 29 is provided with a full detection sensor 60 (in this embodiment, a detection sensor for detecting the state of game balls stored in the upper tray 9) that detects when the upper tray 9 is full of game balls. , a front door open sensor 61 (in this embodiment, a detection sensor that detects at least the open state of the front frame 2) is connected.

The payout control board 29 can transmit various status signals to the main control unit 20 based on detection signals from the full detection sensor 60, the front door open sensor 61, the supply shortage detection sensor 19a, and the ball counting sensor 19b. It has become. This state signal includes a ball clogged signal indicating a full state, a door open signal indicating that at least the front frame 2 is open, a resupply out signal indicating insufficient supply of game balls from the game ball payout device 19, and prize balls. A count error signal indicating an insufficient payout of balls or an abnormality in the ball counting sensor 19b, and a payout completion signal indicating completion of the payout operation are included, and various status signals can be transmitted. Based on these status signals, the main control unit 20 determines whether the front frame 2 is open (door open error), whether the game ball dispensing device 19 is normally dispensed (out-of-supply error), and whether the upper tray 9 Monitor the full state (ball clogging error), etc.

Furthermore, a firing control board 28 is connected to the payout control board 29, and a permission signal for permitting firing can be transmitted to the firing control board 28. FIG. The firing control board 28 controls energization of a firing solenoid (not shown) provided in the firing device 32 based on the output of the permission signal from the dispensing control board 29, and operates the firing operation handle 15. It realizes the shooting operation of the game ball by. Specifically, when a firing permission signal is output from the payout control board 29 (the firing permission signal is ON), and a touch sensor (not shown) provided on the firing operation handle 15 touches the handle by the player, The shooting operation of the game ball is permitted on the condition that the presence of the game ball is detected and the shooting stop switch (not shown) provided on the shooting operation handle 15 is not operated. Therefore, when the shooting permission signal is not output (shooting permission signal OFF state), even if the shooting operation handle 15 is operated, the shooting operation is not executed and the game ball is not shot. In addition, the strength of launching the game ball can be changed according to the operation amount of the shooting operation handle 15. - 特許庁
When the payout control board 29 detects the ball jam error, it transmits a ball jam signal to the main control unit 20 and stops outputting the firing permission signal to the firing control board 28 (fire permission signal OFF). Until the full state of is eliminated, the control is performed to stop the launching operation.
Also, the payout control board 29 outputs a launch permission signal to the launch control board 28 on condition that the main control unit 20 instructs launch permission.

Here, the main control unit 20 is connected to a setting key switch 94 and a RAM clear switch 98, and can receive detection signals from these switches.

The RAM clear switch 98 is, for example, a push button type switch for inputting an instruction to initialize a predetermined area of the RAM 20c.
The setting key switch 94 is a key switch for switching to a setting change mode (at the time of ON operation) by inserting a setting key possessed by the hall staff and performing an ON/OFF operation when power is turned on.
Here, the setting change mode is a mode in which the set value Ve can be changed. The set value Ve is a value representing the stage of the winning probability of whether or not to win a game state advantageous to the player.

The RAM clear switch 98 is turned ON/OFF according to the operation of a RAM clear button which is operable with the front frame 2 opened. The setting key switch 98 is provided with a key cylinder into which the above-described setting key can be inserted and removed. When it is turned in the opposite direction from the ON state, it is turned OFF. The key cylinder is provided so that it can be operated by inserting a setting key while the front frame 2 is open. Note that the key cylinder functions as an operator that can be operated by inserting a setting key.

In this example, the above RAM clear button is also used for changing the set value Ve. Specifically, the RAM clear button also functions as an operator for forwarding the set value Ve.

A RAM clear switch 98 and a setting key switch 94 are provided at appropriate locations inside the gaming machine 1 . For example, it is arranged on the main control board 20 .

A setting/performance indicator 97 is also connected to the main controller 20 .
The setting/performance display 97 is configured with, for example, a 7-segment display, and functions as display means capable of displaying setting values Ve and performance information (to be described later). The setting/performance indicator 97 is mounted, for example, on the main control unit (main control board) 20 at a position where it can be easily viewed.
The main control unit 20 can transmit a control signal for displaying the setting value Ve and performance information to the setting/performance display device 97 .

Here, the set value Ve mainly defines the lottery probability (winning probability) of at least the jackpot (hit type that will operate the condition device described later) for each stage (for example, 6 stages of settings 1 to 6) The higher the set value Ve, the higher the probability of winning (setting 1 is the lowest probability of winning, and thereafter, the probability of winning increases in ascending order of the set values), which works in favor of the player. there is In other words, the higher the set value Ve, the higher the so-called "mechanical discount (payout rate, payout rate)", which is advantageous to the player.
In this way, the set value Ve is a value that defines the probability of winning a jackpot, a machine discount, etc., and means a value for a grade related to the probability of occurrence of a specific event such as a profit state that acts on a player. , in the present embodiment, the degree of advantage in the game is defined according to each set value Ve.

In this example, it is assumed that there are six levels of set value Ve (levels of advantage) that are legally available. Specifically, it is assumed that the legally usable range of the set value Ve (hereinafter referred to as “usable range Re”) is in the range of “1” to “6”.
Under this premise, the pachinko gaming machine 1 of this example uses only a part of the set values Ve among the set values Ve that can be used under the rules. Specifically, the pachinko game machine 1 of this example uses only three values, for example, "1", "2", and "6", among the set values Ve within the usable range Re, which are "1" to "6". do. In other words, the specification is limited to three stages for the winning probability, instead of six stages, which is the maximum stage according to the rules.
Hereinafter, the range of setting values Ve actually used in the pachinko game machine 1, specifically, the range of setting values Ve actually used among the setting values Ve within the usable range Re (in the above example, "1 ", "2", and "6") is referred to as "usage range Ru".

The set value Ve is set exclusively by a hall staff such as a hall clerk based on the sales strategy of the hall (game shop). When there are a plurality of types of jackpots, it is possible to appropriately determine which jackpot winning probability is changed according to the set value Ve, or the type of target jackpot. For example, if there are three types of jackpots 1 to 3, the higher the set value Ve is, the higher the winning probability of all the jackpots 1 to 3 may be. The combined winning probability may be increased. Also, the winning probability of some jackpots may be increased. For example, only the winning probabilities of the jackpots 1 and 2 may be increased, and the winning probability of the jackpot 3 may be set to be constant with all set values Ve.

(Regarding setting value change operation)

In order to change the setting value Ve, in this example, the setting key switch 94 is turned ON (operated to the setting change mode side) in a state in which the gaming machine 1 is powered off and the front frame 2 is released, and The game machine 1 is powered on while the RAM clear button is pressed (the RAM clear switch 98 is ON). Then, the current setting value Ve is displayed on the setting/performance display 97, and the setting value Ve (1, 2, and 6 in this example) can be changed in a "setting change mode".

In this example, the determination as to whether or not to shift to the setting change mode is made in the main control side main process, which will be described later (see step S104 in FIG. 5). When the above operation conditions for shifting to the setting change mode are satisfied, processing for setting change is executed accordingly.

After shifting to the setting change mode, when the RAM clear button functioning as a change operator for the set value Ve is turned ON, the current display value of the setting/performance display 97 changes to "1→2→6→1→ 2→6→ . . . ” within the usage range Ru. When the desired setting value Ve is reached, the setting key switch 94 is turned off, and the setting value Ve is determined, and information on the determined setting value Ve is stored in a predetermined area of the RAM 20c.
When the setting key switch 94 is turned off, the setting change mode is terminated and the display of the setting/performance display 97 is cleared.
When the setting change mode ends, the game is shifted to a state in which the progress of the game is permitted.

(About performance display)

The main control unit 20 can transmit a control signal for displaying predetermined performance information to the setting/performance display device 97 .
The performance information is information that pachinko halls and related government agencies want to confirm, and typical examples thereof include information on the presence or absence of fraudulent prize balls such as excess prize balls for the gaming machine 1 and information on the original performance of the gaming machine 1. is. Therefore, the performance information itself is information that is not directly related to the progress of the game itself when the player is enjoying the game, unlike the advance notice effect or the like.

For this reason, the setting/performance display device 97 is inside the game machine 1, for example, the main control unit (main control board) 20, the payout control board 29, the launch control board 28, the relay board, the production control unit (production control board (liquid crystal It is provided at a position where the display information can be viewed when the front frame 2 is opened, such as on the control board) ) 24 or a board case (a protective cover that protects the board).

Here, the following information can be specifically adopted as the performance information.

(1) The total number of payout balls paid out due to winning during a specific state (total number of prize balls during a specific state: α) is The information (specific ratio information) based on the value (α/β) divided by the number of pieces: β can be adopted as the performance information.
The above-mentioned "total number of payouts" is the total value of the game balls (prize balls) paid out when entering the winning opening (upper starting opening 34, lower starting opening 35, general winning opening 43, big winning opening 50). is. In the case of the present embodiment, there are three upper starting openings 34 or lower starting openings 35, thirteen large winning openings 50, and ten general winning openings 43. FIG.
Further, which state to adopt as the specific state can be appropriately determined according to the state under which performance information is desired to be grasped. In the case of this embodiment, any state can be employed among the normal state, latent probability state, time saving state, probability variable state, and jackpot game. Also, a plurality of types of states may be measured. For example, a normal state and a variable probability state, and all game states except during a winning game, etc., and the types to be measured can be determined as appropriate.
Also, as the period of the specific state, the period of either the low probability state or the high probability state of the jackpot lottery probability may be adopted.
Also, the total number of payouts excluding one or a plurality of specific winning holes from the measurement target may be the total number of payouts (total number of payouts excluding specific winning holes). For example, the total number of payouts may be obtained by excluding the big winning opening 50 from the measurement target among the winning openings.

(2) In addition, only one of the total number of payouts, the total number of payouts excluding a specific winning hole, or the total number of out-balls may be measured, and the measurement result may be used as the performance information.

In this embodiment, the total number of balls paid out during the normal state (normal number of balls paid out) and the total number of out balls during the normal state (normal number of out balls) are measured in real time. The value obtained by multiplying the value divided by 100 (normal payout count/normal out count x 100) is displayed as performance information (hereinafter referred to as “normal ratio information”). In addition, the display value at this time shall be the value rounded off to the first decimal place.
Therefore, the normal payout number, the normal out number, and the normal ratio information are respectively stored in the corresponding areas of the RAM 20c (specified total winning ball number storage area, specified out number storage area, specific ratio information storage area). It is designed to be stored (memorized). However, when the total number of out-balls reaches a predetermined specified number (for example, 60,000), the measurement is stopped once, instead of simply measuring permanently and displaying the performance information. This prescribed number is not the total number of out balls in the normal state, but the total number of out balls during all game states (including during winning games) (hereinafter referred to as "the number of out balls in all states"). This all-state-out number is also measured in real time and stored in the corresponding area (all-state-out number storage area) of the RAM 20c. Hereinafter, for convenience of explanation, the specified total number of winning balls storage area, specified out number storage area, specified ratio information storage area, and all state out number storage area are abbreviated as "measurement information storage area".

Then, the normal ratio information at the end point is stored in a predetermined area (performance display storage area) of the RAM 20c (this normal ratio information is stored), and then the measurement information storage area (normal payout number, normal out number and the total number of out balls) are cleared, and measurement is started again (measurement of the number of normal payouts, the normal number of out balls, the normal ratio information, and the number of out balls in all states is started). The setting/performance display device 97 displays the previous normal time ratio information (measurement history information) and the normal time ratio information currently being measured. It should be noted that not only the information of the previous time but also the history of the time before last or the time before that (three times before) may be displayed.

Here, in the case of this example, the setting/performance indicator 97 alternatively displays the setting value Ve and the performance information. Specifically, in this example, settings are changed and checked only when the power is turned on. After the set value Ve is displayed on the performance indicator 97 and the setting change or setting confirmation is completed, the performance information is displayed.
It should be noted that the configuration in which the set value Ve and the performance information are displayed by a common display is not limited, and a configuration in which they are displayed by separate displays can also be adopted. In that case, the setting value Ve and the performance information may be displayed in parallel.

(Production control command)

The main control unit 20 can transmit various effect control commands including information on special symbol variation display games, information on errors, etc. to the effect control unit 24 according to the processing state. However, in order to prevent fraudulent acts such as goto, the main control unit 20 only transmits a signal to the effect control unit 24, and a one-way communication configuration that cannot receive a signal from the effect control unit 24 is used. It's becoming

Here, the effect control command defines the function by a 2-byte configuration consisting of a 1-byte length mode (MODE) and a 1-byte length event (EVENT). Bit7 is ON, and Bit7 of EVENT is OFF. When transmitting these information as valid, a strobe signal is output corresponding to each of the mode (MODE) and the event (EVENT). That is, when there is a command to be transmitted, the CPU 20a (main control CPU) sets and outputs mode (MODE) information for transmitting the command to the effect control unit 24, and after a predetermined time has passed since this setting, the first time strobe signal. Further, event (EVENT) information is set and output after a predetermined period of time has elapsed from the transmission of this strobe signal, and the second strobe signal is transmitted after a predetermined period of time has elapsed from this setting. The strobe signal is controlled to be in an active state by the CPU 20a for a predetermined period during which the CPU 24a (effect control CPU) can reliably receive commands.

[2-2. Production control unit]

The production control unit 24 is equipped with a microprocessor that incorporates a CPU 24a (production control CPU), a ROM 24b (production control ROM) that stores production data required for production control processing, and a RAM 24c that functions as a work area and buffer memory ( It is composed mainly of a microcomputer equipped with a performance control RAM), and is also equipped with a sound control unit (sound source IC), RTC (Real Time Clock) function unit, counter circuit, interrupt controller circuit, reset circuit, WDT circuit, etc. and controls the entire production operation.

The effect control CPU 24a performs arithmetic processing for various effect operations and controls each effect means based on the effect control program and the effect control command received from the main control unit 50. FIG. In the case of the pachinko game machine 1 of this embodiment, the rendering means includes the liquid crystal display device 36 (main liquid crystal display device 36M, sub liquid crystal display device 36S), optical display device 45a, sound generator 46a, and a movable Become a body role.

The effect control ROM 24b stores a control program for the effect operation by the effect control CPU 24a and various data necessary for control of the effect operation.
The effect control RAM 24c is used as a work area used by the effect control CPU 24a for various arithmetic processing, a table data area, a buffer area for various input/output data and processing data, and the like.
The arithmetic control unit 24 can be configured to include a one-chip microcomputer and its peripheral circuits, but various configurations of the performance control unit 24 are conceivable. For example, in addition to a microcomputer, an interface circuit with each part, a random number generation circuit that generates random numbers for lottery for production, CTC for various time counts, a watchdog timer (WDT) circuit, an interrupt signal to production control CPU 24a may also include an interrupt controller circuit or the like that provides

The main roles of this production control unit 24 are reception of production control commands from the main control unit 20, selection and determination of production based on the production control commands, display control of the liquid crystal display device 36 (supply of display data), sound generator 46a. , light emission control of the optical display device 45a (LED), operation control of the movable body role object (drive control of the movable body role object motor 80c), and the like.

Since the effect control unit 24 also functions as a control device for the liquid crystal display device 36, the effect control unit 24 also functions as a so-called VDP (Video Display Processor), an image ROM, and a VRAM (Video RAM). The provided effect control CPU 24a also functions as a liquid crystal control section.
VDP refers to a function of controlling overall video output processing such as image expansion processing and image drawing.
The image ROM refers to a memory in which image data (effect image data) on which the VDP performs image expansion processing is stored.
VRAM is an image memory area for temporarily storing image data developed by VDP.

Based on these configurations, the effect control section 24 generates various image data based on commands from the main control section 20, and outputs the data to the main liquid crystal display device 36M and the sub liquid crystal display device 36S. As a result, various effect images are displayed on the main liquid crystal display device 36M and the sub liquid crystal display device 36S.

The effect control unit 24 also has a sound control unit (sound controller: sound source IC) for the sound generator 46a including the speaker 46, and the sound signal output by the sound control unit is amplified by the amplifier unit 46d and is amplified by the speaker 46. supplied to
In addition, the production control unit 24 includes a lamp driver unit 45d that functions as an optical display control unit for the optical display device 45a that includes the decorative lamp 45 and various LEDs, and a movable body accessory motor that operates a movable body (not shown). A motor driver section 80d (motor drive circuit) that functions as a drive control section for 80c is connected. The effect control section 24 instructs the lamp driver section 45d and the motor driver section 80d to control the light display operation by the light display device 45a and the operation of the movable body accessory motor 80c.

An origin switch 81 and a position detection sensor 82 are also connected to the performance control section 24 for monitoring the movement of the movable accessory.
The origin switch 81 is composed of, for example, a photointerrupter or the like, and detects whether or not the movable accessory motor 80c is at the origin position. The origin position is, for example, a position where the movable body does not normally appear on the board surface of FIG. Based on the detection information of the origin switch 81, the effect control section 24 can determine whether or not the movable accessory motor 80c is at the origin position.
In addition, based on the detection information from the position detection sensor 82, the effect control unit 24 controls the action mode while monitoring the current action position (for example, the amount of movement from the origin position) of the movable body role. Furthermore, the effect control unit 24 monitors malfunctions in the motion of the movable body role based on the detection information from the position detection sensor 82, and if malfunctions occur, detects them as errors.

The effect control unit 24 is connected to switches of the effect button 13, the cross key 15a, and the decision button 15b shown as the operation unit 17 in the figure, that is, the operation detection switches of the effect button 13, the cross key 15a, and the decision button 15b. The effect control unit 24 can receive operation detection signals from the effect button 13, the cross key 15a, and the decision button 15b.

Further, the effect control section 24 is provided with a handle sensor 83 (touch sensor) for detecting whether or not the operating handle 15 shown in FIG. 1 is being touched by a user such as a player. The performance control unit 24 can determine whether or not the operating handle 15 is touched by the user based on the detection information of the handle sensor 83 .

Based on the performance control command sent from the main control unit 20, the performance control unit 24 selects (determines) a performance pattern by lottery or uniquely from a plurality of types of performance patterns prepared in advance, and selects (determines) the required performance pattern. To display a desired performance by controlling various performance means at timing. As a result, the display of the effect image by the liquid crystal display device 36 corresponding to the effect pattern, the reproduction of the sound from the speaker 46, the lighting and blinking driving of the decorative lamp 45 and the LED are realized, and various effect patterns (decorative pattern fluctuation display operation, A "drawing scenario" in a broad sense is realized by the time-series development of advance notice effects, etc.

Here, for the production control command, the production control unit 24 (CPU 24a) generates an interrupt process based on the input of the above-described strobe signal transmitted by the main control unit 20 (CPU 20a), and receives and analyzes it. Specifically, the CPU 24a executes a control program for command reception interrupt processing based on the input of the strobe signal described above, and acquires the effect control command in the interrupt processing realized thereby, and analyzes the command contents. conduct.
At this time, when an interrupt occurs based on the input of the strobe signal, the CPU 24a performs the processing even during execution of interrupt processing based on another interrupt (timer interrupt processing that is periodically executed). is interrupted to perform command reception interrupt processing, and even if other interrupts occur at the same time, command reception interrupt processing is performed preferentially.

<3. Overview of operation>
[3-1. Symbol variation display game]

Next, the outline of the game operation of the gaming machine 1 realized by the control configuration (FIG. 3) as described above will be described.
First, the symbol variation display game will be described.

(Special symbol variation display game)

In the gaming machine 1 of the present embodiment, the main control unit 20 performs A "big hit lottery" will be held by random number lottery. Based on the lottery result, the main control unit 20 variably displays the special symbol 1 and the special symbol 2 on the special symbol display devices 38a and 38b to start the special symbol variation display game. Derivation display is performed on the symbol display device, thereby ending the special symbol variation display game.

Here, in the present embodiment, the big-hit lottery based on winning the upper starting port 34 and the big-winning lottery based on winning the lower starting port 35 are performed separately and independently. Therefore, the big-hit lottery result for the upper starting port 34 is derived from the special symbol display device 38a side, and the big-hit lottery result for the lower starting port 35 is derived from the special symbol display device 38b side. Specifically, on the side of the special symbol display device 38a, on the condition that the game ball enters the upper starting port 34, the special symbol 1 is variably displayed and the first special symbol variation display game is started. On the other hand, on the side of the special symbol display device 38b, on the condition that the game ball enters the lower starting port 35, the special symbol 2 is variably displayed and the second special symbol variability display game is started. ing. Then, when the special symbol variation display game on the special symbol display device 38a or the special symbol display device 38b is started, after a predetermined variation display time elapses, if the big win lottery result is a "big win", a predetermined "big win". In other cases, the special symbol during variable display is stopped and displayed in a predetermined "lost" mode, thereby deriving the game result (big hit lottery result).

In this specification, for convenience of explanation, the first special symbol variation display game on the side of the special symbol display device 38a is referred to as "special symbol variation display game 1", and the second special symbol on the side of the special symbol display device 38b. The variable display game is called "special symbol variable display game 2". In addition, unless particularly necessary, "special symbol 1" and "special symbol 2" are simply referred to as "special symbol" (sometimes abbreviated as "special symbol"), and "special symbol variation display game 1" and ""Special symbol variation display game 2" is simply referred to as "special symbol variation display game".

(Decorative pattern variation display game)

Further, when the above-mentioned special symbol variation display game is started, along with this, the decorative symbol variation display game is started by variably displaying decorative symbols (dramatic game symbols) on the main liquid crystal display device 36M. Various productions are developed along with. When the special symbol variation display game ends, the decoration symbol variation display game also ends, the special symbol display device displays a predetermined special symbol indicating the big win lottery result, and the main liquid crystal display device 36M reflects the big win lottery result. The decorative pattern is derived and displayed. In other words, the result of the special symbol variation display game is reflected and displayed by the dramatic decorative symbol variation display game including the decorative symbol variation display operation.

Therefore, for example, when the result of the special symbol variation display game is "big win" (when the big win lottery result is "big win"), the decorative symbol variation display game develops an effect reflecting the result. Then, in the special symbol display device, when the special symbol is stopped and displayed in a display mode indicating a big hit (for example, the display state of "7" in the 7 segment), the main liquid crystal display device 36M displays "left", "middle", " In each of the "right" display areas, the decorative pattern reflects the "big hit" (for example, in each of the "left", "middle" and "right" display areas, the three decorative patterns are "7", "7", " 7” display state).

When the "big hit" is achieved, specifically, the special symbol variation display game ends, and the decorative symbol variation display game ends accordingly, and as a result, the "big win" symbol mode is derived and displayed. After that, the large winning opening solenoid 52c of the special variable winning device 52 is actuated to open and close the opening door 52b in a predetermined pattern. A special game state (jackpot game) occurs. In this jackpot game, the open door 52b is operated until the opening time of the jackpot opens for a predetermined time (maximum opening time: for example, 29.8 seconds) or until the number of game balls that win the jackpot (big prize jack) 50) (maximum number of winning balls: maximum number of winning balls allowed for a winning opening whose entrance is opened or enlarged by one actuation of the accessory: e.g. 9) until the winning area is opened or expanded, and if any of these conditions are met, the big winning opening is closed. round) repeated.

When the big win game is started, an opening performance for notifying the start of the big win is first performed, and after the opening performance is completed, the round game is performed a plurality of times with a predetermined number of rounds as an upper limit. After the end of the specified number of rounds, an ending effect is performed to inform that the big win is over, thereby ending the big win game.

Regarding the information necessary for executing the decorative symbol variation display game, first, the main control unit 20, based on the entry (winning) of the game ball into the upper starting port 34 or the lower starting port 35, specifically On the condition that the game ball is detected by the upper starting opening sensor 34a or the lower starting opening sensor 35a and the starting condition (starting condition related to special symbols) is met, a lottery will be held to determine whether it is a "big hit" or "lose". If it is a ``jackpot'', the type of the jackpot is drawn, and if it is a ``losing'', the drawing of the winning type (winning type (hit type) lottery) ) 'and (if there is only one type of loss, the lottery may be omitted because there is no need to perform a type lottery for the loss), and based on the lottery result information, the special symbol fluctuation pattern Also, a special symbol (hereinafter referred to as "special stop symbol") to be finally stopped and displayed is determined according to the winning type.
Then, the main control unit 20, as the production control command to specify the processing state, at least special symbol variation pattern information (for example, information on the big hit lottery result and special symbol variation time, etc.) "variation pattern specification command" including It is transmitted to the production control section 24 side. As a result, the basic information required for the decorative symbol variation display game is sent to the effect control section 24 . In addition, in this embodiment, in order to increase the variety of effects, a "decorative design designation command" including special stop design information (symbol lottery result information (information on winning type)) is also transmitted to the effect control unit 24. It's like

The above-mentioned special symbol variation pattern information can include information designating whether or not a specific advance notice effect (for example, "ready-to-win effect" or "pseudo-continuous effect", which will be described later) will occur. More specifically, the variation patterns of the special symbols are broadly classified into a "hit variation pattern" for winning and a "losing variation pattern" for losing, depending on the result of the jackpot lottery. For these variation patterns, for example, 'reach variation pattern' that specifies the occurrence of reach production described later, 'normal variation pattern' that does not specify the occurrence of reach production, pseudo-continuous production and reach production (overlapping occurrence) Multiple types of variation patterns are included, such as 'pseudo-continuous reach fluctuation pattern' to be specified, 'pseudo-continuous normal fluctuation pattern' that specifies the occurrence of pseudo-continuous production and does not specify the occurrence of reach production. In order to secure the performance time of the ready-to-win effect and the pseudo-continuous effect, the variation pattern that designates the ready-to-win effect and the pseudo-continuous effect is usually set to have a longer variation time than the normal variation pattern.

Effect control unit 24, based on the information included in the effect control command (here, variation pattern designation command and decorative design designation command) sent from the main control unit 20, chronologically during the decorative design variation display game Decide the production content to be developed (production scenario such as advance notice production) and the decorative pattern to be finally displayed stopped (decorative stop pattern), and display the decorative pattern by fluctuating according to the time schedule based on the special pattern fluctuation pattern. A pattern variation display game is executed. As a result, the decorative symbols are variably displayed by the main liquid crystal display device 36M in synchronization with the variable display of the special symbols by the special symbol display devices 38a and 38b, and the period of the special symbol variable display game and the decorative symbol variable display game. The middle period has substantially the same time width. The effect control unit 24 also controls the main liquid crystal display device 36M, the optical display device 45a, or the sound generator 46a so as to correspond to the effect scenario, and develops various effects in the decorative symbol variation display game. As a result, image reproduction (image effect), sound effect reproduction (sound effect), and lighting and blinking driving of the decoration lamp 45 and LED (light effect) are realized on the main liquid crystal display device 36M.

As described above, the special symbol variation display game and the decorative symbol variation display game have an inseparable relationship, and the display results of the special symbol variation display game are reflected in the decoration symbol variation display game. , These two symbol variation display games may be regarded as equivalent symbol games. In this specification, the above-described two symbol variation display games may be simply referred to as "symbol variation display games" unless otherwise specified.

(Normal pattern fluctuation display game)

In addition, in the gaming machine 1, based on the fact that the game ball has passed through the normal symbol starting port 37 (winning a prize), the main control unit 20 performs an "auxiliary winning lottery" by random number lottery. Based on the result of the lottery, the normal symbol represented by the LED is variably displayed on the normal symbol display device 39a to start the normal symbol variation display game, and after a certain period of time has passed, the result is changed to a combination of lighting and non-lighting of the LED. stop display. For example, when the result of the normal symbol variation display game is "assist hit", the display unit of the normal symbol display device 39a is set to a specific lighting state (for example, two LEDs 39 are all lit, or "○" and " The LED on the side of "○" among the LEDs representing "x" is in a lit state), and the display is stopped.

When this "assist hit" occurs, the normal electric accessory solenoid 41c (see FIG. 3) operates, whereby the movable wing 47 opens in an inverted "V" shape and the lower starting port 35 opens. Or it becomes a state (starting opening open state) that is enlarged and the game ball is easy to flow in, and an auxiliary game state (hereinafter referred to as "general electric open game") that is more advantageous to the player than the normal game state occurs. In this normal electric open game, by the movable wing piece 47 of the normal variable winning device 41, until the opening time of the lower starting port 35 passes a predetermined time (for example, 0.2 seconds), or the game winning the lower starting port 35 The winning area is opened or expanded until the number of balls reaches a predetermined number (for example, 4). 2 times) is repeated.

(About hold)

Here, in this embodiment, during the special/decorative pattern variation display game, during the normal pattern variation display game, during the jackpot game, or during the general electric open game, the upper start port 34, the lower start port 35, or the normal symbol start port 37 When a prize is generated, that is, there is an input of a detection signal from the upper starting opening sensor 34a or the lower starting opening sensor 35a or the normal symbol starting opening sensor 37a, and the corresponding starting condition (symbol game starting condition) is established, As data relating to the right to start the variable display game, this data is reserved and stored up to a predetermined maximum number of reserved memories (for example, a maximum of 4), excluding data related to the variable display. The reserved data that is not used for the symbol variation display operation or the game ball related to the reserved data is also referred to as "operational reserved ball". In order to make clear to the player the number of activated balls held, a dedicated holding display (not shown) provided at an appropriate place on the gaming machine 1 or the liquid crystal display device 36 (main liquid crystal display device 36M or sub liquid crystal display device) is displayed. 36S) light up a hold indicator provided as an icon image in the screen.

Also, in this embodiment, up to four operation reserve balls relating to special design 1, special design 2, and normal design are reserved and stored in the corresponding storage area of the RAM 20c, and reserved as the number of times of determining the fluctuation of the special design or normal design. In addition, the maximum memory number (maximum reservation memory number) of each operation reservation ball number regarding the special symbol 1, the special symbol 2, and the normal symbol is not particularly limited. In addition, all or part of the maximum reserved memory number of each symbol may be different, and the number can be appropriately determined according to the game characteristics.

[3-2. game state]

The gaming machine 1 according to the present embodiment is configured to be capable of generating a plurality of types of game states in addition to the big win which is the special game state. In order to facilitate understanding of this embodiment, first, various game states will be described.

The gaming machine 1 of the present embodiment is configured to be able to execute and control at least four types of game states: a normal state, a time-saving state, a latent probability state, and a probability variable state. These game states are distinguished by whether or not a jackpot lottery probability state (low probability state, high probability state) or an electric chew support state (privilege game) occurs (with electric support, without electric support).

"Electric chew support state" means that the opening operation period of the movable wing 47 of the normal variable winning device 41 in the general electric open game (at least one of the opening time of the movable wing 47 and the number of times it is opened) is in the normal state Refers to the "open extension state" extended than. When the open extension state occurs, the opening operation period of the movable wing piece 47 is extended from 0.2 seconds in the normal state (under the non-open extension state) to 1.7 seconds, and the number of times of opening and closing is increased, for example. It is extended from the normal 1 time to 2 to 3 times.
In the case of the present embodiment, under the electric chew support state, the auxiliary winning lottery probability varies from a low probability (for example, 1/256) of a predetermined probability (normal probability) to a high probability (for example, 255/256) (normal A pattern probability fluctuation state) occurs, and a 'normal pattern time saving state' that shortens the average time required for one normal pattern fluctuation display game (normal pattern fluctuation display operation time) occurs (for example, from 10 seconds 1 second). Therefore, when the electric chew support state occurs, the common electric open game occurs frequently, and the operating rate improved state (high base state) in which the operating rate of the movable wing pieces 47 per unit time is improved than in the normal state. Hereinafter, the state under the electric chewing support state is abbreviated as "with electric support", and the other case is abbreviated as "without electric support".

In the present embodiment, the “normal state” means that the jackpot lottery probability is a low probability (for example, 1/399) of a predetermined probability (normal probability), and the game state without electric support (low probability + no electric support). To tell.

"Time-saving state" means that the probability of the jackpot lottery is as low as the normal state, but the average time required for one special symbol variation display game (variation display operation time of special symbols)) is lower than the normal state. It is a game state in which a 'special symbol time saving state' that is also shortened occurs and an electric chew support state occurs. In other words, during the time saving state, it becomes "low probability + electric sapo + special symbol time saving state".

The “potential state” is a “special symbol probability variable state” in which the jackpot lottery probability has changed to a high probability (for example, 1/39.9) that is higher than the above low probability, and a game state without an electric sapo (high Probability + no electricity support).

"Probability variable state" is a game state in which the jackpot lottery probability is as high as the latent probability state, but the special symbol time saving state and the electric chew support state occur. In other words, during the variable state, it becomes "high probability + electric sapo + special pattern time saving state".

Regarding the game state, focusing on the jackpot lottery probability, if the game state is "normal state" or "time saving state", at least the jackpot lottery probability is "low probability state", and the game state is "latent state" or "variable probability". state”, at least the jackpot lottery probability becomes a “high probability state”. During the big win, a big win game in which the big prize opening is opened and closed occurs, but the big win lottery probability and the presence or absence of an electric support are placed under the same low probability and no electric support game state as in the above normal state.

[3-3. About hit]

Next, the “hit” in the game machine 1 will be explained.
In the gaming machine 1 of the present embodiment, a big win lottery (hit lottery) is performed for a plurality of types of wins. In the case of this example, the types of hits include, for example, "normal 4R", "normal 6R", "variable probability 6R", and "variable probability 10R".
Note that the notation of "R" means the prescribed number of rounds (maximum number of rounds).

The jackpot type is a hit that triggers the operation of the condition device. Here, the "conditional device" is a device whose operation is a necessary condition for the operation of the accessory continuous operation device for performing a round game, and a combination of specific special symbols is displayed, or a game ball is displayed. It means something that operates when passing through a specific area in the big winning opening.

The variable probability state ends the high probability state and shifts to the low probability state when the special symbol variation display game is executed a predetermined number of times (for example, 70 times: the prescribed ST number) without winning the jackpot type. , It is a so-called "number-of-times-cutting variable machine (ST machine)", and when the prescribed number of STs is completed, the game is shifted to the normal state from the next game. However, it may be a "general probability changer" that continues until the next big hit is won.
The number of executions of the special symbol variation display game may be the total number of executions of the special symbol variation display game 1 and the special symbol variation display game 2 (the total number of variations of the special symbol 1 and the special symbol 2), It may be the number of executions of either one (for example, the number of executions of the special symbol variation display game 2). Also, the number of times of the time-saving state is not limited to 60 times or 100 times, and can be determined as appropriate according to the playability. Also, there is no particular limitation on the type of hit to be provided, and it can be determined as appropriate.

Here, in this example, a plurality of types are provided for "losing" as well as the jackpot types. Specifically, there are provided three types of loss, "loss 1", "loss 2", and "loss 3".
As described above, when the result of the win-lose lottery is "lost", the lottery for the type of loosing is performed in the symbol lottery.

[3-4. About production]
(Direction mode)

Next, the production mode (production state) will be described. The gaming machine 1 of the present embodiment is provided with a plurality of types of performance modes for producing performances related to game states, and is configured to be able to move between the performance modes. Specifically, there are provided a normal production mode, a time saving production mode, a latent probability production mode, and a probability variable production mode corresponding to each of the normal state, the time saving state, the latent probability state, and the probability variable state. In each production mode, the background display as the background of the variable display screen of decorative patterns is displayed with different background production, so that the player can grasp what kind of game state he is currently staying in. It has become.

The production control unit 24 (CPU 24a) has a functional unit (production state transition control means) that controls transition between a plurality of types of production modes. Effect control unit 24 (CPU24a), the specific effect control command sent from the main control unit 20 (CPU20a), specifically to the effect control command including the game state information managed by the main control unit 20 side Based on this, the current game state is grasped in a form that maintains consistency with the game state managed by the main control unit 20 side, and transition control between a plurality of types of presentation modes is possible. As the specific effect control command as described above, there are, for example, a variation pattern designation command, a decorative design designation command, a game state designation command sent when a change occurs in the game state, and the like.

(Notice production)

Next, the advance notice effect will be described. The production control unit 24 is based on the content of the production control command from the main control unit 20, specifically, at least the variation pattern information included in the variation pattern designation command, variously related to the current production mode and the jackpot lottery result. It is configured to be able to control the appearance of such a "notice effect". Such a notice effect is used as a "promotion effect" to suggest (notice) the degree of expectation of whether or not the winning type has been won (hereinafter referred to as "expectation to win"), and to arouse the player's expectation of winning. work. Typical advance notice effects include "ready effect", "pseudo-continuous effect", and "pre-reading effect". The effect control unit 24 functions as a notice effect control means capable of controlling execution (appearance) of these effects.

"Reach production" refers to a production mode with a reach state (variation display mode with a reach state: reach fluctuation pattern), specifically, to derive and display the final game result via the reach state Say the production mode. The ready-to-win effects include multiple types of ready-to-win effects associated with winning expectations. For example, in some cases, the degree of winning expectation is relatively higher than when the normal reach effect appears. Such reach performance is called 'super reach performance'. Many of these "super reach" have relatively longer presentation time (fluctuation time) than normal reach in order to arouse expectation of winning. In addition, normal reach and super reach include multiple types of reach effects. In this example, the super reach includes a plurality of types of reach effects such as super reach 1, 2, 3, and 4, and the winning expectation of these super reach 1 to 4 is "super reach 1 < super reach 2 < super Reach 3 < Super Reach 4” relationship.

"Pseudo-continuous effect" refers to a mode of production accompanied by a pseudo-continuous change display state (pseudo-continuous change) of decorative patterns. It refers to a variable display mode in which a part or all of the symbols are temporarily stopped, and the display operation is repeated once or more than once, such as performing the re-variable display operation of the decorative symbols from the temporarily stopped state. In this respect, it is different from the later-described "pre-reading forewarning effect (continuous forewarning effect)" that is developed over a plurality of symbol variation display games. Such a "pseudo-run" basically has a rate of occurrence (appearance rate) that increases the expectation of winning as the number of pseudo-fluctuations increases. It is made easy to select an effect for arousing expectations such as reach.

"Pre-reading notice effect" (hereinafter sometimes abbreviated as "pre-reading notice" or "pre-reading effect") is based on the result of pre-reading judgment, before the fluctuation display of the pattern to be judged is performed, It means an effect that notifies the possibility of being controlled in an advantageous state. The term "advantageous state" means a state that is advantageous to the player.
Specifically, the look-ahead effect of this example is mainly for pending display of the operation pending balls (undigested operation pending balls) that have not yet been subjected to the execution of the symbol variation display game (the special symbol variation display operation). Before the operation reserve ball is offered to the symbol variation display game, it is performed in a performance mode in which the degree of winning expectation can be notified in advance by using the aspect and the background effect of the symbol variation display game to be executed first. . In addition, in the pattern variation display game, in addition to the above-mentioned "reach effect", various effects such as so-called "SU (step-up) notice effect", "timer notice effect", "resurrection effect", and "premier notice effect" are available. It occurs, and it is designed to excite the game content.

Here, with reference to FIG. 4, the "holding change notice effect" as an example of the look-ahead notice effect will be described.
In the case of the gaming machine 1 of the present embodiment, a display area for displaying a decorative symbol variation display game (decorative symbol variation display effect or advance notice effect is displayed) is provided in the upper display area within the screen of the main liquid crystal display device 36M. display area) is provided, and in the lower display area in the screen, a reservation display area 76 (reservation display part a1 to d1) that displays the number of operation reservation balls on the special symbol 1 side and a special A reservation display area 77 (reservation display portions a2 to d2) for displaying the number of operation reservation balls on the symbol 2 side is provided. As for the presence or absence of the operation pending ball, that effect is reported by a predetermined pending display mode. In FIG. 4, the presence or absence of the operation retention ball is lit (with operation retention ball: “○ (white circle)” in the illustration), or in the off state (no operation retention ball: dashed circle in the illustration). It shows an example in which information about the number of balls in operation is notified.

The display (suspension display) regarding the presence or absence of the operation reserve ball is sequentially displayed in the order of occurrence (the order of winning). It is displayed as the first (that is, the oldest) active holding ball on the time axis among the holding balls. Further, on the left side of the holding display areas 76 and 77, there is provided a changing display area 78 for showing the active holding ball currently being used in the special symbol changing display game. In the case of this embodiment, the changing display area 78 is configured such that an image in which the icon of the game pending K currently being played is placed on the icon of the strike seat J. That is, when the variable display of the special symbol 1 or the special symbol 2 is started, the oldest pending a1 or a2 icon (icon image) displayed in the pending display areas 76 and 77 is the pending K during game execution. As an icon, it moves onto the icon of the striker J in the changing display area 78, and this state is maintained for a predetermined display time.

When an operation pending ball occurs, from the main control unit 20, the pre-reading judgment information related to the jackpot lottery result and the number of operation holding balls at the time of the pre-reading judgment (the number of the existing operation holding balls including the operation holding ball that occurred this time) is transmitted to the effect control unit 24 (see steps S1309 to S1312 in FIG. 28).
In the case of this embodiment, the pending addition command is composed of 2 bytes, and the pending addition command can specify the upper byte side data that can specify the number of operation pending balls at the time of prefetching determination, and the prefetching determination information. It consists of lower byte side data.

Here, as can be understood from the above description, in the present embodiment, based on the occurrence of a winning prize in the upper starting port 34 or the lower starting port 35 and a new reserved ball, the prediction of the reserved ball is performed. As a judgment, a jackpot lottery for the symbol variation display game related to the reserved ball is performed. As will be described later, the main control unit 20 reserves and stores information representing the result of the big hit lottery performed as such prefetch determination in the corresponding storage area of the RAM 20c.
The information of the jackpot lottery result obtained at the time of the prefetch determination is used to select (lottery) the pattern variation pattern in the pattern variation display game, and can be rephrased as "variation pattern selection information". Therefore, it can be said that the main control unit 20 carries out a pre-reading determination and reserves and stores the "variation pattern selection information" obtained as a result in a predetermined area of the RAM 20c.

When the effect control unit 24 receives the pending addition command transmitted by the main control unit 20, based on the prefetch determination information included therein, as part of the display control processing related to the pending display, "prefetching preview effect" is performed. Effect control processing related to is performed. Specifically, a "prefetching notice lottery" is carried out to determine whether or not the prefetching notice effect can be executed.

Here, the look-ahead determination information is, specifically, the result of the jackpot lottery (jackpot lottery result at the start of variation) executed when the operation reserve ball is offered to the symbol variation display game in the main control unit 20, This is the game information obtained by pre-reading and judging the fluctuation pattern at the time of fluctuation start. That is, this information includes at least the information (prefetching winning/losing information) that prefetches the winning/losing lottery result at the start of the fluctuation, and the information that prefetches the pattern lottery result (prefetching pattern information) and the fluctuation at the start of the fluctuation. Information (prefetch variation pattern information) obtained by prefetch determination of the pattern can be included. What kind of information is included in the pending addition command to be sent to the effect control unit 24 can be appropriately determined according to the contents to be notified by the pre-reading notice.
In this example, it is assumed that the pending addition command includes prefetch hit/loss information, prefetch pattern information, and prefetch variation pattern information.

It should be noted that the "look-ahead fluctuation pattern" obtained by the look-ahead judgment when the operation reserve ball is generated is not necessarily the "variation pattern at the start of fluctuation" obtained when the operation reserve ball is actually used for the fluctuation display operation. no. For example, representatively explaining the case where the fluctuation pattern at the start of fluctuation is a fluctuation pattern that specifies "super reach 1", in this case, the content specified by the look-ahead fluctuation pattern is called "super reach 1" It is possible to specify that it is not the type of reach production itself, but the "super reach type" that is the gist of it.

In the case of this embodiment, when the pre-reading notice lottery is won, among the holding icons of the holding display portions a1 to d1 and a2 to d2, the holding icon targeted for the pre-reading notice is, for example, a normal holding display (Normal pending display mode) can change from white (normal pending display mode) to pending display (special pending display mode) with blue, green, red, and danger patterns (or special colors and patterns such as rainbow colors) for advance notice display (special pending display mode) System" pre-reading notice effect (also referred to as "holding change notice") is performed.
FIG. 4 shows an example in which the operation holding ball of the hatched holding display portion b1 has changed to a special holding display. Here, the display of blue, green, red, and danger pattern of the pending icon means that the expectation of winning is high in this order, and especially the display of the pending icon with the danger pattern has an extremely high expectation of winning the jackpot. It is a premium pending icon that will be displayed.

(Direction means)

Various effects in the game machine 1 are produced by effect means provided in the game machine 1 . The directing means may be a stimulus transmission means capable of exhibiting a directing effect by appealing to human perception such as sight, hearing, and touch. light effect means), sound generator such as speaker 46 (sound generator 46a: sound effect means), effect display device (display means) such as main liquid crystal display device 36M and sub liquid crystal display device 36S, contact with operator's body Typical examples include a pressure device that transmits pressure, a wind pressure device that applies wind pressure to the player's body, and a movable body accessory that exerts a visual performance effect by its operation. Here, the effect display device is a display device that appeals to the sense of sight like the image display device, but differs from the image display device in that it also includes devices that do not rely on images (for example, a 7-segment display device). When it is called an image display device, it mainly refers to a type that produces effects by image display, and devices that produce effects by means other than images, such as 7-segment displays, are included in the concept of the above-mentioned effect display device.

<4. Processing of Main Control Unit>

Next, processing performed by the main control unit 20 of this embodiment will be described. The processing of the main control unit 20 mainly consists of predetermined main processing (main control side main processing: FIG. 8) and timer interrupt processing (main control side timer interrupt processing: FIG. 20) that is started by a regular interrupt from CTC. and

[4-1. Main control side main processing]

FIG. 5 is a flow chart showing main processing on the main control side.
The main processing on the main control side is started when a system reset occurs due to a system reset signal from the power supply board during recovery from a power outage or power failure, or when the control program goes out of control, the watchdog timer function ( WDT) is exhibited and the CPU 20a is forcibly reset (WDT reset). In any case, when the main processing is started, the main control unit 20 (CPU 20a) first executes initial setting processing necessary for starting the game operation, such as initial setting of register values of each unit including the CPU 20a. (step S101).

(Initial setting processing)

FIG. 6 is a flow chart showing the initial setting process in step S101.
In FIG. 6, when the above system reset or WDT reset occurs, the CPU 20a sets itself to the interrupt disabled state in step S201, and then, as stack pointer setting processing in step S202, the value of the stack pointer in the RAM 20c is transferred to the stack area. Execute the setting process corresponding to the final address of Then, in the following step S203, the RAM protection is invalidated, and the prohibition area in the outside-designated-area travel prohibition function of the RAM 20c is invalidated.

Next, in step S204, the CPU 20a executes processing for turning off the security signal, setting value display, and firing permission signal. Here, the security signal is a signal output to the hall computer HC through the frame external common terminal board 21, and functions as a signal for notifying the hall computer HC of a state such as a setting being changed. Turning off the set value display means turning off the display of the set value Ve on the setting/performance indicator 97 .
The firing permission signal is a signal output from the payout control board 29 to the firing control board 28 as described above, and the CPU 20a instructs the payout control board 29 to turn off the firing permission signal.
Here, turning off the security signal and turning off the set value display are countermeasures against turning on/off the power during setting change. That is, since the power may have been turned off while the set value Ve was being displayed in the setting change process, the set value display and the security signal are temporarily turned off.

In step S205 following step S204, the CPU 20a executes power supply abnormality check processing.
As shown in FIG. 7, in the power failure check process, the WDT timer is cleared (step S11), and it is determined whether or not the power failure signal is ON (step S12). The power failure signal is a signal output from the power supply board, and indicates that the power failure signal OFF is at a normal level, and that the power failure signal ON is not at a normal level (that is, is abnormal). If the power failure signal is ON, the CPU 20a returns to step S101 shown in FIG. 5 and redoes the main control side main processing from the beginning. That is, when an abnormality is recognized in the power supply, the main processing on the main control side is reset.
If the power supply abnormality signal is not ON, the CPU 20a terminates the power supply abnormality check process because no abnormality is recognized in the power supply.

Returning to FIG. 6, the CPU 20a performs various setting processes at the time of startup in step S206 in response to completion of the power abnormality check process in step S205. In the setting process of step S206, for example, an interrupt mode setting process for setting a predetermined interrupt mode, an internal hard random number setting process for activating an internal hard random number circuit, and the like are executed. In addition, in the setting process of step S206, a process of setting an initial value to a predetermined register among various registers provided in the CPU 20a is also performed.

In step S207 following step S206, the CPU 20a sets the activation waiting time of the sub-control board (effect control unit 24). Then, through the processing of steps S208 to S210, it waits until the set activation waiting time elapses. Specifically, 1 is subtracted from the set start-up waiting time (step S208), the power failure check process (step S209) is executed, and if the start-up waiting time is not zero (step S210: ≠0), step S208 return to the process of Activation of the effect control unit 24 is completed by the standby process based on such an activation waiting time.

In step S<b>210 , when the activation waiting time has elapsed (waiting time=0), the CPU 20 a proceeds to step S<b>211 and transmits a standby screen display command to the effect control section 24 .
In response to this standby screen display command, the effect control unit 24 causes the liquid crystal display device 36 to display a predetermined screen, such as a screen on which characters such as "Please wait..." Control for execution.

In response to the execution of the transmission process of step S211, the CPU 20a advances the process to step S212, and performs payout control while executing the power supply abnormality check process (S212: see FIG. 7) through the processes of step S212 and step S213. It waits for a power-on signal from the board 29 to be sent. This power-on signal is a signal output when the payout control board 29 normally starts up, and the CPU 20a waits until the payout control board 29 starts normally. Accordingly, when the payout control board 29 does not function normally due to some trouble, the processing of steps S212 and S213 is repeated and the game operation is not started. Therefore, an abnormal payout such as failure to pay out prize balls does not occur, and the player is prevented from feeling distrustful.
When the power-on signal is sent (step S213: ON), the CPU 20a ends the initial setting process of step S101.

(Processing after initial setting)

After completing the initial setting process, the CPU 20a proceeds to step S102 shown in FIG.
In step S102, the CPU 20a acquires the information of the input port n (that is, the predetermined input port) and copies it to the W register.
Here, the input port n is a 1-byte (8-bit) port, and in this example, the following signals are input. Note that "b0" to "b7" shown below represent bit positions.

b0: setting key (input signal from setting key switch 94)
b1: out-of-supply detection signal b2: counting error signal b3: disconnection detection signal 1
b4: disconnection detection signal 2
b5: door open signal (detection signal of front door open sensor 61)
b6: RAM clear button (input signal from RAM clear switch 98)
b7: Power-on signal and dispensing communication confirmation signal

Here, for the setting key b0, "0" means that the setting key switch 94 is OFF, and "1" means that the setting key switch 94 is ON. As for the door open signal b5, "0" means that the door is closed (the front frame 2 is closed), and "1" means that the door is open. Further, with respect to the RAM clear button b6, "0" means that the RAM clear switch 98 is OFF (button non-operated state), and "1" means that the RAM clear switch 98 is ON (button operated state).

In step S103 following step S102, the CPU 20a masks the value of the W register. Specifically, the values required for determining the migration of setting change processing (S115), RAM clear processing (at least S117 and S118), setting confirmation processing (S109), and backup restoration processing (S111) described below. The setting key (b0), the RAM clear button (b6), and the door open signal (b5) are masked.
As can be understood from the above description, the conditions for transitioning to the setting change process are that, at startup, both the setting key and the RAM clear button are in the operating state with the front frame 2 opened. ing.
Further, in this example, the condition for shifting to the RAM clear process is, in terms of operation, that the setting key is in a non-operating state and the RAM clear button is in an operating state at the time of startup.
In terms of operation, the conditions for transitioning to the setting confirmation process are that the front frame 2 is opened, the setting key is in the operating state, and the RAM clear button is in the non-operating state.
Further, as a condition for transitioning to the backup restoration process, in terms of operation, both the setting key and the RAM clear button are to be in a non-operating state at the time of startup.

FIG. 8 shows the relationship between each determination condition in terms of operation and the value of the W register when shifting to these setting change processing, RAM clear processing, setting confirmation processing, and backup restoration processing.
FIG. 8 shows the order of setting change processing, RAM clearing processing, setting confirmation processing, and transition determination to backup restoration processing.
As shown in the figure, the judgment conditions for transition to the first setting change process are: setting key: ON (setting key switch 94: ON), door open: ON (front door open sensor 61: ON), RAM clear switch 98 : ON, therefore, the conditions for the value of the W register are the 0th bit: 1, the 5th bit: 1, and the 6th bit: 1.
The determination of the transition to the second RAM clearing process is performed by determining whether or not the RAM clear switch 98 is ON and the value of the W register is 1 at the 6th bit. Here, in this example, the determination of transition to the RAM clearing process is performed when the conditions for transitioning to the setting change process are not met. In addition, the RAM clear switch 98 must be OFF in order to shift to the setting confirmation process and the backup restoration process. From these points, if the condition for transition to the setting change process is not satisfied and the RAM clear switch 98 is ON, it can be estimated that the transition operation to the RAM clear process is being performed. For this reason, in this example, as described above, in judging the transition to the RAM clearing process, in terms of operation, it is only necessary to judge whether the RAM clear switch 98 is ON (6th bit: 1 or not). and

The judgment conditions for the transition to the third setting confirmation process are set key: ON, door open: ON, and RAM clear switch 98: OFF. : 1, 6th bit: 0 is the condition.
Further, the determination conditions for the determination of the transition to the fourth backup restoration process are set key: OFF, RAM clear switch 98: OFF, and accordingly, the W register value is 0:0, 6th bit: 0. conditional.

Here, regarding the backup restoration process, the transition condition for performing only the backup restoration process without going through the setting confirmation process is described as the setting key: OFF and the RAM clear switch 98: OFF in terms of operation as described above. However, regardless of whether or not the setting confirmation process is executed, the condition for determining whether or not to simply perform the backup restoration process is that the backup flag, which will be described later, is ON (step S106). (Refer to the judgment process of ).

Returning to FIG.
After performing the masking process in step S103, the CPU 20a executes setting change condition satisfaction determination process in step S104. Specifically, it is determined whether or not the masked value (3 bits) in step S103 is "111" in order to determine whether or not to shift to the setting change mode.
If the masked value is "111" and a positive result is obtained that the setting change condition is satisfied, the CPU 20a executes the setting change process of step S115. That is, processing for newly setting the set value Ve is performed according to the operation of the RAM clear button or setting key.
Details of the setting change processing in step S115 will be described later.

Here, as described above, in this embodiment, detection signals from the setting key switch 94, the front door open sensor 61, and the RAM clear switch 98, in other words, detection signals used to determine whether to shift to the setting change mode The signals are input to the same input port of the main control unit 20, and collective determination is made as to whether or not the values of the input detection signals satisfy predetermined conditions.
As a result, the number of judgment processes can be reduced in comparison with the case of individually judging whether or not the value of each detection signal satisfies a predetermined condition for judging transition to the setting change mode.

In response to executing the setting change process in step S115, the CPU 20a executes RAM clearing process in step S116. This RAM clearing process is a process for initializing values in a predetermined area (used area) including the work area in the RAM 20c, and a setting for notifying the effect control unit 24 of the end of the setting change process executed in step S115. This includes processing for transmitting a change end command, the details of which will be described later.

Subsequently, in step S104, if the value after masking in step S103 is not "111" and a negative result is obtained that the setting change condition is not satisfied, the CPU 20a proceeds to step S105 to Determine whether or not Specifically, at least it is determined whether or not the "set value" stored in the work area of the RAM 20c is a value outside the use range Ru (outside the range of "1", "2", and "6" in this example). do.
Here, there is a set value Vd as a value handled by the CPU 20a with respect to the set value Ve. The set value Vd is a value corresponding to the set value Ve. In this example, it is a 1-byte value. Values from (0) to 02H(3) are defined. In addition, "H" means a hexadecimal number (the same shall apply hereinafter). In this example, the set value Vd=00H represents the set value Ve="1", the set value Vd=01H represents the set value Ve="2", and the set value Vd=02H represents the set value Ve="6". assumed. In the main control unit 20, the setting value Vd is mainly handled as the "setting value", and this setting value Vd is stored in the "setting value" storage area in the work area of the RAM 20c of the main control unit 20. .
In the determination process of step S105, it is determined whether or not the set value Vd stored in the work area is within the range of 00H to 02H.

If it is determined in step S105 that the set value is outside the use range Ru (that is, outside the normal range) and the RAM is abnormal, the CPU 20a waits for the power to be turned on again after step S112. Afterwards.
Specifically, in step S112, the CPU 20a sends an effect control command (setting Waiting for change command) to the production control unit 24. When a RAM abnormality is detected at startup, the setting change mode is forcibly entered, and the change (setting) of the set value Ve is accepted. Therefore, in step S112, the CPU 20a first notifies the effect control section 24 that the setting change wait command is used to shift to the setting change mode.
Receiving the setting change waiting command, the effect control unit 24 executes a screen display on the liquid crystal display device 36 for prompting the setting change operation, such as a screen including characters such as "Please open the door and change the setting". Let At this time, the effect control unit 24 may perform control to cause the corresponding light effect (for example, lighting of all LEDs in the light display device 45a) and sound effect to appear together with the screen display.

In step S113 following step S112, the CPU 20a sets the backup flag to 00H (that is, OFF), and then repeats the error display process of step S114. In the error display process of step S114, a process for causing the setting/performance indicator 97 to display an error is performed. This error display process is repeated until the power of the pachinko game machine 1 is cut off, and when the power is turned on again, the processes after step S101 are executed again as the main control side main process. At this time, if an operation to shift to the setting change mode has been performed according to the screen display or the like, the shift to the setting change mode is performed, and the RAM abnormal state is resolved.

If it is determined in step S105 that the set value is not outside the use range Ru and the RAM is not abnormal, the CPU 20a advances to step S106 to determine whether the backup flag is ON (backup flag=5AH in this example). is ON state).
In the gaming machine 1, when the power is cut off, the information stored in the RAM 20c is backed up by the power check/backup process (step S901, see FIG. 19) described later in the main control side timer interrupt process. If the backup process has been properly performed at the time of power shutdown, the backup flag is turned ON (see step S1010 in FIG. 19). Therefore, in step S106, the backup flag is checked to determine whether or not backup recovery is possible. Specifically, in step S106, it is determined whether or not the backup flag stored in the predetermined area of the RAM 20c is in the ON state (5AH).

When determining in step S106 that the backup flag is not ON, the CPU 20a advances the process to step S112 described above. As a result, when the backup return condition is not satisfied, the setting change mode is forcibly entered in the same manner as in the case where the RAM abnormality described above is recognized.

Here, as described above, the determination process in step S106 corresponds to the process of determining whether the transition to the state in which the backup restoration process is performed is possible regardless of whether or not the setting confirmation process is executed.

On the other hand, if it is determined in step S106 that the backup flag is ON, the CPU 20a determines in step S107 whether or not the RAM clear condition (condition for transition to RAM clear processing) is satisfied. Specifically, it is determined whether or not the value of the 6th bit of the W register is "1".
When the value of the 6th bit of the W register is "1" and a positive result indicating that the RAM clear condition is satisfied is obtained, the CPU 20a advances the processing to step S116 described above. As a result, the above-described RAM clear processing is executed.

Here, as can be seen by referring to the route from steps S107 to S116 described above, in the gaming machine 1 of the present embodiment, it is possible to clear the RAM without changing the settings. This makes it possible to clear data other than the set value Ve, such as payout-related data in the RAM 20c.

Further, in step S107, if the value of the 6th bit of the W register is not "1" and a negative result is obtained that the RAM clear condition is not satisfied, the CPU 20a proceeds to step S108 and sets the confirmation condition ( It is determined whether or not the transition condition to the setting confirmation process) is established. That is, it is determined whether or not the value of the W register after being masked in step S103 is "110".
When the value of the W register after masking is "110" and a positive result is obtained that the setting confirmation condition is satisfied, the CPU 20a executes the setting confirmation process of step S109, and advances the process to step S110. In other words, the process shifts to backup restoration.
The details of the setting confirmation process in step S109 will be explained again.

On the other hand, if the value of the W register after masking is not "110" and a negative result is obtained that the setting confirmation condition is not satisfied, the CPU 20a skips the setting confirmation processing of step S109 and proceeds to step S110. .

In step S110, the CPU 20a performs processing of transmitting a predetermined effect control command corresponding to the time of backup return to the effect control unit 24 as command transmission processing at the time of backup return.

In step S111 following step S110, the CPU 20a performs backup restoration processing.
The backup restoration process is a process of restoring the operation before the power shutdown after the power is turned on based on the memory contents of the RAM 20c backed up at the time of the power shutdown. Specifically, the CPU 20a restores the stack pointer before the power shutdown, and performs processing for starting the game operation from the processing state at the time of the power shutdown.
Also, in the backup recovery process, a power failure recovery display command (OB03H) for instructing information display corresponding to the backup recovery is transmitted to the effect control unit 24 in the main loop pre-processing of step S119 to be described later. Therefore, a process of storing the lower byte data of the recovery from power failure display command in the register is executed.

When the backup restoration process of step S111 is executed, or when the RAM clear process of step S116 described above is executed (that is, when both the setting change process and the RAM clear process are executed, or only the RAM clear process is executed) , the CPU 20a proceeds to step S117.

In step S117, the CPU 20a sets a CTC for periodically generating a timer interrupt every predetermined time such as 4 ms.
By performing the setting process of step S117, an interrupt request signal to the interrupt controller is periodically output thereafter, and the main control side timer interrupt process is executed.

In subsequent step S118, the CPU 20a performs processing of transmitting an effect control command for instructing the start of the game to the effect control unit 24, then advances the process to step S119 to execute main loop pre-processing, and then step S120. main loop processing.
Note that the main loop pre-processing in step S119 will be described later.

(main loop processing)

FIG. 9 is a flow chart showing the main loop processing of step S120.
In the main loop processing of FIG. 9, the CPU 20a sets itself to an interrupt disabled state in step S601, and executes random number update processing in subsequent step S602. In this random number update process, various random numbers used in the special symbol variation display game and the normal symbol variation display game (random numbers related to the jackpot lottery that circulates within a predetermined numerical range by increment processing (special symbol determination used in the symbol lottery) random number) and random number related to the subsidized lottery (random number for the subsidized hit judgment used for the subsidized lottery))) Random number used to change the initial value (start value) (initial value random number for special symbol judgment , the initial value random number for auxiliary hit determination) and the random number for the variation pattern used for selecting the variation pattern are updated.

In the RAM 20c of the present embodiment, as various random number counters used for the symbol lottery related to the big win lottery, the auxiliary winning lottery, or the fluctuation pattern lottery, a counter for generating an initial value of a random number counter for special symbol determination, a special symbol determination A random number counter for auxiliary hit determination, a counter for generating an initial value of a random number counter for auxiliary hit determination, a random number counter for auxiliary hit determination, a random number counter for variation pattern, and the like are provided. These counters serve as random number generating means for generating random numbers by software. In the random number update process of step S602, the two initial value generation counters for generating the initial values of the special symbol determination random number counter and the auxiliary hit determination random number counter described above, the variation pattern random number counter, etc. are updated, and the above various generate soft random numbers for . For example, if the numerical range that can be taken as the random number counter for the fluctuation pattern is "0 to 238", the value is obtained from the count value storage area for generating the value of the random number for the fluctuation pattern of the RAM 20c, and the obtained value is After adding "1", it is stored in the original count value storage area. At this time, if the result of adding "1" to the obtained value is "239", "0" is stored in the original random number counter storage area. Other random number counters for initial value generation are similarly updated.

After completing the random number update process in step S602, the CPU 20a saves the values of all the registers in step S603, and performs performance display monitor tally division process in step S604.
This performance display monitor aggregate division process is a process of calculating a value as the above-described performance information (here, for example, a value as the above-described "normal time ratio information"). As described above, the value of the normal ratio information is calculated using the total number of payouts and the total number of out balls. Lower starting port 35, general winning port 43, big winning port 50) is calculated based on the result of counting the number of winning game balls, and the total number of out balls is the number of game balls discharged from the out port 49. Find by counting.
The number of winning balls and the number of out balls are counted in the later-described input management process (see step S904 in FIG. 18) in the main control side timer interrupt process. The CPU 20a calculates a value as normal time ratio information in step S604 based on the count values obtained by counting the number of winning balls and the number of out balls performed by the timer interrupt processing side. As described above, the calculated value as the normal time ratio information is stored in a predetermined area (measurement information storage area) of the RAM 20c.
The value of the normal time ratio information calculated in this way is displayed on the setting/performance indicator 97 by the later-described performance display monitor display process (see step S916 in FIG. 18) in the main control side timer interrupt process.

In step S605 following step S604, the CPU 20a performs all register restoration processing, sets itself to the interrupt enabled state in step S606, and returns to step S601.

Thus, in the main loop process of step S123, the processes of steps S601 to S606 are repeated in an infinite loop. The CPU 20a repeatedly executes the processing of steps S601 to S606 except while the intermittent timer interrupt processing is being performed.

(setting change processing)

FIG. 10 is a flow chart showing the setting change process in step S115.
In this setting change process, a process for setting the set value Ve based on the operation, and an effect control command for notifying that the setting is being changed or that the setting change has been completed (completed) are sent to the effect control unit 24. Processing and the like for transmission are performed.

In FIG. 10, the CPU 20a first executes a process of transmitting a setting changing command (BA76H) to the effect control section 24 in step S401.
In response to this setting change command, the effect control unit 24 displays a screen on the liquid crystal display device 36 to notify that the setting is being changed, such as a screen on which characters such as "setting is being changed" are arranged. A process is executed to cause the setting to be executed, or to output a corresponding sound from the speaker 46 while the setting is being changed. Furthermore, at this time, the effect control unit 24 may light predetermined LEDs (for example, all LEDs) in the above-described light generating means (light display device 45a) according to a predetermined lighting pattern.

In subsequent step S402, the CPU 20a sets the backup flag to 00H (that is, OFF state), and then sets system operation status=2 in step S403. This system operation status is information for at least identifying whether or not the setting change process of step S115 has been passed at the time of startup. A value (for example, "0") indicates that the setting change process has not been performed.
As can be seen with reference to FIG. 5, in this example, the RAM is changed depending on whether both the setting change process and the RAM clear process (S116) are executed, and when only the RAM clear process is executed without executing the setting change process. Although the clear processing (program) is shared, by using the above system operation status, it is possible to execute the processing separately in the former case and the latter case while sharing the RAM clear processing program. .

In step S404 following step S403, the CPU 20a executes a process of acquiring a setting value. Specifically, the set value Vd (one of 00H to 02H in this example) stored in the work area of the RAM 20c is obtained.

The processing from step S405 following step S404 updates the display value on the setting/performance display 97 in accordance with the forward feeding operation of the set value Ve (operation of the RAM clear button), or completes the setting change operation (operation of the setting key). operation) to set the set value Ve.
First, in step S405, the CPU 20a decrements the acquired set value Vd by 1 ("set value -1"), and in subsequent step S406, determines whether or not the set value Vd is greater than 1 (set value > 1). ). In this example, since the maximum value of the setting value Vd is 02H, it is not determined that the setting value>1 in step S406, which is executed for the first time after the setting change process is started.
In step S406, if the set value Vd is not greater than 1, the CPU 20a sets the carry flag (on) in step S407, and increments the set value Vd by 1 ("set value + 1") in step S408. ), and in step S409, it is determined whether or not the carry flag is ON. If the carry flag is ON, the CPU 20a executes the setting change command acquisition process in step S411, and transmits the setting change command to the effect control unit 24 by the command process in the subsequent step S412.
The setting change command will be described later.
After executing the command transmission process of step S412, the CPU 20a executes the output management process of step S413. By this output management process, the setting value Ve corresponding to the current setting value Vd is displayed on the setting/performance indicator 97 . Details of the output management process in step S413 will be described later.

In step S414 following step S413, the CPU 20a determines whether the setting key is OFF, that is, whether the setting key switch 94 is OFF. It is determined whether or not the RAM clear switch 98 is ON. If the RAM clear switch 98 is not ON, the CPU 20a executes the output management process of step S413 again.
By the processing of steps S413 to S415, the CPU 20a waits until either the setting key or the change switch is turned on, and during the standby, causes the setting/performance display 97 to display the current set value Ve by the processing of step S413. Repeat the process for

In step S415, if the change switch is ON, the CPU 20a returns to step S406.
If the set value Vd acquired at the start of the setting change process in step S115 (the set value Vd that was being set until then) is 02H, it is determined that the change switch is ON in step S415. In the process of step S406, which is executed accordingly, a determination result of "set value>1" is obtained (because -1 is decremented in step S405, but +1 is decremented in step S408). The setting value Vd should be returned to 00H in response to a change operation (forward feeding operation) performed when the setting value Vd is 02H. Therefore, if it is determined in step S406 that "set value>1", the carry flag setting process in step S407 is skipped and the process proceeds to step S408. As a result, the carry flag is determined to be OFF in step S409, so the process proceeds to step S410 and the set value Vd is returned to 00H ("set value←0").
In response to returning the set value Vd to 00H in step S410, the CPU 20a advances the process to step S413 via the processes of steps S411 and S412. That is, in this case, the setting/performance indicator 97 displays the setting value Ve ("1" in this example) corresponding to the setting value Vd=00H.

Through the above process, while the setting is being changed, the set value Vd is cyclically changed within the range of 00H to 02H (within the use range Ru) according to the change operation, and the changed set value Vd is changed. The set value Ve is displayed on the setting/performance indicator 97 .

Further, the setting change time command transmitted in step S412 is a command for notifying the effect control unit 24 of the setting value Ve corresponding to the setting value Vd being selected during the setting change process. It is a command in which information representing Ve is stored.
Through the series of processes of steps S406 to S415 described above, every time the setting value Ve being selected is switched by the forward feeding operation of the setting value, a setting change time command reflecting the setting value Ve after switching is transmitted to the effect control unit 24. will be
10, the CPU 20a uses a set value offset conversion table (see FIG. 16) to obtain the set value Ve corresponding to the set value Vd.

When it is determined in step S415 that the setting key is OFF, the CPU 20a proceeds to step S416 and executes processing for saving the setting value Vd. That is, a process of storing the set value Vd in a predetermined area in the work area of the RAM 20c is executed.
The CPU 20a ends the setting change process of step S115 in response to executing the save process of step S416.

FIG. 11 is a flow chart of the output management process in step S413.
First, the CPU 20a executes security signal output processing in step S501. Specifically, a process for outputting a security signal to the hall computer HC through the external common terminal board 21 for frame is performed.
In the subsequent step S502, the CPU 20a executes processing for outputting 0 to the LED common port, that is, the common port of the LED as the setting/performance indicator 97, and acquires display data from the 7-segment decode table in step S503. Execute the process. That is, it is a process of acquiring display data of set values Ve (“1”, “2”, and “6”) based on set values Vd.
When 0 is output to the LED common port in step S502, the setting/performance indicator 97 is turned off (no display), the significance of which will be described later.

FIG. 12 shows an example of a 7-segment decode table, and FIG. 13 shows an example of the relationship between the segment configuration and segment display patterns in the setting/performance display 97. In FIG.
The 7-segment decoding table is stored in the ROM 20b of the main control section 20. FIG.

In this example, the seven segments in the setting/performance indicator 97 are numbered from 0 to 6 as shown in FIG. 13A. The setting/performance indicator 97 is provided with a DP (dot point) display section (light emitting section) as well as these seven segments 0 to 6, and the DP display section is numbered "7". ing.
As the 7-segment display data, a total of 10 pieces are prepared, from the display data "SEG_0" representing the numerical value "0" to the display data "SEG_9" representing the numerical value "9". The display data is 1-byte (8-bit) data, and if the least significant bit position is the first bit position, the first bit position is segment "0" display/non-display (light emission/non-light emission). represents Similarly, the second bit position is segment "1", the third bit position is segment "2", the fourth bit position is segment "3", the fifth bit position is segment "4", and the sixth bit position is segment "4". bit position indicates display/non-display of segment "5", and the seventh bit position indicates display/non-display of segment "6".
Also, in the display data in this example, the eighth bit position represents display/non-display of DP (“7”).

The 7-segment decode table shown in FIG. 12 is configured so that the corresponding display data, specifically the display data of SEG_1, SEG_2, and SEG_6 are obtained from the set values Vd=00H, 01H, and 02H. It is configured.
Specifically, in the 7-segment decode table of this example, at least an area for storing display data for each set value Vd of 00H to 05H is secured, such as the address area of "6203" to "6208" in the figure. The display data SEG_1 (“06” in the figure) corresponding to the set value Vd=00H is stored in the uppermost layer area (the area with the lowest numbered address) in this area, and the set value is stored in the second area. Display data SEG_2 ("5B" in the figure) corresponding to Vd=01H is stored, and display data SEG_6 ("7D" in the figure) corresponding to the set value Vd=02H is stored in the third area.
In this example, the fourth area corresponding to the setting value Vd=03H, the fifth area corresponding to the setting value Vd=04H, and the sixth area corresponding to the setting value Vd=05H are provided for display purposes. "00" is stored as data, but its significance will be explained again.
In the 7-segment decode table of this example, display data SEG_E ("79") for displaying "E" representing a set value error is stored in the seventh area. A setting value error can be notified through the setting/performance indicator 97 in response to a case where the setting value Vd indicates an abnormal value such as a value outside the use range Ru. .

Returning the description to FIG.
The CPU 20a performs a process of outputting the display data acquired from the 7-segment decoding table by the process of step S503 to the setting/performance display device 97 in step S504.
The subsequent processing of steps S505 to S508 is processing for dynamically lighting (intermittently lighting) the LED for displaying the set value Ve in the setting/performance display unit 97 . Specifically, in step S505, the CPU 20a increments the LED counter by 1, and in subsequent step S506, determines whether or not the 0th and 1st bits (lower 2 bits) of the LED counter are "11". Here, the low-order 2 bits of the LED counter become "11" when the increment processing in step S505 is performed multiple times of 4.
In step S506, if the 1st and 0th bits of the LED counter are "11", the CPU 20a proceeds to step S507, outputs the data designating the segment for displaying the setting value to the LED common port, and outputs the data for displaying in step S508. Execute timer count processing. By executing the output process in step S507, the setting/performance display device 97 displays the set value Ve based on the display data output in step S504. This display state is continued for the time set by the display timer in step S508 (4 ms in this example).

The output management process shown in FIG. 11 ends when the process of step S509 following the timer count process of step S508 is executed, and the process proceeds to step S414 shown in FIG. And if the change switch is ON, the output management process of step S413 is repeated. As described above, 0 is output to the LED common port in step S502, so the lighting state of the set value display LED started in the previous step S507 is canceled by execution of step S502. Since the LED counter is incremented by 1 in step S505, it is determined in step S506 that the 0th and 1st bits of the LED counter are not "11". executed. That is, after the process of step S507 is executed and the set value display LED is lit for a period of at least 4 ms, until the 0th and 1st bits of the LED counter become "11" again, that is, in this example, The LED is turned off for at least 4 ms×3=12 ms.
In this manner, dynamic lighting is realized in which the set value display LED is intermittently lit at a predetermined cycle.

In FIG. 11, the CPU 20a executes input data creation processing in step S509 in response to executing timer count processing in step S508.
This input data creation process is executed by calling the same process of step S902 in the main control side timer interrupt process (FIG. 18), for example. As will be described later, the input data created in the input data creation process includes input data of the RAM clear switch 98 indicating whether or not there is an operation to sequentially feed the set value Ve, and setting key switch 98 indicating whether or not there is an operation to complete the setting change. 94 input data are included.
As can be seen from FIG. 10, the determination of whether or not there has been an operation to complete the setting change (S414) and the determination of whether or not there has been an operation to feed the set value Ve forward (S415) are executed after the output management process of step S413. By executing the input data creation process in step S509, the data required for these determination processes are obtained in advance.

(RAM clear processing)

FIG. 14 is a flow chart of the RAM clearing process (S116) shown in FIG.
First, in step S601, the CPU 20a executes an area RAM initialization process. The initialization process in step S601 is a process of initializing (clearing) values in a predetermined area (used area) including the work area in the RAM 20c. However, in the initialization process of step S601, the storage area of the set value Vd in the work area is excluded from initialization.

Note that the performance information described above is stored in an area outside the use area of the RAM 20c (details will be described later with reference to FIG. 21), so it is not cleared in the initialization process of step S601.
The objects to be cleared by the RAM clear processing are the data in the RAM area (normal data storage area) such as various flags, timers, counters, etc. necessary for normal game progress. These data include, for example: That is, data related to the game state designation (normal state, probability variable state, time saving state, latent probability state, etc., the game state flag that specifies the current game state), a flag that specifies whether it is in a winning game (condition device operation flag), various data related to the execution of winning games (current number of rounds, maximum number of rounds, etc.), data related to jackpot lottery results (jackpot judgment flag: winning lottery result information, special pattern judgment data: pattern lottery result information) , Suspension data related to operation suspension balls (number of operation suspension balls, various random numbers used for jackpot lottery, various random numbers used for auxiliary winning lottery, random numbers for fluctuation patterns), special symbol operation status, game progress Timer (special pattern accessory operation timer), input/output data related to switches and sensors, various winning counters that count the number of winning balls in the winning opening, flag specifying the presence or absence of electric support state (open extension flag), electric Electric support number counter that counts the remaining number of support, counter that counts the remaining number of times in high probability state (special figure probability variable number counter, general figure probability variable number counter), various error flags (excluding RAM error flag), and payout related data, etc. In any case, when the RAM clear process is executed, all data other than specific data (set value Vd and performance information) are set to the initial state.

Here, as can be understood from the description of FIG. 5 above, when the setting change process (S115) is executed, the process proceeds to step S116 and the RAM clear process is executed.
The setting value Vd can be changed in the setting change process. If the set value Vd is changed, there is a possibility that the values stored in the work area of the RAM 20c other than the set value Vd will not match the changed set value Vd. Therefore, when the setting change process is performed, the area other than the set value Vd in the work area is cleared (initialized) by executing the RAM clear process.

In response to the execution of the initialization process of step S601, the CPU 20a sets 30 s to the RAM clear notification timer in step S602 and executes the process for setting the deviation to this special figure. The RAM clear notification timer is a timer for setting the RAM clear notification time executed by the effect control unit 24 according to the RAM clear command transmitted in the processing of step S803 in FIG. set. In addition, the special figure referred to here means, for example, the special figure 1 and the special figure 2 described above.

In step S603 following step S602, the CPU 20a determines whether or not the above-described system operation status is "2". That is, it is determined whether or not the setting change process of step S115 has been performed after activation.
If the system operation status is "2", the CPU 20a executes the processing corresponding to the setting change processing in steps S604 to S612.
If the system operation status is not "2", the CPU 20a advances the process to step S613, stores the lower byte data of the RAM clear command in the register, and ends the RAM clear process of step S116.
The operation of storing the lower byte data of the command in the register as described above functions as the operation of designating the command type to be transmitted in step S804 of the main loop preprocessing (FIG. 17), which will be described later.

After going through the setting change process, the CPU 20a first resets the system operation status to "0" in step S604, executes the process of acquiring the setting change end command (BA77H) in step S605, and executes the command acquisition process in step S606. A setting change end command is transmitted to the effect control unit 24 by transmission processing.

The processing of steps S607 to S612 subsequent to step S606 is processing related to the display of the set value Ve on the setting/performance indicator 97. FIG.
First, in step S607, the CPU 20a outputs data designating a segment for setting value display to the LED common port. DP is added to the display data in step S609, that is, the value of the 7th bit position of the display data is set to "1". Output to the setting/performance indicator 97 .

The processing of steps S612 and S613 following step S611 is processing for continuing the display state of the set values Ve and DP on the setting/performance display 97 for a predetermined time (1 s in this example). Specifically, the CPU 20a repeatedly executes display timer count processing in step S612 (for example, timer count processing with a period of 4 ms similar to the previous step S508 (see FIG. 11)) until it is determined in step S612 that 1 s has elapsed. do.

If it is determined in step S612 that 1 s has passed, the CPU 20a executes the storage processing in step S613 and ends the RAM clear processing in step S116.

As can be understood from the description so far, when the setting change process of step S115 is executed and the setting change completion operation is performed (step S412 of FIG. 10: Y), in the RAM clear process of step S116 A setting change end command is transmitted to the effect control unit 24 (S605, S606), and notification of the end of the setting change is made.
In the case of this example, the setting change end command notifies the effect control unit 24 that the setting change has ended, and does not have the function of notifying the set value Ve set in the setting change process. .
In this example, the setting value Ve set in the setting change process is notified to the effect control unit 24 by a setting value command transmitted in the process of step S808 in FIG. 17 (main loop pre-processing) described later.

(Setting confirmation process)

FIG. 15 is a flow chart showing the setting confirmation process in step S109.
The setting confirmation process is a process for confirming and displaying the setting value Ve being set.
In FIG. 15, the CPU 20a first sets the fraud information timer to 30s in step S701. The fraud information timer is a timer for managing the output time of the security signal to the hole computer HC.
In subsequent step S702, a process of acquiring current set value information is performed. That is, the set value Vd stored in the work area of the RAM is acquired.

In step S703 following step S702, the CPU 20a executes processing for acquiring setting value data from the setting value offset conversion table.

FIG. 16 shows an example of the set value offset conversion table stored in the ROM 20b of the main control section 20. As shown in FIG.
The set value offset conversion table converts the set value Vd (00H to 02H) to the set value Ve (“1
, '2', '6') as a table for conversion into identification data ('SETNUM1' to 'SETNUM6').
In this example, the set value offset conversion table has at least an area for storing the identification data of the set value Ve for each of the set values Vd of 00H to 05H, such as the address areas of "6215" to "6220" in the figure. The identification data (“00” in the drawing) of the setting value Ve “1” corresponding to the setting value Vd=00H is stored in the uppermost area of this area, and the setting value Vd=01H is stored in the second area. The identification data (“01” in the drawing) of the corresponding setting value Ve “2” is stored, and the identification data (“05” in the drawing) of the setting value Ve “6” corresponding to the setting value Vd=02H is stored in the third area. stored.
In this example, the fourth area corresponding to the setting value Vd=03H, the fifth area corresponding to the setting value Vd=04H, and the sixth area corresponding to the setting value Vd=05H have the setting value "00" is stored as the identification data of Ve, but its significance will be explained again.

In FIG. 15, the CPU 20a acquires the above identification data as "set value data" by the acquisition process of step S703.

In response to the execution of the acquisition process of step S703, the CPU 20a executes the acquisition process of the setting confirmation command (BA6xH) in step S704, and transmits the setting confirmation command to the effect control unit 24 by the command transmission process of the following step S705. Send.
In the acquisition process of step S704, the CPU 20a performs a process of including the setting value data acquired in step S703, that is, the identification data for identifying the setting value Ve being set among the current setting values in the setting checking command.
As a result, the command transmission process of step S705 is executed, so that the effect control unit 24 is notified of the fact that the setting is being checked and the current set value Ve.

The processing of steps S706 and S707 subsequent to step S705 is processing for displaying the current set value Ve on the setting/performance display 97 .
Specifically, in step S706, the CPU 20a first executes a process of acquiring set values and DP data. That is, a process of acquiring the current set value Vd stored in the work area of the RAM 20c and the DP data ("1") in the setting/performance indicator 97 is executed. After that, the output management process of step S707 is executed. The output management process in step S707 is the same as the output management process in step S413 shown in FIG. As a result, the setting/performance indicator 97 in this case displays the value representing the current set value Ve and DP.

In step S708 following step S707, the CPU 20a determines whether or not the setting key is OFF (the setting key switch 94 is OFF), that is, whether or not an instruction to end the setting confirmation display has been performed. If so, the output management process in step S707 is executed again. As a result, after the setting confirmation command is transmitted in step S705, the process of step S708 waits until an instruction to end the setting confirmation display is performed. The process of displaying the current set values Ve and DP on the display 97 is continued.

When it is determined that the setting key is OFF in step S708, the CPU 20a executes the acquisition processing of the setting confirmation end command (BA67H) in step S709, and transmits the setting confirmation end command to the effect control unit 24 by the command transmission processing of step S710. Then, the setting confirmation process of step S109 is completed.

(main loop preprocessing)

FIG. 17 is a flowchart of main loop pre-processing in step S119.
In the main loop pre-processing, the CPU 20a first executes an initialization command acquisition process in step S801, and transmits the initialization command to the effect control unit 24 by command transmission processing in subsequent step S802. The initialize command is a command for instructing initialization (origination return) of the movable body role product motor 80c that operates the movable body as the role product.

In step S803 following step S802, the CPU 20a performs processing for acquiring transmission command data from the acquired lower byte command, and transmits the acquired command data to the effect control unit 24 by command transmission processing in step S804.
Here, in the acquisition process of step S803, the data of the command whose lower byte data is stored in the register in the course of the process passed after activation is acquired. Specifically, when the RAM clearing process of step S116 is performed (when both the setting change process and the RAM clear process are performed, or when the setting change process is not performed and only the RAM clear process is performed), Data of the RAM clear command (BA02H) is obtained. On the other hand, if the backup restoration process of step S111 is performed (when both the setting confirmation process and the backup restoration process are performed, or when only the backup restoration process is performed without the setting confirmation process), the power failure restoration is performed. Data of the display command (OB03H) is acquired.
As a result, the effect control unit 24 executes different processes depending on whether the RAM clear process is performed or the backup return process is performed.

In step S805 following step S804, the CPU 20a executes processing for transmitting the pending number of the special figure 1 and the special figure 2. Here, in the process of step S805, when the backup return process of step S111 is performed, the pending number of special figures 1 and 2 is transmitted to the effect control unit 24, and the RAM clear process of step S116 is performed. If so, the pending number is not transmitted (because the pending number information has been cleared).

The processing of steps S806 to S808 following step S805 is processing for notifying the effect control unit 24 of the current set value Ve by a set value command.
First, in step S806, the CPU 20a acquires the setting value Vd stored in the work area of the RAM 20c as processing for acquiring current setting value information. 16) to acquire the set value data. Specifically, the identification data of the setting values Ve (“1”, “2”, and “5”) corresponding to the setting values Vd (00H to 02H) obtained in step S806 are obtained.
Then, the CPU 20a performs acquisition processing of the set value command (F6xxH) in subsequent step S808, and transmits the set value command to the effect control unit 24 by command transmission processing in step S809.
In acquisition processing in step S808, a setting value command including the identification data acquired in step S807 is acquired. With such a setting value command, it is possible to notify the present setting value Ve to the effect control section 24 .

In response to execution of the command transmission processing in step S809, the CPU 20a executes internal function register setting processing in step S810, that is, register setting processing for initial setting of various functions such as the hardware random number counting function. In S811, a process of setting the performance display monitor lighting timer to 5 seconds is executed. The performance display monitor lighting timer is a timer for managing the operation time of the operation confirmation lighting operation (blinking operation for 5 seconds in this example) when the setting/performance indicator 97 is activated.

Furthermore, in step S812 following step S811, the CPU 20a resets the system operation status to "0", and turns on the firing permission signal for the payout control board 29 in step S813. In response to this, the payout control board 29 determines that the shooting permission state is set, outputs the permission signal to the shooting control board 28, and permits the shooting operation of the game ball by the shooting device 32. FIG. Thereby, the game ball can be shot by the shooting operation handle 15. - 特許庁
In this case, the discharge control board 29 receives a discharge permission signal from the main control unit 20 and permits the discharge operation. However, the present invention is not limited to this, and for example, a configuration in which the main control unit 20 directly outputs the firing permission signal to the firing control board 28 is also possible. .
After executing the process of step S813, the CPU 20a ends the main loop pre-processing of step S119.

(Advantages of the set value display data table and the set value conversion table)

Here, in this embodiment, like the setting value offset conversion table shown in FIG. is stored.
This data table contains set value related information selected when the main control unit 20 refers to set values Vd (“00H” to “02H”) that can be set by the setting change process (see FIG. 10). It includes certain first set value related information and second set value related information that is set value related information that is selected when the main control unit 20 refers to a set value that cannot be set by the setting change process. Specifically, as the first set value related information, "00", "01", and "05" respectively stored at addresses "6215", "6216", and "6217" in the set value offset conversion table shown in FIG. 16 correspond. , "00", "00", and "00" stored in addresses "6218", "6219", and "6220" correspond to the second set value related information.
Further, in the data table, as the first set value related information, at least specific information (that is, "00" at the address "6215") related to the set value Ve representing the stage with the lowest winning probability is stored, and the second set value related information is stored. As the value-related information, the same information as the specific information is stored.

When the set value Vd is a value that cannot be set, it is conceivable to rewrite the set value Vd stored in the RAM 20c to a value representing the lowest level.
However, if it is tampered with after being rewritten, there is a risk that the corresponding information will be obtained from the data table based on the unsettable set value Vd, and that an operation will be implemented according to the unsettable set value.
According to the above configuration, since it is impossible to obtain information corresponding to the set value Vd that cannot be set from the data table, it is possible to prevent fraudulent acts from being established, and the game is fair. can increase

Further, in this embodiment, 0 is stored as the specific information described above.
As a result, it is possible to prevent fraud due to falsification of setting values by a simple method of writing specific information=0 in the setting value related information. That is, the fairness of the game can be enhanced by a simple method.

In the present embodiment, the 7-segment decoding table shown in FIG. 12 is also set value-related information selected when the main control unit 20 refers to the settable set value Vd through the setting change process. Setting value related information (addresses “6203” to “6205”) and second setting value related information that is setting value related information that is selected when the main control unit 20 refers to a setting value that cannot be set by setting change processing. (addresses "6206" to "6208") are included. In the 7-segment decoding table, 0 is stored as the second set value related information.
As a result, even if the data table is referenced by the setting value Vd that cannot be set in the setting change process due to fraudulent activity or some kind of malfunction, the setting value display means (in this example, the setting/performance display unit 97) can still be set. It is possible to prevent the value display from being performed. Specifically, in this example, data of "00", that is, "00000000" is acquired as the display data, so all the segments "0" to "6" in the seven segments for setting value display are hidden. As a result, numerical values are not displayed.
Therefore, erroneous display of set values can be prevented.

[4-2. Main control side timer interrupt processing]

The main control side timer interrupt processing will be described with reference to the flowchart of FIG.
The main control side timer interrupt processing is started by an interrupt from the CTC at regular intervals (about 4 ms), and is executed by interrupting the execution of the main control side main processing.

In FIG. 18, when a timer interrupt occurs, the CPU 20a first executes power check/backup processing in step S901. This power supply check/backup process mainly monitors the level of power supplied from the power supply board, and if an abnormality such as a power failure occurs, the power is restored so that the game can be resumed without hindrance when the power is restored. A backup process or the like is performed to store predetermined game information in the RAM 20c.

(power supply check/backup processing)

FIG. 19 is a flowchart showing the power supply check/backup process in step S901.
In the power supply check/backup process, in step S1001, the CPU 20a reads the power failure signal output from the power supply board twice, and in the following step S1002, determines whether or not the read values match. If the two values do not match, the process returns to step S1001 and the power failure signal is read twice.

If both values match in step S1002, the CPU 20a determines in step S1003 whether or not the power failure signal is at a normal level (the power failure signal is OFF=normal level, ON=not normal level).
If the power failure signal is at the normal level (step S1003: OFF), the CPU 20a turns the backup flag OFF in step S1004, clears the power failure check counter in step S1005, and ends the power failure check process in step S901. That is, when it is confirmed that the power failure signal is at a normal level, the timer interrupt processing is continued without executing the backup processing described below.

On the other hand, if the power supply abnormality signal is not at the normal level in step S1003 (step S1003: ON), the CPU 20a increments the value of the power supply abnormality confirmation counter by one in step S1006, and increases the value of the power supply abnormality confirmation counter in step S1007. It is determined whether or not the value is equal to or greater than a predetermined threshold (threshold = a natural number equal to or greater than 2: for example, "2").
If the value of the power supply abnormality confirmation counter is not equal to or greater than the threshold, the CPU 20a ends the power supply abnormality check process in step S901. In other words, when the power failure signal is detected to be at a non-normal level but not continuously detected, the backup process is not performed and the timer interrupt process is continued.

On the other hand, if the value of the power supply abnormality confirmation counter is equal to or greater than the threshold, the CPU 20a performs backup processing shown as steps S1008 to S1011.
Specifically, the CPU 20a first clears the value of the power supply abnormality confirmation counter (S1108), turns off the firing enable signal (S1009), and turns on the backup flag (S1010).
Furthermore, the CPU 20a transmits a power-off command to the effect control unit 24 (S1011), and advances the process to step S1012.

In step S1012, the CPU 20a performs a process of validating RAM protection and invalidating the prohibited area.
RAM protection is a function to prevent rewriting of the RAM 20c due to malfunction or erroneous operation. By setting the RAM protection to valid, only data reading from the RAM 20c is allowed and data writing is disabled.
Also, the prohibited area is an area corresponding to the specified area in the IAT (prohibition of traveling outside the specified area) function, and by setting the prohibited area to invalid, the IAT reset will not occur thereafter.

In step S1013 following step S1012, the CPU 20a clears the value of the output port, and in step S1014, stops timer interrupt processing, sets itself to an interrupt disabled state, and shifts to infinite loop processing.
During this infinite loop, the CPU 20a is reset by the WDT and transitions to an operation stop state due to loss of operating power.

Returning the description to FIG.
In FIG. 18, after completing the power supply check/backup process in step S901, the CPU 20a executes input data creation process in step S902. Specifically, input data is created based on input information (ON/OFF signals and rising states (ON edge, OFF edge)) from various sensors and switches.
The input information here is, for example, the upper starting opening sensor 34a, the lower starting opening sensor 35a, the normal symbol starting opening sensor 37a, the big winning opening sensor 52a, the general winning opening sensor 43a, and the OUT monitoring switch 49a. ON/OFF information (winning detection information) of the switch signal to be output, ON/OFF information (operation information), state signals from the payout control board 29 (ON/OFF information of the front door open sensor 61 and the full detection sensor 60), and the like. As a result, whether or not a game ball is detected in an out hole or each winning hole is monitored for each interruption.

After finishing the input data creation process of step S902, CPU20a is step S903 and performs the timer management process which manages the timer used for game motion control. Here, the values of various timers used for game operation control of the gaming machine 1 are updated (subtraction processing).

Next, in step S904, the CPU 20a performs input management processing. In this input management process, based on the input data created in the input data creation process (S902), the values of the winning counter and OUT ball monitoring counter are updated. A "winning counter" is a counter that is provided for each winning hole and counts the number of winning game balls (the number of winning balls). The OUT ball monitoring counter is a counter for counting game balls discharged from the OUT port 49 (out balls).
The input management process in step S904 functions as input management means for managing input signals (detection signals) from various winning opening sensors.

In step S905 following step S904, the CPU 20a executes a setting abnormality check process.

FIG. 20 is a flowchart showing the setting abnormality check process in step S905.
In FIG. 20, the CPU 20a checks the set value error flag in step S1101. The setting value error flag is a flag that is set (turned ON) by the processing of step S1103 described below when an abnormality is recognized in the setting value Vd. In this example, "5AH" means the ON state. .

In step S1101, if the set value error flag is "5AH" (ON state), the CPU 20a ends the setting abnormality check process in step S905. That is, the fact that the setting value error flag is determined to be ON in step S1101 means that the transmission of the setting value abnormality command (the command for instructing the performance control unit 24 to perform setting error notification) has already been executed in step S1104, which will be described later. Therefore, the setting error check process ends without sending the setting value error flag again.

On the other hand, if it is confirmed in step S1101 that the set value error flag is not "5AH" (it is OFF), the CPU 20a determines in step S1102 whether the set value Vd is within the normal range (within the range of 0 to 2). determine whether or not Specifically, the setting value Vd stored in the work area of the RAM 20c is obtained, and it is determined whether or not the value is within the range of "00H" to "02H".

If the set value Vd is within the normal range, the CPU 20a ends the setting abnormality check process in step S905.
If the set value Vd is not within the normal range, the CPU 20a advances to step S1103 to set the set value error flag (ON state). A value abnormality command is transmitted to the production control unit 24, and the setting abnormality check process is finished.
Here, the setting value error flag includes step S1308 in FIG. 25 (setting error determination at the time of winning) to be described later, step S1501 in FIG. It is used in step S1701 in FIG. 30 (setting error determination when performing variation pattern lottery at the start of variation).

Here, upon receiving the set value abnormality command, the effect control unit 24 performs processing for notifying data abnormality of the set value Ve. For example, the liquid crystal display device 36 is caused to display an image including a message such as "RAM is abnormal. Please call a member of staff."
In the gaming machine 1, a setting error (setting value error) can be canceled by performing a setting change operation.

Return the description to FIG.
After completing the setting abnormality check process in step S905, the CPU 20a executes error management process in step S906. In this error management process, based on input data related to various sensors and status signals from the payout control board 29, the presence or absence of error occurrence is monitored.
When an error occurs, the CPU 20a transmits the corresponding command to the effect control unit 24 as an error process when the error type requires transmission of an error command. When the effect control unit 24 receives this error command, it executes error notification according to the error type. In addition, the CPU 20a transmits an error cancellation command to the effect control section 24 when the occurring error is eliminated. When the performance control unit 24 receives this error cancellation command, it terminates the error notification being executed.

Next, in step S907, the CPU 20a executes timer interrupt random number management processing for periodically updating the random numbers associated with each variation display game. Here, in order to make the count value of the random number counter random, for the random number for special symbol judgment and the random number for auxiliary hit judgment, update the random number (add +1 for each interrupt), and Then, the process of changing the start value of the random number counter is performed. Note that the internal lottery random numbers (big hit determination random numbers) are generated by the random number generation circuit, and are not updated here.

In step S908 following step S907, the CPU 20a executes prize ball management processing. In this winning ball management process, the winning counter is checked, and if there is a winning, a payout control command designating the number of winning balls is transmitted to the payout control board 29 . When the payout control board 29 receives the payout control command, it controls the game ball payout device 19 based on the prize ball number information included in the payout control command to execute the payout operation for the designated number of prize balls.

Subsequently, CPU20a is step S909 and usually performs design management processing. In this normal symbol management process, a process necessary for executing the normal symbol variation display game is performed. Here, it monitors whether or not the game ball is detected by the normal symbol start opening sensor 37a, and when the game ball is detected, predetermined game information (such as a random number for auxiliary hit determination) necessary for the auxiliary winning lottery is generated. Acquire (random number acquisition process), hold and store the maximum number of held balls up to the upper limit with the game information as hold data (operation hold balls related to normal symbols) (hold storage process). Then, when the predetermined fluctuation display start condition regarding the normal pattern is satisfied, an auxiliary winning lottery based on the operation holding ball is performed, and the selection of the normal pattern fluctuation pattern based on the auxiliary winning lottery result and the normal pattern stop display mode (normal stop symbol). Further, here, in order to cause the normal symbols to perform a variable display operation, LED display data for variable display is created if the pattern is fluctuating, and LED display data for stop display is created if the pattern is not fluctuating.

Further, the CPU 20a executes a normal electric accessary product management process in step S910. In this normal electric accessary product management process, a process necessary for executing the normal electric open game is performed. Specifically, when the lottery result of the auxiliary winning lottery is a hit, a process of setting solenoid control data for the normal electric accessory solenoid 41c is performed. Based on the solenoid control data set here, an excitation signal is output to the ordinary electric accessory solenoid 41c, whereby the opening/closing operation pattern of the movable wing 47 is controlled.

Next, the CPU 20a executes special symbol management processing in step S911. In this special symbol management process, a big hit lottery is mainly performed in the special symbol variation display game, and based on the result of the lottery, the special symbol variation pattern (forecast variation pattern and variation pattern at the start of variation) and the special stop symbol are determined. is determined, and other processes necessary for the special symbol variation display game are executed.

Next, the CPU 20a executes a special electric accessary product management process in step S912. In this special electric accessary product management process, the setting process necessary for controlling the execution of the winning game is performed. Specifically, when the jackpot lottery result is a jackpot, the execution control of the hit game (jackpot game) corresponding to the hit type is performed.
Specifically, it sets solenoid control data for the big winning hole solenoid 52c, counts the number of rounds (in the case of a big hit), and monitors the maximum number of winnings to the big winning hole 50 and the opening time. In addition, when the winning game is finished, transition setting of the game state is performed based on the game state at the time of winning and the winning type.

Also, here, a plurality of production control commands are transmitted according to the progress of the winning game. At the start of the jackpot, at the start of the round game, at the end of the round game, at the end of the maximum number of rounds, etc., the timing of sending the jackpot start command, the round start command, the round end command, the big win opening prize command, and the jackpot end command has arrived. send accordingly. The big win start command includes the current winning type information, and is used on the side of the performance control section 24 when determining a series of winning performance scenarios to be developed during the winning game. In addition, the jackpot end command includes information about the type of the hit this time and the game state at the time of winning the hit, that is, information capable of specifying the game state after the end of the hit game. It is used when deciding the production mode after the game. Therefore, since this "jackpot end command" can specify the game state after the end of the winning game, it plays a role as a game state designation command for designating the game state.

After completing the process for progressing the game up to step S912, the CPU 20a performs an external terminal management process in step S913. In this external terminal management process, the operating state information of the gaming machine 1 is output to external devices such as the hall computer HC and island lamps through the external centralized terminal board 21 for frame. The operating state information includes, for example, game information such as winning game occurrence information, symbol variation display game execution start information, number of wins/number of prize balls, and error information.

Next, the CPU 20a executes LED management processing in step S914. In this LED management process, output control of control signals (dynamic lighting data) for LED indicators such as the normal symbol display device 39a, the special symbol display devices 38a and 38b, and the setting/performance indicator 97 is performed. A control signal based on display data created in normal symbol management processing (step S909), special symbol management processing (step S911), etc. is output to the corresponding display device or indicator in this LED management processing, and display control is performed. done. As a result, a series of variable display operations (variable display and stop display) of the special symbols in the special symbol display devices 38a and 38b and the normal symbols in the normal symbol display device 39a are realized.

In step S915 following step S914, the CPU 20a saves the values of all registers, and then performs performance display monitor display processing in step S916. That is, this is a process for causing the setting/performance indicator 97 to display the value as the above-described normal time ratio information.
As mentioned above, in the case of this example, the value of the normal time ratio information is recalculated each time the number of out balls in all states reaches a predetermined specified value, and the setting/performance indicator 97 displays the current normal It is possible to display the time ratio information and the previous normal time ratio information (normal time ratio information whose calculation was completed at the most recent recalculation timing). Therefore, in the display processing in step S916 in this case, processing for displaying the values as the normal time ratio information on the setting/performance display unit 97 is performed.
It should be noted that the current normal time ratio information value is a value calculated in the processing of step S604 in the main loop processing (FIG. 11) described above, and the previous normal time ratio information value is stored in a predetermined area of the RAM 20c. Then, the CPU 20a reads out the stored value and causes the setting/performance display 97 to display it.

Next, the CPU 20a restores the values of all registers in step S917, clears the WDT count value in step S918, and ends the main control side timer interrupt processing.

When the above timer interrupt processing ends, the CPU 20a executes the main loop processing (S123) until the next timer interrupt occurs.

<5. Processing Transition Between In-Area Processing and Out-of-Area Processing>
[5-1. About used area and non-used area]

FIG. 21 is an explanatory diagram of areas (memory areas) set in the memory in the main control unit 20. As shown in FIG. Specifically, it is an explanatory diagram of the areas set in the memory accessible by the CPU 20a as the ROM 20b and the RAM 20c.

The memory accessible by the CPU 20a includes a first memory area (shaded area in the drawing) and a second memory area (satin-finished area in the drawing). The first memory area is defined as an area for arranging predetermined programs and data used by the CPU 80a in progressing game operations (games). The second memory area is defined as an area for arranging programs and data permitted to be arranged outside the first memory area.
In this example, the programs and data related to the management and display of the performance information described above are allowed to be allocated in the second memory area. Specifically, the program and data related to the performance display monitor total division processing (S304) in the main loop processing (S120) shown in FIG. 9, and the performance display monitor display processing in the main control side timer interrupt processing shown in FIG. These are programs, data, etc. related to (S916).

Here, the first memory area is called a "usable area" in the sense of an area made available for use in the game progress process. On the other hand, the second memory area is called an "outside use area" in the sense that it is an area that can be used in specific processes other than the game progress process.
In addition, hereinafter, the area "outside the use area" as the second memory area may be referred to as "outside use area". Further, in the following description, "inside the area" and "outside the area" mean "inside the use area" and "outside the use area", respectively, unless otherwise specified.

As shown, each of the first memory area and the second memory area includes a control area for storing the program, a data area for storing data used by the program, and various data generated in the course of processing by the program. A R/W area (Read/Write area) is set to rewritably store flags, timer values, and the like. The control area and data area correspond to areas within the ROM 20b, and the R/W area corresponds to an area within the RAM 20c.

FIG. 22 is an explanatory diagram of regulations defined for the first memory area and the second memory area.
In each of the first and second memory areas, the program in the control area is permitted to refer to and update (record) the data in the R/W area within its own area. On the other hand, in each of the first and second memory areas, the program in the control area is only permitted to refer to the data in the R/W area in the other memory area, but is not permitted to update it. For example, the program in the first memory area can only refer to the flag recorded in the R/W area in the second memory area by the program in the second memory area, and cannot update it. .
Although not shown, only programs in the same memory area are permitted to refer to data in the data area. That is, a program in the first memory area refers to data in the data area in the second memory area, and a program in the second memory area refers to data in the data area in the first memory area. such is not allowed.

[5-2. Processing transition method in the preceding example]

Here, in the process of the CPU 20a executing the processes described with reference to FIGS. There is a process of returning to the processing of the program in the area upon completion of the processing of . That is, there is a processing transition between in-region and out-of-region. As a specific example of such process transition, in the main loop process (S120) shown in FIG. After executing the process of the program outside the area), a process of transitioning again to the random number update process in step S302 can be mentioned.

Here, first, a method as a prior example will be described with respect to the method of processing transition between the inside and the outside of the area as described above.
FIG. 23 is a diagram showing the register configuration of the CPU 20a in the prior example.
As shown in the figure, the CPU 20a in the prior example includes a PC (program counter) register 100, an I (interrupt) register 101, and an R (refresh) register 102, as well as a table register 103 and a back register 104 each comprising a plurality of registers. It has
Table register 103 includes Q register 105, A (accumulator) register 106, F (flag) register 107, B register 108, C register 109, D register 110, E register 111, H register 112, L register 113, and IX register 114. , IY register 115 and SP (stack pointer) register 116 .
The back register 104 includes Q'register 105', A'register 106', F'register 107', B'register 108', C'register 109', D'register 110', E'register 111', H'register. 112', L' register 113', IX' register 114', and IY' register 115'.
Among these various registers, at least the B register 108 to L register 113 and the B' register 108' to L' register 113' are general-purpose registers.

An example of a program relating to processing transition between inside and outside the area will be described with reference to FIGS. 24 and 25. FIG.
FIG. 24 exemplifies a program of a portion mainly corresponding to the main loop processing of step S120 (especially the portion waiting for an interrupt: see FIG. 9) in the main control side main processing (FIG. 5), and FIG. A program related to the performance display monitor tabulation division process (S304) is exemplified as an external program.

For confirmation, the main instructions among the various instructions used in the program will be explained. The instruction here refers to a mnemonic instruction in assembly language.
"DI" is an interrupt disable instruction, and "EI" is an interrupt enable instruction.
"PUSH" is an instruction to stack (save) the value of a specified register in the stack area of the memory (RAM 20c), and "POP" is an instruction to retrieve (write) the value of the stack area to a specified register.
"LD" is a load instruction, which is an instruction to write the value of the location specified on the right side to the location specified on the left side after the description of "LD". For example, the description "LD R,n" (where R is a value that specifies a register and n is a value that specifies an address in memory) is the register specified by R and the It is an instruction to write the value of the address on the memory. Also, the description "LD n, R" is an instruction to write the value of the register specified by R to the address on the memory specified by n.
"CALL" is a program call instruction, and "RET" is an instruction to return processing to the caller.

The lower portion of FIG. 24 ("ZANYO_1" in the figure) shows a program for interrupt waiting processing in the main loop processing (S120). As can be seen from FIG. 9, in the main loop process, the random number update process (step S302) and the performance display monitor tally division process are executed while waiting for this interrupt.
First, in the interrupt waiting process, an interrupt disabled state is set by the DI instruction. The reason why the interrupt is prohibited here is to prevent the interrupt processing from being executed during the random number update processing executed by the next instruction. It also has the meaning of preventing interrupt processing from being executed during the execution of an out-of-area program, which will be described later. If an interrupt processing program is executed as an in-area program while an out-of-area program is being executed, the interrupt processing program accesses the work memory in the use area and updates the memory. That is, interrupt processing is prohibited because the inside of the area will be updated during the execution of the program outside the area.

Next, various random number update processes are called and executed by the command "CALL M_RNDJOB".

The values of the A register 106 and F register 107 are saved in the memory by the "PUSH AF" instruction following the "CALL M_RNDJOB" instruction. This instruction is executed because the contents of the F register 107 need to be saved since the contents of the F register 107 change when "LD SP,n" is executed in the out-of-area program described below.

The "CALL_SHKSHM" instruction following the above "PUSH AF" calls the performance display monitor aggregate division processing outside the area.

As shown in FIG. 25, in the performance display monitor tabulation division process, first, a stack pointer specifying an address outside the use area is set by the instruction "LD SP,_ESTPNT". Then, all the registers from the B register 108 to the L register 113 are saved by the instructions "LD (_RBCBUF), BC", "LD (_RDEBUF), DE", and "LD (_RHLBUF), HL" in the figure.
Various instructions after "LD (_RHLBUF), HL" perform processing for calculating values as performance information.

In the figure, the instructions ``LD BC, (_RBCBUF)'', ``LD DE, (_RDEBUF)'' and ``LD HL, (_RHLBUF)'' from 2 lines to 4 lines before the last line restore all registers. The stack pointer is restored by the instruction "LD SP,_ISTPNT2" one line before the last line. Then, the "RET" instruction on the last line returns the processing to the caller. That is, it returns to the processing of the program in the area.

In response to the above "RET" instruction, the instruction "POP AF" after "CALL_SHKSHM" in FIG. 24 is executed. The values of the A register 106 and F register 107 are restored by this "POP AF".
Next, "EI" enables interrupt processing, and "JR ZANYO_1" returns the processing to the top of "ZANYO_1" to implement loop processing as interrupt wait processing.

Here, in the preceding example, since there is one SP (stack pointer) register 116, the SP pointer 116 is shared by the program inside the area and the program outside the area. For this reason, it is necessary to perform "PUSH AF" or "POP AF" processing when processing transitions between inside and outside the area. That is, when calling a program outside the area in the program inside the area, it is necessary to write these "PUSH AF" and "POP AF" instructions without fail.
As mentioned above, the use area is an area in which programs related to the progress of game operations are placed. The usage area tends to be squeezed. Therefore, it is requested to reduce the program capacity in the used area.

[5-3. Process migration method as an embodiment]

FIG. 26 is a diagram showing the register configuration of the CPU 20a in the embodiment.
As shown, the CPU 20a of the embodiment comprises a PC register 100, an I register 101, and an R register 102, as well as a first register bank 121, a second register bank 122, and an IFF (interrupt control flag) register 125. there is
Here, the register bank is a register group consisting of a plurality of registers including general-purpose registers. The first register bank 121 and the second register bank 122 each have a main register 123 and a sub-register 124. The main register 123 corresponds to the table register 103 shown in FIG. , A register 106, F register 107, B register 108, C register 109, D register 110, E register 111, H register 112, L register 113, IX register 114, IY register 115, and SP register 116. .
The sub-registers 124 correspond to the sub-registers 104 shown in FIG. It has D' registers 110', E' registers 111', H' registers 112', L' registers 113', IX' registers 114', and IY' registers 115'.
The main register 123 has a U register 130, which will be explained later.

The IFF register 125 is a register for storing an interrupt control flag IFF. The interrupt control flag IFF is a flag for managing the enable/disable state of interrupt processing, that is, the interrupt control state. In this example, two types, "IFF1" and "IFF2", are handled as the interrupt control flag IFF. Correspondingly, the IFF register 125 can individually store the interrupt control flags IFF1 and IFF2.
Of the interrupt control flags IFF1 and IFF2, only the IFF1 side is used as a reference value for the interrupt control state, and the IFF2 is used auxiliary to manage the value of IFF1.

In this embodiment, as shown in FIG. 26, a first register bank 121 and a second register bank 122 are provided. used by the program. That is, the register bank to be used is switched from the first register bank 121 to the second register bank 122 when shifting from the processing of the program within the region to the processing of the program outside the region. Conversely, when the process of the program outside the area is shifted to the process of the program inside the area, the register bank to be used is switched from the second register bank 122 to the first register bank 121 .

As described above, the first register bank 121 and the second register bank 122 are provided, and the first register bank 121 is used inside the area and the second register bank 122 is used outside the area. It becomes possible to use the dedicated SP register 116 for each external program, eliminating the need to execute "PUSH AF" or "POP AF". Therefore, it is possible to reduce the program capacity of the intra-area program.

Also, in this embodiment, "CALLEX" and "RETEX" are adopted as instructions that can be substituted for "CALL" and "RET".
"CALLEX" is an instruction to call a program outside the area from a program inside the area. ) instruction and the CALL instruction of the specified outside program are aggregated as a single instruction.
"RETEX" is an instruction for returning from a program outside the area to a program inside the area. The execution instruction for returning the interrupt control state (permitted/prohibited) to the state immediately before the execution of the CALLEX instruction and the RET instruction for returning the processing to the caller are aggregated as a single instruction.

Here, as described above, "CALLEX" disables interrupts, and "RETEX" returns the interrupt control state to the state immediately before the CALLEX instruction was executed. It is defined that the interrupt control flag IFF is updated as follows when executing DI and EI.
FIG. 27 is an explanatory diagram of an update rule for the interrupt control flag IFF.
As shown in the figure, when the "DI" instruction is executed, both the interrupt control flags IFF1 and IFF2 are set to "0" (disabled value) indicating that the interrupt is disabled. On the other hand, when the "EI" instruction is executed, both the interrupt control flags IFF1 and IFF2 are set to "1" (permission value) indicating that the interrupt is permitted.
Also, when the "CALLEX" instruction is executed, the interrupt control flag IFF1 is set to the prohibited value "0", and the value of the interrupt control flag IFF2 is maintained (that is, not changed). Furthermore, when executing the "RETEX" instruction, the value of the interrupt control flag IFF2 is substituted for the interrupt control flag IFF1. At this time, the value of the interrupt control flag IFF2 is maintained.

By updating the interrupt control flag IFF according to the above rules, the execution of the "CALLEX" instruction realizes the interrupt disabled state, and the execution of the "RETEX" instruction changes the interrupt control state to immediately before the execution of the CALLEX instruction. will be returned to the state of

FIG. 28 and FIG. 29 exemplify a program as an embodiment in which "CALLEX" and "RETEX" are applied to the program relating to processing transition between inside and outside the area illustrated in FIGS.
In FIGS. 28 and 29, among the various instructions shown in FIGS. 24 and 25, the instructions omitted by applying the technique of the embodiment are grayed out.

As described above, by providing the first register bank 121 and the second register bank 122, in the program within the area, "PUSH AF" required when calling the program outside the area and return from the program outside the area "POP AF", which was sometimes required, is no longer necessary.
As a result, it is possible to reduce the program capacity of the intra-area program.

Here, since "CALLEX" includes the "DI" instruction, the effect of reducing the "DI" instruction (the effect of reducing the program capacity) may be obtained in some cases. In the example of FIG. 24, since the program configuration is such that the random number update process is performed before calling the program outside the area, the "DI" instruction is executed before the random number update process, and the program outside the area is called while interrupts are disabled. is done. In such a case, since it is not necessary to execute the "DI" instruction to call the program outside the area, the effect of reducing the "DI" instruction by applying "CALLEX" cannot be obtained. However, in the interrupt enabled state, there may be a case where a program configuration is adopted that calls out the program outside the area. In such a case, since the "DI" instruction is executed before calling the program outside the area by "CALL", the application of "CALLEX" can reduce the "DI" instruction, and the program A capacity reduction effect can be obtained.

In the embodiment, the provision of the second register bank 122 for outside the area eliminates the need to save and restore register values when shifting from the inside program to the outside program. Therefore, in the program outside the area (Fig. 29), each instruction "LD (_RBCBUF), BC", "LD (_RDEBUF), DE", "LD (_RHLBUF), HL" for saving the register value, ``LD BC, (_RBCBUF)'', ``LD DE, (_RDEBUF)'', and ``LD HL, (_RHLBUF)'' instructions for restoring the saved values, and for restoring the value of the stack pointer in the area. It is no longer necessary to write the "LD SP,_ISTPNT2" instruction.

Here, as can be understood with reference to the program illustrated in FIG. 28, in the present embodiment, after executing the "DI" instruction and before executing the "EI" instruction in the intra-area program, A "CALLEX" instruction is being executed. If the "EI" instruction is the "first instruction", the "DI" instruction is the "second instruction", and the "CALLEX" instruction is the "third instruction", then the first instruction is executed after the second instruction is executed. In other words, the third instruction is executed before execution.

Interrupts must be disabled when executing an out-of-area program. Based on this premise, if EI (first instruction) is executed before CALLEX (third instruction) is executed, interrupt disabled state and interrupt enabled state will frequently switch.
Specifically, when performing EI before CALLEX, interrupts are disabled at the first DI in the loop processing → random number update processing is executed → interrupts are enabled at EI → interrupts are disabled at CALLEX → interrupts are enabled at RETEX . That is, the number of times of switching within the main loop processing is 3 times. On the other hand, in the case of the embodiment where EI is performed after CALLEX, the interrupt disabled state is maintained continuously from the first DI to the execution of the program outside the area → returning to the program inside the area, and then switched to the interrupt enabled state by EI. . That is, the number of times of switching in the main loop process=1.
Therefore, if EI is performed before CALLEX, the control state will switch frequently and the stability of control will be impaired. It is possible to improve the stability of control.

Further, according to the migration method as the above-described embodiment, PUSH and POP processing are not required, so the processing speed can be improved.

30 and 31 exemplify a program when CALLEX and RETEX are applied to calling the program outside the area in the main control side timer interrupt processing shown in FIG. 18, and FIG. A program (in-area program) is exemplified, and FIG. 31 exemplifies a program (out-of-area program) corresponding to the performance display monitor display process in step S916.
For convenience of illustration, FIG. 30 omits the illustration of the instruction corresponding to the WDT clearing process in step S918. 30 and 31, as well as FIGS. 30 and 31, as well as FIGS. 28 and 29, the instructions omitted by applying CALLEX and RETEX are grayed out. ing.

In FIG. 30, when the CALL instruction is adopted instead of CALLEX for calling the performance display monitor display process, which is a program outside the area (that is, when adopting the register configuration of FIG. 23), the necessary instruction is "PUSH AF" → "DI" → "CALL _SHYMT" → "POP AF" → "EI" → "RETI", but when CALLEX is adopted (when adopting the register configuration shown in Fig. 26), the necessary instruction is "CALLEX _SHYMT ' → 'EI' → 'RETI', and by reducing the number of 'PUSH AF', 'DI' and 'POP AF' instructions, it is possible to reduce the program capacity of the program in the area.

Also, in the performance display monitor display processing program shown in FIG. 31, first, a stack pointer specifying an address outside the use area is set by the instruction "LD SP,_ESTPNT". In the case of the preceding example that adopts CALL or RET, "LD (_RBCBUF), BC", "LD (_RDEBUF), DE", "LD ( _RHLBUF), HL" were required, but these instructions are omitted in this embodiment.
In the drawing, each command from "RWM initial determination" to "initial display timer subtraction process" is a command for realizing the process of displaying the value of the performance information on the setting/performance indicator 97. FIG. After these instructions, in the previous example, "LD BC, (_RBCBUF)", "LD DE, (_RDEBUF)", and "LD HL, (_RHLBUF)" instructions for restoring the saved values to the registers, and Although the instruction "LD SP,_ISTPNT2" for restoring the stack pointer in the area was required, these instructions are also omitted in this embodiment.
By "RETEX" on the last line, the register bank to be used is switched from the second register bank 122 to the first register bank 121, the interrupt control state is restored (in this case, the disabled state is maintained), and the processing to the caller is terminated. A return is made.

Note that the "EI" instruction one line before the last line in FIG. 30 is not essential. If the interrupt control state immediately before execution of the CALLEX instruction in FIG. 30 is the "interrupt enabled state", execution of the RETEX instruction shown in FIG. It is for the sake of becoming.

Here, in FIGS. 29 and 31, in the first line of the outside program, the instruction "LD SP,_ESTPNT" is executed, that is, the SP register 116 in the second register bank 122 is used in the outside program. It is assumed that the process of storing the address value of the stack memory (stored value of "ESTPNT" on the memory) is executed. This can be rephrased as follows. That is, when calling by specifying the first address of the program outside the area by the "CALLEX" instruction in the program inside the area ("CALLEX_SHKSHM" in FIG. 28), and when calling by specifying the second address ("CALLEX _SHYMT"), and the stack memory common to the SP register 116 of the second register bank 122 is stored in the outside program regardless of whether the first address is called or the second address is called. It executes an instruction (fifth instruction) to store address information (stored value of "ESTPNT").

This makes it possible to reset the value of the stack pointer used by the out-of-area program each time the out-of-area program is called.
Therefore, even if the stored value of the second stack pointer changes due to some problem after executing a certain out-of-area program, the correct value of the stack pointer will be set when another out-of-area program is executed. It can be fixed, and the stability of stack handling by out-of-bounds programs can be improved.

Since the value of the stack pointer that should be set at the start of processing of the program outside the area is a fixed value as "ESTPNT", execute "LD SP,_ESTPNT" each time the processing of the program outside the area starts. is not required. Specifically, the instruction "LD SP,_ESTPNT" may be executed only when the out-of-area program is executed at least for the first time every time the gaming machine is activated.
For example, if the program outside the area shown in FIG. 29 is executed before the program outside the area shown in FIG. 31, the instruction "LD SP,_ESTPNT" should be executed only in the program outside the area shown in FIG. Alternatively, conversely, if the program outside the area shown in FIG. 31 is executed before the program outside the area shown in FIG. .
This can be rephrased as follows. That is, when executing the CALLEX instruction to call the program outside the area in the program inside the area, specifying the first address of the program outside the area and calling it (calling either the program outside the area shown in FIG. 29 or 31 case), and at a later timing, there is a case where the second address is specified and called (when the other outside program in FIG. 29 or FIG. 31 is called), and in the outside program, the first address is Only when called, an instruction (sixth instruction) for storing common stack memory address information in the second stack pointer is executed.

As described above, the address information of the stack memory that should be set at the start of processing of the program outside the area is fixed address information, so the program at the second address is executed after the program at the first address as the program outside the area. In that case, it is sufficient to store the address information for the second stack pointer only in the program of the first address that is executed first.
Therefore, by executing the instruction to store the address information of the predetermined stack memory in the second stack pointer only when the first address is called as described above, it is possible to improve the processing efficiency.

[5-4. Another example of the program]

32 and 33 show another example of the program shown in FIGS. 28 and 29 above. Specifically, another example of a program (FIG. 32) corresponding to a portion of calling an out-of-area program in the main loop processing (S120) and another example of an out-of-area program (FIG. 33) called by the processing of FIG. showing.

34 and 35 show another example of the program shown in FIGS. 30 and 31, that is, another example of the main control side timer interrupt processing program (FIG. 34), and an area outside the area called by the timer interrupt processing. FIG. 35 shows another example of the program (FIG. 35).

33 and 35, the addresses on the memory for storing the values to be set in the second stack pointer (SP register 116 in the second register bank 122) are shown in FIGS. It is defined as "@RWM2SP" instead of "ESTPNT" in the case.
As can be seen by referring to the "LD SP, @RWM2SP" instruction in FIGS. 33 and 35, here, a common address as the storage value of "@RWM2SP" is stored in the second stack pointer for each execution of the program outside the area. An example of setting information is given, but in this case also, it is also possible to store the address information for the second stack pointer only in the outside program that is executed first.

FIGS. 36 to 53 show examples of programs in the case of applying the processing transition method as an embodiment to the processing of the main control unit in a reel-type gaming machine (slot machine).
36, 38, 40, 42, 44, 46, 48, 50, and 52 show the processing of the region program executed by the main control unit of the reel-type game machine. It shows an example of a program for various processes including an instruction to call an external program. Specifically, FIG. 36 shows initial setting processing when power is turned on, FIG. 38 shows game execution processing, FIG. 40 shows processing according to insertion of game medals and operation of the start lever, FIG. FIG. 44 shows the role ratio monitor display related information update process, FIG. 46 shows the setting change process, FIG. 48 shows the condition device signal output process, FIG. 50 shows the game medal insertion process, and FIG. ing.
FIGS. 37, 39, 41, 43, 45, 47, 49, 51, and 53 exemplify out-of-area programs called by the CALLEX instruction in the processing of the various in-area programs described above. Specifically, FIG. 37 is outside area work area processing 3, FIG. 39 is replay state identification signal output processing, FIG. 41 is condition device signal output clear processing, FIG. 47 illustrates the program for the outside work area process 1, FIG. 49 shows the condition device signal output monitoring process, FIG. 51 shows the retention check process, and FIG. 53 shows the outside work area process 2. .

In addition, regarding the program in the area exemplified here, for example, "(DI guarantee)" shown in FIGS. This means that it is guaranteed (that is, it is guaranteed that the DI instruction has been executed in any line before this line).

38, 40, and 48 among the programs in the area illustrated here, after executing the "DI" instruction and before executing the "EI" instruction, the "CALLEX" instruction corresponds to the example of executing
As a result, frequent switching of the interrupt control state can be prevented, and control stability can be improved.

In particular, in the program of FIG. 48, two CALLEX instructions are written in succession. " instruction is not executed, and the "EI" instruction is executed before the "CALLEX" instruction is executed, the interrupt control state is switched five times. Specifically, DI → EI → CALLEX (switches to interrupt disabled state) → RETEX (returns to interrupt enabled state) → CALLEX (switches to interrupt disabled state) → RETEX (returns to interrupt enabled state) for a total of 6 times. . On the other hand, when adopting the method of executing the "CALLEX" instruction before executing the "EI" instruction after executing the "DI" instruction as in the embodiment, the number of times the interrupt control state is switched is reduced to one. can be suppressed, and the stability of control can be enhanced.

37, 39, 41, 43, 45, 47, 49, 51, and 53, shown on the first line of each figure, "LD SP, CMN_STACK", this The storage address of the stack pointer for the unused area (the value to be set in the SP register 116 in the second register bank 122) is defined as "CMN_STACK".
As can be understood from the fact that the "LD SP, CMN_STACK" instruction is included in each diagram such as FIG. Here is an example of setting.

In the case of a reel-type game machine, there are three or more types of out-of-area programs called from in-area programs. In this way, when there are three or more types of outside programs to be called, at least regarding the relationship between two of them, only the outside program executed first needs to store the address information for the second stack pointer. It is also possible to make it happen. At this time, in order to improve the efficiency of the processing, it is desirable that the address information storage processing for the second stack pointer is executed only in the first out-of-area program among the three or more types of out-of-area programs. .

[5-5. Variation of program]

Next, modified examples of the program will be described with reference to FIGS. 54 to 63. FIG.
In the explanation so far, an example of including a register bank switching instruction used for CALLEX and RETEX was given, but the register bank switching instruction can also be defined as an independent instruction. Here, an example in which the register bank switching instruction (mnemonic) is defined as "BANKF" is given, but the specific name of the switching instruction is not limited to "BANKF".

When using independent register bank switching instructions as "BANKF", one "CALL" instruction, two "BANKF" instructions, and one "RET" command will be used.
54, 56, 58, and 60 show various program examples that can be considered as application examples of the "BANKF" instruction for the initial setting process at power-on illustrated in FIG. 55, 57, 59, and 61 show examples of the outside program (outside work area process 3) called by the inside program in FIGS. 54, 56, 58, and 60, respectively. .

In the example shown in the pair of FIGS. 54 and 55, a "BANKF" instruction for switching the register bank from the first register bank 121 for inside the area to the second register bank 122 for outside the area is performed on the outside program side. This is an example in which a "BANKF" instruction for switching from the second register bank 122 for external use to the first register bank 121 for internal use is performed on the internal program side.
In the program within the area in this case, as shown in FIG. 54, the register bank is switched from the second register bank 122 to the first register bank 121 following the "CALL" instruction (CALL O_CLRWM3) for calling the target outside program. A "BANKF" instruction is described for Further, in the program outside the area in this case, as shown in FIG. 55, a "BANKF" instruction for switching the register bank from the first register bank 121 to the second register bank 122 is described in the first line, and "RET" instruction is described.

Here, in the program outside the area shown in FIG. When executing the "BANKF" instruction for switching to the second register bank 122, the "BANKF" instruction is executed before executing the "LD SP, CMN_STACK" instruction.

56 and 57 show a "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 and a "BANKF" instruction for switching from the second register bank 122 to the first register bank 121. ” is an example in which both commands are performed on the intra-area program side.
In the internal program in this case, as shown in FIG. 56, a "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 is described in the line immediately preceding the "CALL" instruction. A "BANKF" instruction for switching from the second register bank 122 to the first register bank 121 is described on the line following the instruction.

58 and 59, the "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 is executed on the internal program side, and the second register bank 122 to the first register bank 121 is executed. This is an example in which a "BANKF" instruction for switching to is performed on the outside program side.
As shown in FIG. 58, in the program within the area in this case, the "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 is described in the line immediately before the "CALL" instruction, and the program outside the area is Then, as shown in FIG. 59, the "BANKF" instruction for switching from the second register bank 122 to the first register bank 121 is described in the line immediately before the "RET" instruction.

60 and 61 show a "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 and a "BANKF" instruction for switching from the second register bank 122 to the first register bank 121. ” is an example in which both commands are performed on the outside program side. As shown in FIG. 61, in the outside program in this case, the "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 is described in the first line, and the line immediately before the "RET" instruction is A “BANKF” instruction for switching from the second register bank 122 to the first register bank 121 is described.

By defining the "BANKF" instruction as above, options other than CALLEX and RETEX (CALL and BANKF, or RET and BANKF) are provided as instructions for realizing processing transition between inside and outside the area. This makes it possible to improve the degree of freedom in program creation.

Here, it is not essential to apply CALLEX and RETEX to all processing transitions between inside and outside the region. For example, in a program within a region, depending on the processing contents of the program before and after the call instruction of the program outside the region, CALL and RET may be used as usual instead of CALLEX and RETEX. For example, in a situation where there is processing to be performed in a state in which interrupts are disabled after returning to the area by a return instruction to the program within the area, there is no need to execute EI when returning to the area, so CALL, RETEX, and not CALLEX or RETEX. Even with RET, the appropriate interrupt control state can be achieved.

A set of FIGS. 62 and 63 shows examples of programs inside and outside the region when CALL and RET are used in such situations.
62 and 63 show a program example in which the second register bank 122 for outside the area is not used, but by using "BUNKF" described in FIGS. Instructions for saving and restoring AF ("PUSH AF", "POP AF") in programs are omitted, and instructions for saving and restoring the stack pointer (stack pointer for inside the area) in programs outside the area (" LD (W_STKBAK),SP", "LD SP,(W_STKBAK)") and instructions for saving and restoring all registers ("PUSH ALL", "EX AF, AF'", "EXX", "PUSH GPR", "POP GPR , ``EX AF,AF''', ``EXX'', and ``POP ALL'') can be omitted.

[5-6. Other Modifications]

In the explanation so far, when a program outside the area is called from a program inside the area, after executing DI (second instruction) and before executing EI (first instruction), CALLEX (third instruction ) has been given, but it is also possible to adopt a method of executing CALLEX after executing EI, in other words, executing EI before CALLEX.
By executing EI before executing CALLEX, you can shorten the duration of the interrupt disabled state. That is, it is possible to suppress the processing delay due to the inability to execute interrupt processing.

Here, in the gaming machine 1 of this example, the winning information is updated in the timer interrupt process (see the prize ball management process of S908). Among the various out-of-area programs exemplified, in the performance display monitor tally division process shown in FIG. Therefore, if a method of executing EI before CALLEX is adopted when calling such performance display monitor aggregate division processing, the performance information calculation in the out-of-area program will be updated just before that. It can be performed using winning information, which is preferable.

<6. About Q register and U register>

Next, the Q registers (Q register 105 and Q' register 105') and U register 130 will be described.
First, the memory address space of the CPU 20a in the main control section 20 will be described with reference to the memory map of FIG.
As shown in the figure, a memory address space of 65536 bytes from address 0000h (h means a hexadecimal number) to address FFFFh is prepared as the memory address space of the CPU 20a.
An area of 16384 bytes (16 kbytes) from address 0000h to address 3FFFh is an internal ROM area, and an area of 1024 bytes (1 kbyte) from address F000h to address F3FFh is an internal RAM area.
An area from address 4000h to address EFFFh located between these built-in ROM and built-in RAM areas is an unused area.

An area from address F400h to FDFFh is an unused area, an area from address FE00h to FEFFh is an internal register 1 area, and an area from address FF00h to address FFCFh is an internal register 2 area.

An area from address FFD0f to address FFFFh is used as an XCS decode area.
Here, the CPU 20a of this example employs a memory mapped I/O method as a data input/output management method. As is well known, memory mapped I/O is a method of allocating I/O registers to the same address space as data memory.
In this example, a storage area corresponding to an I/O register is assigned to the XCS decode area. In this sense, the XCS decode area is hereinafter referred to as an "input/output port area (I/O port area)".

As described above with reference to FIG. 21, the memory area accessible by the CPU 20a is divided into the used area as the first memory area and the unused area as the second memory area. In FIG. 64, the area of the internal RAM is divided into the used area and the unused area. A 256-byte area from address F200h to address F2FFh is an unused area.

Based on the above, the Q register and the "LDQ" instruction, which is an instruction related to the Q register, will be described.
The Q register 105 and Q' register 105' are registers that store upper values of some addresses handled by the "LDQ" instruction. In this example, these Q register 105 and Q' register 105' are 8-bit (1 byte) registers.

The "LDQ" instruction is written, for example, as "LDQ R,m" (where R is a value that specifies a register and m is a value that specifies an address in memory) or "LDQ m,R". It functions as a load instruction similar to the "LDQ" instruction, and is basically an instruction that writes the value of the location specified on the right side to the location specified on the left side after the description of "LDQ". The difference from the "LD" instruction is that only the lower value of the address on the memory should be described as the value of "m". That is, the "LDQ" instruction is an instruction that accesses an address whose lower value is the value described as "m" and whose upper value is the value stored in the Q register 105 or Q' register 105'. Specifically, for "LDQ R,m", the value of "m" is the lower value and the value stored in the Q register 105 or Q' register 105' is the upper value for the register designated by "R". This is an instruction to write the value stored in the address on the memory that was written. Also, if it is "LDQ m,R", specify with "R" the address on the memory where the value of "m" is the lower value and the value stored in the Q register 105 or Q' register 105' is the upper value. command to write the value of the registered register.

The Q register is a register provided to implement such an "LDQ" instruction. By providing the Q register, it is no longer necessary to describe the upper value of the address in the program, and the program capacity can be reduced.

Here, in this example, the "LDQ" instruction as described above is applied to access to the used area in the internal RAM area shown in FIG. Therefore, "F0h" and "F1h" are stored in the Q register 105 and the Q' register 105', respectively.
As shown in FIG. 64, the use area in the built-in RAM is set as an area from address F000h to address F1FFh. That is, the used area has a size exceeding 256 bytes that can be covered by the lower 1 byte (8 bits) of the address value. For this reason, if only one Q register is provided, the above "LDQ" instruction can only be applied to areas where the upper address value in the used area is either "F0h" or "F1h". .
In this example, the Q register 105 and the Q' register 105' are provided as Q registers so that the "LDQ" instruction can be applied to any address in the use area of the built-in RAM.

In this example, the storage of "F0h" and "F1h" as described above is not only for the Q registers 105 and Q' registers 105' in the first register bank 121, but also for the Q registers 105 in the second register bank 122. , Q' register 105'. The processing of storing "F0h" and "F1h" in these Q register 105 and Q' register 105' is automatically performed as initial value setting processing for the Q register 105 and Q' register 105' when the CPU 20a is started after being reset. is executed.
Alternatively, the storage processing of "F0h" and "F1h" in these Q register 105 and Q' register 105' can be executed, for example, in "various setting processing at startup" (S206) in "initial setting processing" (S101). can also

As mentioned above, the second register bank 122 is a group of registers used by out-of-bounds programs.
By storing "F0h" and "F1h" respectively in the Q register 105 and Q' register 105' of the second register bank 122 as described above, the out-of-area program stores the used area in the built-in RAM. The "LDQ" instruction can also be used when referring to data. That is, it is possible to reduce the program capacity by using the "LDQ" instruction for the out-of-area program as well.
For confirmation, the program outside the area is not allowed to update the data in the used area, but is allowed to refer to it (see FIG. 22).

Here, please refer to FIGS. 36, 39, 40, 42, 43, 46, 50, etc. for actual usage examples of the "LDQ" instruction. Among them, the "LDQ" instruction shown in FIGS. 39 and 43 corresponds to the instruction to access the address of the used area when executing the program outside the area.

In order to properly access the internal RAM usage area using the "LDQ" instruction, it is necessary to switch the Q register referenced by the "LDQ" instruction according to the address to be accessed in the usage area. . Specifically, it is necessary to appropriately switch which of the Q register 105 and the Q' register 105' is to be referred to.

In this example, such switching of the Q register is implemented by the "EX" instruction. Specifically, it is realized by the command "EX Q, Q'".
In this example, the "EX Q, Q'" instruction is an instruction that toggles the Q register referred to by the "LDQ" instruction between the Q register 105 and the Q' register 105'. That is, in accordance with the instruction "EX Q, Q'" in the state of Q register to be referenced=Q register 105, the Q register to be referenced is switched to Q' register 105'. Also, the Q register to be referenced is switched to the Q register 105 according to the instruction "EX Q, Q'" in the state of the Q register to be referenced=Q' register 105'.

In the above example, the area to which the "LDQ" instruction is applied (that is, the area used in the internal RAM in this example) is 256 x 2 = 512 bytes, and two Q registers are provided accordingly. However, the area to which the "LDQ" instruction applies can be an area with a size larger than 512 bytes. In that case, by setting the number of Q registers to 3 or more, the "LDQ" instruction can be used when accessing any address in the target area.

Next, the U register 130 will be explained.
U register 130 is a register for storing the upper address value of the input/output port area shown in FIG. Specifically, "FFh" is stored in the U register 130 in this example.
By providing this U register 130, when specifying the access destination address of the input/output port area in an input/output instruction (“IN” instruction or “OUT” instruction), it is necessary to describe the upper value of the access destination address in the program. can be eliminated.

In this example, memory-mapped I/O is used, but the same "IN" and "OUT" instructions as in the case of adopting port-mapped I/O are used for data input/output instructions. instructions (see, eg, FIGS. 38, 40, 48, etc.).
Specifically, the "IN" instruction in this case is described as "IN r,m", which lowers the value described as "m" to the register designated by "r". This is an instruction to write a value stored in an address (that is, a virtual input/output register) in the input/output port area with the value stored in the U register 130 as an upper value. The "OUT" instruction is described as "OUT m,r", which is an input/output port whose lower value is the value described as "m" and whose upper value is the value stored in the U register 130. This is an instruction to write the value stored in the register specified by "r" to the address within the area.
As can be understood from the above description of the "IN" and "OUT" instructions, when memory-mapped I/O is employed, the "LD" instruction can also be used as an instruction related to data input/output. .

As shown in FIG. 26, only one U register 130 is provided in each of the first register bank 121 and the second register bank 122 in this example. Specifically, the U register 130 is provided as one of the main registers 123 in each of the first register bank 121 and the second register bank 122 .
By providing the U register 130 for the second register bank 122 as well, access to the input/output port area using the upper address value stored in the U register 130 can be performed even when executing a program outside the area. is allowed. That is, it is possible to eliminate the need to write the upper value of the access destination address in the "IN" instruction and the "OUT" instruction even in the program outside the area.

As described above, the input/output port area is an area from address FFD0h to address FFFFh, and the area size is 48 bytes. In other words, it is the area size that can be covered by the lower value of the address.
Therefore, the number of U registers 130 is singular in each of the first register bank 121 and the second register bank 122 .

Here, as for the Q register, a common value is stored for each of the Q register 105 and the Q' register 105' in each of the first register bank 121 and the second register bank 122 as described above. also store a common value in each of the first register bank 121 and the second register bank 122 . Specifically, in this example, “FFh” is stored in each U register 130 .
Such a process of storing "FFh" in the U register 130 is automatically executed as a process of setting an initial value in the U register 130 when the CPU 20a is activated after being reset.
Alternatively, the process of storing "FFh" in the U register 130 can be executed, for example, in the "various setting processes at startup" (S206) in the "initial setting process" (S101).

In addition, in the explanation of the Q register mentioned above, it was mentioned that the "EX" instruction is used when accessing areas with different upper address values, but it is not essential to use the "EX" instruction, and in some cases Access can also be performed by describing the upper value of the access destination address in the program.
For example, when accessing the address of the upper value "F1h" while the Q register to be used is selected as the Q register 105, instead of switching the Q register to be used to the Q' register 105' with the "EX" instruction , address information including the upper value "F1h" may be described in the program as access destination address information. Alternatively, when accessing the address of the upper value "F0h" while the Q' register 105' is selected as the Q register to be used, instead of switching the Q register to be used to the Q register 105 with the "EX" instruction , address information including the upper value "F0h" may be described in the program as access destination address information.
Here, in the former case, the Q register is used when accessing the address with the higher value "F0h", but is not used when accessing the address with the higher value "F1h". In the latter case, the Q register is used when accessing the address with the higher value "F1h", but is not used when accessing the address with the higher value "F0h". In other words, the Q register in these cases may or may not be used when accessing the used area of memory (that is, the target area of memory).
On the other hand, since the U register 130 treats only the area of the upper address value "FFh" as the target area, it is always used when the target area on the memory is accessed.

<7. Summary of Embodiments>

As described above, the first gaming machine as an embodiment includes a first register group (first register bank 121) each comprising a plurality of general-purpose registers, and a second register group (second register bank 122 ), a first interrupt management register (IFF1 of the IFF register 125), and a second interrupt management register (IFF2 of the IFF register 125).
In addition, the first instruction ("EI" instruction) that writes the permitted value to the first interrupt management register and the second interrupt management register, and the second instruction ("DI" instruction), the third instruction ("CALLEX" instruction) used when calling the program outside the area from the program inside the area ("CALLEX" instruction), and the fourth instruction used when returning from the program outside the area to the program inside the area ( "RETEX" command) and .
Then, the third instruction can execute processing for writing a prohibited value to the first interrupt management register and switching the register group to be used from the first register group to the second register group before calling the program outside the area. , and the fourth instruction overwrites the value of the second interrupt management register to the first interrupt management register before returning to the program in the area, and changes the register group to be used from the second register group to the first register group. It is possible to execute processing for switching to
Furthermore, in the local program, after executing the second instruction, the third instruction is executed before executing the first instruction.

Interrupts must be disabled when executing programs outside the area. Therefore, if the first instruction is executed before the third instruction is executed, the interrupt disabled state and the interrupt enabled state are frequently switched. On the other hand, if the third instruction is executed after the second instruction is executed as described above and before the first instruction is executed, the interrupt disabled state is maintained and the out-of-area program is executed. Since the call is made and the return to the program within the area is performed, the number of times the interrupt control state is switched can be reduced.
Therefore, the number of times the control state is switched can be suppressed, and the stability of control can be improved.

In addition, in the first gaming machine as an embodiment, the first register group has a first stack pointer (SP register 116 of the first register bank 121) that stores a stack pointer, and the second register group has It has a second stack pointer (SP register 116 of second register bank 122) for storing a stack pointer, the first stack pointer stores the address information of the stack memory used by the program in the area, and the second stack pointer , the address information of the stack memory used by the program outside the area is stored, and when the program outside the area is called by executing the third instruction in the program inside the area, the first address of the program outside the area is specified and called. , and may be called by specifying the second address. In the outside program, the common stack for the second stack pointer is used regardless of whether the first address is called or the second address is called. A fifth instruction is executed to store memory address information.

This makes it possible to reset the value of the stack pointer used by the out-of-area program each time the out-of-area program is called.
Therefore, even if the stored value of the second stack pointer changes due to some problem after executing a certain out-of-area program, the correct value of the stack pointer will be set when another out-of-area program is executed. It can be fixed, and the stability of stack handling by out-of-bounds programs can be improved.

Further, in the first gaming machine as an embodiment, the first register group has a first stack pointer that stores a stack pointer, and the second register group has a second stack pointer that stores a stack pointer. and storing the address information of the stack memory used by the program in the area in the first stack pointer, the address information of the stack memory used in the program outside the area in the second stack pointer, and the program in the area. , when executing the third instruction to call the program outside the area, there are cases where the program is called by specifying the first address of the program outside the area, and after that, the program is called by specifying the second address. , in the program outside the area, only when the first address is called, the sixth instruction for storing the predetermined stack memory address information in the second stack pointer is executed.

Since the address information of the stack memory that should be set to the second stack pointer at the start of processing of the program outside the area is fixed address information, as the program outside the area, after the program of the first address is executed, the second address When the programs are executed, it suffices to store the address information for the second stack pointer only in the program at the first address, which is the first program to be executed.
Therefore, by executing the instruction to store the address information of the predetermined stack memory in the second stack pointer only when the first address is called as described above, it is possible to improve the processing efficiency.

A second gaming machine as an embodiment comprises control means for controlling the progress of a game. It has at least one register group (register bank) each including a plurality of high-order value registers which are registers for storing high-order values of addresses of .
In the memory address space, there are a first area ("internal RAM" area) having a predetermined area size and a second area (" The high-value register consists of a first-class high-value register (Q register) associated with the first area and a second-class high-value register (Q register) that stores the high-order value of the address in the second area. There is an upper value register (U register), the number of first type upper value registers is plural and the number of second type upper value registers is singular in the register group, and the register group has plural first type upper value registers includes a first first class upper value register (Q register 105) and a second first class upper value register (Q' register 105').

By providing the upper value register, when accessing a desired address in the first area or the second area, the access using the upper value stored in the upper value register enables the program to access the higher address of the address. It is possible to eliminate the need to describe the value. That is, it is possible to reduce the program capacity. At this time, depending on the number of bytes of the address lower value, the entire area to be accessed may not be covered. For example, assuming that the size of the area that can be covered by the lower address value is 256 bytes (that is, the lower address value = 1 byte), if the size of the first area exceeds 256 bytes, the lower address value The value cannot cover the entire first area. In other words, in this case, it is necessary to use different upper address values for the area within 256 bytes and the area exceeding 256 bytes in the first area. For this reason, as the first type upper value register, a first first type upper value register and a second first type upper value register that stores a value consecutive to the stored value of the first first type upper value register At least a register is provided. As a result, any address in the first area can be accessed using the upper value stored in the upper value register, eliminating the need to describe the upper value of the access destination address in the program. It is possible to eliminate it. Since the second area is smaller than the predetermined size, it is possible to eliminate the need to describe the upper value of the access destination address in the program even if there is only one type 2 upper value register.
Therefore, the program capacity can be reduced by using a plurality of first type upper value registers and a single second type upper value register as described above.

Also, in the second gaming machine as an embodiment, the second area is an area to which the input/output registers of the control means are assigned.

This makes it possible to employ memory mapped I/O.
Since memory-mapped I/O eliminates the need to provide an I/O register as hardware, it is possible to simplify the internal circuitry of the control means, thereby speeding up processing and reducing costs.

Furthermore, in the second gaming machine as an embodiment, the first area includes a use area that is an area made available by the inside-area program and an unusable area that is an area made available by the outside-area program. The used area consists of two areas with consecutive upper address values. A first register group used in a program is provided, and the first first class upper value register and the second first class upper value register are provided in the first register group.

As a result, when accessing any address in the used area, it is possible to perform access using the address upper value stored in the corresponding one of the two first-class upper value registers. That is, it is possible to eliminate the need to describe the upper value of the access destination address in the intra-area program.
Therefore, it is possible to reduce the program capacity in the used area.

Furthermore, in the second gaming machine as an embodiment, the first area includes a use area that is an area made available by the inside-area program and a use area that is an area made available by the outside-area program. An outer area is included, and two register groups, a first register group used by the program inside the area and a second register group used by the program outside the area, are provided. There are a first type upper value register, a second first type upper value register and a second type upper value register, and in each of the first and second register groups, the first first type upper value register and the second A common value is stored in each of the first type upper value register and the second type upper value register.

That is, the same values as those on the first register group side are stored in the two first type upper value registers and the single second type upper value register in the second register group. As a result, when accessing the first area or second area when executing a program outside the area (that is, when using the second register group), the Address high value can be used. In other words, it is possible to eliminate the need to describe the address high-order value in the instruction for accessing the first area and the second area even for the program outside the area.
Therefore, it is possible to prevent the capacity of the out-of-area program from increasing unnecessarily.

1 Pachinko game machine 13 Production button 15a Cross key 15b Decision button 20 Main control board (main control unit)
20a CPU
20b ROM
20c RAM
24 production control board (production control unit)
24a CPU
24b ROM
24c RAM
36M main liquid crystal display device 36S sub liquid crystal display device 38a, 38b special pattern display device 45 decoration lamp 45a light display device 46 speaker 46a sound generator 61 front door opening sensor 83 handle sensor 94 setting key switch 97 setting/performance display device 98 RAM Clear switch 100 PC (program counter) register 105 Q register 105'Q' register 116 SP (stack pointer) register 121 first register bank 122 second register bank 125 IFF (interrupt control flag) register 130 U register

Claims (4)

Equipped with control means for controlling the progress of the game,
The control means is
having an accessible memory address space,
at least one register group including a plurality of general-purpose registers and a plurality of high-order value registers that store high-order values of addresses in the memory address space handled in some instructions;
The memory address space includes a first area having a predetermined area size and a second area different from the first area and having an area size smaller than the predetermined size,
The upper value registers include a first type upper value register associated with the first area and a second type upper value register for storing an upper value of an address in the second area,
In the register group, the number of the first type upper value registers is plural and the number of the second type upper value registers is singular,
The plurality of first-class upper-value registers in the register group include a first first-class upper-value register and a second first-class upper-value register for storing a value that is continuous with the value stored in the first first-class upper-value register. A game machine including a first class upper value register. The gaming machine according to claim 1, wherein the second area is an area to which input/output registers of the control means are allocated. In the first area,
Including a used area that is an area made available by an in-area program and an out-of-use area that is an area made available by an out-of-area program,
The used area is composed of two areas with consecutive upper address values, and the unusable area is an area with a different upper address value from the used area,
At least a first register group used in the program in the area is provided as the register group,
3. The gaming machine according to claim 1, wherein the first register group includes the first first class upper value register and the second first class upper value register. In the first area,
Including a used area that is an area made available by an in-area program and an out-of-use area that is an area made available by an out-of-area program,
As the register group, two of a first register group used in the program inside the area and a second register group used in the program outside the area are provided,
each of said first and second register groups includes said first first class upper value register, said second first class upper value register and said second class upper value register;
In each of the first and second register groups, a common value is stored in each of the first first class upper value register, the second first class upper value register, and the second class upper value register. The game machine according to any one of claims 1 to 3.

Images