JP2021049021A - Game machine - Google Patents

Abstract

To reduce a program capacity.SOLUTION: A game machine according to the present invention comprises control means for executing control relating to game progress, where the control means includes an accessible memory address space, and at least one register group including respectively a plurality of general-purpose registers and high value registers, the registers for storing higher values of addresses of the memory address space handled in some instructions. The memory address space includes a first area whose area size is prescribed size, and a second area which is different from the first area and whose area size is smaller than the prescribed size. The high value register includes a type-1 high value register relating to the first area, and a type-2 high value register for storing higher values of addresses in the second area. It is so defined that the register group includes a plurality of numbers of the type-1 high value registers and a single number of the type-2 high value register, and the plurality of type-1 high value registers in the register group includes a first type-1 high value register, and a second type-1 high value register for storing values continuous to the storage values of the first type-1 high value register.SELECTED DRAWING: Figure 26

Description

The present invention relates to a game machine, and more particularly to a register configuration of control means in the game machine.

For example, in a game machine such as a ball game machine as a pachinko game machine or a rotating body type game machine as a slot machine, an arithmetic processing unit such as a CPU (Central Processing Unit) is provided as a control means for controlling the progress of the game. Then, the arithmetic processing unit performs processing according to the instructions described in the program, so that various operations of the gaming machine are realized.

The following Patent Document 1 can be mentioned as a related prior art.

JP-A-2019-141675

In recent game machines, the capacity of programs is increasing along with the increase in the functions to be realized, which is squeezing the memory.

Therefore, an object of the present invention is to reduce the program capacity.

The gaming machine according to the present invention includes a control means for controlling the progress of the game, and the control means has an accessible memory address space, a general-purpose register, and the memory address space handled by some instructions. It has at least one register group including a plurality of upper value registers, which are registers for storing the upper value of the address, and the memory address space includes a first area having a predetermined area size and the first area. There is a second region which is different from the above region and whose region size is smaller than the predetermined size, and the upper value register includes a first-class upper value register related to the first region and a second region in the second region. There is a type 2 upper value register that stores the upper value of the address, and in the register group, the number of the first type upper value registers is a plurality, the number of the second type upper value registers is a single number, and the register. In the plurality of first-class upper-value registers in the group, a first-first first-class upper-value register and a second first-second value that stores consecutive values in the stored values of the first-class upper-value register It contains a species high-value register.

By providing the upper value register, when accessing the required address in the first area or the second area, the upper value of the address is given to the program by accessing using the upper value stored in the upper value register. It is possible to eliminate the need to describe the value. That is, it is possible to reduce the program capacity. At this time, depending on the number of bytes of the lower address value, the entire area to be accessed may not be covered. For example, assuming that the size of the area that can be covered by the address lower value is 256 bytes (that is, the address lower value = 1 byte), if the size of the first area exceeds 256 bytes, the address lower value is used. The value cannot cover the entire first area. That is, in this case, it is necessary to use different address upper values in the area within 256 bytes and the area exceeding 256 bytes in the first area. Therefore, as the first-class upper-value register, the second-class upper-value register that stores consecutive values in the first-class upper-value register and the first-class upper-value register is stored. At least a register is provided. As a result, when accessing any address in the first area, it is possible to access using the upper value stored in the upper value register, and it is necessary to describe the upper value of the access destination address in the program. It will be possible to eliminate it. Since the second area is smaller than a predetermined size, it is possible to eliminate the need to describe the upper value of the access destination address in the program even if the number of the second type upper value registers is singular.

Further, in the game machine according to the present invention described above, the second area can be configured to be an area to which the input / output registers of the control means are allocated.

This makes it possible to employ Memory Mapped I / O.

Further, in the game machine according to the present invention described above, in the first area, a used area which is an area made available by the in-area program and an unused area which is an area made available by the out-of-area program. The used area includes an area, the used area is composed of two areas in which the upper value of the address is continuous, and the unused area is an area in which the upper value of the address is different from the used area, and is used as the register group. A configuration in which at least a first register group used in the program in the region is provided, and the first register group is provided with the first type first upper value register and the second type first upper value register. It is possible to do.

As a result, when accessing any address in the used area, it is possible to perform access using the address upper value stored in any of the two first-class upper value registers. That is, it is possible to eliminate the need to describe the upper value of the access destination address in the program in the area.

Further, in the game machine according to the present invention described above, the first area includes a used area that is a region that can be used by the in-area program and a non-use area that is a region that can be used by the out-of-area program. A region is included, and the register group includes two groups, a first register group used in the in-region program and a second register group used in the out-of-region program, and each of the first and second register groups There are the first type first upper value register, the second type first upper value register, and the second type upper value register, and in each of the first and second register groups, the first first type. It is possible to have a configuration in which a common value is stored for each of the first-class upper-value register, the second first-class upper-value register, and the second-class upper-value register.

That is, the same values as those on the first register group side are stored in each of the two first-class upper-value registers and the singular second-class upper-value register in the second register group. As a result, when accessing the first area or the second area when the program outside the area is executed (that is, when the second register group is used), it is stored in the first-class upper-value register or the second-class upper-value register. It is possible to use the upper address value. That is, it is possible to eliminate the need to describe the address upper value in the instruction for accessing the first area and the second area even for the program outside the area.

According to the present invention, the program capacity can be reduced.

It is a front side perspective view which shows the appearance of the game machine as the embodiment which concerns on this invention. It is a figure which shows the structure of the game board of the game machine as an embodiment. It is a block diagram which shows the control composition of the game machine as an embodiment. It is explanatory drawing about the example of the look-ahead notice production in an embodiment. It is a flowchart which showed the main process of the main control side of embodiment. It is a flowchart which showed the initial setting process in FIG. It is a flowchart which showed the power supply abnormality check process of embodiment. It is a figure which showed the correspondence relationship between each judgment condition in operation side at the time of transition to a setting change processing, a RAM clear processing, a setting confirmation processing, and a backup restoration processing, and a value of a W register. It is a flowchart which showed the main loop processing in FIG. It is a flowchart which showed the setting change process in FIG. It is a flowchart which showed the output management process in FIG. It is a figure which showed the example of the 7-segment decoding table. It is a figure which illustrated the relationship between the segment composition and the display pattern of a segment in the display of a set value. It is a flowchart which showed the RAM clear process in FIG. It is a flowchart which showed the setting confirmation process in FIG. It is a figure which showed the example of the set value offset conversion table. It is a flowchart which showed the main loop preprocessing in FIG. It is a flowchart which showed the timer interrupt processing of the main control side of embodiment. It is a flowchart which showed the power supply check / backup process in FIG. It is a flowchart which showed the setting abnormality check process in FIG. It is explanatory drawing about the area set in the memory of a main control part. It is explanatory drawing about the regulation defined in each area. It is a figure which showed the register structure in the prior example. It is a figure which illustrated the program of the part mainly corresponding to the main loop processing (FIG. 9) in the main control side main processing (FIG. 5). It is a figure which illustrated the program which concerns on the performance display monitor total division processing (S304). It is a figure which showed the register structure in an embodiment. It is explanatory drawing about the update rule of an interrupt control flag in an embodiment. It is a figure which illustrated the program in an area when the process transition method as an embodiment is applied. It is a figure which illustrated the program outside the area when the process transition method as an embodiment is applied. It is a figure which showed the other example of the program in an area when the process transition method as an embodiment is applied. It is a figure which showed the other example of the out-of-region program when the process transition method as an embodiment is applied. It is a figure which showed another example of the program in an area when the process transition method as an embodiment is applied. It is a figure which showed another example of the out-of-region program when the process transition method as an embodiment is applied. It is a figure which showed another example of the program in an area when the process transition method as an embodiment is applied. It is a figure which showed another example of the out-of-region program when the process transition method as an embodiment is applied. It is a figure which showed another example of the program in an area when the process transition method as an embodiment is applied. It is a figure which showed another example of the out-of-region program when the process transition method as an embodiment is applied. It is a figure which showed another example of the program in an area when the process transition method as an embodiment is applied. It is a figure which showed another example of the out-of-region program when the process transition method as an embodiment is applied. It is a figure which showed another example of the program in an area when the process transition method as an embodiment is applied. It is a figure which showed another example of the out-of-region program when the process transition method as an embodiment is applied. It is a figure which showed another example of the program in an area when the process transition method as an embodiment is applied. It is a figure which showed another example of the out-of-region program when the process transition method as an embodiment is applied. It is a figure which showed another example of the program in an area when the process transition method as an embodiment is applied. It is a figure which showed another example of the out-of-region program when the process transition method as an embodiment is applied. It is a figure which showed another example of the program in an area when the process transition method as an embodiment is applied. It is a figure which showed another example of the out-of-region program when the process transition method as an embodiment is applied. It is a figure which showed another example of the program in an area when the process transition method as an embodiment is applied. It is a figure which showed another example of the out-of-region program when the process transition method as an embodiment is applied. It is a figure which showed another example of the program in an area when the process transition method as an embodiment is applied. It is a figure which showed another example of the out-of-region program when the process transition method as an embodiment is applied. It is a figure which showed another example of the program in an area when the process transition method as an embodiment is applied. It is a figure which showed another example of the out-of-region program when the process transition method as an embodiment is applied. It is a figure which showed the modification of the program in the area which concerns on a register bank switching instruction. It is a figure which showed the modification of the out-of-region program which concerns on the register bank switching instruction. It is a figure which showed the modification of the program in the area which concerns on a register bank switching instruction. It is a figure which showed the modification of the out-of-region program which concerns on the register bank switching instruction. It is a figure which showed the modification of the program in the area which concerns on a register bank switching instruction. It is a figure which showed the modification of the out-of-region program which concerns on the register bank switching instruction. It is a figure which showed the modification of the program in the area which concerns on a register bank switching instruction. Is. It is a figure which showed the modification of the out-of-region program which concerns on the register bank switching instruction. It is a figure which showed the example of the program in an area when the "CALL" and "RET" instructions are used. It is a figure which showed the example of the out-of-region program when the "CALL" and "RET" instructions are used. It is a figure which showed the memory map of the main control part in embodiment.

Hereinafter, embodiments according to the present invention will be described in the following order with reference to the accompanying drawings.

<1. Game machine structure>
<2. Game machine control configuration>
[2-1. Main control unit]
(About the operation to change the set value)
(About performance display)
(Direction control command)
[2-2. Production control unit]
<3. Outline explanation of operation ＞
[3-1. Design fluctuation display game]
(Special symbol variation display game)
(Decorative pattern variation display game)
(Normal symbol fluctuation display game)
(About hold)
[3-2. Game state]
[3-3. About hit]
[3-4. About the production]
(Direction mode)
(Notice production)
(Direction means)
<4. Main control processing>
[4-1. Main control side main processing]
(Initial setting process)
(Processing after initial setting)
(Main loop processing)
(Setting change processing)
(RAM clear processing)
(Setting confirmation process)
(Main loop pre-processing)
(Advantages of data table for setting value display and setting value conversion table)
[4-2. Main control side timer interrupt processing]
(Power check / backup process)
(Error management and processing for game progress, etc.)
<5. About processing transition between intra-area processing and out-of-area processing>
[5-1. About used area and non-used area]
[5-2. Processing migration method in the preceding example]
[5-3. Processing migration method as an embodiment]
[5-4. Another example of the program]
[5-5. Program modification]
[5-6. Other variants]
<6. About Q register and U register>
<7. Summary of embodiments>

<1. Game machine structure>

The structure of the pachinko gaming machine 1 as the embodiment according to the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a perspective view of the front side showing the appearance of the pachinko gaming machine 1, and FIG. 2 is a view showing the front side of the gaming board 3 of the pachinko gaming machine 1.

The pachinko gaming machine 1 shown in FIG. 1 (hereinafter, may be abbreviated as “game machine 1”) has a frame-shaped front frame 2 attached to the front surface of a wooden outer frame 4 so as to be openable and closable, and is attached to the back surface of the front frame 2. A game board 3 (see FIG. 2) is mounted in the mounted game board storage frame (not shown), and the game area 3a formed on the surface of the game board 3 faces the opening of the front frame 2. Have. A glass door 6 supporting transparent glass is provided on the front side of the game area 3a. Further, on the back side of the game board 3, various control boards (see FIG. 3) for controlling the game operation are arranged.

A key cylinder (not shown) for unlocking the door is provided on the front side of the glass door 6, and if a key is inserted into this key cylinder and operated on one side, the locked state of the glass door 6 with respect to the front frame 2 can be obtained. By operating the other side, the locked state of the front frame 2 with respect to the outer frame 4 can be released and the front frame 2 can be opened to the front side.

Below the glass door 6, a front operation panel 7 that is pivotally supported by a hinge (not shown) on the front frame 2 is arranged. The front operation panel 7 is provided with an upper tray unit 8, and the upper tray unit 8 is formed with an upper tray 9 for storing the discharged game balls.

Further, the upper saucer unit 8 has a ball removal button 14 for pulling out the game balls stored in the upper saucer 9 below the game machine 1, and payout of the game balls to the game ball lending device (not shown). A ball lending button 11 for requesting and a card returning button 12 for requesting the return of the valuable medium inserted in the game ball lending device are provided. Further, the upper saucer unit 8 is provided with an effect button 13 (operating means) configured to be operable by the player. The built-in lamp (button LED75) of the effect button 13 is lit during a predetermined input reception period to enable operation (input reception is possible), and a predetermined operation (press, repeated hit, long press, etc.) is performed while the built-in lamp is lit. It is possible to bring about a change in the production by doing.
Further, although not shown in FIG. 1, the front operation panel 7 includes a cross key 15a for a user such as a player or a hall staff to select various items and give direction instructions, and a selection item. An operator such as a decision button 15b for instructing the decision is provided.

Further, a launch operation handle 15 for operating the launch device 32 (see FIG. 3) is provided on the right end side of the front operation panel 7.

Further, speakers 46 that exert a sound effect (sound effect) by sound are provided on both sides of the upper part of the front frame 2 and on the upper side of the firing operation handle 15. Further, a plurality of decorative lamps 45 (for example, LEDs for light effect by full-color LED) are provided at appropriate positions of the glass door 6 to exert a light effect by decorating light. A plurality of full-color LEDs (LEDs for light production) as the decorative lamp 45 are provided around the pachinko gaming machine, that is, around the periphery of the front frame of the glass door 6 in the circumferential direction.

The configuration of the game board 3 will be described with reference to FIG. On the illustrated game board 3, a ball guide rail 5 for guiding the launched game ball is annularly mounted as a board surface partition member, and a substantially circular region surrounded by the ball guide rail 5 is a game area 3a. The four corners are non-gaming areas.

In the substantially central portion of the game area 3a, for example, in three (left, middle, right) display areas (design variation display areas), a plurality of types of decorative symbols (for example, symbols, characters, symbols, etc.) are independently used. A liquid crystal display (LCD) 36 capable of variable display operation (variable display and stop display) of the left symbol (corresponding to the left display area), the middle symbol (corresponding to the middle display area), and the right symbol (corresponding to the right display area). It is provided. In the following description, a plurality of types of decorative symbols that are variablely displayed on the left symbol, the middle symbol, and the right symbol may be described as "design groups". That is, for example, the symbol stopped and displayed in the left display area is regarded as one of the symbol groups constituting the left symbol.
Under the control of the effect control unit 24, which will be described later, the liquid crystal display device 36 displays various effects as images in addition to the variable display operation of the decorative symbol.

Further, in the game area 3a, a center decoration 48 is provided so as to surround the display surface of the liquid crystal display device 36 in a long-winded manner. The center decoration 48 is provided along the front side of the game board 3 to protect the display surface of the liquid crystal display device 36 from the surrounding game balls, and the flow of the game balls depends on the launch strength or stroke length of the game balls. It works as a flow path distribution means that enables the road to be distributed to the left and right. In the present embodiment, the center decoration 48 is arranged substantially in the center of the game area 3a so that the flow paths of the game balls are formed on both upper sides (left side and right side) in the game area 3a due to the presence of the center decoration 48. ing. The game ball driven into the upper side of the game area 3a by the launching device 32 is distributed to the left and right on the upper side of the armor frame portion 48b, and has a left flow path 3b on the left side of the center decoration 48 and a right flow path 3c on the right side. Flow down either.

In addition, the non-game area near the upper right edge (upper right corner) of the game board 3 is a various function display unit, and the 7-segment display (with dots) is started at the upper start port 34 (for the first special symbol) and the lower start. A special symbol display device 38a (first special symbol display means) and a special symbol display device 38b (second special symbol display means) configured side by side corresponding to the mouth 35 (for the second special symbol). Is provided. In the special symbol display devices 38a and 38b, a special symbol variation display game is executed by the variation display operation of the "special symbol" represented by the 7-segment display. Then, in the liquid crystal display device 36 described above, the decorative symbol by the image is variablely displayed in synchronization with the variable display of the special symbol by the special symbol display devices 38a and 38b, and is decorated with various notice effects (effect images). The symbol variation display games are being executed (details of these symbol variation display games will be described later).

Further, in the various function display units, a composite display device (LED display for holding composite display) 38c composed of a 7-segment display (with dots) is arranged next to the special symbol display devices 38a and 38b. There are five types of compound called compound: special symbols 1 and 2, display of the number of balls on hold for normal symbols, status notification during the fluctuation time shortening function operation (during time reduction) and during high probability state (during high probability). This is because it is a hold / time saving / high-accuracy composite display device (hereinafter, simply referred to as “composite display device”) having a display function.

Further, the various function display units are provided with a normal symbol display device 39a (normal symbol display means) in which a plurality of (two in this embodiment) LEDs are arranged next to the composite display device 38c. In this ordinary symbol display device 39a, the ordinary symbol variation display game is executed by the variation display operation of the ordinary symbol represented by the two LEDs. For example, as a variable display operation, the normal symbol on the LED repeatedly turns on and off in a seesaw manner, and stops with either side lit, so that the success or failure of the normal symbol fluctuation display game can be determined. There is. Further, a round number display device 39b is provided in which three LEDs (first to third round display LEDs) are arranged adjacent to the normal symbol display device 39a. The round number display device 39b notifies the specified number of rounds (maximum number of rounds) related to the jackpot by combining the lighting and extinguishing states of the three LEDs.

Below the center decoration 48, an upper starting port 34 (first special symbol starting port: first starting means) and a lower starting port 35 (second special symbol starting port: second starting means) are provided. Ordinary variable winning devices 41 are provided above and below, and detection sensors 34a and 35a (upper start port sensor 34a, lower start port sensor 35a: see FIG. 3) are formed inside each of them to detect the passage of a game ball. ing.

The upper starting port 34, which is the first special symbol starting port, is the first special symbol in the special symbol display device 38a (hereinafter, the first special symbol is referred to as "special symbol 1", and in some cases, "special symbol 1". It is a winning opening related to the starting condition of the variable display operation (abbreviated as), and is configured as a winning rate fixed winning device having no starting opening opening / closing means (means for opening or expanding the starting opening). In the present embodiment, due to the action of the game ball falling direction changing member (for example, a game nail (not shown), a windmill 44, a center decoration 48, etc.) in the game area 3a, the left flow path 3b to the upper start port 34 The game ball that has flowed down the ball has a structure that makes it easy to enter (win), while the game ball that has flowed down the right flow path 3c has a structure that makes it difficult or impossible to enter.

The ordinary variable winning device 41 is configured as a winning rate variable winning device in which the winning rate of the game ball at the starting port can be changed by the starting port opening / closing means. In the present embodiment, the so-called "electric tulip" is provided with a pair of left and right movable wing pieces (movable members) 47 that allow the lower starting port 35, which is the second special symbol starting port, to be opened or expanded as the starting port opening / closing means. It is configured as a "type" winning device.

The lower start port 35 of the ordinary variable winning device 41 is referred to as a second special symbol in the special symbol display device 38b (hereinafter, the second special symbol is referred to as "special symbol 2", and in some cases, abbreviated as "special symbol 2". ) Is a winning opening related to the starting condition of the variable display operation, and the winning area of the lower starting opening 35 is an open state (operated or not activated) that facilitates winning according to the operating state (operated or non-operating) of the movable wing piece 47. It is converted into a closed state (difficult to win), which makes it more difficult to win or makes it impossible to win than the open state. In the present embodiment, when the movable wing piece 47 is inactive, it holds a closed state (a winning impossible state) that makes it impossible to win a prize in the lower starting port 35.

Further, on both sides of the normal variable winning device 41, three general winning openings 43 are arranged on the left side and one on the right side, for a total of four, and inside each of them, a general winning hole for detecting the passage of a game ball is provided. A mouth sensor 43a (see FIG. 3) is formed. Further, in the area of the game board, a movable body accessory (not shown) that exerts a visual effect is arranged at a position that does not interfere with the flow of the game ball.

Further, diagonally upward to the right of the normal variable winning device 41, that is, above the middle portion of the right flow path 3c, a normal symbol start port 37 (third start) composed of a passage gate (specific passage area) through which the game ball can pass. Means) are provided. The normal symbol start port 37 is a winning opening related to the fluctuation display operation of the normal symbol in the normal symbol display device 39a, and inside the normal symbol start port sensor 37a (see FIG. 3), which detects a passing game ball. Is formed. In the present embodiment, the normal symbol start port 37 is formed only on the right flow path 3c side, and is not formed on the left flow path 3b side. However, the present invention is not limited to this, and may be formed only in the left flow path 3b, or may be formed in both flow paths, respectively.

In the middle of the route from the normal symbol start port 37 in the right flow path 3c to the normal variable winning device 41, the large winning opening 50 can be opened or expanded by the retractable open door 52b. A device 52 (special electric accessory) is provided, and a large winning opening sensor 52a (see FIG. 3) for detecting a game ball that has entered the large winning opening 50 is formed inside the device 52 (special electric accessory).

The circumference of the large winning opening 50 is a bulging portion (decorative member) 55 bulging from the surface of the game board 3, and the upper side 55a of the bulging portion 55 forms a downstream guide portion of the right flow path 3c. There is. If the large winning opening 50 is closed by the open door 52b (the large winning opening is closed), the downstream guide portion of the right flow path 3c (by forming a surface continuous with the upper side 55a of the bulging portion 55). It is designed to form a part of the upper side 55a). Further, in the downstream region of the right flow path 3c, in the region above the upper side 55a of the bulge portion 55, to be exact, in the game region above the grand prize opening 50, the flow path correction plate is substantially parallel to the flow direction of the game ball. The 51d is projected so as to move the flowing game ball toward the large winning opening 50.

The process of entering the game ball into the grand prize opening 50 is as follows.
The game ball that has passed through the floating area between the upper surface of the center decoration 48 and the ball guide rail 5 is placed on the top surface (upper side) 55a of the bulging portion 55 that protrudes from the game board 3 and functions as a guide for the game ball. It flows down along. Then, the game ball comes into contact with the right end of the flow path correction plate 51d protruding from the three surfaces of the game board, whereby the flow direction of the game ball is corrected to the direction (downward direction) of the large winning opening 50. At this time, if the large winning opening 50 is covered by the retractable open door 52b (the large winning opening is closed), the game balls roll on the large winning opening 50, and the game balls are further arranged in a predetermined arrangement (not shown). The game nail guides the player in the direction of the tulip-type normal variable winning device 41 (lower starting port 35). At this time, if the lower start opening 35 is in a winning state (starting opening open state), the game ball can win in the lower starting opening 35. On the other hand, if the open door 52b is retracted into the game board surface and the large winning opening 50 is open (the large winning opening 50 is open), the game ball is guided into the large winning opening 50.

In the game machine 1 of the present embodiment, when the player aims at the launch position on the special variable winning device 52 side (when the game ball is aimed so as to pass through the right flow path 3c), the upper start port The game ball is difficult to be guided or is not guided to the 34 side. Therefore, in the "large winning opening closed state", it is difficult or impossible to win a prize in each of the starting ports 34 and 35 unless the movable wing piece 47 of the normal variable winning device 41 operates. The movable wing piece 47 operates in an opening / closing pattern that is more advantageous than the normal state when it is in a gaming state accompanied by a state with electric support, which will be described later.

In the case of the present embodiment, what kind of striking method the player should take to obtain an advantageous situation changes depending on the gaming state. Specifically, in the game state accompanied by the "state without electric support" described later, the "left-handed" aiming at the game ball to pass the left flow path 3b is considered to be advantageous, and the "electric support" described later is considered to be advantageous. In the game state accompanied by the "presence state", the "right-handed" aiming at the game ball so as to pass through the right flow path 3c is considered to be advantageous.

In the game machine 1 of the present embodiment, if there is a prize in a prize opening other than the normal symbol start opening 37 among various winning openings provided in the game area 3a, each winning opening is promised. The number of prize balls per winning ball (for example, 3 for the upper starting opening 34 or the lower starting opening 35, 13 for the large winning opening 50, and 10 for the general winning opening 43) is the game ball payout device 19 (FIG. 3). It is supposed to be paid out from (see). The game balls that do not win in each of the above winning openings are discharged from the gaming area 3a through the out opening 49.
Here, "winning" means a winning opening that does not have a structure in which the winning opening takes in the game ball inside, or the winning opening takes in the game ball inside, but a winning opening consisting of a passing gate (for example, a normal symbol starting port 37). If is, it means that the game ball passes through the gate, and when the game ball is actually detected by each winning detection switch formed for each winning opening, "winning" occurs in the winning opening. It is treated as if it had been done. The game ball related to this winning is also referred to as a "winning ball". If a game ball enters the winning opening, the game ball will be detected by the winning detection switch. Therefore, unless otherwise specified in the present specification, whether or not the game ball is detected by the winning detection switch. Regardless of this, it may be referred to as "winning" including the case where the game ball enters the winning opening.

<2. Game machine control configuration>

A configuration (control configuration) for realizing game motion control of the game machine 1 will be described with reference to the block diagram of FIG.
The game machine 1 of the present embodiment includes a main control board (main control means) 20 (hereinafter referred to as "main control unit 20") and a main control unit that collectively control control (game operation control) related to the overall game operation. An effect control board (effect control means) 24 (hereinafter referred to as "effect control unit 24") that receives an effect control command from 20 and controls the execution control (appearance control) of the effect by the effect means, and a prize ball. A payout control board (payout control means) 29 that controls payouts, and a power supply board (power supply control means (not shown)) that generates and supplies the power supply required for the game machine 1 from an external power source (not shown). Is configured to have.
In FIG. 3, the power supply route to each part is omitted.

[2-1. Main control unit]

The main control unit 20 is equipped with a microcomputer having a built-in CPU (Central Processing Unit) 20a (main control CPU), and in addition to a control program that describes a game operation control procedure, various data necessary for game operation control are stored. It is equipped with a ROM (Read Only Memory) 20b (main control ROM) for storing and a RAM (Random Access Memory) 20c (main control RAM) that functions as a work area or buffer memory, and constitutes a microcomputer as a whole. ..

Although not shown, the main control unit 20 is used for a CTC (Counter Timer Circuit) for realizing a periodic interrupt, a pulse output creation function (bit rate generator) for a fixed period, and a time measurement function, and a CPU 20a. An interrupt controller circuit that exerts an interrupt enable / interrupt prohibit function such as a timer interrupt that gives an interrupt signal, and can output a system reset signal to reset the CPU 20a by detecting power on / off or power failure. Reset circuit, watchdog timer (WDT) circuit that monitors the operation abnormality of the control program, and out-of-area travel prohibition (IAT) circuit that monitors whether the program is correctly executed within the preset address range. , And a counter circuit for generating a certain range of random numbers in terms of hardware.

The counter circuit includes a random number generation circuit that generates a random number and a sampling circuit that samples a random number value at a predetermined timing from the random number generation circuit, and acts as a 16-bit counter as a whole. By sending an instruction to the sampling circuit according to the processing state, the CPU 20a acquires the numerical value indicated by the random number generation circuit as an internal lottery random number value (big hit determination random number (random number size: 65536)). , The random number value is used for the big hit lottery. It should be noted that the random number for the internal lottery is obtained by adding the soft random number value generated by appropriate software processing and the hard random number value in order to prevent the hitting and the like.

Further, the CPU 20a includes a plurality of registers for storing various values. The details of the registers included in the CPU 20a in the embodiment will be described later.

The main control unit 20 includes an upper start port sensor 34a for detecting a winning (ball winning) in the upper starting port 34, a lower starting port sensor 35a for detecting a winning in the lower starting port 35, and a normal symbol starting port 37. The normal symbol start port sensor 37a for detecting the passage of the above, the large winning opening sensor 52a for detecting the winning of the large winning opening 50, the general winning opening sensor 43a for detecting the winning of the general winning opening 43, and the out opening 49. An OUT monitoring switch 49a for detecting a game ball (out ball) discharged from the player is connected, and the main control unit 20 is capable of receiving detection signals output from these. Based on the detection signals from each sensor, the main control unit 20 can grasp which winning opening the game ball has entered.

Further, the main control unit 20 includes a normal electric accessory solenoid 41c for controlling the opening and closing of the movable wing piece 47 of the lower starting port 35, and a large winning opening solenoid 52c for controlling the opening and closing of the opening door 52b of the large winning opening 50. Is connected, and the main control unit 20 can transmit control signals for controlling them.

Further, the special symbol display device 38a and the special symbol display device 38b are connected to the main control unit 20, and the main control unit 20 can transmit a control signal for displaying and controlling the special symbols 1 and 2. .. Furthermore, a normal symbol display device 39a is connected to the main control unit 20, and it is possible to transmit a control signal for displaying and controlling the normal symbol.

Further, a composite display device 38c and a round number display device 39b are connected to the main control unit 20, and the main control unit 20 displays and controls various information displayed on the composite display device 38c, such as control signals and rounds. It is possible to transmit a control signal for displaying and controlling a specified number of rounds by a big hit displayed on the number display device 39b.

Further, the frame external centralized terminal board 21 is connected to the main control unit 20, and the main control unit 20 is predetermined to the hall computer HC provided outside the game machine via the frame external centralized terminal board 21. It is possible to transmit game information (for example, jackpot information, prize ball number information, symbol change execution information, etc.).
The hall computer HC is an information processing device (computer device) for monitoring game information from the main control unit 20 and comprehensively managing the operating status of the pachinko hall game machine.

Furthermore, a payout control board (payout control unit) 29 is connected to the main control unit 20, and when it is necessary to pay out prize balls, a control command (number of prize balls) related to payout is given to the payout control board 29. It is possible to send a payout control command) that specifies.

The payout control board 29 is connected to a launch control board (launch control unit) 28 that controls the launch device 32 and a game ball payout device (game ball payout means) 19 that pays out game balls. The main roles of the payout control board 29 are receiving a payout control command from the main control unit 20, controlling the prize ball payout of the game ball payout device 19 based on the payout control command, transmitting a status signal to the main control unit 20, and the like. Is.

The game ball payout device 19 is provided with a supply shortage detection sensor 19a for detecting a supply shortage of game balls and a ball counting sensor 19b for detecting a game ball (prize ball) to be paid out. It is possible to receive each detection signal of. Further, the game ball payout device 19 is provided with a payout motor 19c for driving a ball payout mechanism unit (not shown) for paying out the game ball, and the payout control board 29 controls the payout motor 19c. It is possible to transmit the control signal of.

Further, the payout control board 29 has a full detection sensor 60 (in the present embodiment, a detection sensor that detects the storage state of the game balls stored in the upper tray 9) and a full detection sensor 60 that detects the full state of the upper tray 9 with the game balls. , The front door open sensor 61 (in this embodiment, a detection sensor that detects at least the open state of the front frame 2) is connected.

The payout control board 29 can transmit various status signals to the main control unit 20 based on the detection signals from the fullness detection sensor 60, the front door opening sensor 61, the supply shortage detection sensor 19a, and the ball counting sensor 19b. It has become. This status signal includes a ball jam signal indicating a full state, a door opening signal indicating that at least the front frame 2 is open, a supply shortage signal indicating an insufficient supply of game balls from the game ball payout device 19, and a prize ball. A counting error signal indicating that the payout is insufficient or an abnormality has occurred in the ball counting sensor 19b, a payout completion signal indicating that the payout operation has been completed, and the like are included, and various status signals can be transmitted. Based on these status signals, the main control unit 20 determines the open state of the front frame 2 (door opening error), whether the payout operation of the game ball payout device 19 is normal (supply shortage error), and the upper tray 9. Monitor the full state (ball jam error), etc.

Furthermore, the launch control board 28 is connected to the payout control board 29, and it is possible to transmit a permission signal for permitting the launch to the launch control board 28. The launch control board 28 controls energization of the launch solenoid (not shown) provided in the launch device 32 based on the output of the permission signal from the payout control board 29, and operates the launch operation handle 15. Realizes the firing operation of the game ball by. Specifically, the player touches the handle by the fact that the launch permission signal is output from the payout control board 29 (launch permission signal ON state) and the touch sensor (not shown) provided on the launch operation handle 15. The firing operation of the game ball is permitted on condition that the presence is detected and the firing stop switch (not shown) provided on the firing operation handle 15 is not operated. Therefore, when the launch permission signal is not output (launch permission signal OFF state), the launch operation is not executed even if the launch operation handle 15 is operated, and the game ball is not launched. Further, the launch strength of the game ball can be changed according to the operation amount of the launch operation handle 15.
When the payout control board 29 detects the ball clogging error, the ball jamming signal is transmitted to the main control unit 20 and the output of the firing permission signal to the firing control board 28 is stopped (launch permission signal OFF), and the upper tray 9 is used. It is designed to stop the launching operation until the full state of the is cleared.
Further, the payout control board 29 outputs a launch permission signal to the launch control board 28 on condition that the launch permission is instructed by the main control unit 20.

Here, the main control unit 20 is connected to the setting key switch 94 and the RAM clear switch 98, and is capable of receiving detection signals from these switches.

The RAM clear switch 98 is, for example, a push button type switch for instructing and inputting to initialize a predetermined area of the RAM 20c.
The setting key switch 94 is a key switch for switching to the setting change mode (at the time of ON operation) by inserting the setting key possessed by the hall staff at the time of turning on the power and performing the ON / OFF operation.
Here, the setting change mode is a mode in which the setting value Ve can be changed. The set value Ve is a value indicating a stage regarding the winning probability of whether or not the player is allowed to win a favorable gaming state.

The RAM clear switch 98 is turned ON / OFF in response to the operation of the RAM clear button provided so as to be operable in the state where the front frame 2 is open. Further, the setting key switch 98 is provided with a key cylinder in which the above-mentioned setting key can be inserted and removed, and is turned on by rotating the setting key inserted in the key cylinder in the forward direction. It is turned off by being rotated in the opposite direction from the ON state. The key cylinder is provided so that the operation can be performed by inserting the setting key with the front frame 2 open. The key cylinder functions as an operator that can be operated by inserting the setting key.

In this example, the above RAM clear button is also used for the operation of changing the set value Ve. Specifically, the RAM clear button also functions as an operator for sequentially advancing the set value Ve.

The RAM clear switch 98 and the setting key switch 94 are provided at appropriate positions inside the game machine 1. For example, it is arranged on the main control board 20.

A setting / performance indicator 97 is connected to the main control unit 20.
The setting / performance display 97 is configured to include, for example, a 7-segment display, and functions as a display means capable of displaying a set value Ve and performance information (described later). The setting / performance indicator 97 is mounted at a position on the main control unit (main control board) 20 that is easy to see, for example.
The main control unit 20 is capable of transmitting a control signal for displaying the set value Ve and performance information to the setting / performance display 97.

Here, the set value Ve mainly defines the lottery probability (winning probability) of at least a big hit (a hit type in which the condition device described later is activated) for each stage (for example, 6 stages of settings 1 to 6). Therefore, the higher the set value Ve, the higher the winning probability (setting 1 is the lowest winning probability, and thereafter, the winning probability increases in ascending order of the set value), which is advantageous to the player. There is. In other words, the higher the set value Ve, the higher the so-called "machine discount (ball output rate, PAYOUT rate)", which is advantageous for the player.
In this way, the set value Ve is a value that defines the jackpot winning probability, machine discount, etc., and means a value related to the susceptibility to a specific event such as a profit state acting on the player. In the present embodiment, the advantage related to the game is defined according to each set value Ve.

In this example, it is assumed that there are 6 stages (advantage stages) of the set value Ve that can be used according to the rules. Specifically, it is assumed that the range that can be used according to the rules of the set value Ve (hereinafter referred to as "usable range Re") is the range of "1" to "6".
Under this premise, the pachinko gaming machine 1 of this example uses only a part of the set values Ve among the set values Ve that can be used according to the rules. Specifically, the pachinko gaming machine 1 of this example uses only three values of, for example, "1", "2", and "6" among the set values Ve of "1" to "6" in the usable range Re. To do. In other words, the specification is limited to 3 stages instead of 6 stages, which is the maximum stage in the rules, regarding the winning probability.
Hereinafter, the range of the set value Ve actually used in the pachinko gaming machine 1, specifically, the range of the set value Ve actually used among the set value Ve within the usable range Re (“1” in the above example. "The range of" 2 "and" 6 ") is referred to as" the range of use Ru ".

The set value Ve is set exclusively by the hall staff such as the hall clerk based on the sales strategy of the hall (game store). When there are a plurality of types of jackpots, it is possible to appropriately determine which jackpot winning probability is to be changed according to the set value Ve, and the target jackpot type. For example, if there are three types of jackpots 1-3, the higher the set value Ve, the higher the probability of winning all of the jackpots 1-3, or the jackpots 1-3. The total winning probability may be increased. In addition, the probability of winning some big hits may be increased. For example, only the winning probability of the jackpots 1 and 2 may be increased, and the winning probability of the jackpot 3 may be constant with all the set values Ve.

(About the operation to change the set value)

In order to change the set value Ve, in this example, the setting key switch 94 is turned on (operated to the setting change mode side) while the power of the game machine 1 is turned off and the front frame 2 is released. The power to the game machine 1 is turned on while the RAM clear button is pressed (the RAM clear switch 98 is ON). Then, the current set value Ve is displayed on the setting / performance indicator 97, and the mode shifts to the "setting change mode" in which the set value Ve (1, 2, 6 in this example) can be changed.

In this example, the determination as to whether or not to shift to the setting change mode is performed in the main control side main process described later (see step S104 in FIG. 5). When the above-mentioned operating conditions for shifting to the setting change mode are satisfied, the process for changing the setting is executed accordingly.

After the transition to the setting change mode, when the RAM clear button that functions as the setting value Ve change operator is turned on, the current display value of the setting / performance indicator 97 changes to "1 → 2 → 6 → 1 → 1 →". It can be switched to the circulation type within the range of use Ru like "2 → 6 → ...". Then, when the desired set value Ve is reached, when the setting key switch 94 is turned off, the set value Ve is determined, and the information of the determined set value Ve is stored (stored) in a predetermined area of the RAM 20c.
When the setting key switch 94 is turned off, the setting change mode is terminated and the display of the setting / performance indicator 97 is cleared.
When the setting change mode ends, the state shifts to the state where the game progress is allowed.

(About performance display)

The main control unit 20 is capable of transmitting a control signal for displaying predetermined performance information on the setting / performance display 97.
Performance information is information that pachinko halls and related agencies want to confirm, and typical examples are information on the presence or absence of illegal prize balls such as excess prize balls for game machine 1 and information on the original ball ejection performance of game machine 1. Is. Therefore, the performance information itself is information that is not directly related to the progress of the game when the player plays the game, unlike the advance notice effect.

Therefore, the setting / performance display 97 is inside the game machine 1, for example, the main control unit (main control board) 20, the payout control board 29, the launch control board 28, the relay board, and the effect control unit (effect control board (liquid crystal)). It is provided at a position where the display information can be visually recognized when the front frame 2 is opened, such as on the (including the control board) 24) or the board case (protective cover that protects the board).

Here, the following information can be specifically adopted as the performance information.

(1) The total number of payouts paid out by winning in the specific state (total number of prize balls in the specific state: α) is the total number of out balls discharged from the out port 49 in the specific state (out in the specific state). Information (specific ratio information) based on the value (α / β) divided by the number: β) can be adopted as the performance information.
The above "total number of payouts" is the total value of the game balls (prize balls) paid out when winning the winning openings (upper starting opening 34, lower starting opening 35, general winning opening 43, large winning opening 50). Is. In the case of the present embodiment, the upper starting port 34 or the lower starting port 35 is 3, the large winning opening 50 is 13, and the general winning opening 43 is 10.
In addition, which state is to be adopted as the specific state can be appropriately determined depending on what kind of state the performance information is to be grasped. In the case of the present embodiment, any of the normal state, the latent probability state, the time saving state, the probability variation state, and the jackpot game can be adopted. Further, a plurality of types of states may be measured. For example, it is a normal state and a probable change state, all game states except during a hit game, and the type to be measured can be appropriately determined.
Further, as the period in the specific state, a period in which the jackpot lottery probability is either a low probability state or a high probability state may be adopted.
Further, the total number of payouts may be one or a plurality of specific winning openings excluded from the measurement target (total number of payouts excluding specific winning openings). For example, among the winning openings, the one excluding the large winning opening 50 from the measurement target may be used as the total number of payouts.

(2) In addition, only any one of the total number of payouts, the total number of payouts excluding specific winning openings, and the total number of out balls may be measured, and the measurement result may be used as performance information.

In the present embodiment, the total number of payouts in the normal state (number of payouts in the normal state) and the total number of out balls in the normal state (number of outs in the normal state) are measured in real time, and the number of payouts in the normal state is the number of outs in the normal state. The value obtained by multiplying the value divided by is multiplied by 100 (the value calculated by the number of payouts in normal time ÷ the number of outs in normal time × 100) is displayed as performance information (hereinafter referred to as “normal time ratio information”). The displayed value at this time shall be a value rounded off to the first decimal place.
Therefore, each data of the normal payout number, the normal out number, and the normal time ratio information is stored in the corresponding area of the RAM 20c (specific medium total prize ball number storage area, specific medium out number storage area, specific ratio information storage area), respectively. It is designed to be stored (memorized). However, instead of simply measuring permanently and displaying the performance information, when the total number of out balls reaches a predetermined specified number (for example, 60,000), the measurement is temporarily terminated. This specified number is not the total number of out balls in the normal state, but the total number of out balls during the total gaming state (including during the winning game) (hereinafter referred to as "total number of out balls"). The total number of outs is also measured in real time and stored in the corresponding area of the RAM 20c (all state outs storage area). Hereinafter, for convenience of explanation, the specific medium total prize ball number storage area, the specific medium out number storage area, the specific ratio information storage area, and the all state out number storage area are abbreviated as "measurement information storage area".

Then, the normal time ratio information at the end time is stored in a predetermined area (performance display storage area) of the RAM 20c (the current normal time ratio information is stored), and then the measurement information storage area (normal time payout number, normal time out number). And all state out number), and then start the measurement again (normal time payout number, normal time out number, normal time ratio information and all state out ball number measurement are started). Then, the setting / performance display 97 displays the previous normal time ratio information (measurement history information) and the normal time ratio information currently being measured. In addition to the previous information, the history of the previous two times or the previous time (three times before) may be displayed so that the information up to the previous time can be appropriately determined.

Here, in the case of this example, the set value Ve and the performance information are selectively displayed on the setting / performance display 97. Specifically, in this example, setting changes and setting confirmations are performed only at startup when the power is turned on, so settings are made according to the transition to the setting change mode or setting confirmation mode after startup when the power is turned on. The set value Ve is displayed on the performance display 97, and the performance information is displayed after the setting change and the setting confirmation are completed.
The configuration is not limited to displaying the set value Ve and the performance information on a common display, and it is also possible to display the set value Ve and the performance information on separate displays. In that case, the set value Ve and the performance information may be displayed in parallel.

(Direction control command)

The main control unit 20 is capable of transmitting various effect control commands including information on the special symbol variation display game, information on errors, and the like to the effect control unit 24 according to the processing state. However, in order to prevent fraud such as goto acts, the main control unit 20 only transmits a signal to the effect control unit 24, and the signal from the effect control unit 24 cannot be received. It has become.

Here, the effect control command defines a function by a 2-byte configuration consisting of a 1-byte length mode (MODE) and a 1-byte length event (EVENT), and in order to distinguish between MODE and EVENT, the effect control command of MODE Bit7 is ON, and Bit7 of EVENT is OFF. When this information is transmitted as valid, a strobe signal is output corresponding to each of the mode (MODE) and the event (EVENT). That is, when there is a command to be transmitted, the CPU 20a (main control CPU) sets and outputs mode (MODE) information for transmitting the command to the effect control unit 24, and the first time after a predetermined time has elapsed from this setting. The strobe signal is transmitted. Further, the event (EVENT) information is set and output after a lapse of a predetermined time from the transmission of the strobe signal, and the second strobe signal is transmitted after the lapse of a predetermined time from this setting. The strobe signal is controlled to be active by the CPU 20a for a predetermined period during which the CPU 24a (effect control CPU) can reliably receive the command.

[2-2. Production control unit]

The effect control unit 24 is equipped with a microprocessor incorporating a CPU 24a (effect control CPU), a ROM 24b (effect control ROM) that stores the effect data required for the effect control process, and a RAM 24c (effect control ROM) that functions as a work area or a buffer memory. It is mainly composed of a microcomputer equipped with a production control RAM), and is also equipped with an acoustic control unit (sound source IC), RTC (Real Time Clock) function unit, counter circuit, interrupt controller circuit, reset circuit, WDT circuit, etc. And control the overall production operation.

The effect control CPU 24a performs arithmetic processing for various effect operations and controls of each effect means based on the effect control program and the effect control command received from the main control unit 50. In the case of the pachinko gaming machine 1 of the present embodiment, the effect means are a liquid crystal display device 36 (main liquid crystal display device 36M, sub liquid crystal display device 36S), an optical display device 45a, a sound generator 46a, and a movable device (not shown). It becomes a physical accessory.

The effect control ROM 24b stores a control program for the effect operation by the effect control CPU 24a and various data necessary for the effect operation control.
The effect control RAM 24c is used as a work area used by the effect control CPU 24a for various arithmetic processing, a table data area, a buffer area for various input / output data and processing data, and the like.
The arithmetic control unit 24 may be configured to include a one-chip microprocessor and its peripheral circuits, but various configurations of the effect control unit 24 can be considered. For example, in addition to a microcomputer, an interface circuit with each part, a random number generation circuit for generating lottery random numbers for production, a CTC for various time counting, a watchdog timer (WDT) circuit, and an interrupt signal to the production control CPU 24a. In some cases, it is provided with an interrupt controller circuit or the like.

The main roles of the effect control unit 24 are receiving the effect control command from the main control unit 20, determining the selection of the effect based on the effect control command, controlling the display of the liquid crystal display device 36 (display data supply), and the sound generator 46a. Voice output control, light emission control of the light display device 45a (LED), operation control of the movable body accessory (drive control of the movable body accessory motor 80c), and the like.

Since the effect control unit 24 also has a function as a control device for the liquid crystal display device 36, the effect control unit 24 also has functions as a so-called VDP (Video Display Processor), an image ROM, and a VRAM (Video RAM). The effect control CPU 24a is also provided, and also functions as a liquid crystal control unit.
VDP refers to a function that controls overall video output processing such as image development processing and image drawing.
The image ROM refers to a memory in which image data (effect image data) for which VDP performs image development processing is stored.
The VRAM is an image memory area that temporarily stores the image data developed by the VDP.

With these configurations, the effect control unit 24 generates various image data based on the command from the main control unit 20 and outputs the various image data to the main liquid crystal display device 36M and the sub liquid crystal display device 36S. As a result, various effect images are displayed on the main liquid crystal display device 36M and the sub liquid crystal display device 36S.

Further, the effect control unit 24 has an acoustic control unit (sound controller: sound source IC) for the sound generator 46a including the speaker 46, and the acoustic signal output by the acoustic control unit is amplified by the amplifier unit 46d and is amplified by the speaker 46. Is supplied to.
Further, the effect control unit 24 includes a lamp driver unit 45d that functions as an optical display control unit for an optical display device 45a including a decorative lamp 45 and various LEDs, and a movable body accessory motor that operates a movable body (not shown). A motor driver unit 80d (motor drive circuit) that functions as a drive control unit for the 80c is connected. The effect control unit 24 gives instructions to the lamp driver unit 45d and the motor driver unit 80d to control the light display operation by the light display device 45a and the operation of the movable accessory motor 80c.

An origin switch 81 and a position detection sensor 82 for monitoring the operation of the movable body accessory are also connected to the effect control unit 24.
The origin switch 81 is composed of, for example, a photo interrupter or the like, and detects whether or not the movable accessory motor 80c is at the origin position. The origin position is, for example, a position where the movable body does not normally appear on the board surface of FIG. The effect control unit 24 can determine whether or not the movable body accessory motor 80c is at the origin position based on the detection information of the origin switch 81.
Further, the effect control unit 24 controls the operation mode while monitoring the current operation position (for example, the amount of movement from the origin position) of the movable body accessory based on the detection information from the position detection sensor 82. Further, the effect control unit 24 monitors the malfunction of the operation of the movable body accessory based on the detection information from the position detection sensor 82, and if a malfunction occurs, detects it as an error.

Further, the effect button 13, the cross key 15a, and the switch of the decision button 15b shown as the operation unit 17 in the drawing, that is, the operation detection switch of the effect button 13, the cross key 15a, and the decision button 15b are connected to the effect control unit 24. The effect control unit 24 is capable of receiving operation detection signals from the effect button 13, the cross key 15a, and the decision button 15b, respectively.

Further, the effect control unit 24 is provided with a handle sensor 83 (touch sensor) for detecting whether or not the operation handle 15 shown in FIG. 1 is touched by a user such as a player. The effect control unit 24 can determine whether or not the operation handle 15 is touched by the user based on the detection information of the handle sensor 83.

Based on the effect control command sent from the main control unit 20, the effect control unit 24 selects (determines) the effect pattern from a plurality of types of effect patterns prepared in advance by lottery or uniquely, and is required. By controlling various production means at the timing, the desired production is produced. As a result, the display of the effect image by the liquid crystal display device 36 corresponding to the effect pattern, the reproduction of the sound from the speaker 46, the lighting and blinking drive of the decorative lamp 45 and the LED are realized, and various effect patterns (decorative pattern variation display operation and By developing the notice production etc. in chronological order, a "production scenario" in a broad sense is realized.

Here, regarding the effect control command, the effect control unit 24 (CPU 24a) generates an interrupt process based on the input of the above-mentioned strobe signal transmitted by the main control unit 20 (CPU 20a), and receives and analyzes the interrupt process. Specifically, the CPU 24a executes a control program for command reception interrupt processing based on the above-mentioned input of the strobe signal, acquires an effect control command in the interrupt processing realized by the control program, and analyzes the command contents. Do.
At this time, when an interrupt occurs based on the input of the strobe signal, the CPU 24a performs the interrupt processing (timer interrupt processing that is periodically executed) based on another interrupt. The command reception interrupt processing is performed by interrupting to, and even if other interrupts occur at the same time, the command reception interrupt processing is preferentially performed.

<3. Outline explanation of operation ＞
[3-1. Design fluctuation display game]

Next, an outline of the gaming operation of the gaming machine 1 realized by the control configuration (FIG. 3) as described above will be described.
First, a symbol variation display game will be described.

(Special symbol variation display game)

In the game machine 1 of the present embodiment, the main control unit 20 receives a predetermined start condition, specifically, the game ball enters (wins) the upper start port 34 or the lower start port 35. A "big hit lottery" is held by random number lottery. Based on the lottery result, the main control unit 20 variablely displays the special symbol 1 and the special symbol 2 on the special symbol display devices 38a and 38b to start the special symbol variation display game, and after a lapse of a predetermined time, specializes the result. Derived display is performed on the symbol display device, thereby ending the special symbol variation display game.

Here, in the present embodiment, the big hit lottery based on the winning of the upper starting port 34 and the big hit lottery based on the winning of the lower starting port 35 are performed separately and independently. Therefore, the jackpot lottery result for the upper starting port 34 is derived on the special symbol display device 38a side, and the jackpot lottery result for the lower starting port 35 is derived on the special symbol display device 38b side. Specifically, on the special symbol display device 38a side, on the condition that the game ball enters the upper start port 34, the special symbol 1 is variablely displayed and the first special symbol variable display game is started. On the other hand, on the special symbol display device 38b side, the special symbol 2 is variablely displayed and the second special symbol variable display game is started on the condition that the game ball enters the lower starting port 35. ing. Then, when the special symbol variation display game on the special symbol display device 38a or the special symbol display device 38b is started, after a predetermined variation display time elapses, if the jackpot lottery result is a "big hit", a predetermined "big hit" In the mode, in other cases, in a predetermined "missing" mode, the special symbol being displayed in a variable manner is stopped and displayed, whereby the game result (big hit lottery result) is derived.

In the present specification, for convenience of explanation, the first special symbol variation display game on the special symbol display device 38a side is referred to as "special symbol variation display game 1", and the second special symbol on the special symbol display device 38b side is referred to as "special symbol variation display game 1". The variable display game is referred to as a "special symbol variable display game 2". Unless otherwise required, "special symbol 1" and "special symbol 2" are simply referred to as "special symbol" (sometimes abbreviated as "special symbol"), and "special symbol variation display game 1" and "special symbol". The "special symbol variation display game 2" is simply referred to as a "special symbol variation display game".

(Decorative pattern variation display game)

Further, when the above-mentioned special symbol variable display game is started, a decorative symbol (directive game symbol) is variablely displayed on the main liquid crystal display device 36M, and the decorative symbol variable display game is started. Along with this, various productions are developed. When the special symbol variation display game ends, the decorative symbol variation display game also ends, the special symbol display device reflects a predetermined special symbol indicating the jackpot lottery result, and the main liquid crystal display device 36M reflects the jackpot lottery result. The decorative design is derived and displayed. That is, the result of the special symbol variation display game is reflected and displayed by the dramatic decorative symbol variation display game including the variation display operation of the decorative symbol.

Therefore, for example, when the result of the special symbol variation display game is "big hit" (when the jackpot lottery result is "big hit"), the decorative symbol variation display game develops an effect reflecting the result. Then, in the special symbol display device, when the special symbol is stopped and displayed in a display mode indicating a big hit (for example, the 7-segment display state is "7"), the main liquid crystal display device 36M is displayed with "left", "middle", and "middle". In each display area of "right", the decorative symbols reflect "big hit" (for example, in each display area of "left", "middle", and "right", three decorative symbols are "7", "7", and "right". 7 ”is displayed) and the display is stopped.

In the case of this "big hit", specifically, the special symbol variation display game ends, and the decorative symbol variation display game ends accordingly, and as a result, the symbol mode of the "big hit" is derived and displayed. After that, the large winning opening solenoid 52c of the special variable winning device 52 operates to open and close the opening door 52b in a predetermined pattern, whereby the large winning opening 50 is opened and closed, which is more advantageous to the player than in the normal gaming state. A special game state (big hit game) occurs. In this big hit game, the number of game balls won by the opening door 52b until a predetermined time (maximum opening time: for example, 29.8 seconds) elapses or the number of game balls won in the big winning opening (big winning opening). A predetermined number of winning balls to 50) (maximum number of winning balls: maximum number of winning balls allowed for a winning opening whose entrance is opened or expanded by one operation of the accessory: for example, 9) The "round game", in which the winning area is opened or expanded until the number of winnings is reached, and the large winning opening is closed when any of these conditions is met, is defined as a predetermined number of rounds (for example, a maximum of 16). Round) Repeated.

When the jackpot game starts, an opening effect for notifying that the jackpot has started is performed first, and after the opening effect is completed, the round game is performed a plurality of times up to a predetermined number of predetermined rounds. Then, after the end of the specified number of rounds, an ending effect is performed to notify that the big hit is finished, so that the big hit game is finished.

Regarding the information necessary for executing the above-mentioned decorative symbol variation display game, first, the main control unit 20 first enters (wins) a game ball into the upper start port 34 or the lower start port 35, and specifically. , On the condition that the game ball is detected by the upper start opening sensor 34a or the lower start opening sensor 35a and the starting condition (starting condition related to the special symbol) is satisfied, a lottery is made as to whether it is a "big hit" or a "missing". "Winning lottery (winning type lottery)" and if it is a "big hit", the big hit type is drawn, and if it is "missing", the losing type is drawn. )'And a big hit lottery (if there is only one type of loss, the lottery may be omitted because it is not necessary to perform a type lottery for the loss), and based on the lottery result information, the variation pattern of the special symbol In addition, a special symbol (hereinafter referred to as "special stop symbol") to be finally stopped and displayed is determined according to the winning type.
Then, the main control unit 20 issues a "variation pattern designation command" including at least the variation pattern information of the special symbol (for example, information on the jackpot lottery result and the variation time of the special symbol) as the effect control command for specifying the processing state. It is transmitted to the effect control unit 24 side. As a result, the basic information required for the decorative symbol variation display game is sent to the effect control unit 24. In the present embodiment, a "decorative symbol designation command" including information on the special stop symbol (design lottery result information (information on the winning type)) is also transmitted to the effect control unit 24 in order to enrich the variation of the effect. It has become like.

The variation pattern information of the special symbol may include information for designating whether or not a specific advance notice effect (for example, "reach effect" or "pseudo-continuous effect" described later) is generated. In detail, the fluctuation pattern of the special symbol is roughly classified into a "hit fluctuation pattern" in the case of a hit and a "missing fluctuation pattern" in the case of a miss, depending on the result of the big hit lottery. These fluctuation patterns include, for example, a'reach fluctuation pattern'that specifies the occurrence of the reach effect described later, a'normal fluctuation pattern'that does not specify the occurrence of the reach effect, and the occurrence (overlap occurrence) of the pseudo continuous effect and the reach effect. A plurality of types of fluctuation patterns are included, such as a specified'pseudo-ream reach variation pattern', a'pseudo-ream normal variation pattern'that specifies the occurrence of a pseudo-ream effect, and does not specify the occurrence of a reach effect. In addition, in order to secure the production time of the reach effect and the pseudo-continuous effect, the variation pattern that specifies the reach effect and the pseudo-continuous effect is usually set to have a longer variation time than the normal variation pattern.

The effect control unit 24 is time-series during the decorative symbol variation display game based on the information included in the effect control commands (here, the variation pattern designation command and the decorative symbol designation command) sent from the main control unit 20. The content of the production to be developed (the production scenario such as the advance notice production) and the decorative design to be finally stopped and displayed (decorative stop design) are determined, and the decorative design is variablely displayed and decorated according to the time schedule based on the variable pattern of the special design. Run the symbol variation display game. As a result, the decorative symbol by the main liquid crystal display device 36M is variablely displayed in synchronization with the variable display of the special symbol by the special symbol display devices 38a and 38b, and the period of the special symbol variable display game and the decorative symbol variable display game. The period in the middle is substantially the same time width. Further, the effect control unit 24 controls the main liquid crystal display device 36M, the light display device 45a, or the sound generator 46a, respectively, so as to correspond to the effect scenario, and develops various effects in the decorative symbol variation display game. As a result, image reproduction (image effect), sound effect reproduction (sound effect), and lighting / blinking drive (light effect) of the decorative lamp 45, LED, etc. are realized on the main liquid crystal display device 36M.

In this way, the special symbol variation display game and the decorative symbol variation display game have an inseparable relationship, and what reflects the display result of the special symbol variation display game is expressed in the decorative symbol variation display game. , These two symbol variation display games may be regarded as equivalent symbol games. Unless otherwise specified in the present specification, the above two symbol variation display games may be simply referred to as "symbol variation display games".

(Normal symbol fluctuation display game)

Further, in the game machine 1, based on the fact that the game ball has passed (winning) through the normal symbol start port 37, the main control unit 20 performs an "auxiliary hit lottery" by a random number lottery. Based on this lottery result, the normal symbol represented by the LED is variablely displayed on the normal symbol display device 39a to start the normal symbol variable display game, and after a certain period of time, the result is a combination of lighting and non-lighting of the LED. It is designed to stop and display. For example, when the result of the normal symbol variation display game is "auxiliary hit", the display unit of the normal symbol display device 39a is in a specific lighting state (for example, all two LEDs 39 are in a lighting state, or "○" and "○" and ". Of the LEDs expressing "x", the LED on the "○" side is in the lit state) to stop and display.

In the case of this "auxiliary hit", the normal electric accessory solenoid 41c (see FIG. 3) is activated, whereby the movable wing piece 47 opens in an inverted "C" shape and the lower starting port 35 opens. Alternatively, the game ball is expanded to a state in which the game ball easily flows in (starting opening open state), and an auxiliary game state (hereinafter referred to as "solenoid open game") that is more advantageous to the player than the normal game state occurs. In this general electric opening game, a game in which the opening time of the lower starting port 35 elapses for a predetermined time (for example, 0.2 seconds) or the lower starting port 35 is won by the movable wing piece 47 of the normal variable winning device 41. Until the number of balls reaches a predetermined number (for example, 4), the winning area is opened or expanded, and when any of these conditions is satisfied, the lower starting port 35 is closed, and the like is performed a predetermined number of times (for example, maximum). (Twice) It is supposed to be repeated.

(About hold)

Here, in the present embodiment, during the special / decorative symbol variation display game, the normal symbol variation display game, the jackpot game, the normal electric opening game, etc., the upper start port 34, the lower start port 35, or the normal symbol start port 37 When a prize is generated, that is, when a detection signal is input from the upper start port sensor 34a, the lower start port sensor 35a, or the normal symbol start port sensor 37a, and the corresponding start condition (symbol game start condition) is satisfied. This is used as data related to the start right of the variable display game, and is stored up to the maximum number of reserved storages (for example, up to 4), which is a predetermined upper limit value, except for those related to the variable display. The pending data that is not used for this symbol variation display operation, or the game ball related to the reserved data, is also referred to as an "operation pending ball". In order to clarify the number of operation holding balls to the player, a dedicated holding display (not shown) or a liquid crystal display device 36 (main liquid crystal display device 36M or sub liquid crystal display device) provided at an appropriate position in the game machine 1 is provided. The hold display provided as an icon image is lit and displayed on the screen according to 36S).

Further, in the present embodiment, up to four operation holding balls related to the special symbol 1, the special symbol 2, and the normal symbol are reserved and stored in the corresponding storage area of the RAM 20c, and are retained as the number of times the fluctuation of the special symbol or the ordinary symbol is confirmed. The maximum number of stored balls (maximum number of reserved balls) for each of the special symbol 1, the special symbol 2, and the normal symbol is not particularly limited. In addition, all or part of the maximum number of reserved memories of each symbol may be different, and the number can be appropriately determined according to the playability.

[3-2. Game state]

The gaming machine 1 according to the present embodiment is configured to be capable of generating a plurality of types of gaming states in addition to the above-mentioned jackpot which is a special gaming state. In order to facilitate the understanding of this embodiment, first, various gaming states will be described.

The gaming machine 1 of the present embodiment is configured to be able to execute and control at least four types of gaming states: a normal state, a time saving state, a latent probability state, and a probability variation state. These game states are distinguished by the presence or absence of a jackpot lottery probability state (low probability state, high probability state) and an electric chew support state (privilege game) (with electric support, without electric support).

The "electric chew support state" is a normal state in which the opening operation period of the movable wing piece 47 of the normal variable winning device 41 (at least one of the opening time of the movable wing piece 47 and the number of times of opening the movable wing piece 47) in the normal variable opening game is Refers to the "open extension state" that is more extended than. When the open extension state occurs, the open operation period of the movable wing piece 47 is extended from 0.2 seconds in the normal state (under the non-open extension state) to 1.7 seconds, and the number of times of opening and closing thereof is, for example, It is extended from 1 time in normal time to 2 to 3 times.
In the case of the present embodiment, under the electric chew support state, the lottery probability per auxiliary varies from a low probability (for example, 1/256) of a predetermined probability (normal probability) to a high probability (for example, 255/256) (usually). Along with the occurrence of the figure probability fluctuation state, the'normal symbol time reduction state'that shortens the average time required for one normal symbol fluctuation display game (normal symbol fluctuation display operation time) occurs (for example, from 10 seconds). It is shortened to 1 second). Therefore, when the electric chew support state occurs, the normal electric opening game frequently occurs, and the operating rate is improved (high base state) in which the operating rate of the movable wing piece 47 per unit time is improved as compared with the normal state. Hereinafter, the state under the electric chew support state is abbreviated as "with electric support", and the case without it is abbreviated as "without electric support".

In the present embodiment, the "normal state" means that the jackpot lottery probability is a low probability (for example, 1/399) of a predetermined probability (normal probability), and a gaming state without electric support (low probability + no electric support). To tell.

In the "time saving state", the jackpot lottery probability is as low as the normal state, but the average time required for one special symbol variation display game (special symbol variation display operation time) is higher than the normal state. It is a game state in which a'special symbol time reduction state'is generated and the electric chew support state is set. In other words, during the time saving state, it becomes "low probability + with electric support + special symbol time saving state".

The "latent probability state" is a "special symbol probability change state" in which the jackpot lottery probability fluctuates to a high probability (for example, 1 / 39.9) higher than the above low probability, and is a gaming state without electric support (high). Probability + no electric support).

The "probability change state" refers to a game state in which the jackpot lottery probability has the same high probability as the latent probability state, but a special symbol time reduction state and an electric chew support state occur. In other words, during the probability change state, it becomes "high probability + with electric support + special symbol time saving state".

Regarding the game state, paying attention to the jackpot lottery probability, when the game state is "normal state" and "time saving state", at least the jackpot lottery probability becomes "low probability state", and the game state is "latent state" and "probability change". In the case of "state", at least the jackpot lottery probability is "high probability state". During the big hit, a big hit game in which the big winning opening is opened and closed occurs, but the big hit lottery probability and the presence or absence of the electric support are placed under the same low probability / no electric support game state as the above normal state.

[3-3. About hit]

Next, the "hit" in the game machine 1 will be described.
In the game machine 1 of the present embodiment, a big hit lottery (winning lottery) is performed for a plurality of types of hits. In the case of this example, the hit type includes, for example, "normal 4R", "normal 6R", "probability variation 6R", and "probability variation 10R" belonging to the jackpot type.
The notation of "R" means the specified number of rounds (maximum number of rounds).

The jackpot type is a hit that triggers the operation of the condition device. Here, the "condition device" is a device whose operation is a condition necessary for the operation of the accessory continuous operation device for performing a round game, and a combination of specific special symbols is displayed or the game ball is displayed. A game that operates when a specific area in the winning opening is passed.

In the above probability variation state, when the number of executions of the special symbol variation display game ends a predetermined number of times (for example, 70 times: the specified number of STs) without winning the jackpot type, the high probability state is terminated and the probability shifts to a low probability. , So-called "number-cutting probability change machine (ST machine)", and when the specified number of ST times is completed, the game shifts to the normal state from the next game. However, it may be a type of "general probability change machine" that continues until the next big hit is won.
The number of executions of the special symbol variation display game may be the total number of executions of the special symbol variation display game 1 and the special symbol variation display game 2 (total number of fluctuations of the special figure 1 and the special figure 2). It may be the number of executions of either one (for example, the number of executions of the special symbol variation display game 2). Further, the number of times of the time saving state is not limited to 60 times or 100 times, and can be appropriately determined according to the playability. In addition, there is no particular limitation on what kind of hit is provided, and it can be appropriately determined.

Here, in this example, a plurality of types are provided for "missing" as well as the jackpot type. Specifically, there are three types of outliers, "outlier 1", "outlier 2", and "outlier 3".
As described above, when the result of the winning lottery is "missing", the lottery of the losing type is performed in the symbol lottery.

[3-4. About the production]
(Direction mode)

Next, the effect mode (effect state) will be described. The gaming machine 1 of the present embodiment is provided with a plurality of types of effect modes for displaying an effect related to the gaming state, and is configured to be able to go back and forth between the effect modes. Specifically, a normal effect mode, a time-saving effect mode, a latent effect mode, and a probabilistic effect mode are provided corresponding to each of the normal state, the time-saving state, the latent state, and the probabilistic state. In each effect mode, the background display as the background of the variable display screen of the decorative pattern is displayed by different background effects so that the player can grasp what kind of game state he / she is currently staying in. It has become.

The effect control unit 24 (CPU 24a) has a function unit (effect state transition control means) for transition control between a plurality of types of effect modes. The effect control unit 24 (CPU 24a) is a specific effect control command sent from the main control unit 20 (CPU 20a), specifically, an effect control command including game state information managed by the main control unit 20 side. Based on this, the current game state is grasped in a form that is consistent with the game state managed by the main control unit 20 side, and the transition control between a plurality of types of effect modes is possible. Specific effect control commands as described above include, for example, a variation pattern designation command, a decorative symbol designation command, and a game state designation command sent when a change occurs in the game state.

(Notice production)

Next, the advance notice production will be described. The effect control unit 24 is based on the content of the effect control command from the main control unit 20, specifically, at least the variation pattern information included in the variation pattern designation command, and variously related to the current effect mode and the jackpot lottery result. It is configured so that the appearance of the "notice effect" can be controlled. Such a notice effect suggests (notices) the degree of expectation (hereinafter referred to as "winning expectation") of whether or not a player has won the winning type, and serves as a "fanning effect" to fuel the player's sense of expectation of winning. work. Typical notice productions include "reach production", "pseudo-continuous production", and "look-ahead notice production". The effect control unit 24 functions as a notice effect control means capable of executing (appearing) and controlling these effects.

The "reach effect" refers to an effect mode with a reach state (variation display mode with a reach state: reach variation pattern), and specifically, the final game result is derived and displayed via the reach state. A mode of production. Reach effects include multiple types of reach effects associated with winning expectations. For example, there are cases where the expectation of winning is relatively higher than when a normal reach effect appears. Such a reach production is called a "super reach production". Many of these "super reach" have a relatively longer production time (variable time) than the normal reach in order to fuel the expectation of winning. In addition, normal reach and super reach include multiple types of reach effects. In this example, the super reach includes a plurality of types of reach effects of super reach 1, 2, 3, and 4, and the winning expectation of these super reach 1 to 4 is "super reach 1 <super reach 2 <super". It has a relationship of "reach 3 <super reach 4".

The "pseudo-continuous effect" refers to an effect mode accompanied by a pseudo continuous variation display state (pseudo-continuous variation) of the decorative symbol, and the "pseudo-continuous variation" is one of the decorative symbols in the decorative symbol variation display game. It refers to a variable display mode in which a display operation is repeated once or a plurality of times, such as temporarily setting a part or all of them in a temporarily stopped state and executing a re-variable display operation of a decorative symbol from the temporarily stopped state. In this respect, it is different from the "look-ahead notice effect (continuous notice effect)" described later, which is developed over a plurality of symbol variation display games. Basically, the occurrence rate (appearance rate) of such a "pseudo-ream" is determined so that the higher the number of pseudo-variations, the higher the expectation of winning. It is easy to select a production to fuel expectations such as reach.

The "look-ahead notice effect" (hereinafter, may be abbreviated as "look-ahead notice" or "look-ahead effect") is based on the result of the look-ahead judgment and before the variable display of the symbol to be judged is performed. It means an effect of notifying the possibility of being controlled in an advantageous state. The "advantageous state" means an advantageous state for the player.
Specifically, the look-ahead effect of this example is mainly for holding display of operation-holding balls (undigested operation-holding balls) that have not yet been used for execution of the symbol variation display game (variation display operation of special symbols). It is performed in an effect mode that can notify the winning expectation in advance before the operation holding ball is provided to the symbol variation display game by using the mode and the background effect of the symbol variation display game executed earlier. .. In the symbol variation display game, in addition to the above-mentioned "reach effect", various effects such as so-called "SU (step-up) notice effect", "timer notice effect", "revival effect", and "premier notice effect" are performed. It occurs and the game content is getting excited.

Here, with reference to FIG. 4, the "pending change notice effect" as an example of the pre-reading notice effect will be described.
In the case of the game machine 1 of the present embodiment, in the upper display area in the screen of the main liquid crystal display device 36M, a display area for displaying the decorative symbol variation display game (decorative symbol variation display effect and notice effect appear. A display area for displaying) is provided, and a special display area 76 (hold display units a1 to d1) for displaying the number of operation hold balls on the special symbol 1 side is provided in the lower display area in the screen. A hold display area 77 (hold display units a2 to d2) for displaying the number of operation hold balls on the symbol 2 side is provided. Regarding the presence or absence of the operation holding ball, the fact is notified by a predetermined holding display mode. In FIG. 4, the presence or absence of the operation holding ball is currently lit (with the operation holding ball: “○ (white circle)” in the figure) or off (without the operation holding ball: the dashed circle in the figure). An example is shown in which information on the number of balls on hold is notified.

The display regarding the presence / absence of the operation hold ball (hold display) is sequentially displayed in the order of occurrence (winning order), and in each hold display area 76, 77, the leftmost operation hold ball is all the operations in the hold display. It is displayed as the earliest (that is, the oldest) activated holding ball on the time axis among the holding balls. Further, on the left side of the hold display areas 76 and 77, a changing display area 78 for showing the operation hold ball actually used in the special symbol change display game is provided. In the case of the present embodiment, the changing display area 78 is configured so that an image in which the icon of the game execution hold K currently used for the game is placed appears on the icon of the seat J. That is, when the variable display of the special symbol 1 or the special symbol 2 is started, the oldest icon (icon image) of the hold a1 or a2 displayed in the hold display areas 76 and 77 is the hold K during game execution. As an icon, the icon is moved onto the icon of the seat J in the changing display area 78, and the state is maintained for a predetermined display time.

When an operation-holding ball is generated, the main control unit 20 sends the look-ahead determination information related to the jackpot lottery result and the number of operation-holding balls at the time of the look-ahead judgment (the number of existing operation-holding balls including the operation-holding ball generated this time). A "hold addition command" for designating the above is transmitted to the effect control unit 24 (see steps S1309 to S1312 in FIG. 28).
In the case of the present embodiment, the hold addition command is composed of 2 bytes, and the hold addition command makes it possible to specify the data on the upper byte side that can specify the number of operation hold balls at the time of the look-ahead determination and the look-ahead judgment information. It is composed of low-order byte side data.

Here, as understood from the above description, in the present embodiment, a look-ahead about the reserved ball is made based on the fact that a prize is generated in the upper starting port 34 or the lower starting port 35 and a new reserved ball is generated. As a determination, a big hit lottery is performed for the symbol variation display game related to the reserved ball. As will be described later, the main control unit 20 holds and stores information representing the result of the jackpot lottery performed as such a look-ahead determination in the corresponding storage area of the RAM 20c.
The information of the jackpot lottery result obtained at the time of the look-ahead determination is used for selecting (lottery) the symbol variation pattern in the symbol variation display game, and can be paraphrased as "variation pattern selection information". Therefore, it can be said that the main control unit 20 performs the look-ahead determination and holds and stores the "variation pattern selection information" obtained as a result in a predetermined area of the RAM 20c.

When the effect control unit 24 receives the hold addition command transmitted by the main control unit 20, the effect control unit 24 receives the "look-ahead advance notice effect" as a part of the display control process related to the hold display based on the look-ahead determination information included therein. Performs production control processing related to. Specifically, a "look-ahead notice lottery" is performed to draw a lottery as to whether or not the look-ahead notice effect can be executed, and if this is won, the look-ahead notice effect is displayed.

Here, the look-ahead determination information is specifically a jackpot lottery result (big hit lottery result at the start of fluctuation) executed when the operation holding ball is provided to the symbol variation display game in the main control unit 20. This is game information obtained by pre-reading and determining the fluctuation pattern at the start of fluctuation. That is, this information includes at least information that pre-reads the winning lottery result at the start of fluctuation (pre-reading winning information), and other information that pre-reads the symbol lottery result (pre-reading symbol information) and fluctuation at the start of fluctuation. Information for which the pattern is pre-read-determined (pre-reading fluctuation pattern information) can be included. What kind of information is included in the hold addition command to be sent to the effect control unit 24 can be appropriately determined according to the content to be notified by the pre-reading notice.
In this example, it is assumed that the hold addition command includes the look-ahead winning information, the look-ahead symbol information, and the look-ahead fluctuation pattern information.

It should be noted that the "look-ahead fluctuation pattern" obtained by the look-ahead determination when the operation-holding ball occurs must be the "variation pattern at the start of fluctuation" itself obtained when the operation-holding ball is actually subjected to the fluctuation display operation. There is no. For example, if the case where the fluctuation pattern at the start of the fluctuation is a fluctuation pattern that specifies "super reach 1" is typically described, in this case, the content specified by the look-ahead fluctuation pattern is called "super reach 1". It is possible to specify that it is not the type of reach production itself, but the "super reach type" that is the gist of the effect.

In the case of the present embodiment, when the look-ahead notice lottery is won, among the hold icons of the hold display units a1 to d1 and a2 to d2, the hold icon targeted for the look-ahead notice is, for example, a normal hold display. A "hold display change" that can change from white (normal hold display mode) to hold display (special hold display mode) with blue, green, red, and danger patterns (or special colors and patterns such as rainbow colors) of the notice display. A look-ahead notice effect (also called "pending change notice") of "system" is performed.
FIG. 4 shows an example in which the hatched hold display unit b1 has changed to a special hold display. Here, the display of the hold icon in blue, green, red, and the Danger pattern means that the expectation of winning is high in this order, and in particular, the display of the hold icon of the Danger pattern has an extremely high expectation of winning a big hit. It is a premium hold icon to be displayed.

(Direction means)

Various effects in the game machine 1 are expressed by the effect means provided in the game machine 1. The directing means may be any stimulus transmitting means capable of exerting a directing effect by appealing to human perception such as sight, hearing, and touch, and is a light generating means such as a decorative lamp 45 or an LED device (light display device 45a: Light effect means), sound generator such as speaker 46 (sound generator 46a: sound effect means), effect display device (display means) such as main liquid crystal display device 36M and sub liquid crystal display device 36S, contact with operator's body Typical examples are a pressurizing device that transmits pressure, a wind pressure device that applies wind pressure to a player's body, and a movable body accessory that exerts a visual effect by its operation. Here, the effect display device is a display device that appeals to the eyes like the image display device, but differs from the image display device in that it includes a display device that does not depend on an image (for example, a 7-segment display). The term "image display device" mainly refers to a type in which an effect is displayed by displaying an image, and a device that displays an effect by means other than an image, such as a 7-segment display, is included in the concept of the effect display device.

<4. Main control processing>

Subsequently, the processing performed by the main control unit 20 of the present embodiment will be described. The processing of the main control unit 20 is mainly a predetermined main processing (main control side main processing: FIG. 8) and a timer interrupt processing activated by a scheduled interrupt from the CTC (main control side timer interrupt processing: FIG. 20). And are included.

[4-1. Main control side main processing]

FIG. 5 is a flowchart showing the main processing on the main control side.
The main processing on the main control side is started when a system reset occurs due to a system reset signal from the power supply board when recovering from a power failure or power failure, or when the control program runs out of control, the watchdog timer function ( WDT) may be exerted and the CPU 20a may be forcibly reset (WDT reset). In any case, when the main process is started, the main control unit 20 (CPU 20a) first executes the initial setting process necessary for starting the game operation, such as initializing the register values of each unit including the CPU 20a. (Step S101).

(Initial setting process)

FIG. 6 is a flowchart showing the initial setting process of step S101.
In FIG. 6, when the above system reset or WDT reset occurs, the CPU 20a sets itself in the interrupt disabled state in step S201, and then sets the stack pointer value of the RAM 20c to the stack area as the stack pointer setting process in step S202. Executes the process to set according to the final address of. Then, in the following step S203, the RAM protection is invalidated, and the prohibited area in the out-of-designated area travel prohibition function of the RAM 20c is invalidated.

Next, in step S204, the CPU 20a executes a process for turning off the security signal, turning off the set value display, and turning off the firing permission signal. Here, the security signal is a signal output to the hall computer HC through the external centralized terminal board 21 for the frame, and functions as a signal for notifying the hall computer HC of a status such as a setting change being changed. The setting value display OFF means turning off the display of the set value Ve on the setting / performance indicator 97.
The launch permission signal is a signal output from the payout control board 29 to the launch control board 28 as described above, and the CPU 20a gives an instruction to the payout control board 29 to turn off the launch permission signal.
Here, the security signal OFF and the set value display OFF are measures for turning on / off the power while the setting is being changed. That is, since the power may have been turned off while the set value Ve is being displayed in the setting change process, the set value display and the security signal are temporarily turned off.

In step S205 following step S204, the CPU 20a executes a power supply abnormality check process.
As shown in FIG. 7, in the power supply abnormality check process, the WDT timer is cleared (step S11), and it is determined whether or not the power supply abnormality signal is ON (step S12). The power supply abnormality signal is a signal output from the power supply board, indicates that the power supply abnormality signal OFF is at a normal level, and indicates that the power supply abnormality signal ON is not at a normal level (that is, is abnormal). If the power supply abnormality signal is ON, the CPU 20a returns to step S101 shown in FIG. 5 and restarts the main processing on the main control side from the beginning. That is, when an abnormality is found in the power supply, the main processing on the main control side is reset.
Then, if the power supply abnormality signal is not ON, no abnormality is found in the power supply, so that the CPU 20a finishes the power supply abnormality check process.

Returning to FIG. 6, the CPU 20a performs various setting processes at startup in step S206 in response to the completion of the power supply abnormality check process in step S205. In the setting process of step S206, for example, an interrupt mode setting process for setting a predetermined interrupt mode, an internal hard random number setting process for activating an internal hard random number circuit, and the like are executed. Further, in the setting process of step S206, a process of setting an initial value to a predetermined register among various registers provided in the CPU 20a is also performed.

In step S207 following step S206, the CPU 20a sets the startup waiting time of the sub control board (effect control unit 24). Then, the process of steps S208 to S210 waits for the set start-up waiting time to elapse. Specifically, after subtracting 1 from the set startup waiting time (step S208) and executing the power supply abnormality check process (step S209), if the startup waiting time is not zero (step S210: ≠ 0), step S208 Return to the processing of. By the standby process based on such an activation waiting time, the activation of the effect control unit 24 is completed.

In step S210, when the above-mentioned startup waiting time has elapsed (waiting time = 0), the CPU 20a proceeds to step S211 and transmits a standby screen display command to the effect control unit 24.
In response to this standby screen display command, the effect control unit 24 displays a predetermined screen display, such as a screen on which characters such as "Please Wait ..." are arranged, on the liquid crystal display device 36 at the time of startup. Control to execute.

In response to the execution of the transmission process of step S211 the CPU 20a proceeds to step S212, and the process of step S212 and step S213 executes the power supply abnormality check process (S212: see FIG. It waits for the power-on signal from the board 29 to be sent. This power-on signal is a signal that is output when the payout control board 29 starts up normally, and the CPU 20a waits until the payout control board 29 starts up normally. As a result, when the payout control board 29 is not functioning normally due to some trouble, the game operation is not started only by repeating the processes of steps S212 and S213. Therefore, it is possible to prevent the player from being distrusted because the payout abnormality such as the prize ball not being paid out does not occur.
When the power-on signal is sent (step S213: ON), the CPU 20a ends the initial setting process in step S101.

(Processing after initial setting)

The CPU 20a proceeds to step S102 shown in FIG. 5 in response to the completion of the above initial setting process.
In step S102, the CPU 20a acquires the information of the input port n (that is, a predetermined input port) and copies it to the W register.
Here, the input port n is a 1-byte (8-bit) port, and in this example, the following signals are input. In addition, "b0" to "b7" shown below represent a bit position.

b0: Setting key (input signal from setting key switch 94)
b1: Out of supply detection signal b2: Counting error signal b3: Disconnection detection signal 1
b4: Disconnection detection signal 2
b5: Door open signal (detection signal of front door open sensor 61)
b6: RAM clear button (input signal from RAM clear switch 98)
b7: Power-on signal and payout communication confirmation signal

Here, regarding the setting key of b0, "0" means the setting key switch 94 = OFF, and "1" means the setting key switch 94 = ON. Regarding the door opening signal of b5, "0" means the door is closed (front frame 2 is closed), and "1" means the door is opened. Further, regarding the RAM clear button of b6, "0" means RAM clear switch 98 = OFF (button non-operation state), and "1" means RAM clear switch 98 = ON (button operation state).

In step S103 following step S102, the CPU 20a masks the value of the W register. Specifically, the values required for determining the migration of the setting change processing (S115), RAM clear processing (at least S117 and S118), setting confirmation processing (S109), and backup restoration processing (S111) described below. The process of masking the values other than the setting key (b0), the RAM clear button (b6), and the door opening signal (b5) is performed.
As can be understood from the above explanation, the transition condition to the setting change process is that at the time of startup, both the setting key and the RAM clear button are in the operating state with the front frame 2 open. ing.
Further, in this example, the transition condition to the RAM clear processing is that, in terms of operation, the setting key is in the non-operation state and the RAM clear button is in the operation state at the time of startup.
Further, the transition condition to the setting confirmation process is that, in terms of operation, the setting key is in the operating state and the RAM clear button is in the non-operating state when the front frame 2 is open.
Further, the transition condition to the backup restoration process is that, in terms of operation, both the setting key and the RAM clear button are in the non-operation state at the time of startup.

FIG. 8 shows the correspondence between each determination condition on the operation side in shifting to the setting change processing, the RAM clear processing, the setting confirmation processing, and the backup restoration processing, and the value of the W register.
FIG. 8 shows the order of setting change processing, RAM clear processing, setting confirmation processing, and transition determination to backup restoration processing.
As shown in the figure, the judgment conditions for the transition to the first setting change process are: setting key: ON (setting key switch 94: ON), door opening: ON (front door opening sensor 61: ON), RAM clear switch 98. : ON, and therefore the value of the W register is conditioned on the 0th bit: 1, the 5th bit: 1, and the 6th bit: 1.
In the second determination of transition to the RAM clear process, it is determined whether or not the determination condition is the RAM clear switch 98: ON and the value of the W register is the 6th bit: 1. Here, in this example, the transition determination to the RAM clear process is executed when the transition condition of the setting change process is not satisfied. Further, in the transition to the setting confirmation process and the backup restoration process, it is a condition that the RAM clear switch 98 is OFF. From these points, if the transition condition to the setting change processing is not satisfied and the RAM clear switch 98 is ON, it can be estimated that the transition operation to the RAM clear processing is being performed. Therefore, in this example, in the transition determination to the RAM clear processing as described above, in terms of operation, only whether or not the RAM clear switch 98 is ON (6th bit: 1 or not) is determined. It is supposed to be.

In the judgment of transition to the third setting confirmation process, the judgment conditions are set key: ON, door open: ON, RAM clear switch 98: OFF, and therefore the W register value is the 0th bit: 1st and 5th bits. The condition is: 1, 6th bit: 0.
Further, in the determination of transition to the fourth backup restoration process, the determination conditions are set key: OFF and RAM clear switch 98: OFF, and therefore, the W register values are 0th bit: 0 and 6th bit: 0. It is a condition.

Here, regarding the backup restoration process, as the transition condition for performing only the backup restoration process without going through the setting confirmation process, the setting key: OFF and the RAM clear switch 98: OFF are described on the operation side as described above. However, the condition for whether or not to simply shift to the state in which the backup restoration process is performed regardless of whether or not the setting confirmation process is executed is that the backup flag described later is ON (step S106). Refer to the judgment process of).

The explanation is returned to FIG.
The CPU 20a executes the setting change condition establishment determination process in step S104 in response to performing the mask process in step S103. Specifically, in order to determine whether or not to shift to the setting change mode, it is determined whether or not the masked value (3 bits) in step S103 is "111".
When the value after masking is "111" and an affirmative result that the setting change condition is satisfied is obtained, the CPU 20a executes the setting change process in step S115. That is, a process for newly setting the set value Ve is performed according to the operation of the RAM clear button or the setting key.
The details of the setting change process in step S115 will be described later.

Here, as described above, in the present embodiment, the detection signals by the setting key switch 94, the front door opening sensor 61, and the RAM clear switch 98, in other words, each detection used in determining the transition to the setting change mode. A signal is input to the same input port of the main control unit 20, and it is collectively determined whether or not the value of each input detection signal satisfies a predetermined condition.
As a result, the number of determination processes for the determination of transition to the setting change mode can be reduced as compared with the case of individually determining whether or not the value of each detection signal satisfies a predetermined condition.

In response to the execution of the setting change process in step S115, the CPU 20a executes the RAM clear process in step S116. This RAM clear process is a setting for notifying the effect control unit 24 of the process of initializing the value in the predetermined area (used area) including the work area in the RAM 20c and the end of the setting change process executed in step S115. It includes the process of sending the change end command, but the details will be described later.

Subsequently, in the previous step S104, if the value after masking by step S103 is not "111" and a negative result is obtained that the setting change condition is not satisfied, the CPU 20a proceeds to step S105 and the RAM is abnormal. Judge whether or not. Specifically, it is at least determined whether or not the "set value" stored in the work area of the RAM 20c is a value outside the usage range Ru (in this example, outside the range of "1", "2", and "6"). To do.
Here, as a value handled by the CPU 20a with respect to the set value Ve, there is a set value Vd. The set value Vd is a value corresponding to the set value Ve, which is a 1-byte value in this example, and is 00H so as to be able to express at least three stages corresponding to the above-mentioned usage range Ru. The values of (0) to 02H (3) are defined. In addition, "H" means a hexadecimal number (hereinafter, the same applies). In this example, the set value Vd = 00H represents the set value Ve = "1", the set value Vd = 01H represents the set value Ve = "2", and the set value Vd = 02H represents the set value Ve = "6". It is supposed to be. In the main control unit 20, the set value Vd is mainly handled as the "set value", and this set value Vd is stored in the storage area of the "set value" in the work area of the RAM 20c of the main control unit 20. ..
In the determination process of step S105, it is determined whether or not the set value Vd stored in the work area is a value in the range of 00H to 02H.

In step S105, when the set value is a value outside the above usage range Ru (that is, outside the normal range) and it is determined that the RAM is abnormal, the CPU 20a is a process for waiting for the power supply is turned on again after step S112. After that.
Specifically, in step S112, the CPU 20a instructs the pachinko gaming machine 1 to be notified to re-turn on the power and change the setting as a command transmission process when the power is turned on again (setting). A process of transmitting a change waiting command) to the effect control unit 24 is performed. If a RAM abnormality is detected at startup, the mode is forcibly shifted to the setting change mode and the change (setting) of the set value Ve is accepted. Therefore, the CPU 20a first notifies the effect control unit 24 side in step S112 that the setting change mode is to be entered by the setting change waiting command.
In response to the setting change waiting command, the effect control unit 24 executes a screen display on the liquid crystal display device 36 to prompt the setting change operation, such as a screen containing characters such as "Open the door and change the setting". Let me. At this time, the effect control unit 24 may perform control to display the corresponding light effect (for example, lighting of all LEDs in the light display device 45a) and the sound effect together with the screen display.

In step S113 following step S112, the CPU 20a sets the backup flag to 00H (that is, OFF), and repeats the error display process in step S114. In the error display process of step S114, a process for causing the setting / performance indicator 97 to execute the error display is performed. This error display process is repeated until the power of the pachinko gaming machine 1 is turned off, and when the power is turned on again, the processes after step S101 are executed again as the main process on the main control side. At this time, if the operation for shifting to the setting change mode is performed according to the above screen display or the like, the shift to the setting change mode is performed and the RAM abnormal state is resolved.

In step S105 described above, if it is determined that the set value is not a value outside the range of use Ru and is not a RAM abnormality, the CPU 20a proceeds to step S106 to see if the backup flag is ON (in this example, the backup flag = 5AH). Is ON state) is determined.
In the game machine 1, when the power is cut off, the storage information of the RAM 20c is backed up by the power check / backup process (step S901, see FIG. 19) described later in the timer interrupt process on the main control side. If the backup process is properly performed when the power is cut off, the backup flag is turned on (see step S1010 in FIG. 19). Therefore, in step S106 described above, the backup flag is confirmed, and it is determined whether or not the backup can be restored. Specifically, in step S106, it is determined whether or not the backup flag stored in the predetermined area of the RAM 20c is in the ON state (5AH).

If it is determined in step S106 that the backup flag is not ON, the CPU 20a proceeds to step S112 described above. As a result, when the backup restoration condition is not satisfied, the transition to the setting change mode is forcibly performed as in the case where the RAM abnormality described above is recognized.

Here, as described above, the determination process in step S106 corresponds to the process of determining whether or not to shift to the state in which the backup restoration process is performed regardless of whether or not the setting confirmation process is executed.

On the other hand, when it is determined in step S106 that the backup flag is ON, the CPU 20a determines in step S107 whether or not the RAM clear condition (transition condition to the RAM clear process) is satisfied. Specifically, it is determined whether or not the value of the 6th bit of the W register is "1".
When the value of the 6th bit of the W register is "1" and an affirmative result that the RAM clear condition is satisfied is obtained, the CPU 20a proceeds to the process in step S116 described above. As a result, the RAM clearing process described above is executed.

Here, as can be seen by referring to the route from step S107 to S116 described above, in the game machine 1 of the present embodiment, it is possible to clear the RAM without changing the setting. This makes it possible to deal with cases where it is desired to clear data other than the data related to the set value Ve, such as data related to payout in the RAM 20c.

Further, in step S107, if the value of the 6th bit of the W register is not "1" and a negative result that the RAM clear condition is not satisfied is obtained, the CPU 20a proceeds to step S108 to confirm the setting (setting confirmation condition). It is determined whether or not the transition condition to the setting confirmation process) is satisfied. That is, it is determined whether or not the value of the W register after masking in step S103 is "110".
When the value of the W register after masking is "110" and an affirmative result that the setting confirmation condition is satisfied is obtained, the CPU 20a executes the setting confirmation process in step S109 and proceeds to step S110. That is, the process shifts to the process for restoring the backup.
The details of the setting confirmation process in step S109 will be described again.

On the other hand, if the value of the W register after masking is not "110" and a negative result that the setting confirmation condition is not satisfied is obtained, the CPU 20a passes the setting confirmation process in step S109 and proceeds to step S110. ..

In step S110, the CPU 20a performs a process of transmitting a predetermined effect control command corresponding to the backup return to the effect control unit 24 as a command transmission process at the time of backup return.

In step S111 following step S110, the CPU 20a performs a backup restoration process.
The backup restoration process is a process of restoring the operation after the power is turned on and before the power is turned off, based on the stored contents of the RAM 20c backed up when the power is turned off. Specifically, the CPU 20a returns the stack pointer before the power is cut off, and performs a process for starting the game operation from the processing state when the power is cut off.
Further, in the backup restoration process, the power failure restoration display command (OB03H) for issuing the information display instruction corresponding to the backup restoration is transmitted to the effect control unit 24 in the main loop preprocessing in step S119 described later. Therefore, the process of storing the lower byte data of the power failure recovery display command in the register is executed.

When the backup restoration process in step S111 is executed, or when the RAM clear process in step S116 described above is executed (that is, when both the setting change process and the RAM clear process are executed, or when only the RAM clear process is executed). , CPU 20a proceeds with step S117 processing.

In step S117, the CPU 20a sets the CTC for periodically generating a timer interrupt at predetermined time intervals such as 4 ms.
By performing the setting process in step S117, the interrupt request signal to the interrupt controller is periodically output thereafter, and the timer interrupt process on the main control side is executed.

In the following step S118, the CPU 20a performs a process of transmitting an effect control command for instructing the start of the game to the effect control unit 24, then proceeds to step S119 to execute the main loop preprocessing, and then step S120. Executes the main loop processing of.
The main loop preprocessing in step S119 will be described later.

(Main loop processing)

FIG. 9 is a flowchart showing the main loop processing in step S120.
In the main loop process of FIG. 9, the CPU 20a sets itself in the interrupt disabled state in step S601, and executes the random number update process in the subsequent step S602. In this random number update process, various random numbers used in the special symbol variation display game and the normal symbol variation display game (random numbers related to the jackpot lottery circulating in a predetermined numerical range by the increment process (special symbol determination used for the symbol lottery). Random numbers used to change the initial value (start value) of random numbers related to the lottery for auxiliary hits (random numbers for auxiliary hit judgment used in the winning lottery for auxiliary hits) (initial value random numbers for special symbol judgment) , Initial value random number for auxiliary hit judgment) and random number for fluctuation pattern used for selection of fluctuation pattern are updated.

In the RAM 20c of the present embodiment, as various random number counters used for a symbol lottery related to a big hit lottery, an auxiliary hit lottery, a variable pattern lottery, etc., a random number counter for special symbol determination, a counter for generating an initial value, and a special symbol determination A random number counter for, a random number counter for determining auxiliary hits, a counter for generating initial values, a random number counter for determining auxiliary hits, a random number counter for fluctuation patterns, and the like are provided. These counters serve as random number generating means for generating random numbers by software. In the random number update process of step S602, the above-mentioned special symbol determination random number counter, the two initial value generation counters that generate the initial values of the auxiliary hit determination random number counter, the fluctuation pattern random number counter, and the like are updated, and the above various types are Generate soft random numbers. For example, assuming that the numerical range that can be taken as the random number counter for the fluctuation pattern is "0 to 238", a value is acquired from the count value storage area for generating the value of the random number for the fluctuation pattern of the RAM 20c, and the acquired value is used. After adding "1", it is stored in the original count value storage area. At this time, if the result of adding "1" to the acquired value is "239", "0" is stored in the original random number counter storage area. Other random number counters for initial value generation are updated in the same way.

When the random number update process in step S602 is completed, the CPU 20a performs a process of saving the values of all the registers in step S603, and then performs a performance display monitor aggregation division process in step S604.
This performance display monitor aggregation division process is a process for calculating a value as the performance information described above (here, for example, a value as the “normal time ratio information” described above). As described above, the value of the normal time ratio information is calculated using the total number of payouts and the total number of out balls, but the CPU 20a has a winning opening (upper start opening 34, for the total number of payouts). Calculated based on the result of counting the number of game balls that won in the lower start opening 35, general winning opening 43, and large winning opening 50). For the total number of out balls, the number of game balls discharged from the out opening 49 is used. Obtained by counting.
The number of winning balls and the number of out balls are counted in the input management process (see step S904 in FIG. 18) described later in the main control side timer interrupt process. The CPU 20a calculates the value as the normal time ratio information in step S604 based on the count values of the count of the number of winning balls and the count of the number of out balls performed on the timer interrupt processing side in this way. As described above, the calculated value as the normal time ratio information is stored in the predetermined area (measurement information storage area) of the RAM 20c.
The value of the normal time ratio information calculated in this way is displayed on the setting / performance indicator 97 by the performance display monitor display process (see step S916 in FIG. 18) described later in the main control side timer interrupt process.

In step S605 following step S604, the CPU 20a performs all register reset processing, sets itself in the interrupt enabled state in the following step S606, and then returns to step S601.

As described above, in the main loop processing of step S123, the processing of steps S601 to S606 is repeated in an infinite loop. The CPU 20a repeatedly executes the processes of steps S601 to S606 except during the timer interrupt process that is intermittently executed.

(Setting change processing)

FIG. 10 is a flowchart showing the setting change process in step S115.
In this setting change process, a process for setting the set value Ve based on the operation and an effect control command for notifying the effect that the setting is being changed or the setting change is completed (completed) are sent to the effect control unit 24. Processing for transmission is performed.

In FIG. 10, the CPU 20a first executes a process of transmitting a setting changing command (BA76H) to the effect control unit 24 in step S401.
In response to this setting changing command, the effect control unit 24 displays on the liquid crystal display device 36 a screen display for notifying that the setting is being changed, such as a screen on which characters such as "setting is being changed" are arranged. Processing is performed to execute the command or to output the corresponding sound from the speaker 46 while the setting is being changed. Further, at this time, the effect control unit 24 may light a predetermined LED (for example, all LEDs) in the above-mentioned light generating means (light display device 45a) according to a predetermined lighting pattern.

In the following step S402, the CPU 20a sets the backup flag to 00H (that is, the OFF state), and then sets the system operation status = 2 in the step S403. This system operation status is information for at least identifying whether or not the system has passed the setting change process of step S115 at the time of startup, and "2" indicates that the setting change process has been performed, and is other than "2". Indicates that the value (for example, "0") does not go through the setting change process.
As can be seen with reference to FIG. 5, in this example, there are cases where both the setting change process and the RAM clear process (S116) are executed, and the case where only the RAM clear process is executed without executing the setting change process. Although the clear process (program) is shared, by using the above system operation status, it is possible to execute the process separately in the former case and the latter case while sharing the RAM clear process program. ..

In step S404 following step S403, the CPU 20a executes a process of acquiring a set value. Specifically, the set value Vd (any of 00H to 02H in this example) stored in the work area of the RAM 20c is acquired.

In the processing after step S405 following step S404, the display value on the setting / performance indicator 97 is updated according to the progressive operation of the set value Ve (operation of the RAM clear button), or the setting change completion operation (setting key operation) is performed. It is a process for setting the set value Ve according to the operation).
First, the CPU 20a decrements the acquired set value Vd by 1 in step S405 (“set value -1”), and determines whether or not the set value Vd is larger than 1 in the following step S406 (set value> 1”. ). In this example, since the maximum value of the set value Vd is 02H, it is not determined that the set value> 1 in step S406, which is executed for the first time after the start of the setting change process.
In step S406, if the set value Vd is not larger than 1, the CPU 20a sets the carry flag in step S407 (after turning it ON), and then increments the set value Vd by 1 in step S408 (“set value + 1”). ), And it is determined in step S409 whether or not the carry flag is ON. If the carry flag is ON, the CPU 20a executes the setting change command acquisition process in step S411, and transmits the setting change command to the effect control unit 24 by the subsequent command process in step S412.
The command for changing the setting will be described later.
Then, in response to executing the command transmission process in step S412, the CPU 20a executes the output management process in step S413. By this output management process, the set value Ve corresponding to the current set value Vd is displayed on the setting / performance display 97. The details of the output management process in step S413 will be described later.

In step S414 following step S413, the CPU 20a determines whether the setting key is OFF, that is, whether the setting key switch 94 is OFF, and if the setting key is not OFF, the change switch, that is, in step S415. It is determined whether or not the RAM clear switch 98 is ON. If the RAM clear switch 98 is not ON, the CPU 20a re-executes the output management process in step S413.
By the processing of steps S413 to S415, the CPU 20a waits until either the setting key or the change switch is turned ON, and during the standby, the setting / performance indicator 97 displays the current set value Ve by the processing of step S413. Repeat the process for.

If the change switch is ON in step S415, the CPU 20a returns to step S406.
Here, if the set value Vd (set value Vd that was being set up to that point) acquired at the start of the setting change process in step S115 is 02H, it is determined in step S415 that the change switch is ON. In the process of step S406 executed accordingly, a determination result that "set value>1" is obtained (because it is -1 in step S405 but +1 in step S408). The set value Vd should be returned to 00H according to the change operation (progressive operation) performed while the set value Vd is 02H. Therefore, when it is determined in step S406 that "set value>1", the carry flag set process in step S407 is passed, and the process proceeds to step S408. As a result, since the carry flag is determined to be OFF in step S409, the process proceeds to step S410 and the set value Vd is returned to 00H (“set value ← 0”).
The CPU 20a proceeds to step S413 via the processes of steps S411 and S412 in response to returning the set value Vd to 00H in step S410. That is, in this case, the set value Ve (“1” in this example) corresponding to the set value Vd = 00H is displayed on the setting / performance display 97.

By the above processing, during the setting change, the set value Vd is cyclically changed within the range of 00H to 02H (within the usage range Ru) according to the change operation, and corresponds to the changed set value Vd. The set value Ve is displayed on the setting / performance display 97.

Further, the setting change command transmitted in step S412 is a command for notifying the effect control unit 24 of the setting value Ve corresponding to the set value Vd being selected during the setting change process, and the selected setting value. It is a command that stores information representing Ve.
By the series of processes of steps S406 to S415 described above, every time the selected set value Ve is switched by the progressive operation of the set value, a setting change command reflecting the changed set value Ve is transmitted to the effect control unit 24. Will be.
Although the description by illustration is omitted in FIG. 10, the CPU 20a uses the set value offset conversion table described later in acquiring the set value Ve corresponding to the set value Vd (see FIG. 16).

If it is determined in step S415 that the setting key is OFF, the CPU 20a proceeds to step S416 to execute a process of saving the set value Vd. That is, the process of storing the set value Vd in a predetermined area in the work area of the RAM 20c is executed.
The CPU 20a ends the setting change process in step S115 in response to the execution of the save process in step S416.

FIG. 11 is a flowchart of the output management process in step S413.
First, the CPU 20a executes the security signal output process in step S501. Specifically, a process is performed so that a security signal is output to the hall computer HC through the external centralized terminal board 21 for the frame.
In the following step S502, the CPU 20a executes a process of outputting 0 to the LED common port, that is, the LED common port as the setting / performance indicator 97, and then acquires display data from the 7-segment decoding table in step S503. Execute the process. That is, it is a process of acquiring display data of the set value Ve (“1”, “2”, “6”) based on the set value Vd.
When 0 is output to the LED common port in step S502, the setting / performance indicator 97 is in the display OFF state (non-display state), the significance of which will be described later.

FIG. 12 shows an example of a 7-segment decoding table, and FIG. 13 is a diagram illustrating the relationship between the segment configuration and the segment display pattern in the setting / performance display 97.
The 7-segment decoding table is stored in the ROM 20b of the main control unit 20.

In this example, the seven segments of the setting / performance indicator 97 are numbered by numerical values 0 to 6 as shown in FIG. 13A. The setting / performance display 97 is provided with a DP (dot point) display unit (light emitting unit) together with these seven segments 0 to 6, and the DP display unit is numbered “7”. ing.
As the 7-segment display data, a total of 10 data are prepared, from the display data of "SEG_0" representing the numerical value "0" to the display data of "SEG_9" representing the numerical value "9". The display data is 1 byte (8 bits) of data, and when the least significant bit position is the first bit position, the first bit position is the display / non-display of the segment "0" (light emission / non-light emission). Represents. After that, similarly, the second bit position is the segment "1", the third bit position is the segment "2", the fourth bit position is the segment "3", the fifth bit position is the segment "4", and the sixth bit position. The bit position of is the display / non-display of the segment "5", and the 7th bit position is the display / non-display of the segment "6".
Further, in the display data in this example, the eighth bit position represents the display / non-display of the DP (“7”).

In the 7-segment decoding table shown in FIG. 12, the corresponding display data, specifically, the display data of SEG_1, SEG_2, and SEG_6 are acquired from the set values Vd = 00H, 01H, and 02H, respectively. It is configured.
Specifically, in the 7-segment decoding table of this example, an area for storing display data for each set value Vd of at least 00H to 05H is secured, such as the address areas of "6203" to "6208" in the figure. The display data SEG_1 (“06” in the figure) corresponding to the set value Vd = 00H is set in the second area in the uppermost area (the area of the address with the youngest number) in this area. The display data SEG_2 (“5B” in the figure) corresponding to Vd = 01H is stored, and the display data SEG_6 (“7D” in the figure) corresponding to the set value Vd = 02H is stored in the third area.
In this example, the fourth area corresponding to the set value Vd = 03H, the fifth area corresponding to the set value Vd = 04H, and the sixth area corresponding to the set value Vd = 05H are for display. Although "00" is stored as data, its significance will be described again.
Further, in the 7-segment decoding table of this example, display data SEG_E ("79") for displaying "E" indicating a setting value error is stored in the 7th area. It is possible to notify the set value error through the setting / performance indicator 97 in response to the case where the set value Vd shows an abnormal value such as the set value Vd is a value outside the usage range Ru. ..

The explanation is returned to FIG.
The CPU 20a performs a process of outputting the display data acquired from the 7-segment decoding table by the process of step S503 to the setting / performance display 97 in step S504.
Subsequent steps S505 to S508 are processes for dynamically lighting (intermittently lighting) the LED for displaying the set value Ve on the setting / performance indicator 97. Specifically, in step S505, the CPU 20a increments the LED counter by 1, and in the subsequent step S506, determines whether or not the 0th and 1st bits (lower 2 bits) of the LED counter are "11". Here, the lower 2 bits of the LED counter become "11" when the increment process of step S505 is performed a multiple of 4.
In step S506, if the 1st and 0th bits of the LED counter are "11", the CPU 20a proceeds to step S507, outputs data for designating a segment for displaying the set value to the LED common port, and displays data in step S508. Executes timer count processing. By executing the output process in step S507, the setting / performance indicator 97 displays the set value Ve based on the display data output in step S504. Then, this display state is continued for the time of the display timer in step S508 (4 ms in this example).

The output management process shown in FIG. 11 ends in response to the execution of the process of step S509 following the timer count process of step S508, and the process proceeds to step S414 shown in FIG. If the change switch is ON, the output management process of step S413 is repeated. As described above, since 0 is output to the LED common port in step S502, the lighting state of the LED for setting value display started in the process of step S507 is canceled by the execution of step S502. Since the LED counter is incremented by 1 in step S505, it is determined in step S506 that the 0th and 1st bits of the LED counter are not "11", the output processing in step S507 is passed, and the timer count processing in step S508 is performed. Will be executed. That is, after the process of step S507 is executed and the LED for displaying the set value is turned on for a period of at least 4 ms, until the 0th and 1st bits of the LED counter become "11" again, that is, in this example. The LED is turned off for at least 4 ms × 3 = 12 ms.
In this way, dynamic lighting is realized in which the LED for displaying the set value is intermittently lit at a predetermined cycle.

In FIG. 11, the CPU 20a executes the input data creation process in step S509 in response to executing the timer count process in step S508.
This input data creation process is executed by calling, for example, the same process in step S902 in the main control side timer interrupt process (FIG. 18). As will be described later, the input data created by the input data creation process includes the input data of the RAM clear switch 98 indicating the presence / absence of the progressive operation of the set value Ve and the setting key switch indicating the presence / absence of the setting change completion operation. Contains 94 input data.
As can be seen with reference to FIG. 10, the determination of the presence / absence of the setting change completion operation (S414) and the determination of the presence / absence of the progressive operation of the set value Ve (S415) are executed after the output management process of step S413. Therefore, by executing the input data creation process in step S509, the data required for these determination processes can be obtained in advance.

(RAM clear processing)

FIG. 14 is a flowchart of the RAM clearing process (S116) shown in FIG.
First, the CPU 20a executes the in-region RAM initialization process in step S601. The initialization process of step S601 is a process of initializing (clearing) the value in the predetermined area (used area) including the work area in the RAM 20c. However, in the initialization process of step S601, the storage area of the set value Vd in the work area is excluded from the initialization target.

The above-mentioned performance information is stored in an area outside the used area (details will be described later with reference to FIG. 21) in the RAM 20c, and therefore is not cleared by the initialization process in step S601.
The data to be cleared in the RAM clearing process is data in the RAM area (normal data storage area) such as various flags, timers, and counters required for normal game progress. These data include, for example, the following. That is, data related to the game state designation (a game state flag that specifies the current game state such as a normal state, a probability change state, a time saving state, and a latent state), and a flag that specifies whether or not a winning game is in progress (conditional device). Operation flag), various data related to the execution of the winning game (current number of rounds, maximum number of rounds, etc.), data related to the big hit lottery result (big hit judgment flag: winning lottery result information, special symbol judgment data: symbol lottery result information) , Manages hold data related to operation hold balls (number of operation hold balls, various random number values used for big hit lottery, various random number values used for auxiliary hit lottery, random number for fluctuation pattern), special symbol operation status, game progress Timer (special symbol accessory operation timer), input / output data related to switches and sensors, various winning counters that count the number of winning balls in the winning opening, flags that specify the presence or absence of electric support status (open extension flag), electric power Electric support count counter that counts the remaining number of support, counter that counts the remaining number of high probability state (special figure probability variation counter, normal figure probability variation counter), various error flags (excluding RAM error flag), and payout related Data etc. In any case, when the RAM clear process is executed, all the data other than the specific data (set value Vd and performance information) are set to the initial state.

Here, as understood from the above description of FIG. 5, when the setting change process (S115) is executed, the process proceeds to step S116 and the RAM clear process is executed.
In the setting change process, the set value Vd can be changed. When the set value Vd is changed, the stored values other than the set value Vd in the work area of the RAM 20c may be inconsistent with the changed set value Vd. Therefore, when the setting change process is performed, the area other than the set value Vd in the work area is cleared (initialized) by executing the RAM clear process.

In response to the execution of the initialization process in step S601, the CPU 20a sets 30s in the RAM clear notification timer in step S602 and also executes a process for setting a misalignment in this special figure. The RAM clear notification timer is a timer for setting the RAM clear notification time executed by the effect control unit 24 in response to the RAM clear command transmitted in the process of step S803 of FIG. 17, which will be described later, and is 30 s in this example. To set. Further, the present special figure referred to here means, for example, the above-mentioned special figure 1 and special figure 2.

In step S603 following step S602, the CPU 20a determines whether or not the system operation status described above is "2". That is, it is determined whether or not the setting change process of step S115 has been performed after the startup.
If the system operation status is "2", the CPU 20a executes the process corresponding to the case of passing through the setting change process in steps S604 to S612.
If the system operation status is not "2", the CPU 20a proceeds with the process in step S613, stores the lower byte data of the RAM clear command in the register, and ends the RAM clear process in step S116.
The operation of storing the lower byte data of the command in the register as described above functions as an operation of designating the command type to be transmitted in step S804 of the main loop preprocessing (FIG. 17) described later.

When passing through the setting change process, the CPU 20a first resets the system operation status to "0" in step S604, executes the acquisition process of the setting change end command (BA77H) in step S605, and then executes the command in step S606. The setting change end command is transmitted to the effect control unit 24 by the transmission process.

The processes of steps S607 to S612 following step S606 are processes related to the display of the set value Ve on the setting / performance indicator 97.
First, in step S607, the CPU 20a outputs data for designating the set value display segment to the LED common port, and in the following step S608, the display data corresponding to the set value Vd is output from the 7 segment decode table (see FIG. 13). After executing the process of acquiring and adding DP to the display data in step S609, that is, the process of setting the value of the 7th bit position of the display data to "1", the display data is output by the output process of step S610. Output to the setting / performance indicator 97.

The processes of steps S612 and S613 following step S611 are processes for continuing the display state of the set values Ve and DP on the setting / performance indicator 97 for a predetermined time (1s in this example). Specifically, the CPU 20a repeatedly executes the display timer count process in step S612 (for example, the timer count process having a cycle of 4 ms similar to that in step S508 (see FIG. 11)) until it is determined in step S612 that 1 s has elapsed. To do.

If it is determined in step S612 that 1 s has elapsed, the CPU 20a executes the storage process of step S613 and ends the RAM clear process of step S116.

As can be understood from the above description, when the setting change process of step S115 is executed and the setting change completion operation is performed (step S412: Y in FIG. 10), the RAM clear process of step S116 The setting change end command is transmitted to the effect control unit 24 (S605, S606), and a notification that the setting change is completed is given.
In the case of this example, the setting change end command notifies the effect control unit 24 that the setting change has been completed, and does not provide the function of notifying the setting value Ve set in the setting change process. ..
In this example, the set value Ve set in the setting change process is notified to the effect control unit 24 by the set value command transmitted in the process of step S808 of FIG. 17 (main loop preprocessing) described later.

(Setting confirmation process)

FIG. 15 is a flowchart showing the setting confirmation process in step S109.
The setting confirmation process is a process for confirming and displaying the set value Ve that is being set.
In FIG. 15, the CPU 20a first sets 30s in the fraudulent information timer in step S701. The fraud information timer is a timer for managing the output time of the above-mentioned security signal to the hall computer HC.
In the following step S702, a process of acquiring the current set value information is performed. That is, the set value Vd stored in the work area of the RAM is acquired.

In step S703 following step S702, the CPU 20a executes a process of acquiring the set value data from the set value offset conversion table.

FIG. 16 shows an example of a set value offset conversion table stored in the ROM 20b of the main control unit 20.
In the set value offset conversion table, the set value Vd (00H to 02H) is set to the set value Ve ("1".
It functions as a table for converting the identification data ("SETNUM1" to "SETNUM6") of "2" and "6").
In the case of this example, the set value offset conversion table has an area for storing the identification data of the set value Ve for at least each set value Vd of 00H to 05H, such as the address areas of "6215" to "6220" in the figure. The identification data (“00” in the figure) of the set value Ve “1” corresponding to the set value Vd = 00H is set to the set value Vd = 01H in the uppermost area in this area. The identification data (“01” in the figure) of the corresponding set value Ve “2” is the identification data (“05” in the figure) of the set value Ve “6” corresponding to the set value Vd = 02H in the third area. It is stored.
In this example, the set value is set in the fourth area corresponding to the set value Vd = 03H, the fifth area corresponding to the set value Vd = 04H, and the sixth area corresponding to the set value Vd = 05H. "00" is stored as the identification data of Ve, and its significance will be described again.

In FIG. 15, the CPU 20a acquires the above-mentioned identification data as “set value data” by the acquisition process in step S703.

In response to the execution of the acquisition process of step S703, the CPU 20a executes the acquisition process of the setting checking command (BA6xH) in step S704, and then sends the setting checking command to the effect control unit 24 by the command transmission process of step S705. Send.
In the acquisition process of step S704, the CPU 20a performs a process of including the setting value data acquired in step S703, that is, the identification data for identifying the set value Ve being set in the currently set value, in the setting checking command.
As a result, when the command transmission process in step S705 is executed, the effect control unit 24 is notified that the setting is being confirmed and the current set value Ve.

The processes of steps S706 and S707 following step S705 are processes for displaying the current set value Ve on the setting / performance indicator 97.
Specifically, the CPU 20a first executes a process of acquiring set values and DP data in step S706. That is, the process of acquiring the current set value Vd stored in the work area of the RAM 20c and the DP data (“1”) in the setting / performance display 97 is executed. Then, the output management process of step S707 is executed. The output management process in step S707 is the same process as the output management process in step S413 shown in FIG. As a result, the setting / performance display 97 in this case displays the value representing the current set value Ve and the DP.

In step S708 following step S707, the CPU 20a determines whether or not the setting key is OFF (the setting key switch 94 is OFF), that is, whether or not the end instruction operation of the setting confirmation display is performed, and the setting key must be OFF. If so, the output management process of step S707 is executed again. As a result, after the setting confirmation command is transmitted in step S705, the process of step S708 waits until the end instruction operation of the setting confirmation display is performed, and during the standby, the setting / performance is set and performed by the process of step S707. The process of displaying the current set values Ve and DP on the display 97 is continuously performed.

When it is determined in step S708 that the setting key is OFF, the CPU 20a executes the acquisition process of the setting confirmation end command (BA67H) in step S709, and issues the setting confirmation end command to the effect control unit 24 by the command transmission process of the subsequent step S710. The transmission is performed, and the setting confirmation process in step S109 is completed.

(Main loop pre-processing)

FIG. 17 is a flowchart of the main loop preprocessing in step S119.
In the main loop pre-processing, the CPU 20a first executes the initialization command acquisition process in step S801, and then transmits the initialization command to the effect control unit 24 by the command transmission process in step S802. The initialization command is a command for instructing the initialization (returning to the origin) of the movable body accessory motor 80c that operates the movable body as a accessory.

In step S803 following step S802, the CPU 20a performs a process of acquiring transmission command data from the acquired lower byte command, and transmits the acquired command data to the effect control unit 24 by the command transmission process of step S804.
Here, in the acquisition process of step S803, the data of the command in which the lower byte data is stored in the register is acquired in the process of the process that has passed after the startup. Specifically, when passing through the RAM clear process in step S116 (when both the setting change process and the RAM clear process are performed, or when the setting change process is not performed and only the RAM clear process is performed), The data of the RAM clear command (BA02H) is acquired. On the other hand, when the backup restoration process of step S111 is performed (when both the setting confirmation process and the backup restoration process are performed, or when the setting confirmation process is not performed and only the backup restoration process is performed), the power failure is restored. The data of the display command (OB03H) is acquired.
As a result, the effect control unit 24 is configured to execute different processes when the RAM clear process is performed and when the backup return process is performed.

In step S805 following step S804, the CPU 20a executes a process for transmitting the reserved number of special figures 1 and 2. Here, in the process of step S805, when the backup restoration process of step S111 is performed, the reserved numbers of special figures 1 and 2 are transmitted to the effect control unit 24, and the RAM clear process of step S116 is performed. In that case, the pending quantity is not transmitted (because the information on the reserved quantity is cleared).

The processes of steps S806 to S808 following step S805 are processes for notifying the effect control unit 24 of the current set value Ve by the set value command.
First, in step S806, the CPU 20a performs a process of acquiring the set value Vd stored in the work area of the RAM 20c as a process for acquiring the current set value information, and in the following step S807, the set value offset conversion table ( The process of acquiring the set value data from FIG. 16) is executed. Specifically, the identification data of the set value Ve (“1”, “2”, “5”) corresponding to the set value Vd (00H to 02H) acquired in step S806 is acquired.
Then, the CPU 20a performs the acquisition process of the set value command (F6xxH) in the following step S808, and transmits the set value command to the effect control unit 24 by the command transmission process of step S809.
In the acquisition process of step S808, the set value command including the identification data acquired in step S807 is acquired. By such a setting value command, the current setting value Ve can be notified to the effect control unit 24.

In response to the command transmission process of step S809, the CPU 20a executes the internal function register setting process, that is, the register setting process for initial setting of various functions such as the hardware random number counting function in step S810, and steps. In S811, the process of setting the performance display monitor lighting timer to 5s is executed. The performance display monitor lighting timer is a timer for managing the operation time of the operation confirmation lighting operation (blinking operation for 5 seconds in this example) at the time of starting the setting / performance indicator 97.

Further, in step S812 following step S811, the CPU 20a resets the system operation status to "0", and in step S813, turns on the launch permission signal for the payout control board 29. In response to this, the payout control board 29 determines that the launch is permitted, outputs the permission signal to the launch control board 28, and allows the launching device 32 to launch the game ball. As a result, the game ball can be launched by the launch operation handle 15.
Here, the configuration in which the payout control board 29 receives the launch permission signal from the main control unit 20 and allows the launch operation, that is, the launch permission instruction information from the main control unit 20 is indirectly transmitted through the payout control board 29. However, the present invention is not limited to this, and for example, a configuration in which a launch permission signal by the main control unit 20 is directly output to the launch control board 28 may be used. ..
The CPU 20a ends the main loop pre-processing in step S119 in response to the execution of the processing in step S813.

(Advantages of data table for setting value display and setting value conversion table)

Here, in the present embodiment, like the set value offset conversion table shown in FIG. 16, the ROM 20b of the main control unit 20 contains a data table including a plurality of set value related information selected by referring to the set value. Is stored.
Then, in this data table, the set value related information selected when the main control unit 20 refers to the set value Vd (“00H” to “02H”) that can be set by the setting change process (see FIG. 10). A certain first set value related information and a second set value related information which is the set value related information selected when the main control unit 20 refers to a set value that cannot be set by the setting change process are included. Specifically, as the first set value related information, "00", "01", and "05" stored in the addresses "6215", "6216", and "6217" in the set value offset conversion table shown in FIG. 16 correspond to each other. As the second set value related information, "00", "00", and "00" stored in the addresses "6218", "6219", and "6220", respectively, correspond to each other.
Further, in the data table, as the first set value related information, at least specific information regarding the set value Ve representing the stage with the lowest winning probability (that is, "00" in the address "6215") is stored, and the second setting is made. The same information as the specific information is stored as the value-related information.

When the set value Vd is a value that cannot be set, it is conceivable to rewrite the set value Vd stored in the RAM 20c to a value representing the lowest stage.
However, if the data is tampered with after rewriting, the corresponding information may be acquired from the data table based on the unsettable setting value Vd, and the operation according to the unsettable setting value may be realized.
According to the above configuration, since it is impossible to acquire information according to the set value Vd that cannot be set from the data table, it is possible to prevent fraudulent acts from being established, and the fairness of the game. Can be enhanced.

Further, in the present embodiment, 0 is stored as the above-mentioned specific information.
As a result, it is possible to prevent the establishment of fraudulent acts by falsifying the set value by a simple method of writing the specific information = 0 in the set value related information. That is, the fairness of the game can be enhanced by a simple method.

Further, in the present embodiment, the 7-segment decoding table shown in FIG. 12 is also set value-related information selected when the main control unit 20 refers to the set value Vd that can be set by the setting change process. Second setting value related information which is the setting value related information selected when the setting value related information (addresses "6203" to "6205") and the setting value which cannot be set by the main control unit 20 are referred to by the setting change process. (Addresses "6206" to "6208") are included. Then, in the 7-segment decoding table, 0 is stored as the information related to the second set value.
As a result, even if the data table is referred to by the set value Vd that cannot be set in the setting change process due to fraudulent activity or some malfunction, it is set in the set value display means (setting / performance indicator 97 in this example). It is possible to prevent the value display from being performed. Specifically, in this example, since the data of "00", that is, "00000000000" is acquired as the display data, all the segments "0" to "6" in the 7-segment display for setting value display are hidden. As a result, the numerical display is not performed.
Therefore, it is possible to prevent erroneous display of the set value.

[4-2. Main control side timer interrupt processing]

The timer interrupt processing on the main control side will be described with reference to the flowchart of FIG.
The main control side timer interrupt process is started by an interrupt from the CTC at regular time intervals (about 4 ms), and is interrupted and executed during the execution of the main control side main process.

In FIG. 18, when a timer interrupt occurs, the CPU 20a first executes the power supply check / backup process in step S901. In this power check / backup process, the power level supplied from the power supply board is mainly monitored, and if an abnormality such as a power failure occurs, the game can be restored without any trouble when the power is restored. A backup process or the like for storing predetermined game information at the time in the RAM 20c is performed.

(Power check / backup process)

FIG. 19 is a flowchart showing the power supply check / backup process in step S901.
In the power supply check / backup process, the CPU 20a reads the power supply abnormality signal output from the power supply board twice in step S1001, and determines whether or not both read values match in the subsequent step S1002. If both values do not match, the process returns to step S1001 and the power supply abnormality signal is read twice again.

If both values match in step S1002, the CPU 20a determines in step S1003 whether or not the power supply abnormality signal is at a normal level (the power supply abnormality signal is OFF = normal level, ON = not normal level).
If the power supply abnormality signal is at a normal level (step S1003: OFF), the CPU 20a turns off the backup flag in step S1004, clears the power supply abnormality confirmation counter in the following step S1005, and ends the power supply abnormality check process in step S901. That is, when it is confirmed that the power supply abnormality signal is at a normal level, the backup processing described below is not performed and the timer interrupt processing is continued.

On the other hand, when the power supply abnormality signal is not at the normal level in step S1003 (step S1003: ON), the CPU 20a increments the value of the power supply abnormality confirmation counter by 1 in step S1006, and then the value of the power supply abnormality confirmation counter is changed in step S1007. It is determined whether or not it is equal to or more than a predetermined threshold value (threshold value = natural number of 2 or more: for example, “2”).
If the value of the power supply abnormality confirmation counter is not equal to or higher than the threshold value, the CPU 20a ends the power supply abnormality check process in step S901. That is, if a state in which the power supply abnormality signal is not at a normal level is detected but is not continuous detection, the backup process is not performed and the timer interrupt process is continued.

On the other hand, if the value of the power supply abnormality confirmation counter is equal to or greater than the threshold value, the CPU 20a performs the backup process shown in steps S1008 to S1011.
Specifically, the CPU 20a first clears the value of the power supply abnormality confirmation counter (S1108), turns off the launch permission signal (S1009), and then turns on the backup flag (S1010).
Further, the CPU 20a transmits a power off command to the effect control unit 24 (S1011), and proceeds to the process in step S1012.

In step S1012, the CPU 20a performs a process of enabling RAM protection and invalidating the prohibited area.
The RAM protect is a rewrite prevention function for the RAM 20c due to a malfunction or erroneous operation. By enabling RAM protection, only data can be read from the RAM 20c, and data cannot be written.
Further, the prohibited area is an area corresponding to the designated area in the IAT (prohibition of traveling outside the designated area) function, and by setting the prohibited area to invalid, the IAT reset will not occur thereafter.

In step S1013 following step S1012, the CPU 20a clears the value of the output port, stops the timer interrupt processing in the subsequent step S1014, sets itself to the interrupt disabled state, and shifts to the infinite loop processing.
In this infinite loop, the CPU 20a is reset by the WDT, and shifts to the operation stop state due to the loss of the operating power supply.

The description returns to FIG.
In FIG. 18, when the power check / backup process in step S901 is completed, the CPU 20a executes the input data creation process in step S902. Specifically, input data is created from various sensors and switches based on input information (ON / OFF signal and rising state (ON edge, OFF edge)).
The input information here is, for example, from a winning detection switch such as an upper starting port sensor 34a, a lower starting port sensor 35a, a normal symbol starting port sensor 37a, a large winning port sensor 52a, a general winning port sensor 43a, and an OUT monitoring switch 49a. ON / OFF information of the output switch signal (winning detection information) and ON / OFF information of the switch signal output from the switch related to the setting operation of the set value Ve such as the setting key switch 94 and the RAM clear switch 98 (operation). Information), a status signal from the payout control board 29 (ON / OFF information of the front door opening sensor 61 and the fullness detection sensor 60), and the like. As a result, whether or not a game ball is detected at the out opening or each winning opening is monitored for each interrupt.

After completing the input data creation process in step S902, the CPU 20a executes a timer management process for managing the timer used for the game operation control in step S903. Here, the values of various timers used for controlling the game operation of the game machine 1 are updated (subtracted).

Next, the CPU 20a performs an input management process in step S904. In this input management process, the values of the winning counter, the OUT ball monitoring counter, and the like are updated based on the input data created in the input data creation process (S902). The "winning counter" is a counter provided for each winning opening and counting the number of winning game balls (number of winning balls). The OUT ball monitoring counter is a counter that counts game balls (out balls) discharged from the out port 49.
The input management process of step S904 functions as an input management means for managing input signals (detection signals) from various winning opening sensors.

In step S905 following step S904, the CPU 20a executes a setting abnormality check process.

FIG. 20 is a flowchart showing the setting abnormality check process in step S905.
In FIG. 20, the CPU 20a confirms the set value error flag in step S1101. The set value error flag is a flag that is set (turned on) by the process of step S1103 described below when an abnormality of the set value Vd is recognized, and in this example, "5AH" means an ON state. ..

If the set value error flag is "5AH" (ON state) in step S1101, the CPU 20a ends the setting abnormality check process in step S905. That is, the fact that the set value error flag is determined to be ON in step S1101 means that the set value error command (command for instructing the effect control unit 24 to execute the set error notification) is already executed in step S1104 described later. Therefore, the setting error check process is completed without sending the setting value error flag again.

On the other hand, when it is confirmed in step S1101 that the set value error flag is not "5AH" (OFF), the CPU 20a determines in step S1102 whether the set value Vd is within the normal range (within the range of 0 to 2). Judge whether or not. Specifically, the set value Vd stored in the work area of the RAM 20c is acquired, and it is determined whether or not the value is in the range of "00H" to "02H".

If the set value Vd is within the normal range, the CPU 20a ends the setting abnormality check process in step S905.
If the set value Vd is not within the normal range, the CPU 20a proceeds to step S1103 to set the set value error flag (ON state), and in the following step S1104, a setting for indicating that an abnormality has occurred in the set value Vd. A value abnormality command is transmitted to the effect control unit 24, and the setting abnormality check process is completed.
Here, the set value error flag includes step S1308 (setting error determination at the time of winning) of FIG. 25, which will be described later, and step S1501 (setting error determination at the time of jackpot random number determination at the start of fluctuation) in FIG. 27. It is used in step S1701 (determination of setting error when performing fluctuation pattern lottery at the start of fluctuation) in FIG. 30.

Here, in response to the above-mentioned set value abnormality command, the effect control unit 24 performs a process for notifying the data abnormality of the set value Ve. For example, the liquid crystal display device 36 is subjected to a process of displaying an image including a display such as "RAM is abnormal. Please call a staff member."
In the game machine 1, a setting error (setting value error) can be canceled by performing a setting change operation.

The description returns to FIG.
When the CPU 20a finishes the setting abnormality check process in step S905, the CPU 20a executes the error management process in step S906. In this error management process, the presence or absence of an error is monitored based on the input data related to various sensors and the status signal from the payout control board 29.
When an error occurs, the CPU 20a transmits the error command to the effect control unit 24 as an error process if the error type requires the transmission of an error command. When the effect control unit 24 receives this error command, it executes error notification according to the error type. Further, when the error being generated is resolved, the CPU 20a transmits an error canceling command to the effect control unit 24. When the effect control unit 24 receives this error release command, the executing error notification is terminated.

Next, in step S907, the CPU 20a executes a random number management process in the timer interrupt that periodically updates the random numbers related to each variation display game. Here, in order to make the count value of the random number counter random, the random number is updated (+1 is added for each interrupt) for the special symbol judgment random number and the auxiliary hit judgment random number, and each time the random number counter goes around. In addition, the process of changing the start value of the random number counter is performed. Since the internal lottery random number (big hit determination random number) is generated by the random number generation circuit, it is not updated here.

In step S908 following step S907, the CPU 20a executes the prize ball management process. In this prize ball management process, the above-mentioned winning counter is confirmed, and if there is a winning, a payout control command for specifying the number of prize balls is transmitted to the payout control board 29. When the payout control board 29 receives the payout control command, the payout control board 29 controls the game ball payout device 19 based on the prize ball number information included in the payout control command, and executes the payout operation for the designated number of prize balls.

Next, the CPU 20a executes the normal symbol management process in step S909. In this normal symbol management process, processing necessary for executing the normal symbol variation display game is performed. Here, whether or not a game ball is detected by the normal symbol start port sensor 37a is monitored, and if the game ball is detected, predetermined game information (random number for determining auxiliary hit, etc.) required for the auxiliary hit lottery is input. Acquire (random number acquisition process), and store the game information as hold data (operation hold ball related to a normal symbol) up to the maximum number of hold balls (hold storage process). Then, when a predetermined variation display start condition for the normal symbol is satisfied, a lottery for the auxiliary hit based on the operation holding ball is performed, the variation pattern of the normal symbol is selected based on the lottery result for the auxiliary hit, and the stop display mode of the normal symbol (normal). Stop symbol) is decided. Further, here, in order to operate the normal symbol in a variable display operation, the LED display data for the variable display is created if it is changing, and the LED display data for the stop display is created if it is not changing.

Further, the CPU 20a executes the normal electric accessory management process in step S910. In this ordinary electric accessory management process, the process necessary for executing the normal electric accessory management process is performed. Specifically, when the lottery result of the auxiliary hit lottery is a win, the solenoid control data setting process for the ordinary electric accessory solenoid 41c is performed. Based on the solenoid control data set here, an excitation signal is output to the ordinary electric accessory solenoid 41c, whereby the opening / closing operation pattern of the movable wing piece 47 is controlled.

Next, the CPU 20a executes a special symbol management process in step S911. In this special symbol management process, a big hit lottery is mainly performed in the special symbol fluctuation display game, and based on the lottery result, the fluctuation pattern of the special symbol (look-ahead fluctuation pattern and the fluctuation pattern at the start of fluctuation) and the special stop symbol are performed. The processing required for the special symbol variation display game, such as the determination of, is executed.

Next, the CPU 20a executes the special electric accessory management process in step S912. In this special electric accessory management process, setting processing necessary for executing and controlling the winning game is performed. Specifically, when the big hit lottery result is a big hit, the hit game (big hit game) corresponding to the hit type is executed and controlled.
Specifically, the solenoid control data is set for the large winning opening solenoid 52c, the number of rounds is counted (in the case of a big hit), the maximum number of winnings to the large winning opening 50 and the opening time are monitored. When the winning game is completed, the transition setting of the game state based on the game state at the time of winning and the winning type is performed.

Further, here, a plurality of effect control commands are transmitted according to the progress of the winning game. At the start of the jackpot, the start of the round game, the end of the round game, the end of the maximum number of rounds, etc., it is time to send the jackpot start command, round start command, round end command, jackpot winning command, and jackpot end command, respectively. Send according to. The jackpot start command includes the hit type information this time, and is used when the effect control unit 24 side determines a series of hit effect scenarios developed during the hit game. In addition, the jackpot end command includes information on the current hit type and the game state at the time of winning the hit, that is, information capable of specifying the game state after the hit game ends, and the effect control unit 24 side hits. It is used when determining the production mode after the game. Therefore, since this "big hit end command" can specify the game state after the end of the hit game, it plays a role as a game state designation command for designating the game state.

When the process for proceeding with the game up to step S912 is completed, the CPU 20a performs the external terminal management process in step S913. In this external terminal management process, the operating state information of the game machine 1 is output to an external device such as a hall computer HC or an island lamp through the frame external centralized terminal board 21. The operation state information includes, for example, game information such as hit game occurrence information, symbol variation display game execution start information, prize number / prize ball number information, and error information.

Next, the CPU 20a executes the LED management process in step S914. In this LED management process, the output of control signals (dynamic lighting data) is controlled for LED indicators such as the normal symbol display device 39a, the special symbol display devices 38a and 38b, and the setting / performance indicator 97. The control signal based on the display data created by the normal symbol management process (step S909), the special symbol management process (step S911), etc. is output to the corresponding display device or display in this LED management process, and the display control is performed. Will be done. As a result, a series of variable display operations (variable display and stop display) of the special symbol on the special symbol display devices 38a and 38b and the normal symbol on the normal symbol display device 39a are realized.

In step S915 following step S914, the CPU 20a saves the values of all the registers and then performs the performance display monitor display process in step S916. That is, it is a process for displaying the value as the above-mentioned normal time ratio information on the setting / performance display 97.
As mentioned earlier, in the case of this example, the value of the normal time ratio information is recalculated every time the number of out-balls in all states reaches a predetermined specified value, and the setting / performance indicator 97 is the current normal value. It is possible to display the time ratio information and the previous normal time ratio information (normal time ratio information whose calculation is completed at the latest recalculation timing). Therefore, in the display process of step S916 in this case, a process of displaying the values as the normal time ratio information of these two types on the setting / performance indicator 97 is performed.
The current value of the normal time ratio information is a value calculated in the process of step S604 in the above-mentioned main loop process (FIG. 11), and the value of the previous normal time ratio information is stored in a predetermined area of the RAM 20c. Then, the CPU 20a reads out the stored value and displays it on the setting / performance display 97.

Next, the CPU 20a restores the values of all the registers in step S917, clears the WDT count value in step S918, and ends the main control side timer interrupt process.

When the above timer interrupt processing is completed, the CPU 20a executes the main loop processing (S123) until the next timer interrupt is generated.

<5. About processing transition between intra-area processing and out-of-area processing>
[5-1. About used area and non-used area]

FIG. 21 is an explanatory diagram of an area (memory area) set in the memory in the main control unit 20. Specifically, it is explanatory drawing about the area set in the memory accessible by CPU 20a as ROM 20b and RAM 20c.

A first memory area (hatched portion in the figure) and a second memory area (pear-skinned portion in the figure) are set in the memory accessible by the CPU 20a. The first memory area is defined as an area for arranging a predetermined program and data used by the CPU 80a in the progress of the game operation (game). The second memory area is defined as an area for arranging programs and data permitted to be arranged outside the first memory area.
In this example, the programs and data related to the management and display of the performance information described above are permitted to be allocated to the second memory area. Specifically, the program and data related to the performance display monitor aggregation division processing (S304) in the main loop processing (S120) shown in FIG. 9 and the performance display monitor display processing in the main control side timer interrupt processing shown in FIG. The program and data related to (S916).

Here, the first memory area is called a "used area" in the sense that it is an area that can be used in the game progress process. On the other hand, the second memory area is called an area "outside the used area" in the sense that it is an area that can be used in a specific process other than the game progress process.
Hereinafter, the area "outside the used area" as the second memory area may be referred to as "outside area". Further, in the following description, the terms "inside the area" and "outside the area" mean "inside the used area" and "outside the used area", respectively, unless otherwise specified.

As shown in the figure, each of the first memory area and the second memory area includes a control area for storing a program, a data area for storing data used by the program, and various types generated in the process of processing by the program. The R / W area (Read / Write area) for rewritably storing the flag and timer value of is set. The control area and the data area correspond to the area in the ROM 20b, and the R / W area corresponds to the area in the RAM 20c.

FIG. 22 is an explanatory diagram of regulations defined for the first memory area and the second memory area.
In each of the first and second memory areas, the program in the control area is permitted to refer to and update (record) the data in the R / W area in its own area. On the other hand, in each of the first and second memory areas, the program in the control area is permitted only to refer to the data in the R / W area in the other memory area, and is not permitted to update. For example, regarding the flag recorded in the R / W area in the second memory area by the program in the second memory area, the program in the first memory area can only refer to it and cannot update it. ..
Although not shown, only programs in the same memory area are allowed to refer to the data in the data area. That is, the program in the first memory area refers to the data in the data area in the second memory area, and the program in the second memory area refers to the data in the data area in the first memory area. Is not allowed.

[5-2. Processing migration method in the preceding example]

Here, in the process in which the CPU 20a executes the processes described with reference to FIGS. 5 to 20, the processing of the out-of-area program is called (CALLed) while the processing of the in-area program is being executed, and the out-of-area program is executed. There is a processing process of returning to the processing of the program in the area according to the completion of the processing of. That is, there is a processing transition between within and outside the region. As a specific example of such a process transition, in the main loop process (S120) shown in FIG. 9, the random number update process (process of the program in the region) in step S302 is performed, and then the performance display monitor aggregation division process (process in step S304) is performed. After executing the processing of the program outside the region), the processing process of transitioning to the random number update processing of step S302 again can be mentioned.

Here, first, a method as a prior example will be described with respect to the method of processing transition between the inside and outside of the area as described above.
FIG. 23 is a diagram showing a register configuration of the CPU 20a in the preceding example.
As shown in the figure, the CPU 20a in the preceding example includes a PC (program counter) register 100, an I (interrupt) register 101, and an R (refresh) register 102, and a front register 103 and a back register 104, each of which is composed of a plurality of registers. It has.
The table register 103 includes a Q register 105, an A (accumulator) register 106, an F (flag) register 107, a B register 108, a C register 109, a D register 110, an E register 111, an H register 112, an L register 113, and an IX register 114. , IY register 115, and SP (stack pointer) register 116.
The back register 104 includes a Q'register 105', an A'register 106', an F'register 107', a B'register 108', a C'register 109', a D'register 110', an E'register 111', and an H'register. It has 112', L'register 113', IX'register 114', and IY'register 115'.
Of these various registers, at least B register 108 to L register 113 and B'register 108'to L'register 113'are general-purpose registers.

With reference to FIGS. 24 and 25, an example of a program related to processing transition between the inside and outside of the area will be described.
FIG. 24 exemplifies a program of a portion mainly corresponding to the main loop processing (particularly interrupt waiting portion: see FIG. 9) in step S120 in the main control side main processing (FIG. 5), and FIG. 25 shows an area. An example of a program related to the performance display monitor aggregation division processing (S304) as an external program.

For confirmation, the main instructions among the various instructions used in the program will be explained. The instruction here refers to a mnemonic instruction in assembly language.
"DI" is an interrupt-disabled instruction, and "EI" is an interrupt-enabled instruction.
"PUSH" is an instruction to stack (save) the value of the specified register in the stack area of the memory (RAM 20c), and "POP" is an instruction to retrieve (write) the value of the stack area to the specified register.
"LD" is a load instruction, and is an instruction to write the value of the place specified on the right side with respect to the place specified on the left side after the description of "LD". For example, the description of "LD R, n" (where R means a value that specifies a register and n means a value that specifies an address in memory) is specified by n for the register specified by R. It is an instruction to write the value of the address in the memory. The description of "LD n, R" is an instruction to write the value of the register specified by R to the address on the memory specified by n.
"CALL" is an instruction to call a program, and "RET" is an instruction to return processing to the caller.

A program for interrupt wait processing in the main loop processing (S120) is shown in the lower part of FIG. 24 (“ZANYO_1” in the figure). As can be seen with reference to FIG. 9, in the main loop processing, the random number update processing (step S302) and the performance display monitor aggregation division processing are executed while waiting for the interrupt.
First, in the interrupt waiting process, the interrupt is disabled by the DI instruction. The reason for disabling interrupts here is to prevent interrupt processing from being executed during the random number update processing executed by the next instruction. It also has a meaning to prevent interrupt processing from being executed during execution of a program outside the region, which will be described later. If the interrupt processing program as the in-area program is executed while the out-of-area program is being executed, the interrupt processing program accesses the work memory in the used area and updates the memory. That is, interrupt processing is prohibited because the inside of the area is updated during the execution of the program outside the area.

Next, the command "CALL M_RNDJOB" calls and executes various random number update processes.

The values of the A register 106 and the F register 107 are saved in the memory by the instruction of "PUSH AF" following the instruction of "CALL M_RNDJOB". The reason for executing the instruction is that it is necessary to save the contents of the F register 107 because the contents of the F register 107 change when "LD SP, n" is executed in the out-of-area program described later.

The "CALL _SHKSHM" command following the above "PUSH AF" calls the performance display monitor aggregation division processing outside the area.

As shown in FIG. 25, in the performance display monitor aggregation division processing, first, a stack pointer that specifies an address outside the used area is set by the instruction of "LD SP, _ESTPNT". Then, all the registers of the B register 108 to the L register 113 are saved by the instructions of "LD (_RBCBUF), BC", "LD (_RDEBUF), DE", and "LD (_RHLBUF), HL" in the figure.
Various instructions after "LD (_RHLBUF), HL" perform processing to calculate the value as performance information.

In the figure, the processing of returning all registers is performed by each instruction of "LD BC, (_RBCBUF)", "LD DE, (_RDEBUF)", and "LD HL, (_RHLBUF)" from the 2nd line to the 4th line before the last line. This is done, and the stack pointer is returned by the instruction "LD SP, _ISTPNT2" one line before the last line. Then, the processing is returned to the caller by the "RET" instruction on the last line. That is, it returns to the processing of the program in the area.

In response to the above "RET" instruction, the instruction "POP AF" after "CALL _SHKSHM" in FIG. 24 is executed. By this "POP AF", the values of the A register 106 and the F register 107 are restored.
Next, "EI" enables interrupt processing, and "JR ZANYO_1" returns the processing to the beginning of "ZANYO_1", and loop processing as interrupt waiting processing is realized.

Here, in the preceding example, since the SP (stack pointer) register 116 is one, the SP pointer 116 is shared by the in-domain program and the out-of-domain program. Therefore, it is necessary to perform "PUSH AF" and "POP AF" processing when transferring processing between the inside and outside of the area. That is, in the in-area program, when the out-of-area program is CALLed, it is necessary to always describe these "PUSH AF" and "POP AF" instructions.
As described above, the used area is defined as the area where the program related to the progress of the game operation is arranged. However, in recent years, the program capacity and the data capacity of the used area have been increasing due to the complexity of the game operation and the like. The area of use tends to be squeezed. Therefore, it is required to reduce the program capacity in the used area.

[5-3. Processing migration method as an embodiment]

FIG. 26 is a diagram showing a register configuration of the CPU 20a in the embodiment.
As shown in the figure, the CPU 20a of the embodiment includes a PC register 100, an I register 101, and an R register 102, as well as a first register bank 121, a second register bank 122, and an IFF (interrupt control flag) register 125. There is.
Here, the register bank is a register group including a plurality of registers including a general-purpose register. The first register bank 121 and the second register bank 122 each have a main register 123 and a sub register 124, and the main register 123 corresponds to the table register 103 shown in FIG. 23, and the Q register 105. , A register 106, F register 107, B register 108, C register 109, D register 110, E register 111, H register 112, L register 113, IX register 114, IY register 115, and SP register 116. ..
The sub-register 124 corresponds to the back register 104 shown in FIG. 23, and has Q'register 105', A'register 106', F'register 107', B'register 108', C'register 109', It has a D'register 110', an E'register 111', an H'register 112', an L'register 113', an IX'register 114', and an IY'register 115'.
The main register 123 has a U register 130, and the U register 130 will be described later.

The IFF register 125 is a register for storing the interrupt control flag IFF. The interrupt control flag IFF is a flag for managing the enable / disable state of interrupt processing, that is, the interrupt control state. In this example, two types of interrupt control flags IFF are handled, "IFF1" and "IFF2". Corresponding to this, the interrupt control flags IFF1 and IFF2 can be individually stored in the IFF register 125.
Here, among the interrupt control flags IFF1 and IFF2, only the IFF1 side is used as the reference value of the interrupt control state, and IFF2 is auxiliary used to manage the value of IFF1.

In the present embodiment, as shown in FIG. 26, the first register bank 121 and the second register bank 122 are provided, the first register bank 121 is used by the in-region program, and the second register bank 122 is out of the region. Used by the program. That is, when shifting from the processing of the in-region program to the processing of the out-of-region program, the register bank to be used is switched from the first register bank 121 to the second register bank 122. On the contrary, when shifting from the processing of the program outside the region to the processing of the program inside the region, the register bank to be used is switched from the second register bank 122 to the first register bank 121.

As described above, the first register bank 121 and the second register bank 122 are provided, and the first register bank 121 is used for the inside of the area and the second register bank 122 is used for the outside of the area. It becomes possible to use the dedicated SP register 116 with the external program, and it is not necessary to execute "PUSH AF" or "POP AF". Therefore, it is possible to reduce the program capacity of the program in the area.

Further, in the present embodiment, "CALLEX" and "RETEX" are adopted as instructions that can be substituted for "CALL" and "RET".
"CALLEX" is an instruction to call an out-of-area program from an in-area program. Specifically, an interrupt processing prohibition instruction (DI) and a register bank to be used are switched (first register bank 121 to second register bank 122). (Switch to) instruction and each instruction of the specified out-of-area program CALL instruction are aggregated as a single instruction.
"RETEX" is an instruction for returning from an out-of-area program to an in-area program. Specifically, an instruction for switching the register bank to be used (switching from the second register bank 122 to the first register bank 121), It is a collection of each instruction of the process execution instruction to return the interrupt control state (permission / prohibition) to the state immediately before the execution of the CALLEX instruction and the RET instruction to return the processing to the caller as a single instruction.

Here, in order to enable the interrupt disabled state by "CALLEX" as described above and the interrupt control state to be returned to the state immediately before the execution of the CALLEX instruction by "RETEX", "CALLEX", "RETEX" and "RETEX" It is stipulated that the interrupt control flag IFF is updated as follows when "DI" and "EI" are executed.
FIG. 27 is an explanatory diagram of an update rule for the interrupt control flag IFF.
As shown in the figure, when the "DI" instruction is executed, both the interrupt control flags IFF1 and IFF2 are set to "0" (prohibited value) indicating interrupt prohibition. On the other hand, when the "EI" instruction is executed, both the interrupt control flags IFF1 and IFF2 are set to "1" (permission value) indicating interrupt permission.
Further, when the "CALLEX" instruction is executed, the interrupt control flag IFF1 is set to the prohibited value "0", and the value of the interrupt control flag IFF2 is maintained (that is, not changed). Further, when the "RETEX" instruction is executed, the value of the interrupt control flag IFF2 is assigned to the interrupt control flag IFF1. At this time, the value of the interrupt control flag IFF2 is maintained.

By updating the interrupt control flag IFF according to the above rules, the interrupt disabled state is realized by executing the "CALLEX" instruction, and the interrupt control state is immediately before the execution of the CALLEX instruction by executing the "RETEX" instruction. Will be returned to the state of.

28 and 29 exemplify a program as an embodiment in which "CALLEX" and "RETEX" are applied to the program related to the process transition between the inside and outside of the region illustrated in FIGS. 24 and 25.
In addition, in FIGS. 28 and 29, among the various instructions shown in FIGS. 24 and 25, the instructions omitted due to the application of the method as the embodiment are grayed out.

As described above, by providing the first register bank 121 and the second register bank 122, the “PUSH AF” required when calling the out-of-area program in the in-region program and the return from the out-of-region program are provided. The "POP AF" that was sometimes needed is no longer necessary.
As a result, it is possible to reduce the program capacity of the program in the area.

Here, since "CALLEX" includes the "DI" instruction, the reduction effect of the "DI" instruction (the effect of reducing the program capacity) may be obtained in some cases. In the example of FIG. 24, since the random number update process is performed before calling the out-of-area program, the “DI” instruction is executed before the random number update process, and the out-of-area program is called while the interrupt is disabled. Is done. In such a case, it is not necessary to execute the "DI" instruction in order to call the program outside the region. Therefore, the effect of reducing the "DI" instruction by applying "CALLEX" cannot be obtained. However, a program configuration that calls an out-of-area program may be adopted in the interrupt enabled state. In such a case, since the "DI" instruction is executed before the "CALL" calls the out-of-area program, the application of "CALLEX" can reduce the "DI" instruction, and the program can be reduced. The capacity reduction effect can be obtained.

In the embodiment, the provision of the second register bank 122 for outside the region eliminates the need to save or restore the register value when the program in the region shifts to the program outside the region. Therefore, in the out-of-area program (Fig. 29), each instruction of "LD (_RBCBUF), BC", "LD (_RDEBUF), DE", "LD (_RHLBUF), HL" for saving the register value, and Each instruction of "LD BC, (_RBCBUF)" "LD DE, (_RDEBUF)" "LD HL, (_RHLBUF)" to restore the saved value, and to restore the value of the stack pointer in the area. There is no need to write the instruction of "LD SP, _ISTPNT2".

Here, as will be understood with reference to the program illustrated in FIG. 28, in the present embodiment, after executing the "DI" instruction in the intra-regional program, before executing the "EI" instruction, The "CALLEX" command is being executed. This means that if the "EI" instruction is the "first instruction", the "DI" instruction is the "second instruction", and the "CALLEX" instruction is the "third instruction", the first instruction is executed after the second instruction is executed. In other words, the third instruction is executed before it is executed.

When executing a program outside the area, it is necessary to put it in the interrupt disabled state. Based on this premise, if the EI (first instruction) is executed before the CALLEX (third instruction) is executed, the interrupt disabled state and the interrupt enabled state are frequently switched.
Specifically, when performing EI before CALLEX, the first DI in the loop processing is in the interrupt disabled state → random number update processing is executed → EI is in the interrupt enabled state → CALLEX is in the interrupt disabled state → RETEX is in the interrupt enabled state. .. That is, the number of switchings in the main loop processing = 3 times. On the other hand, in the case of the embodiment in which EI is performed after CALLEX, the interrupt disabled state is continuously maintained from the first DI to the execution of the out-of-area program → the return to the in-area program, and then the EI switches to the interrupt enabled state. .. That is, the number of switchings in the main loop processing = 1.
Therefore, when EI is performed before CALLEX, the control state is frequently switched and the stability of control is impaired. However, according to the embodiment in which EI is performed after CALLEX, the number of times the control state is switched is suppressed. It is possible to improve the stability of control.

Further, according to the migration method as the above-described embodiment, the processing of PUSH and POP becomes unnecessary, so that the processing speed can be improved.

30 and 31 exemplify a program in which CALLEX and RETEX are applied to the call of the program outside the region in the main control side timer interrupt processing shown in FIG. 18, and FIG. 30 shows the main control side timer interrupt processing. An example of a program (in-area program) is illustrated, and FIG. 31 illustrates a program (out-of-area program) corresponding to the performance display monitor display process in step S916.
In FIG. 30, for convenience of illustration, the instruction corresponding to the WDT clear process in step S918 is not shown. Further, in each of the drawings up to FIG. 63 illustrated below, including those in FIGS. 30 and 31, the instructions omitted due to the application of CALLEX and RETEX are grayed out and shown as in FIGS. 28 and 29 above. ing.

In FIG. 30, when the CALL instruction is adopted instead of CALLEX for calling the performance display monitor display process which is an out-of-area program (that is, when the register configuration of FIG. 23 is adopted), the necessary instruction is “PUSH AF” →. "DI"-> "CALL _SHYMT"-> "POP AF"-> "EI"-> "RETI", but when CALLEX is adopted (when the register configuration shown in Fig. 26 is adopted), the required instruction is "CALLEX _SHYMT". ”→“ EI ”→“ RETI ”, and by reducing the instructions for“ PUSH AF ”,“ DI ”and“ POP AF ”, the program capacity for programs in the area can be reduced.

Further, in the performance display monitor display processing program shown in FIG. 31, first, a stack pointer that specifies an address outside the used area is set by the instruction of "LD SP, _ESTPNT". In the case of the precedent example that adopts CALL or RET, "LD (_RBCBUF), BC""LD (_RDEBUF), DE""LD(" to save the register value as an instruction after "LD SP, _ESTPNT". Each instruction of "_RHLBUF), HL" was required, but these instructions are omitted in this embodiment.
In the figure, each instruction from "initial determination of RWM" to "initial display timer subtraction process" is an instruction for realizing a process of displaying a value of performance information on the setting / performance indicator 97. After these instructions, in the preceding example, the "LD BC, (_RBCBUF)", "LD DE, (_RDEBUF)", "LD HL, (_RHLBUF)" instructions for returning the saved value to the register, and Although the "LD SP, _ISTPNT2" instruction for returning the stack pointer in the area was required, these instructions are also omitted in the present embodiment.
By "RETEX" on the last line, switching from the second register bank 122 of the register bank to be used to the first register bank 121, returning the interrupt control state (maintaining the prohibited state in this case), and processing to the caller are performed. A return is made.

The "EI" instruction one line before the last line in FIG. 30 is not essential. If the interrupt control state immediately before the execution of the CALLEX instruction in FIG. 30 is the "interrupt enable state", the interrupt control state when returning to the in-region program by executing the RETEX instruction shown in FIG. 31 is the "interrupt enable state". This is to become.

Here, in FIGS. 29 and 31, the instruction “LD SP, _ESTPNT” is executed in the first line of the out-of-area program, that is, the SP register 116 in the second register bank 122 is used in the out-of-area program. The process of storing the address value of the stack memory (the stored value of "ESTPNT" in the memory) is to be executed. This can be rephrased as follows. That is, when calling by specifying the first address of the program outside the area by the "CALLEX" instruction in the program inside the area ("CALLEX _SHKSHM" in FIG. 28) and when calling by specifying the second address ("CALLEX" in FIG. 30). _SHYMT "), and in the out-of-area program, the stack memory common to the SP register 116 of the second register bank 122 regardless of whether the first address is called or the second address is called. The instruction (fifth instruction) for storing the address information (stored value of "ESTPNT") is executed.

This makes it possible to reset the value of the stack pointer used in the out-of-area program each time the out-of-area program is called.
Therefore, even if the stored value of the second stack pointer changes due to some trouble after the execution of a certain out-of-area program, the correct stack pointer value is set when another out-of-area program is executed. It can be fixed and the stability of stack processing by the out-of-area program can be improved.

Since the value of the stack pointer that should be set at the start of processing of the out-of-area program is a fixed value as "ESTPNT", execute "LD SP, _ESTPNT" every time the processing of the out-of-area program starts. Is not required. Specifically, the "LD SP, _ESTPNT" command needs to be executed only when the out-of-area program is executed at least for the first time each time the game machine is started.
For example, if the out-of-area program of FIG. 29 is executed before the out-of-area program of FIG. 31, the instruction of "LD SP, _ESTPNT" needs to be executed only in the out-of-area program of FIG. 29. Alternatively, conversely, if the out-of-area program of FIG. 31 is executed before the out-of-area program of FIG. 29, "LD SP, _ESTPNT" need only be executed in the out-of-area program of FIG. ..
This can be rephrased as follows. That is, in the case of calling the out-of-area program by executing the CALLEX instruction in the in-area program, the case where the first address of the out-of-area program is specified and called (the out-of-area program in either FIG. 29 or FIG. 31 is called). In the case), there is a case where the second address is specified and called at a subsequent timing (when the other out-of-area program of FIG. 29 or FIG. 31 is called), and in the out-of-area program, the first address is Only when it is called, the instruction (sixth instruction) for storing the address information of the common stack memory in the second stack pointer is executed.

As described above, since the address information of the stack memory that should be set at the start of processing of the out-of-area program is fixed address information, the program of the second address is executed after the program of the first address as the out-of-area program. In this case, it is sufficient that the memory processing of the address information for the second stack pointer is performed only in the program of the first address executed first.
Therefore, the processing efficiency can be improved by executing the instruction to store the address information of the predetermined stack memory in the second stack pointer only when the first address is called as described above.

[5-4. Another example of the program]

32 and 33 show another example of the program shown in FIGS. 28 and 29 above. Specifically, another example of the program corresponding to the portion that calls the out-of-area program in the main loop processing (S120) (FIG. 32) and another example of the out-of-area program called by the processing of FIG. 32 (FIG. 33) are shown. Shown.

34 and 35 show another example of the program shown in FIGS. 30 and 31, that is, another example of the program for the main control side timer interrupt processing (FIG. 34) and the outside of the area called by the timer interrupt processing. Another example of the program (FIG. 35) is shown.

In the out-of-area program shown in FIGS. 33 and 35, the address on the memory for storing the value to be set in the second stack pointer (SP register 116 in the second register bank 122) is shown in FIGS. 29 and 31. It is defined as "@ RWM2SP" instead of "ESTPNT" in the case.
As can be seen by referring to the instructions of "LD SP, @ RWM2SP" in FIGS. 33 and 35, here, a common address as a stored value of "@ RWM2SP" is set in the second stack pointer for each execution of the out-of-area program. Although an example of setting information is given, in this case as well, it is possible to store the address information for the second stack pointer only in the out-of-area program that is executed first.

36 to 53 show an example of a program when the processing transition method as an embodiment is applied to the processing of the main control unit in the rotating cylinder type game machine (slot machine).
36, 38, 40, 42, 44, 46, 48, 50, and 52 are regions among the processes of the in-region program executed by the main control unit of the rotating cylinder type game machine. An example of a program of various processing including a call instruction of an external program is shown. Specifically, FIG. 36 shows the initial setting process when the power is turned on, FIG. 38 shows the game execution process, FIG. 40 shows the process according to the insertion of the game medal and the operation of the start lever, and FIG. 42 shows the RMW setting process at the start of the game. FIG. 44 illustrates a program for updating information related to the combination monitor display, FIG. 46 shows a setting change process, FIG. 48 shows a condition device signal output process, FIG. 50 shows a game medal insertion process, and FIG. 52 shows a program for a game medal insertion error process. ing.
37, 39, 41, 43, 45, 47, 49, 51, and 53 exemplify an out-of-area program called by the CALLEX instruction in the processing of the various in-area programs described above. Specifically, FIG. 37 shows an out-of-area work area process 3, FIG. 39 shows a replay state identification signal output process, FIG. 41 shows a condition device signal output clear process, FIG. 43 shows a condition device signal output process, and FIG. 45 shows. The role ratio monitor control process, FIG. 47 is an out-of-area work area process 1, FIG. 49 is a condition device signal output monitoring process, FIG. 51 is a retention check process, and FIG. 53 is an example of a program for an out-of-area work area process 2. ..

Regarding the in-region program illustrated here, for example, "(DI guarantee)" shown in FIGS. 36, 38, 40, etc. is an interrupt disabled state at least in the line in which the (DI guarantee) is described. It means that it is guaranteed (that is, it is guaranteed that the DI instruction is executed on any line before the line).

Among the in-region programs illustrated here, the in-region programs shown in FIGS. 38, 40, and 48 have the "CALLEX" instruction after executing the "DI" instruction and before executing the "EI" instruction. Corresponds to the example of executing.
As a result, it is possible to prevent the interrupt control state from being frequently switched, and it is possible to improve the stability of control.

In particular, in the program of FIG. 48, two CALLEX instructions are described in succession. In this case, if the "DI" instruction is executed and then the "EI" instruction is executed, "CALLEX" is executed. If the "EI" instruction is executed before the "CALLEX" instruction is executed instead of executing the "" instruction, the interrupt control state is switched 5 times. Specifically, DI → EI → CALLEX (switch to interrupt disabled state) → RETEX (return to interrupt enabled state) → CALLEX (switch to interrupt disabled state) → RETEX (return to interrupt enabled state) for a total of 6 times. .. On the other hand, when the method of executing the "CALLEX" instruction after executing the "DI" instruction and before executing the "EI" instruction as in the embodiment is adopted, the interrupt control state can be switched once. It can be suppressed and the stability of control can be improved.

As can be seen by referring to "LD SP, CMN_STACK" shown in the first line of each of FIGS. 37, 39, 41, 43, 45, 47, 49, 51, and 53. The storage address of the stack pointer (value to be set in the SP register 116 in the second register bank 122) for the unused area in the case is defined as "CMN_STACK".
Then, as can be understood from the fact that the instruction of "LD SP, CMN_STACK" is included in each figure such as FIG. 37, here, the address information common to the second stack pointer is input for each execution of the out-of-area program. An example of setting is given.

In the case of the rotating drum type game machine, there are three or more types of out-of-area programs called from the in-area programs. When there are three or more types of out-of-area programs to be called in this way, at least for the relationship between two of them, the storage process of the address information for the second stack pointer is performed only in the out-of-area program executed first. It is also possible to make it happen. At this time, in order to improve the efficiency of processing, it is desirable that the storage processing of the address information for the second stack pointer is executed only in the out-of-area program that is executed first among the three or more types of out-of-area programs. ..

[5-5. Program modification]

Subsequently, a modification of the program will be described with reference to FIGS. 54 to 63.
In the explanation so far, an example of including the register bank switching instruction used for CALLEX and RETEX has been given, but the register bank switching instruction can also be defined as an independent instruction. Here, an example in which the register bank switching instruction (mnemonic) is defined as "BANKF" is given, but the specific name of the switching instruction is not limited to "BANKF".

When using an independent register bank switching instruction as "BANKF", one "CALL" instruction, two "BANKF" instructions, and one "BANKF" instruction when transferring processing between the inside and outside of the area. The "RET" instruction will be used.
54, 56, 58, and 60 show various program examples that can be considered as application examples of the "BANKF" instruction to the initial setting process at power-on illustrated in FIG. 36 above. 55, 57, 59, and 61 show examples of an out-of-area program (out-of-area work area processing 3) called by the in-area program of FIGS. 54, 56, 58, and 60, respectively. ..

In the example shown in the set of FIGS. 54 and 55, the "BANKF" instruction for switching the register bank from the first register bank 121 for the inside of the region to the second register bank 122 for the outside of the region is executed on the out-of-region program side, and the region This is an example in which the “BANKF” instruction for switching from the second register bank 122 for external use to the first register bank 121 for internal use is executed on the program side in the area.
In the in-region program in this case, as shown in FIG. 54, the register bank is switched from the second register bank 122 to the first register bank 121 following the "CALL" instruction (CALL O_CLRWM3) for calling the target out-of-region program. The "BANKF" instruction for this is described. Further, in the out-of-area program in this case, as shown in FIG. 55, a "BANKF" instruction for switching the register bank from the first register bank 121 to the second register bank 122 is described in the first line, and "BANKF" instruction is described in the last line. The "RET" instruction is described.

Here, in the out-of-area program shown in FIG. 55, the instruction (set of the second stack pointer) of "LD SP, CMN_STACK" is described in the second line, but from the first register bank 121 on the out-of-area program side. When executing the "BANKF" instruction for switching to the second register bank 122, the "BANKF" instruction is executed before the execution of the "LD SP, CMN_STACK" instruction.

The example shown in the set of FIGS. 56 and 57 includes a "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 and a "BANKF" instruction for switching from the second register bank 122 to the first register bank 121. This is an example in which both instructions are executed on the intra-regional program side.
In the in-region program in this case, as shown in FIG. 56, the "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 is described in the line immediately before the "CALL" instruction, and "CALL". The "BANKF" instruction for switching from the second register bank 122 to the first register bank 121 is described on the next line of the instruction.

In the example shown by the set of FIGS. 58 and 59, the “BANKF” instruction for switching from the first register bank 121 to the second register bank 122 is executed on the intra-region program side, and the second register bank 122 to the first register bank 121 This is an example in which the "BANKF" instruction for switching to is executed on the out-of-area program side.
As shown in FIG. 58, in the in-region program in this case, the "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 is described in the line immediately before the "CALL" instruction, and the out-of-area program Then, as shown in FIG. 59, the "BANKF" instruction for switching from the second register bank 122 to the first register bank 121 is described in the line immediately before the "RET" instruction.

In the example shown in the set of FIGS. 60 and 61, a "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 and a "BANKF" instruction for switching from the second register bank 122 to the first register bank 121 are shown. This is an example in which both instructions are executed on the out-of-area program side. As shown in FIG. 61, in the out-of-area program in this case, a "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 is described in the first line, and the line immediately before the "RET" instruction is used. A "BANKF" instruction for switching from the second register bank 122 to the first register bank 121 is described.

By defining the "BANKF" instruction as described above, options other than CALLEX and RETEX (CALL and BANKF, or RET and BANKF) are provided as instructions for realizing the processing transition between the inside and outside of the area. This makes it possible to improve the degree of freedom in program creation.

Here, it is not essential to apply CALLEX and RETEX to all the processing transitions between the inside and outside of the area. For example, in an intra-regional program, CALL and RET can be used as before, instead of CALLEX and RETEX, depending on the processing contents of the program before and after the call instruction of the out-of-region program. For example, in a situation where there is a process to be performed in the interrupt disabled state after returning to the area by a return instruction to the program in the area, it is not necessary to execute EI when returning to the area, so CALL, not CALLEX or RETEX. Even if RET is used, an appropriate interrupt control state can be realized.

The set of FIGS. 62 and 63 shows an example of a program inside and outside the region when CALL and RET are used in such a situation.
Note that FIGS. 62 and 63 show an example of a program when the second register bank 122 for outside the area is not used. However, by using “BUNKF” described in FIGS. 54 and 55, for example, the inside of the area can be used. Instructions for saving and restoring AF in the program ("PUSH AF", "POP AF") are omitted, and instructions for saving and restoring the stack pointer (stack pointer for the inside of the area) in the program outside the area ("" LD (W_STKBAK), SP "," LD SP, (W_STKBAK) ") and instructions for saving and restoring all registers ("PUSH ALL", "EX AF, AF'", "EXX", "PUSH GPR", "POP GPR""""EX AF, AF'""EXX""POPALL") can be omitted.

[5-6. Other variants]

In the explanation so far, when calling the program outside the area from the program inside the area, after executing DI (second instruction) and before executing EI (first instruction), CALLEX (third instruction) is executed. ) Was given, but it is also possible to execute CALLEX after executing EI, in other words, execute EI before CALLEX.
By executing EI before executing CALLEX, the duration of the interrupt disabled state can be shortened. That is, it is possible to suppress the processing delay due to the inability to execute interrupt processing.

Here, in the game machine 1 of this example, the winning information is updated in the timer interrupt processing (see the prize ball management processing of S908). Then, among the various programs outside the region illustrated, in the performance display monitor aggregation division processing shown in FIG. 29 and the like, the value of the performance information is calculated using the winning information updated by the interrupt processing in this way. Therefore, if the method of executing EI before CALLEX is adopted when calling such a performance display monitor aggregation division process, the calculation of the performance information in the out-of-area program is updated immediately before that. This can be done using the winning information, which is preferable.

<6. About Q register and U register>

Subsequently, the Q register (Q register 105 and Q'register 105') and the U register 130 will be described.
First, the memory address space of the CPU 20a in the main control unit 20 will be described with reference to the memory map of FIG.
As shown in the figure, as the memory address space of the CPU 20a, a space for a total of 65536 bytes from the address 0000h (h means a hexadecimal number) to the address FFFFh is prepared.
The area of 16384 bytes (16 kbytes) from the address 0000h to the address 3FFFh is the area of the built-in ROM, and the area of 1024 bytes (1 kbytes) from the address F000h to the address F3FFh is the area of the built-in RAM.
The area from the address 4000h to the address EFFFh located between the areas of the built-in ROM and the built-in RAM is regarded as an unused area.

The area from the address F400h to the FDFFh is regarded as an unused area, the area from the address FE00h to the FEFFh is the area of the built-in register 1, and the area from the address FF00h to the address FFCFh is the area of the built-in register 2.

The area from the address FFD0f to the address FFFFh is an XCS decoding area.
Here, the CPU 20a of this example adopts a memory-mapped I / O method as a data input / output management method. As is well known, memory-mapped I / O is a method of allocating I / O registers in the same address space as data memory.
In this example, a storage area corresponding to an I / O register is allocated to the XCS decode area. In this sense, the XCS decoding area is hereinafter referred to as an "input / output port area (I / O port area)".

As described with reference to FIG. 21 above, the memory area accessible to the CPU 20a is divided into a used area as a first memory area and an unused area as a second memory area. FIG. 64 shows the division of the used area and the unused area in the built-in RAM area, but as shown in the figure, the built-in RAM area in this example uses 512 bytes of the area from the address F000h to the address F1FFh. The area, which is 256 bytes from the address F200h to the address F2FFh, is regarded as an unused area.

Based on the above, the Q register and the "LDQ" instruction, which is an instruction related to the Q register, will be described.
The Q register 105 and the Q'register 105'are used as registers for storing high-order values of some addresses handled by the "LDQ" instruction. In this example, these Q register 105 and Q'register 105'are 8-bit (1 byte) registers.

The "LDQ" instruction is described as, for example, "LDQ R, m" (R means a value that specifies a register, m means a value that specifies an address in memory) or "LDQ m, R", and is described as "LDQ m, R". It functions as a load instruction similar to the "LD" instruction, and is basically an instruction to write the value of the location specified on the right side with respect to the location specified on the left side after the description of "LDQ". The difference from the "LD" instruction is that only the lower value of the address in the memory needs to be described as the value of "m". That is, the "LDQ" instruction is an instruction to access an address in which the value described as "m" is the lower value and the stored value of the Q register 105 or the Q'register 105'is the upper value. Specifically, in the case of "LDQ R, m", the value of "m" is the lower value and the stored value of the Q register 105 or the Q'register 105'is the upper value with respect to the register specified by "R". It is an instruction to write the value stored in the address on the memory. If it is "LDQ m, R", specify "R" for the address in the memory where the value of "m" is the lower value and the stored value of the Q register 105 or the Q'register 105'is the upper value. It is an instruction to write the value of the registered register.

The Q register is a register provided to realize such an "LDQ" instruction. By providing the Q register, it is not necessary to describe the upper value of the address in the program, and the program capacity can be reduced.

Here, in this example, the above-mentioned "LDQ" instruction is applied to access the used area in the internal RAM area shown in FIG. 64. Therefore, "F0h" and "F1h" are stored in the Q register 105 and the Q'register 105', respectively.
As shown in FIG. 64, the used area in the built-in RAM is set as an area from the address F000h to the address F1FFh. That is, the used area is an area having a size exceeding 256 bytes that can be covered by the lower 1 byte (8 bits) of the address value. Therefore, if only one Q register is provided, the above-mentioned "LDQ" instruction can be applied only to the area where the upper address value in the used area is either "F0h" or "F1h". ..
In this example, by providing two Q registers 105 and Q'register 105', the "LDQ" instruction can be applied to any address in the used area of the built-in RAM.

In this example, the storage of "F0h" and "F1h" as described above is not only for the Q register 105 and the Q'register 105'in the first register bank 121, but also for the Q register 105 in the second register bank 122. , Q'Register 105'is also performed. The storage process of "F0h" and "F1h" for the Q register 105 and the Q'register 105'is automatically set as the initial value setting process for the Q register 105 and the Q'register 105'at the time of starting after the reset of the CPU 20a. Is executed.
Alternatively, the storage processing of "F0h" and "F1h" for the Q register 105 and the Q'register 105'is executed, for example, in the "various setting processing at startup" (S206) in the "initial setting processing" (S101). You can also.

As described above, the second register bank 122 is a group of registers used by the out-of-area program.
By storing "F0h" and "F1h" in the Q register 105 and the Q'register 105'of the second register bank 122 as described above, the out-of-area program can store the used area in the built-in RAM. You can also use the "LDQ" command when referencing data. That is, it is possible to reduce the program capacity by using the "LDQ" instruction even for a program outside the region.
For confirmation, it is not permitted for the out-of-area program to update the data in the used area, but it is permitted to refer to it (see FIG. 22).

Here, please refer to FIG. 36, FIG. 39, FIG. 40, FIG. 42, FIG. 43, FIG. 46, FIG. 50 and the like for an actual usage example of the “LDQ” instruction. Of these, the "LDQ" instruction shown in FIGS. 39 and 43 corresponds to an instruction for accessing the address of the used area when the out-of-area program is executed.

In order to properly access and separate the used area of the built-in RAM using the "LDQ" instruction, it is necessary to switch the Q register referred to by the "LDQ" instruction according to the address of the access destination in the used area. .. Specifically, it is necessary to appropriately switch which of the Q register 105 and the Q'register 105'is referred to.

In this example, such switching of the Q register is realized by the "EX" instruction. Specifically, it is realized by the command of "EX Q, Q'".
In this example, the "EX Q, Q'" instruction is an instruction that toggles the Q register referred to by the "LDQ" instruction between the Q register 105 and the Q'register 105'. That is, the referenced Q register is switched to the Q'register 105'in response to the instruction of "EX Q, Q'" in the state of the referenced Q register = Q register 105. Further, the reference Q register is switched to the Q register 105 in response to the instruction of "EX Q, Q'" in the state of the reference Q register = Q'register 105'.

In the above, the application target area of the "LDQ" instruction (that is, the area used by the built-in RAM in this example) is set to 256 × 2 = 512 bytes, and two Q registers are provided accordingly. However, the application target area of the "LDQ" instruction can be an area having a size larger than 512 bytes. In that case, by setting the number of Q registers to 3 or more, the "LDQ" instruction can be used when accessing any address in the target area.

Subsequently, the U register 130 will be described.
The U register 130 is a register that stores the upper address value of the input / output port area shown in FIG. 64. Specifically, "FFh" is stored in the U register 130 in this example.
By providing this U register 130, when specifying the access destination address of the input / output port area in the input / output instruction ("IN" instruction or "OUT" instruction), it is necessary to describe the upper value of the access destination address in the program. Can be eliminated.

In this example, memory-mapped I / O is adopted, but for instructions related to data input / output, the same "IN" instruction and "OUT" as when port-mapped I / O is adopted. The instructions are adopted (see, for example, FIGS. 38, 40, 48, etc.).
Specifically, the "IN" instruction in this case is described as "IN r, m", which is lower than the value described as "m" for the register specified by "r". It is an instruction to write the value stored in the address (that is, the virtual input / output register) in the input / output port area with the value and the stored value of the U register 130 as the upper value. Further, the "OUT" instruction is described as "OUT m, r", which is an input / output port in which the value described as "m" is the lower value and the stored value of the U register 130 is the upper value. It is an instruction to write the stored value of the register specified by "r" to the address in the area.
As can be understood from the above explanation of the "IN" and "OUT" instructions, when the memory-mapped I / O is adopted, the "LD" instruction can also be used as an instruction related to data input / output. ..

As shown in FIG. 26, in this example, only one U register 130 is provided in each of the first register bank 121 and the second register bank 122. Specifically, in each of the first register bank 121 and the second register bank 122, the U register 130 is provided as one of the main registers 123.
Since the U register 130 is also provided in the second register bank 122, the input / output port area can be accessed using the upper address value stored in the U register 130 even when the out-of-area program is executed. Is possible. That is, it is possible to eliminate the need to describe the upper value of the access destination address in the "IN" instruction and the "OUT" instruction even in the out-of-area program.

As described above, the input / output port area is an area from the address FFD0h to the address FFFFh, and the area size is 48 bytes. That is, it is an area size that can be covered by the lower value of the address.
Therefore, the number of U registers 130 is singular in each of the first register bank 121 and the second register bank 122.

Here, as described above, for the Q register, a common value is stored for each of the Q register 105 and the Q'register 105'in the first register bank 121 and the second register bank 122, respectively, but the U register 130. Also, a common value is stored in each of the first register bank 121 and the second register bank 122. Specifically, in this example, "FFh" is stored in each U register 130.
Such a storage process of "FFh" for the U register 130 is automatically executed as an initial value setting process for the U register 130 at the time of starting after the reset of the CPU 20a.
Alternatively, the storage process of "FFh" in the U register 130 can be executed, for example, in the "various setting processes at startup" (S206) in the "initial setting process" (S101).

In the above-mentioned explanation of the Q register, it was mentioned that the "EX" instruction is used when accessing the area where the upper address value is different, but it is not essential to use the "EX" instruction, and in some cases, it is necessary to use the "EX" instruction. It is also possible to describe the upper value of the access destination address in the program for access.
For example, when accessing the address of the upper value "F1h" while the Q register to be used is selected in the Q register 105, the Q register to be used is not switched to the Q'register 105'by the "EX" instruction. , The address information including the upper value "F1h" may be described in the program as the information of the access destination address. Alternatively, when accessing the address of the upper value "F0h" with the Q'register 105'selected as the Q register to be used, the Q register to be used is not switched to the Q register 105 by the "EX" instruction. , The address information including the upper value "F0h" may be described in the program as the information of the access destination address.
Here, in the former case, the Q register is used when accessing the address of the upper value "F0h", but is not used when accessing the address of the upper value "F1h". Further, in the latter case, the Q register is used when accessing the address of the upper value "F1h", but is not used when accessing the address of the upper value "F0h". That is, the Q register in these cases may or may not be used when the used area on the memory (that is, the target area on the memory) is accessed.
On the other hand, since the U register 130 targets only the area having the address upper value "FFh" as the target area, it is always used when the target area on the memory is accessed.

<7. Summary of embodiments>

As described above, the first gaming machine as the embodiment has a first register group (first register bank 121) and a second register group (second register bank 122), each of which is composed of a plurality of general-purpose registers. ), A first interrupt management register (IFF1 of the IFF register 125), and a second interrupt management register (IFF2 of the IFF register 125).
In addition, the first instruction (“EI” instruction) that writes the permitted value to the first interrupt management register and the second interrupt management register, and the second instruction (“EI” instruction) that writes the prohibited value to the first interrupt management register and the second interrupt management register. The DI "instruction), the third instruction ("CALLEX" instruction) used when calling the out-of-area program from the in-area program, and the fourth instruction ("CALLEX" instruction) used when returning from the out-of-area program to the in-area program. There is a "RETEX" command).
Then, the third instruction can write a prohibited value to the first interrupt management register and execute a process for switching the register group to be used from the first register group to the second register group before calling the out-of-area program. The fourth instruction overwrites the value of the second interrupt management register with the first interrupt management register before returning to the in-region program, and changes the register group to be used from the second register group to the first register group. The process for switching to is enabled.
Further, in the intra-regional program, the third instruction is executed after the second instruction is executed and before the first instruction is executed.

When executing a program outside the area, it is necessary to put it in the interrupt disabled state. Therefore, if the first instruction is executed before the execution of the third instruction, the interrupt disabled state and the interrupt enabled state are frequently switched. On the other hand, if the third instruction is executed after the second instruction is executed and before the first instruction is executed as described above, the interrupt disabled state of the out-of-area program is maintained. Since the call and the return to the program in the area are performed, the number of times the interrupt control state is switched can be suppressed.
Therefore, the number of times the control state is switched can be suppressed, and the stability of control can be improved.

Further, in the first gaming machine as the embodiment, the first register group has a first stack pointer (SP register 116 of the first register bank 121) for storing the stack pointer, and the second register group has It has a second stack pointer (SP register 116 of the second register bank 122) that stores the stack pointer, stores the address information of the stack memory used by the program in the area in the first stack pointer, and stores the address information of the stack memory used in the in-region program in the second stack pointer. , When the address information of the stack memory used in the out-of-area program is stored and the out-of-area program is called by executing the third instruction in the in-area program, the first address of the out-of-area program is specified and called. , The second address may be specified and called. In the out-of-area program, the stack common to the second stack pointer is used regardless of whether the first address is called or the second address is called. The fifth instruction for storing the address information of the memory is executed.

This makes it possible to reset the value of the stack pointer used in the out-of-area program each time the out-of-area program is called.
Therefore, even if the stored value of the second stack pointer changes due to some trouble after the execution of a certain out-of-area program, the correct stack pointer value is set when another out-of-area program is executed. It can be fixed and the stability of stack processing by the out-of-area program can be improved.

Further, in the first gaming machine as the embodiment, the first register group has a first stack pointer that stores the stack pointer, and the second register group has a second stack pointer that stores the stack pointer. Then, the first stack pointer stores the address information of the stack memory used by the in-area program, and the second stack pointer stores the address information of the stack memory used in the out-of-area program. In, when the third instruction is executed and the out-of-area program is called, there are cases where the first address of the out-of-area program is specified and called, and there are cases where the second address is specified and called at a subsequent timing. , In the out-of-area program, the sixth instruction for storing the address information of the predetermined stack memory in the second stack pointer is executed only when the first address is called.

Since the address information of the stack memory that should be set for the second stack pointer at the start of processing of the out-of-area program is fixed address information, the address information of the second address after the execution of the program of the first address as the out-of-area program When the program is executed, it is sufficient that the memory processing of the address information for the second stack pointer is performed only in the program of the first address, which is the program to be executed first.
Therefore, the processing efficiency can be improved by executing the instruction to store the address information of the predetermined stack memory in the second stack pointer only when the first address is called as described above.

The second gaming machine as an embodiment includes a control means for controlling the progress of the game, and the control means has an accessible memory address space, a general-purpose register, and a memory address space handled by some instructions. It has at least one register group (register bank) including a plurality of upper value registers, which are registers for storing the upper values of the addresses of.
Then, in the memory address space, a first area (“built-in RAM” area) having a predetermined area size and a second area (“internal RAM” area) which is different from the first area and whose area size is smaller than the predetermined size (“” There is an area of "input / output port area"), and the upper value register is a first type upper value register (Q register) related to the first area and a second type that stores the upper value of the address in the second area. There is a high-order value register (U register), and in the register group, the number of first-class high-value registers is plural, the number of second-class high-value registers is singular, and a plurality of first-class high-value registers in the register group. The first type upper value register (Q register 105) and the second type first type upper value register (Q') that stores consecutive values in the stored values of the first type first type upper value register. Registers 105') and are included.

By providing the upper value register, when accessing the required address in the first area or the second area, the upper value of the address is given to the program by accessing using the upper value stored in the upper value register. It is possible to eliminate the need to describe the value. That is, it is possible to reduce the program capacity. At this time, depending on the number of bytes of the lower address value, the entire area to be accessed may not be covered. For example, assuming that the size of the area that can be covered by the address lower value is 256 bytes (that is, the address lower value = 1 byte), if the size of the first area exceeds 256 bytes, the address lower value is used. The value cannot cover the entire first area. That is, in this case, it is necessary to use different address upper values in the area within 256 bytes and the area exceeding 256 bytes in the first area. Therefore, as the first-class upper-value register, the second-class upper-value register that stores consecutive values in the first-class upper-value register and the first-class upper-value register is stored. At least a register is provided. As a result, when accessing any address in the first area, it is possible to access using the upper value stored in the upper value register, and it is necessary to describe the upper value of the access destination address in the program. It will be possible to eliminate it. Since the second area is smaller than a predetermined size, it is possible to eliminate the need to describe the upper value of the access destination address in the program even if the number of the second type upper value registers is singular.
Therefore, the program capacity can be reduced by the configuration in which the first-class upper-value register is a plurality and the second-class upper-value register is a single number as described above.

Further, in the second gaming machine as the embodiment, the second area is an area to which the input / output registers of the control means are assigned.

This makes it possible to employ Memory Mapped I / O.
Since it is not necessary to provide an I / O register as hardware in the memory-mapped I / O, the internal circuit of the control means can be simplified, and the processing speed and price can be reduced.

Further, in the second gaming machine as the embodiment, the first area includes a used area, which is an area made available by the in-area program, and an out-of-use area, which is an area made available by the out-of-area program. The used area is composed of two areas in which the upper value of the address is continuous, and the unused area is an area in which the upper value of the address is different from the used area. A first-class register group used in a program is provided, and the first-class upper-value register and the second-class first-class upper-value register are provided in the first register group.

As a result, when accessing any address in the used area, it is possible to perform access using the address upper value stored in any of the two first-class upper value registers. That is, it is possible to eliminate the need to describe the upper value of the access destination address in the program in the area.
Therefore, it is possible to reduce the program capacity in the used area.

Furthermore, in the second gaming machine as the embodiment, the first area is a used area that is a region that can be used by the in-region program and a use that is a region that can be used by the out-of-area program. An outer region is included, and the register group includes two groups, a first register group used in the in-region program and a second register group used in the out-of-region program, and each of the first and second register groups has a first register group. There are a first-class high-value register, a second-class high-value register, and a second-class high-value register. In each of the first and second register groups, the first-class high-value register and the second type high-value register are available. A common value is stored for each of the first-class upper-value register and the second-class upper-value register.

That is, the same values as those on the first register group side are stored in each of the two first-class upper-value registers and the singular second-class upper-value register in the second register group. As a result, when accessing the first area or the second area when the program outside the area is executed (that is, when the second register group is used), it is stored in the first-class upper-value register or the second-class upper-value register. It is possible to use the upper address value. That is, it is possible to eliminate the need to describe the address upper value in the instruction for accessing the first area and the second area even for the program outside the area.
Therefore, it is possible to prevent the capacity of the out-of-area program from being unnecessarily expanded.

1 Pachinko game machine 13 Direction button 15a Cross key 15b Enter button 20 Main control board (main control unit)
20a CPU
20b ROM
20c RAM
24 Production control board (Production control unit)
24a CPU
24b ROM
24c RAM
36M Main liquid crystal display device 36S Sub liquid crystal display device 38a, 38b Special symbol display device 45 Decorative lamp 45a Light display device 46 Speaker 46a Sound generator 61 Front door open sensor 83 Handle sensor 94 Setting key switch 97 Setting / performance display 98 RAM Clear switch 100 PC (program counter) register 105 Q register 105'Q' register 116 SP (stack pointer) register 121 1st register bank 122 2nd register bank 125 IFF (interrupt control flag) register 130 U register

Claims (4)

Equipped with control means to control the progress of the game
The control means
It has an accessible memory address space and
It has at least one register group including a plurality of general-purpose registers and a plurality of upper value registers which are registers for storing upper values of addresses in the memory address space handled in some instructions.
The memory address space includes a first area having a predetermined area size and a second area different from the first area and having an area size smaller than the predetermined size.
The upper value register includes a first type upper value register related to the first area and a second type upper value register for storing an upper value of an address in the second area.
In the register group, the number of the first-class upper-value registers is plural, and the number of the second-class upper-value registers is singular.
In the plurality of the first-class upper-value registers in the register group, a second type-first upper-value register and a second value continuous with the stored values of the first-class upper-value register are stored in the first-class upper-value register. A game machine that includes a first-class high-value register. The gaming machine according to claim 1, wherein the second area is an area to which the input / output registers of the control means are allocated. In the first region,
It includes a used area, which is an area made available by the in-area program, and an out-of-use area, which is an area made available by the out-of-area program.
The used area is composed of two areas in which the upper value of the address is continuous, and the unused area is an area in which the upper value of the address is different from the used area.
As the register group, at least the first register group used in the program in the area is provided.
The gaming machine according to claim 1 or 2, wherein in the first register group, the first type first upper value register and the second type first upper value register are provided. In the first region,
It includes a used area, which is an area made available by the in-area program, and an out-of-use area, which is an area made available by the out-of-area program.
The register group includes two groups, a first register group used in the in-region program and a second register group used in the out-of-region program.
Each of the first and second register groups includes the first type first upper value register, the second type first upper value register, and the second type upper value register.
In each of the first and second register groups, a common value is stored for each of the first type first type upper value register, the second type first type upper value register, and the second type upper value register. The gaming machine according to any one of claims 1 to 3.

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