JP7280600B2 - processor - Google Patents

Description

The present invention relates to processors.

Processors with multiple register banks are known. Each register bank of a conventional processor does not have a Stack Pointer (SP) register, and one SP register is used across multiple register banks.

In a conventional processor having two register banks, when executing a process such as a CALL instruction, the called process selects the second register bank from the first register bank, executes a subroutine, and The first register bank is selected from the second register bank and used immediately before executing the RETURN instruction to return from the process to the original caller process. At that time, it is necessary to save the value of the SP register to another storage area when starting the CALLed process, and restore the value saved when the CALL instruction started to the SP register when executing the RETURN instruction. There is

The process for saving and restoring the value of the SP register must be prepared by the program creator who is the user who uses the processor.

To more easily realize switching of a register bank.

A plurality of register banks each provide a processor having SP registers.

An embodiment of the processor according to the invention comprises a first register bank and a second register bank, each of said first register bank and said second register bank may comprise a stack pointer register.

FIG. 1 shows a device according to an embodiment of the invention. FIG. 2 shows an example of a memory map of a storage device used in a gaming machine. FIG. 3 shows a processing flow by a conventional processor core. FIG. 4 shows a register bank of an embodiment according to the invention. FIG. 5 shows a processing flow by the processor core of the present invention. FIG. 6 shows an example of a processor core using flags IFF and NMIEN. FIG. 7 explains the operation of each instruction.

Overview of Processor Core FIG. 1 shows an overview of a processor core in a microcomputer according to an embodiment of the present invention. Processor core 100 includes external input unit 105 , state control unit 110 , central control unit 115 , register unit 120 , arithmetic logic unit (ALU) 140 , read data (DI) 145 , write data (DO) 150 and data bus 155 . have External input unit 105 receives and provides external signals to state control unit 110 and central control unit 115 . State control unit 110 controls information input/output with central control unit 115 . The central control unit 115 controls the ALU 140 according to the result of decoding the operation code (instruction) input from the read data (DI) 145 by the instruction decoder 117 . Further, the central control unit 115 acquires necessary information from each register of the register unit 120 and controls update based on the decoded result.

The register unit 120 includes a program counter (PC) register 122, an interrupt (I) register 124, a refresh (R) register 126, an RB register 128 indicating the register group (register bank) currently in use, a destination selector port 130, a destination bank It has a selector 132 , a first register bank 133 , a second register bank 134 , a source bank register 135 , a source selector port A 136 , a source selector port B 137 and an address port 138 .

Regarding processor cores in game machines A user who is a game machine maker creates a game machine control program and stores it in a microcomputer in which the processor core is mounted. Thereby, the gaming machine operates based on the program. On the other hand, in a microcomputer of a game machine such as pachinko or pachislot, the game machine is inspected using an inspection program in order to prevent fraud in the game machine.

The storage device has a usable area (within the usable area) that includes a ROM that can be used by the user for the game machine control program and a RAM that is used as a work area, and a ROM that stores the user's inspection program and the inspection program. It is distinguished from the non-use area where the RAM used as a work area is included and the game machine control program cannot be used. The game machine control program cannot update the RAM outside the use area. The test program cannot update the RAM in the used area. (as defined by regulations)
The work areas for the game machine control program and the inspection program include not only work areas for calculations during program execution, but also stack areas for storing registers and return addresses at subroutine CALL.

The storage devices are connected to processor core 100 via buses including data bus 155, not shown in FIG. FIG. 2 shows an example of a memory map of a storage device used in a gaming machine. Y ₁ bytes from address 0000h to XXXX ₁ h is the user program area 205 and Y ₂ bytes from addresses XXXX ₂ h to XXXX ₃ h is the user data area 210 (subscript X means one or more digits and/or letters, for example, single digit values can be 0-9 and A through F. A subscripted Y means one or more digits means an integer, for example, Y can be an integer equal to or greater than 0. The same shall apply hereinafter). The user program area 205 stores a gaming machine control program, and the user data area 210 stores data referred to by the gaming machine control program. The user program area 205 and user data area 210 memories are read-only memories.

Y ₄ bytes from address XXXX ₇ h to XXXX ₈ h are area 225 of the first user RAM and Y 5 bytes from address XXXX ₉ h to XXXX ₁₀ h are area 230 of the second user RAM. . The area 225 of the first user RAM and the area 230 of the second user RAM are work areas used when the gaming machine control program is being executed. The memories in area 225 of the first user RAM and area 230 of the second user RAM are random access memories.

When the game machine control program is executed, the interrupt program is also executed together with the control program. Therefore, the area 225 of the first user RAM and the area 230 of the second user RAM are used as work areas for the control program and the interrupt program, as well as for saving register information, subroutines, and return addresses for interrupt processing. It is also used as a stack area for temporary storage. The user program area 205, the user data area 210, the first user RAM area 225, and the second user RAM area 230 correspond to areas used by the game machine control program.

The Y ₉ bytes from addresses XXXX ₅ h to XXXX ₆ h are the external program area 220 . The external program area 220 stores an inspection program for inspecting the operation of the gaming machine. The memory of the external program area 220 is read-only memory.

Y ₆ bytes from address XXXX ₁₁ h to XXXX ₁₂ h are area 235 of the external user RAM. The area 235 of the external user RAM is a work area used when the inspection program is being executed, and is also used as a stack area for saving register information and temporarily storing return addresses for subroutines and interrupt processing. be done. The memory in area 235 of the external user RAM is random access memory.

The external program area 220 and the area 235 of the external user RAM are not used by the gaming machine control program and correspond to outside the use area used for the inspection program.

As described above, by preparing a memory area within the use area and a memory area outside the use area, the use area can be made independent in each area. That is, it is necessary that the game machine control program is executed within the use area and the inspection program is executed outside the use area so that the game machine control program and the inspection program do not interfere with each other. Regarding this, when the execution of the program moves from the game machine control program to the inspection program, it is necessary to switch the value of the stack pointer from the value corresponding to the inside of the use area to the value corresponding to the outside of the use area. This is because if the switching is not performed, the stack area and other RAM areas located within the used area will be updated by operations that update the stack, such as subroutine calls and register saving that are used outside the used area. . If subroutines and interrupt operations operate regularly, areas other than the stack will not be updated.

PRIOR ART The processor core shown in FIG . Alongside the RB register 128 is a stack pointer register. Processing by a conventional processor core will be described below with reference to FIG.

FIG. 3 shows a processing flow by a conventional processor core. The processing includes processing 302 that is executed using the inside of the storage device's usable area and processing 352 that is executed using the non-used area of the storage device.

First, we start with a process 302 using within the used area that is executed by the processor core. First, the accumulator register A and flag register F are saved (step 304). As an instruction, PUSH AF is executed. (The execution of this instruction means that the contents of the flag register F will be changed when the LD (aaa) and SP are executed. Therefore, the contents of the flag register F must be saved.) Interrupts are prohibited (step 306). As an instruction, DI is executed. The DI instruction disables maskable interrupt processing. A process 352 using the used area is called (step 308). As an instruction, CALL xyz (xyz is a process executed using an area outside the storage device, for example, a process by an inspection program) is executed. As a result, a subroutine that is executed using the area outside the usage area is called, and execution is transferred to the subroutine.

In response to a process call, a process 352 using out-of-use regions executed by the processor core is started. The stack pointer is saved (step 354). As instructions, LD (aaa) and SP are executed (aaa indicates a save destination address outside the area). A stack pointer specifying an address outside the used area is set (step 356). As an instruction, LD SP, mn is executed (mn indicates an address outside the used area). All registers (BC, DE, HL, IX, IY registers) are saved (step 358). As an instruction, PUSH ALL is executed. A process such as an inspection program is executed (step 360). At step 360, the processor core executes processing using the non-use area of the storage device. Thereafter, all registers are restored based on the saved register information (step 362). As an instruction, POP ALL is executed. The stack pointer is restored based on the saved stack pointer information (step 364). LD SP, (aaa) is executed. Processing is returned to step 308 (step 366). As a result, the process returns to the processing of the program using the inside of the used area. As an instruction, RET is executed.

When the instruction returns, enable interrupts (step 310). EI is executed as an instruction. The EI instruction enables maskable interrupt processing that was prohibited in step 306 . Based on the saved information of the A and F registers, these registers are restored (step 312). As an instruction, POP AF is executed. Processing ends (step 314).

In the above processing, even if the DI instruction is executed, the NMI processing cannot be inhibited, so the NMI interrupt processing is executed. Therefore, if the stack pointer is not changed outside the area, the stack at the time of interrupt uses the RAM within the area. In addition, since the RAM area is limited, when the calling side processing within the area nests subroutines and the stack area is reduced, when the CALL instruction is executed, the subroutine CALL, etc. If the nesting of the stack becomes deep, there is a risk that the stack area will be overrun or that the stack and work area within the area will be updated due to program runaway. Furthermore, if all registers are saved in the stack, the stack area is used, so a large amount of stack area must be secured, and the work area used for game machine control is reduced.

Therefore, by separating the work area and the stack area inside and outside the use area of the storage device according to the above processing flow, the influence of interrupt processing on each area is reduced.

Register Bank FIG. 4 shows the register bank of an embodiment according to the invention. FIG. 4 shows the first register bank 133 and the second register bank 134 shown in FIG. The first register bank 133 has a front register group 400 and a back register group 420 . Table register group 400 includes Q register 401, U register 402, A register 403, F register 404, B register 405, C register 406, D register 407, E register 408, H register 409, L register 410, IX register 411, It has an IY register 412 and an SP register 413 .

The reverse register group 420 includes a Q' register 421, a U' register 422, an A' register 423, an F' register 424, a B' register 425, a C' register 426, a D' register 427, an E' register 428, and an H' register 429. , L′ register 430 , IX′ register 431 and IY′ register 432 .

The second register bank 134 has a front register group 440 and a back register group 460 like the first register bank 133 . The front register group 440 and back register group 460 have the same configuration as the front register group 400 and back register group 420 of the first register bank 133 . A conventional processor core does not have a stack pointer register in each register bank, but has one stack pointer register arranged in the processor core. The present invention includes stack pointers 413, 453 in each register bank, as can be understood from FIG.

Although the above embodiment describes an embodiment having two register banks, in other embodiments there may be three or more register banks.

Processing flow by the processor core of the present invention

FIG. 5 shows a processing flow by the processor core of the present invention. The processing includes processing 502 that is executed using the inside of the storage device's available area and processing 552 that is executed using the outside of the storage device's usage area.

First, we start with a process 502 using within the used area that is executed by the processor core. First, the processor core 100 switches the register bank to be used from the first register bank 133 to the second register bank 134 (step 504). Specifically, the processor core 100 changes the information in the RB register 128 holding information indicating the register bank to be used from the first register bank to indicate the second register bank. As a result, the destination bank selector 132 determines whether the write destination register bank is the first register bank 133 or the second register bank 134 based on the information in the RB register 128 . The source bank register 135, like the destination bank selector 132, determines a group of registers to be read.

Disable interrupts (step 506). The DI instruction disables maskable interrupt processing. A process 552 using the used area is called (step 508). Processing executed using the area outside the storage device, for example, processing by an inspection program is executed. As a result, a subroutine that is executed using the area outside the usage area is called, and execution is transferred to the subroutine.

In response to the process call, a process 552 using out-of-use regions executed by the processor core is started. A stack pointer specifying an address outside the used area is set (step 556). As an instruction, LD SP, mn is executed (mn indicates an address outside the used area). A process such as an inspection program is executed (step 560). At step 560, the processor core performs processing using the non-use area of the storage device. Processing is returned to step 508 (step 566). As a result, the process returns to the processing of the program using the inside of the used area. As an instruction, RET is executed.

When the instruction returns, enable interrupts (step 510). The EI instruction enables maskable interrupt processing that was prohibited in step 306 . The processor core 100 switches the register bank to be used from the second register bank 134 to the first register bank 133 (step 512). Specifically, the processor core 100 changes the information in the RB register 128 holding information indicating the register bank to be used from the first register bank to indicate the second register bank, as in step 504 . Processing ends (step 514).

By providing a stack pointer for each register bank, the need to selectively save and restore each register is eliminated. Furthermore, by switching the register bank, the registers can be switched for processing using the inside of the usage area and for processing using the outside of the usage area. As a result, the present invention can reduce the amount of program creation.

Controlling interrupt processing

Interrupt processing must be disabled when a program outside the area of use is being executed. If an interrupt processing program stored in the used area is executed while a program outside the used area is running, the interrupt processing program accesses the work memory in the used area and updates the memory. This is because For example, when non-maskable interrupt processing (NMI interrupt processing) of the Z80 processor, which is often used as a processor device, is executed, a memory area of 0066h (in FIG. 2, address "0066h" is assumed to be user program area 205) is referred to, the user program area 205, which is within the used area, is referred to when NMI interrupt processing is executed while a program outside the used area is being executed.

Interrupt processing can be inhibited from executing maskable interrupt processing (INT interrupt processing) by the DI instruction in the prior art and embodiments of the present invention, as shown in FIGS. However, although the DI instruction can inhibit execution of INT interrupt processing, it cannot inhibit execution of non-maskable interrupt processing (NMI interrupt processing).

As an example of interrupt processing control, a non-maskable interrupt permission flag may be provided in a register or storage device. The processor core 100 checks the permission flag and determines whether execution of non-maskable interrupt processing is permitted. Thereby, the processor core 100 can control permission and prohibition of execution of non-maskable interrupt processing.

As another example of control of interrupt processing, execution of NMI interrupt processing can be prohibited by controlling an NMI acceptance signal by an external circuit of the processor core.

The interrupt processing of the Z80 processor, which is often used as a processor device, can execute interrupt maskable interrupt processing (INT interrupt processing) and non-maskable interrupt processing (NMI interrupt processing). Interrupt control flags IFF1 and IFF2 are used to control permission and prohibition of execution of INT interrupt processing. IFF1 is used to control disabling and enabling of INT interrupt processing of the processor.

IFF2 is set to the same value as IFF1 when an interrupt processing prohibiting instruction (DI instruction) and an interrupt processing enabling instruction (EI instruction) are executed. Specifically, the DI instruction sets IFF1=IFF2=0 and prohibits the execution of interrupt processing, and the EI instruction sets IFF1=IFF2=1 and permits the execution of interrupt processing. Further, when the processor is reset and an interrupt (INT interrupt) process occurs, IFF1=IFF2=0, and execution of the interrupt process is prohibited.

When NMI interrupt processing of the processor occurs, IFF1=0, execution of interrupt processing is prohibited, and the state of IFF2 is not changed. As a result, the value of IFF2 holds the value of IFF1 before NMI interrupt processing. When NMI interrupt processing ends, the RETN instruction is executed to copy the value of IFF2 to IFF1. As a result, when the NMI interrupt processing occurs, the state of the processor interrupt processing is set to IFF2 as a value indicating whether the INT interrupt processing is disabled (IFF1=0) or interrupt processing is enabled (IFF1=1). is held to When returning from NMI interrupt processing, the value of IFF2 is copied to IFF1 by executing the RETN instruction, and the interrupt state before the occurrence of NMI interrupt processing can be restored.

Embodiments in accordance with the present invention have a non-maskable interrupt enable flag (NMIEN flag) for controlling disabling and enabling of NMI interrupt processing, in addition to controlling disabling and enabling of INT interrupt processing.

FIG. 6 shows an example of a processor core using flags IFF and NMIEN. FIG. 6 details the interrupt control and register bank switching shown in the processor core of FIG.
When the central control unit 115 fetches an instruction, the instruction decoder 117 analyzes the instruction, decodes an instruction related to interrupt control, notifies the interrupt control circuit 640 in the external input unit 105 (605) of the result, and decodes the instruction related to bank switching. After decoding, the RB control circuit 655 in the register unit 120 is notified of the result.
The interrupt control circuit 640 receives decode results (641 to 647) of each instruction from the instruction decoder 117 and sets/resets the IFF1 circuit 620, the IFF2 circuit 625 and the interrupt control circuit 635. FIG. Control circuit 635 has a non-maskable interrupt enable flag (NMIEN flag). The interrupt control circuit 640 also receives interrupt signals (INT signal and NMI signal) from the outside and transmits an interrupt instruction 641 based on the interrupt signal to the central control unit 115 .
The external input unit 105 ( 605 ) further includes an INT input control circuit 610 and an NMI input control circuit 630 . The INT input control circuit 610 is connected to the IFF1 circuit 620 as a passing information control signal, and controls whether or not the input of the INT signal is passed depending on the state of the IFF1 circuit 620 . The NMI input control circuit 630 is connected to an interrupt control circuit 635 as a pass control signal, and controls whether or not to pass the NMI signal input depending on the state of the interrupt control circuit 635 .
The INT control circuit and the NMI control circuit are circuits such as tri-state buffers, for example, which pass the pass signal (control signal=1) or not pass the pass signal (control signal=0) according to the control signal (0/1) for the pass signal. or control.
The IFF1 circuit 620, IFF2 circuit 625, and interrupt control circuit 635 can be, for example, flip-flop circuits, but this is an example, and any circuit capable of holding at least 1-bit information may be used.

The external input unit 605 receives the EI instruction from the central control unit 115 and sets IFF1=IFF2=1 to enable the processor core for INT interrupt processing. Also, the external input unit 605 receives a DI command from the central control unit 115 and sets IFF1=IFF2=0, thereby disabling the processor core for INT interrupt processing. When the external input unit 605 receives the INT signal, it issues an interrupt instruction 641 to the central control unit 115 in response to the value of the IFF1 circuit 620 being "1". The INT input control circuit 610 controls to accept an INT interrupt when the INT signal and the IFF1 flag are both "1". The central control unit 115 performs INT interrupt processing according to the interrupt instruction 641 . When the INT interrupt processing ends, the central control unit 115 sends a RETI instruction 644 to the external input unit 605, and the external input unit 605 ends the INT interrupt processing. Even if the external input unit 605 receives the INT signal, it does not issue an INT interrupt processing instruction 641 to the central control unit 115 in response to the value of the IFF1 circuit 620 being "0".

When the external input unit 605 receives the NMI signal, it issues an interrupt instruction 641 to the central control unit 115 in response to the value of the interrupt control circuit 635 being "1". The NMI input control circuit 630 controls to accept an NMI interrupt when both the NMI signal and the NMIEN flag have a value of "1". The central control unit 115 performs NMI interrupt processing according to the interrupt instruction 641 . When the NMI interrupt handling is finished, the central control unit 115 sends a RETN instruction 645 to the external input unit 605 and the external input unit 605 finishes NMI interrupt handling. Even if the external input unit 605 receives the NMI signal, it does not instruct the central control unit 115 to process the NMI interrupt 641 in response to the value of the interrupt control circuit 635 being "0".

Instructions for Register Bank Switching and Interrupt Control Circuit An example of register bank switching by the central control unit 115 will now be described more specifically. When the central control unit 115 fetches the CALLEX instruction 646, it moves instruction execution from inside the used area to outside the used area, and when it fetches the RETEX instruction 647, it moves instruction execution from outside the used area to inside the used area.

Referring to FIG. 6 again, when the central control unit 115 fetches the instruction code, the instruction decoder analyzes it and sends the decoding result (642-647) to the external input unit 605 and the register unit 120. FIG. The external input unit 605 sets the value of the interrupt control circuit 635 to "0" in response to receiving the decoding result 646 of the CALLEX instruction. Furthermore, in response to register unit 120 receiving decode result 646 of the CALLEX instruction, RB control circuit 655 sets the value of the RB register to "1". The destination bank selector 132 and the source bank register 135 specify that the register bank to be used is the second register bank 134 in response to the value of "1" in the RB register. As a result, information is obtained and set in each register in the second register bank 134 when the non-use area is used in the storage device.

The external input unit 605 sets the value of the interrupt control circuit 635 to "1" in response to receiving the decode result 647 of the RETEX instruction. In response to register unit 120 receiving RETEX instruction 647, RB control circuit 655 sets the value of the RB register to "0." The destination bank selector 132 and source bank register 135 specify that the register bank to be used is the first register bank 133 in response to the value of the RB register being "0". As a result, information is acquired and set in each register in the first register bank 133 when the area in the storage device is used.

Timing of Change of Each Flag etc. The following table shows changes of flags etc. due to the operation of the processor core. The meanings of values such as flags in the table below are summarized below.
When the value of the RB register is "0", the first register bank 133 (for inside the use area) is referenced, and when the value of the RB register is "1", the second register bank 134 (for outside the use area) is referred to. Referenced.
When IFF1 is "1", acceptance of INT interrupt is permitted, and when IFF1 is "0", acceptance of INT interrupt is prohibited.
When IFF2 receives an NMI interrupt or the like, IFF2 holds the value of IFF1 before receiving the interrupt.
When NMIEN is "1", NMI interrupt acceptance is permitted, and when NMIEN is "0", NMI interrupt acceptance is prohibited.

#1: When the processor is powered on and reset, the RB register value is "0", the IFF2 flag is "0", the IFF1 flag is "0", and NMIEN is "1". set.
#2: When the DI instruction is executed and the INT interrupt is disabled, the value of the RB register does not change, the IFF2 flag is set to "0" and the IFF1 flag is set to "0", and NMIEN remains unchanged.
#3: When the EI instruction is executed and the INT interrupt is enabled, the value of the RB register does not change, the IFF2 flag is set to "1" and the IFF1 flag is set to "1", and NMIEN remains unchanged.
#4: When the INT interrupt is accepted and the INT interrupt process is executed, the value of the RB register does not change, the IFF2 flag is set to "0" and the IFF1 flag is set to "0", and NMIEN remains unchanged.
#5: When an NMI interrupt is accepted and NMI interrupt processing is executed, the value of the RB register does not change, and the IFF1 flag at the time of accepting the NMI interrupt is copied to the IFF2 flag and the value before IFF1 is retained. , and IFF1 flags are set to "0", and NMIEN is set to "0".
#6: When the RETI instruction terminates the INT interrupt processing and executes a return, the value of the RB register does not change, the IFF2 flag does not change and retains the previous value, and the IFF1 flag contains the value of the IFF2 flag. is set and NMIEN is unchanged.
#7: When NMI interrupt processing ends and a return is executed by the RETN instruction, the value of the RB register does not change, the IFF2 flag does not change and the previous value is retained, and the IFF1 flag has the value of the IFF2 flag. is set, and NMIEN is set to "1".
#8: When the CALLEX instruction is executed when the value of the RB register is "0", and the used area of the storage device is changed from inside the used area to outside the used area, "1" is set in the RB register, The IFF2 flag does not change and retains its previous value, the IFF1 flag is set to "1", and NMIEN is set to "0".
#9: When the CALLEX instruction is executed when the value of the RB register is "1", and the outside of the storage area is used (after the CALLEX instruction is executed, the RETEX instruction is not executed and another CALLEX instruction is executed). is set), the RB register is set to "1", the IFF2 and IFF1 flags do not change and retain their previous values, and NMIEN is set to "0".
#10: When the RETEX instruction is executed when the value of the RB register is "1" and the used area of the storage device is changed from outside the used area to within the used area, "0" is set in the RB register, The IFF2 flag does not change and retains its previous value, the IFF1 flag is set to the value of the IFF2 flag, and NMIEN is set to "1".
#11: When the RETEX instruction is executed when the value of the RB register is "0" and the area used in the storage device is used (when the RETEX instruction is executed while executing within the area), "0" is set, the IFF2 flag does not change and retains its previous value, the IFF1 flag is set to the value of the IFF2 flag, and NMIEN is set to "1".

Concrete Examples of Instructions A CALLEX instruction may be used as an example of an instruction for executing a program stored outside the available area of the storage device. The CALLEX instruction may be used as a machine language instruction in the form of "CALLEX mn" and "CALLEX Yn" (where Y is a character string indicating the upper address of the call destination address of CALLEX). ). A return instruction from a subroutine outside the use area, that is, a return instruction of the "CALLEX" instruction may be used in the form of "RETEX" as a machine language instruction.

A machine language instruction is a mnemonic for describing an assembler language program, which is converted into an instruction code (machine language code actually read and executed by a processor) and executed by the assembler program. The above "CALLEX mn" is converted to "instruction code 1, n, m", "CALLEX Yn" is converted to "instruction code 2, n", and "RETEX" is converted to "instruction code 3". Here, the instruction code is a machine language code of 1 to N bytes and is a binary integer (00h-FFh), and m and n are variables indicating 1-byte binary integers (00h-FFh). As a result, "CALLEX mn" can specify the address of the call destination using 2-byte information. "CALLEX Yn" designates "Y" as a fixed value as upper 1-byte information, and for "n", the user can designate lower 1-byte information. As can be seen from FIG. 2, the external program area 220 begins at address "XXXX ₅ h", so "CALLEX Yn" (eg, if XXXX ₅ =abcd then Y=ab) is useful. Therefore, different values may be used for "Y" in "CALLEX Yn" depending on the memory map in the storage device.

The operation of each command will be described below with reference to flowcharts. The flowchart shows the internal operation of each machine language instruction, and each step is executed in synchronization with the internal clock. In the description of the operation, the instruction fetch operation is omitted, but it will be understood that each instruction is executed after being fetched from memory. In the following description, a processor with a 16-bit stack pointer and an 8-bit address indicated by the value of the stack pointer will be described as an example.

1. CALLEX mn instruction When the processor fetches an instruction, the program counter (PC) is set to the next execution address (when the CALLEX instruction is called in the main routine, the next processing of the program being executed in the main routine is stored in the PC). ), the upper byte of the program counter is stored in the stack indicated by the address of the stack pointer (previous stack pointer) value obtained by subtracting 1 from the current stack pointer (SP) of the register bank indicated by the RB register. (PC _H , upper 1 byte in 2 bytes) is stored (step 702). The processor then subtracts 1 from the current stack pointer (SP) (the value of the stack pointer (one previous stack pointer, the stack pointer before step 700, 2 subtracted (two previous) stack pointer)). The lower byte of the program counter (PC _L , lower 1 byte in 2 bytes) is stored in the stack indicated by the address of (step 704). The processor stores mn in the program counter (PC).

The processor determines the value of the RB register (step 708). If the value of the RB register is "0" (the area of the storage device when executing the CALLEX instruction is within the used area), the processor sets the interrupt flag 1 (IFF1) to "0" and disables the INT interrupt. (step 710). The processor does not execute step 710 if the value of the RB register is "1" (the area of the storage device at the time of executing the CALLEX instruction is outside the available area). The processor sets the value of the RB register to "1" and sets the outside of the used area as the used area of the storage device (step 712). The processor sets the non-maskable interrupt enable flag (NMIEN) to "0" to disable NMI interrupts (step 714). The processor fetches an instruction from the program counter (PC) as the next instruction to shift execution to the CALL-destination program (a program stored outside the use area) (step 716). In the CALLEX mn instruction, the subroutine call address can be specified by a value indicated by 2 bytes of mn, and the instruction can be an instruction of instruction code + 2 bytes.

2. CALLEX Yn instruction When the processor fetches an instruction, the program counter (PC) indicates the next execution address, so the stack pointer (1 The upper byte of the program counter (PC _H , upper 1 byte in 2 bytes) is stored in the stack indicated by the address of the previous stack pointer (step 732). The processor continuously subtracts 1 from the current stack pointer (SP) to obtain the value of the stack pointer (one previous stack pointer, 2 subtracted from the stack pointer in step 730 (two stack pointers before)). The lower byte of the program counter (PC _L , lower 1 byte in 2 bytes) is stored in the stack indicated by the address of (step 734). The processor stores 20h in the high byte of the program counter (PC _H ) and n in the low byte of the program counter (PC _L ) (step 736).

The processor determines the value of the RB register (step 738). If the value of the RB register is "0" (the area of the storage device when executing the CALLEX instruction is within the used area), the processor sets the interrupt flag 1 (IFF1) to "0" and disables the INT interrupt. (step 740). The processor does not execute step 740 if the value of the RB register is "1" (the area of the storage device at the time of executing the CALLEX instruction is outside the available area). The processor sets the value of the RB register to "1" and sets the non-use area as the use area of the storage device (step 742). The processor sets the non-maskable interrupt enable flag (NMIEN) to "0" to disable NMI interrupts (step 744). The processor fetches an instruction from the program counter (PC) as the next instruction to shift execution to the CALL-destination program (a program stored outside the use area) (step 746). In the CALLEX Yn instruction, the subroutine call address is XXXX ₅ h (Y00h) to Yxxh (xx is the value indicated by n and ranges from 00h to FFh), that is, one of 256 addresses starting from Y00h. can be specified. Since the CALLEX Yn instruction can omit the upper byte "m" that was required in the "CALLEX mn instruction", if the minimum instruction code is 1 byte, the instruction can be a 2-byte instruction.

3. RETEX Instruction After the CALLEX instruction is executed, the RETEX instruction is executed to return to the process that was being executed when the CALLEX instruction was called. The processor sets the value of the RB register to "1" and sets the inside of the used area as the used area of the storage device (step 762). The processor loads the stack indicated by the address of the current stack pointer value (equivalent to the stack pointer value set in step 704 or 734) into the lower byte of the program counter (PC _L , lower 1 byte out of 2 bytes). (step 764). The processor increments the current stack pointer by 1 (the next stack pointer) and allocates the stack at the address indicated by the value of the stack pointer (corresponding to the value of the stack pointer set in step 702 or 732) to the program counter (PC _H ) (step 766). The processor then adds 1 to the current stack pointer (SP) (the stack pointer after 1, when viewed from the stack pointer in step 760, adds 2 (two stack pointers after)). is stored in the current stack pointer (step 768).

The processor copies interrupt flag 2 (IFF2) to interrupt flag 1 (IFF1) and the INT interrupt is enabled or disabled (step 770). The processor also sets a non-maskable interrupt enable flag (NMIEN) to "1" to enable NMI interrupts. The processor returns to the CALLed program by fetching the program counter (PC) instruction as the next instruction.

In each of the other examples above, the processor cores shown may be implemented in a processor. The processor may be a gaming machine processor. The game machine processor may be mounted as a processor on the game control board. The game control board is mounted on the game machine.

Some or all of the elements described as being implemented in hardware in the above embodiments can be implemented in software, and some elements described as being implemented in software. may be implemented in hardware.

In the processing or processing order described above, as long as there is no inconsistency in the processing or processing order, such as using data that should not be used yet in a certain processing, the processing or processing order can be changed freely.

Regarding each of the embodiments described above, a part or all of the embodiments may be combined to be realized as one embodiment.

Each embodiment described above is an illustration for explaining the present invention, and the present invention is not limited to these examples. The present invention can be embodied in various forms without departing from the gist thereof.

In each of the above embodiments, instructions that can be used in processors using embodiments of the present invention have been described, and further instructions that can be used in processors are provided below.

100: processor core 105: external input unit 110: state control unit 115: central control unit 117: instruction decoder 120: register unit 122: program counter (PC) register 124: interrupt (I) register 126: refresh (R) register 128 : RB register 130 : destination selector port 132 : destination bank selector 133 : first register bank 134 : second register bank 135 : source bank register 138 : address port 145 : read signal 150 : write signal line 155 : data bus 205: user program area 210: user data area 220: external program area 225: first user RAM area 230: second user RAM area 235: external user RAM area 400: table register group 401: Q register 402 : U register 403 : A register 404 : F register 405 : B register 406 : C register 407 : D register 408 : E register 409 : H register 410 : L register 411 : IX register 412 : IY register 413 : Stack pointer register 420 : Back register group 421 : Q' register 422 : U' register 423 : A' register 424 : F' register 425 : B' register 426 : C' register 427 : D' register 428 : E' register 429 : H' register 430 : L' register 431 : IX' register 432 : IY' register 440 : Table register group 441 : Q register 442 : U register 443 : A register 444 : F register 445 : B register 446 : C register 447 : D register 448 : E register 449: H register 450: L register 451: IX register 452: IY register 453: Stack pointer register 460: Back register group 461: Q' register 462: U' register 463: A' register 464: F' register 465: B' Register 466: C' register 467: D' register 468: E' register 469: H' register 470: L' register 471: IX' register 472: IY' register

Claims (4)

A processor for a gaming machine,
a first register bank;
a second register bank;
A memory having a usable area of a storage device that is usable by a user and a non-usable area of a storage device that cannot be used by the user, and stores programs in the usable area and outside the usable area, respectively. a device;
with
each of the first register bank and the second register bank having a stack pointer register;
A processor for gaming machines, wherein the stack pointer register of the first register bank is used by a program within the usage area, and the stack pointer register of the second register bank is used by a program outside the usage area. further comprising an RB register indicating the currently used register bank;
When executing the program outside the usage area, changing the value of the RB register to a value indicating the second register bank, and when transferring execution from the program outside the usage area to the program inside the usage area, 2. The gaming machine processor according to claim 1, wherein the value of the RB register is changed to a value indicating said first register bank. A circuit storing a flag indicating permission or prohibition of NMI interrupt is further provided, and when the program outside the use area is executed, the flag indicating prohibition of the NMI interrupt is set in the circuit, and the program within the use area is executed. 3. The gaming machine processor according to claim 1, wherein, when executed, a flag indicating permission of said NMI interrupt is set in said circuit. A game machine using the processor according to any one of claims 1 to 3 .

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