JP2021126277A - Game machine - Google Patents

Abstract

To enable securing a capacity of a control area for executing game control processing.SOLUTION: A game machine includes, on a predetermined board to be used in a progress of a game, a CPU, a ROM storing a program used in the CPU, and a RAM retaining a variable updated by the program. The CPU reads out the program from the ROM, calculates, on the basis of the program, a logical add of a value of a first register and a value stored in an address of the RAM designated by a second register, and writes a result of the logical add over the value stored in the address designated by the second register.SELECTED DRAWING: Figure 172

Description

The present invention relates to a gaming machine that determines by lottery whether or not to give a gaming benefit to a player.

Generally, in a game machine (pachinko machine), a game ball is launched toward a game area in the game board by a player's handle operation, and the game ball that has flowed down the game area enters the start port. A lottery related to the symbol is executed. Then, the special symbol is displayed in a variable manner on the special symbol display, and the special symbol determined by the lottery is stopped and displayed, so that the player is notified of the lottery result. At this time, when a specific special symbol indicating that the special symbol is a big hit is stopped and displayed on the special symbol display, a large role game that is more advantageous to the player than the normal game is started. In this big role game, the attacker device opens and closes a predetermined number of times, and the game ball can be entered into the big prize opening, so that the player can receive a large number of prize balls to be paid out.

In such a gaming machine, it is desired to effectively utilize a finite storage area in the memory in order to improve the playability. For example, there is known a technique of associating a control value with a control information of a data set table to effectively use a memory (for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2016-214339

In the game machine, a program related to the game control process for controlling the progress of the game must be arranged in the used area (control area 4.5 kbyte + data area 3.0 kbyte) in the ROM of the main control board.

However, due to the complexity of the game information according to the variety of games, there is a possibility that the used area, particularly the control area, is compressed.

In view of such a problem, an object of the present invention is to provide a gaming machine capable of securing a capacity of a control area for performing a gaming control process.

In order to solve the above problems, the gaming machine of the present invention has a CPU, a ROM in which a program used for the CPU is stored, and a variable updated by the program on a predetermined board used for the progress of the game. A gaming machine including a RAM to be held, the CPU reads the program from the ROM, and based on the program, sets the value of the first register and the address of the RAM indicated by the second register. The logical sum of the stored value is calculated, and the result of the logical sum is overwritten with the value stored at the address indicated by the second register.

The CPU calculates the logical sum of the value of the first register and the value stored in the address indicated by the second register of the RAM without using a register different from the first register and the second register. It may be calculated directly.

According to the present invention, it is possible to secure the capacity of the control area for performing the game control process.

It is a perspective view of the gaming machine which shows the state which the door is opened which concerns on the simultaneous rotation reference example. It is a front view of the gaming machine which concerns on the simultaneous rotation reference example. It is a figure explaining the 2nd big prize opening which concerns on the simultaneous rotation reference example. It is a block diagram which shows the internal structure of the control means which controls the progress of the game which concerns on the simultaneous rotation reference example. This is an address map of the memory area used by the main CPU according to the simultaneous rotation reference example. It is a figure explaining the low probability jackpot determination random number determination table which concerns on the simultaneous rotation reference example. It is a figure explaining the high probability jackpot determination random number determination table which concerns on the simultaneous rotation reference example. It is a figure explaining the hit symbol random number determination table and the small hit symbol random number determination table which concerns on the simultaneous rotation reference example. It is a figure explaining the reach group determination random number determination table which concerns on the simultaneous rotation reference example. It is a figure explaining the reach mode determination random number determination table which concerns on the simultaneous rotation reference example. It is a figure explaining the variation pattern random number determination table which concerns on the simultaneous rotation reference example. It is a figure explaining the fluctuation time determination table which concerns on the simultaneous rotation reference example. It is a figure explaining the game state and the fluctuation time which concerns on the simultaneous rotation reference example. It is 1st figure explaining the special electric accessory actuating ram set table which concerns on the simultaneous rotation reference example. It is the 2nd figure explaining the special electric accessory actuating ram set table which concerns on the simultaneous rotation reference example. It is a figure explaining the game state setting table which concerns on the simultaneous rotation reference example. It is a figure explaining the hit determination random number determination table which concerns on the simultaneous rotation reference example. (A) is a diagram for explaining the normal symbol fluctuation time data table according to the simultaneous rotation reference example, and (b) is a diagram for explaining the open / close control pattern table according to the simultaneous rotation reference example. It is a figure explaining the transition of the game state according to the original game property which concerns on the simultaneous rotation reference example. It is a figure explaining the transition of the game state when the game is not performed appropriately which concerns on the simultaneous rotation reference example. It is a figure explaining the gaming machine state flag which concerns on the simultaneous rotation reference example. It is the first flowchart explaining the CPU initialization process in the main control board which concerns on the simultaneous rotation reference example. It is the 2nd flowchart explaining the CPU initialization process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the subcommand group set processing in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the evacuation process at the time of power-off in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the timer interrupt processing in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the setting-related processing in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the switch management process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the gate passing process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the 1st start port passing process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the 2nd start port passing process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the special symbol random number acquisition process in the main control board which concerns on a simultaneous rotation reference example. It is a flowchart explaining the effect determination processing at the time of acquisition in the main control board which concerns on a simultaneous rotation reference example. It is a flowchart explaining the big prize opening passing process in the main control board which concerns on the simultaneous rotation reference example. It is a figure explaining the special game management phase and the special electric accessory game management phase which concerns on the simultaneous rotation reference example. It is a flowchart explaining the special game management process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the special symbol change waiting process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the special symbol hit detection process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the special symbol variation number determination process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the count-cutting management process in the main control board which concerns on a simultaneous rotation reference example. It is a flowchart explaining the process during special symbol change in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the symbol forced stop processing in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the special symbol stop symbol display processing in the main control board which concerns on simultaneous rotation reference example. It is a flowchart explaining the special electric accessory game management process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the big prize opening opening preprocessing in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the big prize opening open / close switching process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the big prize opening opening control process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the big prize opening closing effective processing in the main control board which concerns on simultaneous rotation reference example. It is a flowchart explaining the big prize opening end weight processing in the main control board which concerns on the simultaneous rotation reference example. It is a figure explaining the normal game management phase which concerns on the simultaneous rotation reference example. It is a flowchart explaining the normal game management process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the normal symbol change waiting process in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the process during the normal symbol change in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the normal symbol stop symbol display processing in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the processing before opening the winning opening of a normal electric accessory in the main control board which concerns on the simultaneous rotation reference example. It is a flowchart explaining the ordinary electric accessory winning opening opening / closing switching process in the main control board which concerns on simultaneous rotation reference example. It is a flowchart explaining the ordinary electric accessory winning opening opening control process in the main control board which concerns on simultaneous rotation reference example. It is a flowchart explaining the ordinary electric accessory winning opening closure effective processing in the main control board which concerns on simultaneous rotation reference example. It is a flowchart explaining the ordinary electric accessory winning opening end weight processing in the main control board which concerns on simultaneous rotation reference example. It is a figure explaining an example of the variation effect of the variation pattern without reach which concerns on the effect reference example. It is a figure explaining an example of the variation effect of the normal reach variation pattern which concerns on the effect reference example. It is a figure explaining an example of the variation effect of the development reach variation pattern at the time of loss which concerns on the effect reference example. It is a figure explaining an example of the variation effect of the development reach variation pattern at the time of a big hit which concerns on the effect reference example. It is a figure explaining an example of the variation effect when the reach development effect which concerns on the effect reference example is executed twice. It is a figure explaining an example of the variation effect of the pseudo continuous reach variation pattern which concerns on the effect reference example. It is a figure explaining the variation effect decision table which concerns on the effect reference example. It is a figure explaining an example of the hold display effect which concerns on the effect reference example. (A) is a diagram for explaining the final hold display pattern determination table according to the effect reference example, and (b) is a diagram for explaining the previous hold display pattern determination table according to the effect reference example. It is a flowchart explaining the sub-CPU initialization process in the sub-control board which concerns on production reference example. It is a flowchart explaining the subtimer interrupt processing in the sub-control board which concerns on production reference example. It is a flowchart explaining the look-ahead designation command reception process in the sub-control board which concerns on production reference example. It is a flowchart explaining the variation command reception process in the sub-control board which concerns on production reference example. It is an external view for demonstrating the schematic mechanical structure of a slot machine. It is an external view in the state which the front door is opened for demonstrating the schematic mechanical structure of a slot machine. It is a figure explaining the symbol arrangement and effective line of a reel. It is a block diagram which showed the schematic electrical structure of a slot machine. It is explanatory drawing for demonstrating the winning combination. It is a figure which shows the lottery table of a winning type. It is a figure which shows the lottery table of a winning type. It is explanatory drawing for demonstrating transition of a game state. It is explanatory drawing for demonstrating transition of production state. It is a flowchart explaining the CPU initialization process in a main control board. It is a flowchart explaining the cold start process in a main control board. It is a flowchart explaining the error stop processing in a main control board. It is a flowchart explaining the setting value switching process in a main control board. It is a flowchart explaining the initialization start process in a main control board. It is a flowchart explaining the state return processing in a main control board. It is a flowchart explaining the game start processing in a main control board. It is a flowchart explaining the game medal insertion process in a main control board. It is a flowchart explaining the internal lottery process in a main control board. It is a flowchart explaining the symbol code setting process in a main control board. It is a flowchart explaining the process during rotation of a rotating cylinder in a main control board. It is a flowchart explaining the rotation cylinder stop processing in a main control board. It is a flowchart explaining the display determination process in a main control board. It is a flowchart explaining the payout process in a main control board. It is a flowchart explaining the game transition process in a main control board. It is a flowchart explaining the evacuation process at the time of power-off in a main control board. It is a flowchart explaining the timer interrupt processing in a main control board. It is a figure for demonstrating the electrical connection around the main CPU. It is a block diagram which showed the internal structure of a CPU core. It is a figure explaining the structure of a register. It is explanatory drawing which shows the memory map. It is a flowchart which showed the specific process of a BYTESEL module. It is explanatory drawing for demonstrating an example of the command for realizing a BYTESEL module. It is explanatory drawing for demonstrating an example of the command for realizing a BYTESEL module. It is explanatory drawing for demonstrating another example of the command for realizing a BYTESEL module. It is explanatory drawing for demonstrating still another example of the command for realizing a BYTESEL module. It is a flowchart which showed the specific processing of the WORDSEL module. It is explanatory drawing for demonstrating an example of the command for realizing a WORDSEL module. It is explanatory drawing for demonstrating an example of the command for realizing a WORDSEL module. It is explanatory drawing for demonstrating another example of the command for realizing a WORDSEL module. It is explanatory drawing for demonstrating still another example of the command for realizing a WORDSEL module. It is explanatory drawing for demonstrating the CAL_MOD module. It is explanatory drawing for demonstrating the HID_JUG module. It is a flowchart which showed the specific processing of a RAMSET module. It is explanatory drawing for demonstrating an example of the command for realizing a RAMSET module. It is explanatory drawing for demonstrating an example of the command for realizing a RAMSET module. It is explanatory drawing for demonstrating another example of the command for realizing a RAMSET module. It is explanatory drawing for demonstrating an example of a command for realizing a TABLESET module. It is explanatory drawing for demonstrating another example of the command for realizing a TABLESET module. It is a flowchart which showed the specific process of a BYTEDEC module. It is explanatory drawing for demonstrating the decrement mode and setting of a zero flag and a carry flag in a BYTEDEC module. It is explanatory drawing for demonstrating an example of the command for realizing a BYTEDEC module. It is explanatory drawing for demonstrating another example of the command for realizing a BYTEDEC module. It is explanatory drawing for demonstrating a RAM_DEC module. It is a flowchart which showed the specific processing of the WORDDEC module. It is explanatory drawing for demonstrating an example of the command for realizing a WORDDEC module. It is explanatory drawing for demonstrating another example of the command for realizing a WORDDEC module. It is explanatory drawing for demonstrating an example of the process which returns from a subroutine. It is explanatory drawing for demonstrating the PY_CMDA module. It is explanatory drawing for demonstrating the GAT_PAS module. It is explanatory drawing for demonstrating the TDN_PAS module. It is explanatory drawing for demonstrating the FD_OPN module. It is explanatory drawing for demonstrating the TZ_STA module. It is explanatory drawing for demonstrating the TZ_RGET module. It is explanatory drawing for demonstrating the TRSVSEL module. It is explanatory drawing for demonstrating the TDOVCHK module. It is explanatory drawing for demonstrating the BER_CHK module. It is explanatory drawing for demonstrating the TEF_SEL module. It is explanatory drawing for demonstrating the SET_RIG module. It is explanatory drawing for demonstrating the PRE_LOT module. It is explanatory drawing for demonstrating the REG_LOT module. It is explanatory drawing for demonstrating the BIG_SLT module. It is explanatory drawing for demonstrating the NAV_SET module. It is a flowchart which showed the specific processing of the TOK_PRC module. It is explanatory drawing for demonstrating an example of the command for realizing the TOK_PRC module. It is a flowchart which showed the specific processing of a TEF_SEL module. It is explanatory drawing for demonstrating an example of the command for realizing a TEF_SEL module. It is a flowchart which showed the specific processing of the SWI_PRC module. It is explanatory drawing for demonstrating an example of the command for realizing the SWI_PRC module. It is a flowchart which showed the specific processing of a CPUINIT module. It is explanatory drawing for demonstrating an example of the command for realizing a CPUINIT module. It is explanatory drawing for demonstrating the TMR_IPT module. It is a flowchart which showed the specific processing of the FZ_SPN module. It is explanatory drawing for demonstrating an example of the command for realizing the FZ_SPN module. It is explanatory drawing for demonstrating an example of the command for realizing a CPUINIT module. It is explanatory drawing for demonstrating an example of the command for realizing an EXE_SET module. It is a flowchart which showed the specific processing of HPT_GRP module. (A) and (b) are explanatory diagrams for explaining an example of a command for realizing an HPT_GRP module, and (c) is an explanatory diagram for explaining an example of a reach group determination random number determination table. be. It is explanatory drawing for demonstrating the E_ILGER module. It is explanatory drawing for demonstrating the E_LEVOT module. It is a flowchart which showed the specific processing of the SBC_OUT module. It is explanatory drawing for demonstrating an example of the command for realizing the SBC_OUT module. It is explanatory drawing for demonstrating an example of another command for realizing the SBC_OUT module. It is explanatory drawing for demonstrating an example of the command for realizing the FZ_OPN module. It is explanatory drawing for demonstrating an example of the command for realizing a TD_OPN module. It is explanatory drawing for demonstrating an example of the command for realizing the HSY_PRC module. It is explanatory drawing for demonstrating an example of the command for realizing the FDN_CHK module. It is explanatory drawing for demonstrating an example of the command for realizing FZ_STP module. It is a block diagram for demonstrating the structure of the random number generator 740-746. It is a figure explaining the combination of the random number generation part. It is a flowchart which showed the specific processing of the SMC_ROT module. It is explanatory drawing for demonstrating an example of the command for realizing the SMC_ROT module. It is explanatory drawing for demonstrating another example of the command for realizing the SMC_ROT module. It is a flowchart which showed the specific processing of the INITIAL module. It is explanatory drawing for demonstrating an example of a command for realizing an INITIAL module. It is explanatory drawing for demonstrating another example of the command for realizing an INITIAL module. It is explanatory drawing for demonstrating the RANKSET module. It is explanatory drawing for demonstrating the PWRFAIL module. It is explanatory drawing for demonstrating the DYM_OUT module. It is a flowchart which showed the specific processing of the IPT_PD module. It is explanatory drawing for demonstrating an example of the command for realizing the IPT_PD module. It is explanatory drawing for demonstrating another example of the command for realizing the IPT_PD module. It is explanatory drawing for demonstrating the DYNMOUT module. It is explanatory drawing for demonstrating the EXT_PRC module. It is a flowchart which showed the specific process of a STOPDCT module. It is explanatory drawing for demonstrating an example of the command for realizing a STOPDCT module. It is explanatory drawing for demonstrating another example of the command for realizing a STOPDCT module. It is a flowchart which showed the specific processing of the E_SETTM module. It is explanatory drawing for demonstrating an example of the command for realizing the E_SETTM module. It is explanatory drawing for demonstrating another example of the command for realizing the E_SETTM module. It is explanatory drawing for demonstrating the DYM_OUT module. It is explanatory drawing for demonstrating the DYM_OUT module. It is a flowchart which showed the specific processing of the E_SETTM module. It is explanatory drawing for demonstrating still another example of the command for realizing an E_SETTM module. It is a flowchart which showed the specific processing of a RAM_INC module. It is explanatory drawing for demonstrating an example of the command for realizing a RAM_INC module. It is explanatory drawing for demonstrating an example of the command for realizing a RAM_INC module. It is explanatory drawing for demonstrating another example of the command for realizing a RAM_INC module. It is explanatory drawing for demonstrating another example of the command for realizing a RAM_INC module. It is a flowchart which showed the specific processing of the TABLEST module. It is explanatory drawing for demonstrating an example of a command for realizing a TABLESET module. It is explanatory drawing for demonstrating an example of a command for realizing a TABLESET module. It is explanatory drawing for demonstrating another example of the command for realizing a TABLESET module. It is a flowchart which showed the specific processing of the IPT_PC module. It is explanatory drawing for demonstrating an example of the command for realizing the IPT_PC module. It is a flowchart which showed the specific processing of the CMDPROC module. It is explanatory drawing for demonstrating an example of the command for realizing a CMDPROC module. It is a flowchart which showed the specific processing of the SET_PLS module. It is explanatory drawing for demonstrating an example of the command for realizing a SET_PLS module. It is a flowchart which showed the specific processing of the OTM_ATK module. It is explanatory drawing for demonstrating an example of the command for realizing the OTM_ATK module. It is explanatory drawing for demonstrating an example of the command for realizing a KRS_JDG module. It is explanatory drawing for demonstrating another example of the command for realizing a KRS_JDG module. It is a figure explaining the structure of the main control board. It is a figure explaining the fixing of the electronic component in the main control board. It is a figure explaining the via hole in the main control board. It is a figure explaining an example of a specific effect. It is a figure explaining an example of suggestion effect. It is a figure explaining an example of the suggestion effect of the 1st suggestion pattern. It is a figure explaining an example of the suggestion effect of the 2nd suggestion pattern. It is a figure explaining an example of the suggestion effect of the 3rd suggestion pattern. (A) is a diagram for explaining an example of specific fluctuation information, and (b) is a diagram for explaining an example of the occurrence timing of a specific effect. It is a figure explaining the specific effect execution lottery table. (A) is a diagram for explaining the effect system determination table, and (b) is a diagram for explaining the additional lottery table. It is a figure explaining the suggestion effect decision table. It is a figure explaining the earned point lottery table. It is a flowchart explaining the sub-CPU initialization process in a sub-control board. It is a flowchart explaining the subtimer interrupt processing in a sub-control board. It is a flowchart explaining the look-ahead designation command reception process in a sub-control board. It is a flowchart explaining the variable command reception processing in a sub-control board.

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The dimensions, materials, other specific numerical values, etc. shown in the embodiment are merely examples for facilitating the understanding of the invention, and do not limit the present invention unless otherwise specified. In the present specification and drawings, elements having substantially the same function and configuration are designated by the same reference numerals to omit duplicate description, and elements not directly related to the present invention are not shown. do.

In the embodiment of the present invention, pachinko machines and slot machines are illustrated in this order as gaming machines, and then specific processing will be described in detail.

<Pachinko machine>
In order to facilitate understanding of the embodiments of the present invention, first, as reference examples of simultaneous rotation, the mechanical configuration and electrical configuration of a so-called simultaneous rotation machine, and specific processing on each substrate will be described. Then, as a reference example of the effect, a specific effect that can be executed by the simultaneous turning machine and a specific process related to the effect will be described. Then, as an example of the present invention, a configuration different from each reference example will be specifically described.

<Simultaneous rotation reference example>
FIG. 1 is a perspective view of the gaming machine 100 according to the simultaneous turning reference example, and shows a state in which the door is opened. As shown in the figure, the gaming machine 100 includes an outer frame 102 in which a surrounding space is formed by four sides assembled in a substantially rectangular shape, and an inner frame 104 that is openably and closably attached to the outer frame 102 by a hinge mechanism. The middle frame 104 is provided with a front frame 106 that is openably and closably attached by a hinge mechanism.

Similar to the outer frame 102, the middle frame 104 has a surrounding space formed by four sides assembled in a substantially rectangular shape, and the game board 108 is held in the surrounding space. Further, the front frame 106 holds a transparent plate 110 made of glass or resin. When the middle frame 104 and the front frame 106 are closed with respect to the outer frame 102, the game board 108 and the transmission plate 110 face each other substantially in parallel while maintaining a predetermined interval, and from the front side of the game machine 100. , The game board 108 becomes visible through the transparent plate 110.

FIG. 2 is a front view of the gaming machine 100 according to the simultaneous turning reference example. As shown in this figure, an operation handle 112 projecting to the front side of the gaming machine 100 is provided at the lower part of the front frame 106. The operation handle 112 is provided so that the player can rotate the operation handle 112, and when the player rotates the operation handle 112 to perform a firing operation, the strength corresponding to the rotation angle of the operation handle 112 is not shown (not shown). A game ball is launched by the launch mechanism. The game ball launched in this way rises between the rails 114a and 114b provided on the game board 108 and is guided to the game area 116.

The game area 116 is a space formed at a distance between the game board 108 and the transmission plate 110, and is an area in which the game ball can flow down or roll. The game board 108 is provided with a large number of nails and windmills (not shown) so that the game ball guided to the game area 116 collides with the nails and windmills and flows down and rolls in an irregular direction. I have to.

The game area 116 includes a first game area 116a and a second game area 116b in which the degree of entry of the game balls is different from each other according to the firing intensity of the firing mechanism and the game balls can be hit separately. The first gaming area 116a is located on the left side of the gaming area 116 as seen from the player facing the gaming machine 100, and the second gaming area 116b is the gaming area 116 as seen by the player facing the gaming machine 100. It is located on the right side of. Since the rails 114a and 114b are on the left side of the game area 116, the game ball launched by the launch mechanism with a launch intensity lower than the predetermined intensity enters the first game area 116a and is launched with a launch intensity equal to or higher than the predetermined intensity. The resulting game ball enters the second game area 116b.

Further, the game area 116 is provided with a general winning opening 118, a first fixed starting port 120A, a first variable starting port 120B, a second starting port 122, and a normal drawing operating port 125 in which a game ball can enter. When a game ball enters these general winning openings 118, the first fixed starting opening 120A, the first variable starting opening 120B, the second starting opening 122, and the normal drawing operating opening 125, predetermined prize balls are paid out to the player. Is done. In the following, the first fixed starting port 120A and the first variable starting port 120B will be collectively referred to as the first starting port 120.

As will be described in detail later, a first starting area is provided in the first starting port 120, and a second starting area is provided in the second starting port 122. Then, when the game ball enters the first starting port 120 or the second starting port 122 and the game ball enters the first starting area or the second starting area, any one of a plurality of special symbols provided in advance is provided. A lottery is held to determine the special symbol of 1. Each special symbol is associated with whether or not a large role game or a small hit game, which is advantageous for the player, can be executed. Therefore, when the game ball enters the first start port 120 or the second start port 122, the player obtains a predetermined prize ball and at the same time obtains an opportunity to acquire the right to receive various game benefits. It becomes.

Further, the first fixed starting port 120A, the second starting port 122, and the normal drawing operating port 125 are configured by a fixed starting port that is open so that the game ball can always enter. On the other hand, the first variable starting port 120B is provided with a movable piece 120b that can be opened and closed, and the ease of entry of the game ball into the first variable starting port 120B changes according to the state of the movable piece 120b. It consists of a variable starting port. Specifically, the movable piece 120b is normally maintained in a closed state, during which time it becomes difficult or impossible for the game ball to enter the first variable starting port 120B.

On the other hand, when the game ball passes through the gate 124 provided in the game area 116 (second game area 116b) or the game ball enters the normal drawing operation port 125, a lottery of the normal symbol described later is performed. If a winner is won by this lottery, the movable piece 120b is controlled to be in the open state for a predetermined time. When the movable piece 120b is opened, the game ball can enter the first variable starting port 120B. As described above, the movable piece 120b is in an open state that allows the game ball to enter the first variable start port 120B, and it is more difficult for the game ball to enter the first variable start port 120B than in the open state. Alternatively, it functions as a movable member (starting variable winning device) that shifts to an impossible closed state.

In addition, only the game ball flowing down the first game area 116a can enter the first fixed start port 120A, and the first variable start port 120B and the second start port 122 flow down the second game area 116b. It is arranged in a position where only the ball can enter. A game ball flowing down the second game area 116b may enter the first fixed start port 120A, but in this case, the game ball flowing down the first game area 116a is the second ball. It is desirable to arrange the game area 116b at a position where it is easier to enter the ball than the game ball flowing down.

Similarly, the first variable start port 120B and the second start port 122 may be filled with a game ball flowing down the first game area 116a, but in this case, a game flowing down the second game area 116b. It is desirable that the ball is arranged at a position where it is easier to enter the ball than the game ball flowing down the first game area 116a. In any case, the first fixed start port 120A is arranged at a position where a game ball flowing down at least the first game area 116a can enter, and the first variable start port 120B and the second start port 122 are at least the first. 2 It is preferable that the game ball flowing down the game area 116b is arranged at a position where the ball can enter.

Further, the second game area 116b is provided with a first large winning opening 126 and a second large winning opening 128. The first prize opening 126 and the second prize opening 128 are arranged at positions where only the game balls flowing down the second game area 116b can enter. However, the first special winning opening 126 and the second large winning opening 128 may be arranged so that any game ball flowing down the first game area 116a and the second game area 116b can be entered.

An opening / closing door 126b is provided in the first large winning opening 126 so as to be openable / closable. Normally, the opening / closing door 126b closes the first large winning opening 126 to allow a game ball to enter the first large winning opening 126. The ball is impossible. Specifically, the opening / closing door 126b is in a state of being flush with the board surface of the game board 108 in the closed state, and the game ball flows down in front of the first large winning opening 126. On the other hand, when the above-mentioned big role game is executed, the opening / closing door 126b is opened and functions as a saucer for guiding the game ball to the first big winning opening 126, and the game ball enters the first big winning opening 126. A sphere is possible. Then, when the game ball enters the first prize opening 126, the predetermined prize ball is paid out to the player.

The second prize opening 128 is provided below the first prize opening 126 in the second game area 116b. The second large winning opening 128 includes a movable piece 128b, and the movable piece 128b is normally maintained in a closed state. On the other hand, when the small hit game described later is executed, the movable piece 128b is controlled to be in the open state, and the game ball can enter the second large winning opening 128. In the following, the first large winning opening 126 and the second large winning opening 128 will be collectively referred to as a large winning opening.

FIG. 3 is a diagram for explaining the second large winning opening 128 according to the simultaneous turning reference example. The second game area 116b is provided with a structure 129 that projects toward the front side of the game board 108. The structure 129 is surrounded by four sides and a bottom side located in the left-right direction and the front-back direction of the gaming machine 100, and an opening is formed in the upper portion. The opening formed in the upper part of the structure 129 becomes the second large winning opening 128. A movable piece 128b is provided on the upper part of the structure 129, and normally, as shown in FIG. 3A, the movable piece 128b is maintained in a closed state in which the second special winning opening 128 is closed. ..

The movable piece 128b projects into the game area 116 in which the game ball rolls and flows down so as to face above the game machine 100. Therefore, when the movable piece 128b is maintained in the closed state, the game ball flowing down the game area 116 (second game area 116b) falls onto the movable piece 128b. Here, the bases of the structure 129 are substantially parallel in the horizontal direction, and the right side surface of the gaming machine 100 has a dimensional relationship slightly longer in the height direction than the left side surface. Therefore, in the second prize opening 128, the left side of the gaming machine 100 is slightly lower than the right side, and the movable piece 128b maintained in the closed state is located so that the left side of the gaming machine 100 is slightly lower than the right side. It is inclined to. Therefore, when the movable piece 128b is in the closed state, as shown by the arrow in FIG. 3A, the game ball that has fallen on the movable piece 128b slowly rolls on the movable piece 128b from right to left. It will move.

Then, when the small hit game described later is executed, the movable piece 128b shifts to an open state in which the second large winning opening 128 is opened. Here, as shown in FIG. 3B, the movable piece 128b shifts from the closed state to the open state by sliding toward the back side of the game board 108. As a result, when the state changes from the closed state to the open state, the game ball rolling on the movable piece 128b falls into the second large winning opening 128 by its own weight.

As described above, in the simultaneous rotation reference example, the movable piece 128b is slightly tilted to secure a long time for the game ball to roll on the movable piece 128b. Then, by changing the movable piece 128b from the closed state to the open state, the game ball rolling on the movable piece 128b is guided into the second large winning opening 128. With the above configuration, a predetermined number of game balls can be guided into the second large winning opening 128 even if the time for maintaining the movable piece 128b in the open state is slightly set. In other words, the time required to keep the movable piece 128b in the open state, which is required to allow a predetermined number of game balls to enter the second large winning opening 128, can be shortened. A hole communicating with the back side of the game board 108 is formed on the back surface of the structure 129, and the game ball that has entered the second special winning opening 128 is discharged to the back side of the game board 108. .. Then, when the game ball enters the second prize opening 128, the predetermined prize ball is paid out to the player.

Although the configuration of the second large winning opening 128 has been described here, the first variable starting port 120B also has the same configuration as the second large winning opening 128. That is, the movable piece 120b of the first variable starting port 120B projects toward the front side of the game board 108 in the closed state, and the game ball rolls on the movable piece 120b. Then, in the open state of the movable piece 120b, the movable piece 120b slides to the back side of the game board 108, and the game ball can enter the first variable starting port 120B. However, as shown in FIG. 2, the movable piece 128b has the right side higher than the left side in the front view of the gaming machine 100, whereas the movable piece 120b has the left side on the right side in the front view of the gaming machine 100. It is in a higher position than.

Here, the board surface configuration of the second game area 116b will be described in detail. In the simultaneous rotation reference example, the second starting port 122 and the gate 124 are arranged in parallel at the uppermost portion of the second game area 116b. All the game balls guided to the second game area 116b enter the second starting port 122 or pass through the gate 124 and flow downward. In the simultaneous rotation reference example, one game ball is paid out as a prize ball for each ball entering the second starting port 122.

When a game ball enters the second starting port 122, one game ball is paid out as a prize ball, and a lottery is performed to determine whether or not a large role game or a small hit game is executed. Further, when the game ball passes through the gate 124, a lottery is performed to determine whether or not to open the first variable starting port 120B (movable piece 120b).

Directly below the second starting port 122 and the gate 124, the first large winning opening 126 is provided. When the first big winning opening 126 is in the open state, all the game balls that have passed through the gate 124 and flowed downward are arranged so as to enter the first big winning opening 126. In the simultaneous turning reference example, the first large winning opening 126 is opened only in the large role game. That is, it can be said that the first large winning opening 126 is a large winning opening dedicated to the big role game. When a game ball enters the first prize opening 126 during a major role game, two or more predetermined numbers (15 in this case) of the game balls are paid out as prize balls for each ball entered. ..

A first variable starting port 120B is provided below the first winning opening 126. Further, an out port 131 is provided between the first large winning opening 126 and the first variable starting port 120B. The out port 131 is an entrance of a passage for discharging the game ball from the game area 116, and even if the game ball enters the out port 131, the prize ball is not paid out.

In the second game area 116b, nails are arranged so that most of the game balls (for example, 90% or more) that have flowed down below the first prize opening 126 fall onto the movable piece 120b. Further, by these nails, a part (for example, 1% to 10%) of the game balls that have flowed down below the first winning opening 126 is guided to the out opening 131.

In the closed state of the first variable starting port 120B, the game ball rolls on the movable piece 120b. If the movable piece 120b is opened while the game ball is rolling on the movable piece 120b, all the game balls on the movable piece 120b are guided into the first variable starting port 120B. When a game ball enters the first variable starting port 120B, one game ball is paid out as a prize ball for each ball entering, and whether or not a large role game or a small hit game is executed is determined. A lottery will be held.

The gaming ball that has not entered the first variable starting port 120B falls from above the movable piece 120b to the right side when viewed from the front of the gaming machine 100. A second big winning opening 128 is provided below the first variable starting opening 120B, and most of the game balls that have fallen from the movable piece 120b roll on the movable piece 128b of the second big winning opening 128. do. The game ball on the movable piece 128b slowly rolls from the right side to the left side in the front view of the game machine 100 due to the inclination of the movable piece 128b.

Although details will be described later, in the simultaneous rotation reference example, the second large winning opening 128 is opened only in the small hit game. That is, it can be said that the second large winning opening 128 is a large winning opening dedicated to small hit games. If the movable piece 128b is opened while the game ball is rolling on the movable piece 128b, all the game balls on the movable piece 128b are guided into the second large winning opening 128. When a game ball enters the second large winning opening 128 during a small hit game, two or more predetermined number of game balls (15 in this case) are paid out as prize balls for each ball entered. Is done.

At the lower left of the second large winning opening 128, a normal drawing operating opening 125 is provided. Here, nails are arranged in the second game area 116b so that almost all the game balls that have fallen downward from the second large winning opening 128 enter the normal drawing operating port 125. In the simultaneous rotation reference example, the normal drawing operating port 125 constitutes a "specific winning opening" in which one game ball is paid out as a prize ball for each entering ball of the game ball. Further, when the game ball enters the normal drawing operating port 125, it is determined whether or not to open the first variable starting port 120B (movable piece 120b) in the same manner as when the game ball passes through the gate 124. A lottery will be held.

At the bottom of the game area 116, a game ball that did not enter any of the general winning opening 118, the first starting opening 120, the second starting opening 122, the normal drawing operating opening 125, and the large winning opening. Is provided on the back side of the game board 108 from the game area 116.

The gaming machine 100 is controlled by an effect display device 200 composed of a liquid crystal display device, an effect accessory device 202 composed of a movable device, and various lighting modes and emission colors as an effect device for producing an effect while the game is in progress. An effect lighting device 204 composed of a lamp, an audio output device 206 composed of a speaker, and an effect operation device 208 that receives an operation of a player are provided.

The effect display device 200 includes a main effect display unit 200a including an image display unit for displaying an image, and the main effect display unit 200a is visually recognized from the front side of the game machine 100 at a substantially central portion of the game board 108. Arranged as possible. As shown in the figure, the main effect display unit 200a is subjected to various effects such as variable display of the three effect symbols 210a, 210b, 210c.

The effect accessory device 202 is arranged in front of the main effect display unit 200a, and is normally retracted in a state of being divided into a plurality of constituent members at the origin position on the back side of the game board 108, so that the player can evacuate. It is not visible. Then, when each component moves to a movable position on the front surface of the main effect display unit 200a by driving the actuator during the variable display of the effect symbols 210a, 210b, 210c, the front surface of the main effect display unit 200a. Each component is united to give the player a sense of expectation of a big hit.

The effect lighting device 204 is provided on the effect accessory device 202, the game board 108, and the like, and is variously controlled to be lit according to an image or the like displayed on the main effect display unit 200a.

The audio output device 206 is provided at the upper position of the front frame 106 and the lowermost position of the outer frame 102, and is variously directed toward the front side of the gaming machine 100 according to an image or the like displayed on the main effect display unit 200a. Output audio.

The effect operation device 208 is composed of buttons that receive a player's pressing operation, is provided at a substantially central position in the width direction of the game machine 100, and is provided at a position below the transmission plate 110. The effect operation device 208 is activated according to an image or the like displayed on the main effect display unit 200a, and when the player's operation is received within the operation effective time, various operations are performed according to the operation. The production is executed.

Reference numeral 132 in the figure is an upper plate on which a prize ball paid out from the game machine 100 and a game ball rented from the game ball lending device are guided. It will be guided to the lower plate 134. Further, on the bottom surface of the lower plate 134, a ball extraction hole (not shown) for discharging the game ball from the lower plate 134 is formed. This ball extraction hole is normally closed by an opening / closing plate (not shown), but by pressing the ball extraction knob 134a, the opening / closing plate slides integrally with the ball extraction knob 134a, and the ball extraction hole It is possible to discharge the game ball below the lower plate 134.

Further, on the game board 108, the first special symbol display 160, the second special symbol display 162, and the first special symbol are held at a position outside the game area 116 and visible to the player. A display 164, a second special symbol hold display 166, a normal symbol display 168, a normal symbol hold display 170, and a right-handed notification display 172 are provided. Each of these indicators 160 to 172 is a device for displaying various situations related to the game, and the details thereof will be described later.

(Internal configuration of control means)
FIG. 4 is a block diagram showing an internal configuration of a control means for controlling the progress of the game according to the simultaneous rotation reference example.

The main control board 300 controls the basic operation of the game. The main control board 300 includes a main CPU 300a, a main ROM 300b, and a main RAM 300c. Based on the input signals from each detection switch and timer, the main CPU 300a reads the program stored in the main ROM 300b and performs arithmetic processing, directly controls each device and display, or produces the result of arithmetic processing. Send commands to other boards accordingly. The main RAM 300c functions as a data work area during arithmetic processing of the main CPU 300a.

The main control board 300 has a general winning opening detection switch 118s for detecting that a game ball has entered the general winning opening 118, and a first fixed device for detecting that a game ball has entered the first fixed starting port 120A. A second variable start port detection switch 120Bs, which detects that a game ball has entered the first variable start port 120B, and a second variable start port detection switch 120Bs, which detects that a game ball has entered the second start port 122. Start port detection switch 122s, gate detection switch 124s for detecting that the game ball has passed through the gate 124, normal figure operation port detection switch 125s for detecting that the game ball has entered the normal figure operation port 125, first large The first large winning opening detection switch 126s that detects that a game ball has entered the winning opening 126 and the second large winning opening detection switch 128s that detects that a game ball has entered the second large winning opening 128 are connected. A detection signal is input to the main control board 300 from each of these detection switches.

Further, on the main control board 300, a normal electric accessory solenoid 120c that operates the movable piece 120b of the first variable starting port 120B and a first large winning opening that operates the opening / closing door 126b that opens and closes the first large winning opening 126 The solenoid 126c and the second large winning opening solenoid 128c that operates the movable piece 128b that opens and closes the second large winning opening 128 are connected, and the first variable starting port 120B and the first large are connected by the main control board 300. The opening and closing control of the winning opening 126 and the second major winning opening 128 is performed.

Further, the main control board 300 includes a first special symbol display 160, a second special symbol display 162, a first special symbol hold indicator 164, a second special symbol hold indicator 166, a normal symbol display 168, and a normal symbol display. The symbol hold indicator 170 and the right-handed notification indicator 172 are connected, and the display control of each of these indicators is performed by the main control board 300.

Further, a setting change switch 180s is provided on the back surface of the game board 108. The setting change switch 180s is configured to be accessible by a dedicated key. The operation of changing and confirming the set value is possible on condition that the setting change switch 180s is turned on. As will be described in detail later, in the gaming machine 100 of the simultaneous rotation reference example, one of the six levels of set values having different degrees of advantage is stored as a registered set value in the set value buffer, and according to the stored registered set value. The game progresses. Here, the set value is set in 6 stages, but the set value may be provided in only 2 stages of high setting and low setting, or may be provided in other plurality of stages. Furthermore, the set value is not essential and the degree of advantage does not have to be changed.

Further, a RAM clear button is provided on the back surface of the game board 108 so that it can be pressed, and the operation of pressing the RAM clear button is detected by the RAM clear switch 182s. The RAM clear switch 182s is connected to the main control board 300, and a RAM clear operation signal is input from the RAM clear switch 182s to the main control board 300. When the RAM clear operation signal is input from the RAM clear switch 182s when the power is turned on, the main CPU 300a clears the main RAM 300c.

A performance display monitor 184 is provided on the back surface of the game board 108. The main control board 300 displays the registered set value and the base ratio on the performance display monitor 184.

Further, the gaming machine 100 of the simultaneous turning reference example mainly includes a special game started by entering the gaming ball into the first starting port 120 or the second starting opening 122, and the passing of the gaming ball through the gate 124, or , It is roughly divided into a normal game started by entering a game ball into the normal drawing operation port 125. The main ROM 300b of the main control board 300 stores various programs for advancing special games and normal games, as well as data and tables required for various games.

Further, the payout control board 310 and the sub control board 330 are connected to the main control board 300. The payout control board 310 controls for firing the game ball and controls for paying out the prize ball. The payout control board 310 also includes a CPU, a ROM, and a RAM, and is connected to the main control board 300 so as to be able to communicate in both directions. A game information output terminal board 312 is connected to the payout control board 310, and various information on the game progress output from the main control board 300 is transmitted via the payout control board 310 and the game information output terminal board 312. , Will be output to the hall computer of the amusement store.

Further, a payout motor 314 for paying out the game balls stored in the storage unit to the player as prize balls is connected to the payout control board 310. The payout control board 310 controls the payout motor 314 based on the payout number designation command transmitted from the main control board 300 to control the player to pay out a predetermined prize ball. At this time, the number of game balls paid out is detected by the payout ball counting switch 316s, and it is possible to grasp whether the prize balls to be paid out have been paid out to the player.

Further, a plate full tank detection switch 318s for detecting the full tank state of the lower plate 134 is connected to the payout control board 310. The plate full tank detection switch 318s is provided in a passage leading the game ball to be paid out as a prize ball to the lower plate 134, and the game ball detection signal is input to the payout control board 310.

Then, when a predetermined amount or more of the game balls are stored in the lower plate 134 and the tank is full, the game balls stay in the passage toward the lower plate 134, and the plate full tank detection switch 318s is directed toward the payout control board 310. , The game ball detection signal is continuously input. When the game ball detection signal is continuously input for a predetermined time, the payout control board 310 determines that the lower plate 134 is in a full tank state, and transmits a plate full tank command to the main control board 300. On the other hand, if the continuous input of the game ball detection signal is interrupted after the dish full tank command is transmitted, it is determined that the full tank state has been released, and the dish full tank release command is transmitted to the main control board 300.

Further, the payout control board 310 is provided with a launch control circuit 320 that controls launch of the game ball. The payout control board 310 is provided with an operation handle 112, and is connected to a touch sensor 112s for detecting that the player touches the operation handle 112 and an operation volume 112a for detecting the operation angle of the operation handle 112. ing. Then, when a signal is input from the touch sensor 112s and the operation volume 112a, the launch control circuit 320 controls to energize the launch solenoid 112c provided in the game ball launcher to launch the game ball.

The sub-control board 330 mainly controls each effect such as during a game or during standby. The sub control board 330 includes a sub CPU 330a, a sub ROM 330b, and a sub RAM 330c, and is connected to the main control board 300 so as to be communicable from the main control board 300 to the sub control board 330 in one direction. .. The sub CPU 330a reads the program stored in the sub ROM 330b, performs arithmetic processing, and executes and controls the effect based on the command transmitted from the main control board 300, the input signal from the timer, and the like. At this time, the sub RAM 330c functions as a data work area during the arithmetic processing of the sub CPU 330a.

Specifically, in the sub control board 330, the sub CPU 330a, the sub ROM 330b, and the sub RAM 330c cooperate to function as a sub main, an image control unit, an accessory control unit, a lighting control unit, and a voice control unit. The sub-main determines the content of the effect to be executed and manages and supervises the execution of the effect according to various input commands. The image control unit performs image display control for displaying an image on the main effect display unit 200a. The sub ROM 330b stores a large amount of image data such as patterns, backgrounds, and subtitles displayed on the main effect display unit 200a, and the image control unit reads the image data from the sub ROM 330b into a VRAM (not shown) and mains the image data. Controls the image display of the effect display unit 200a.

Further, the accessory control unit drives the actuator according to the management of the effect by the sub-main, and movably controls the effect device 202. The lighting control unit controls the lighting of the effect lighting device 204. In addition, the voice control unit performs voice output control for outputting voice from the voice output device 206. A large amount of audio data such as audio and music output from the audio output device 206 is stored in the sub ROM 330b, and the audio control unit reads the audio data from the sub ROM 330b and controls the audio output of the audio output device 206. do.

Further, the sub-control board 330 executes a predetermined effect when an operation detection signal is input from the effect operation device detection switch 208s that detects that the effect operation device 208 has been pressed or rotated.

A power supply board (not shown) is connected to each board, and power is supplied to each board from a commercial power source via the power supply board. Further, the power supply board is provided with a backup power supply composed of a capacitor.

FIG. 5 is an address map of a memory area used by the main CPU 300a according to the simultaneous rotation reference example. In FIG. 5, the address is shown in hexadecimal, and "H" is shown in hexadecimal. As shown in FIG. 5, the memory area used by the main CPU 300a includes a memory area (0000H to 2FFFH) allocated to the main ROM 300b and a memory area (F000H to F3FFH) allocated to the main RAM 300c.

The memory area of the main ROM 300b is a used area (0000H to 1BF3H) for storing a program and data for controlling the progress of the game, and an area other than the used area, and is a process for performing a test specified by the game machine rules. An unused area (2000H to 2BFFF) for storing a program and data for executing a process for displaying the performance display monitor 184 (including a process for calculating the base ratio displayed on the performance display monitor 184). And are provided.

The used area of the main ROM 300b includes a program area (0000H to 0A89H) in which a program for controlling the progress of the game is stored, an unused area (0A8AH to 11FFH), and a data area (1200H) in which data other than the program is stored. ~ 1BF3H) is provided. The used area may not include an unused area (0A8AH to 0FFFH).

The non-use area of the main ROM 300b is a program area (2000H to 27FFH) in which a program for executing a process for performing a test specified by the game machine rules and a process for displaying the performance display monitor 184 is stored. A data area (2800H to 2BFFH) for storing data other than these programs is provided.

In addition to the used area and the unused area, the memory area of the main ROM 300b is a ROM comment area (1E00H to 1EFFH) in which arbitrary data such as an unused area (1A7BH to 1DFFH), a program title, and a version are stored. ), An unused area (1F00H to 1FFFH), an unused area (2C00H to 2FBFH), and a program management area (2FC0H to 2FFFH) in which information necessary for the main CPU 300a to execute a program is stored.

The memory area of the main RAM 300c is a used area (F000H to F1FFH) temporarily used when a program for controlling the progress of the game is executed, and an area other than the used area, according to the rules of the gaming machine. An unused area (F210H to F228H) that is temporarily used when a program for performing a predetermined test or a process for displaying the performance display monitor 184 is executed is provided.

The used area of the main RAM 300c includes a work area (F000H to F12AH) temporarily used when a program for controlling the progress of the game is executed, an unused area (F12BH to F1D7H), and the progress of the game. A stack area (F1D8H to F1FFH) for temporarily saving data during execution of a control program is provided. The used area may not include an unused area (F12BH to F1D7H).

In the non-use area of the main RAM 300c, a work area (F210H) temporarily used when a processing program for performing a test specified by the game machine rules and a processing program for displaying the performance display monitor 184 is being executed. ~ F21FH), and stack areas (F220H to F228H) for temporarily saving data when these programs are being executed are provided.

Further, in the memory area of the main RAM 300c, an unused area (F200H to F20FH) and an unused area (F229H to F3FFH) are provided in addition to the used area and the unused area.

As described above, in the main ROM 300b and the main RAM 300c, the used area used for controlling the progress of the game, the process for performing the test specified by the game machine rules, and the process for controlling the display of the performance display monitor 184. It is provided separately from the unused area used to execute.

In the main RAM 300c, a 16-byte unused area (F200H to F20FH) is provided between the used area and the unused area. The unused areas (F200H to F20FH) are set as boundary areas that separate the used area and the unused area, and the boundary between the used area and the unused area is clarified, and a program for controlling the progress of the game is provided. When the unused area is used during execution, and when the program for performing the test specified by the game machine rules and the processing for controlling the display of the performance display monitor 184 is being executed. It prevents the used area from being used.

The unused area provided between the used area and the unused area may be at least 1 byte or more, preferably 4 bytes or more from the viewpoint of fraud prevention, and is set to 16 bytes or more. Is more desirable. Further, although the unused area is prohibited from writing and reading data, it may be cleared at a predetermined timing from the viewpoint of preventing fraud.

Further, input / output units are assigned to the memory spaces of FE00h to FEFFh. Such an input / output unit will be described in detail later.

Next, the game in the gaming machine 100 of the simultaneous rotation reference example will be described together with various tables stored in the main ROM 300b.

As described above, in the gaming machine 100 of the simultaneous rotation reference example, two types of games, a special game and a normal game, proceed in parallel. In the special game, the game progresses in one of the low-probability game state and the high-probability game state, and the normal game is in any of the non-time-short game state, the medium-time short-time game state, and the short-time game state. The game progresses.

The details of each game state will be described later, but the low-probability game state is a game state in which the probability of acquiring the right to execute a big role game in which the big winning opening is opened is set low, and is called a high-probability game state. Is a game state in which the probability of acquiring the right to perform a major role game is set high. Further, the non-time-saving game state is a game state in which the movable piece 120b is difficult to open and the game ball is difficult to enter into the first variable starting port 120B, and the medium-time-time-saving game state is a non-time-saving game. This is a gaming state in which the movable piece 120b is more likely to be opened than in the state, and the gaming ball is more likely to enter the first variable starting port 120B. Further, the time-saving game state is a gaming state in which the movable piece 120b is more likely to be opened and the game ball is most likely to enter the first variable starting port 120B than in the medium-time-short game state. In the time-saving game state, when the game balls are continuously fired toward the second game area 116b during the game, the game balls are set to decrease slightly or hardly decrease. ..

As described above, since the special game and the normal game proceed in parallel at the same time, in the simultaneous rotation reference example, the low-probability game state or the high-probability game state, the non-time-saving game state, the medium-time short-time game state, and the time-saving game The game state is a combination of any of the states. In the following, for ease of understanding, the gaming state related to the special game, that is, the low-probability gaming state and the high-probability gaming state are referred to as the special gaming state, and the gaming state related to the normal game, that is, the non-time-saving gaming state, medium. The time-saving game state and the time-saving game state may be referred to as a normal game state. The initial state of the gaming machine 100 is set to a low-probability gaming state and a non-time-saving gaming state.

When the player operates the operation handle 112 to launch the game ball into the game area 116 and the game ball flowing down the game area 116 enters the first start port 120 or the second start port 122, the player is allowed to play the game. A lottery for whether or not to give a profit (hereinafter referred to as a "major role lottery") is held. In this big role lottery, if a big hit is won, a big role game is executed in which the big winning opening is opened and a game ball can be entered into the big winning opening, and the game state after the end of the big winning game. Is set to any of the above gaming states. In the following, the major role lottery method will be described.

As will be described in detail later, when a game ball enters the first starting port 120 or the second starting port 122, various random numbers related to the big winning combination lottery (big hit determination random number, winning symbol random number, reach group determination random number, reach). The mode determination random number and the fluctuation pattern random number) are acquired, and each of these random number values is stored in the special figure reservation storage area of the main RAM 300c. In the following, various random numbers stored in the special figure hold storage area when the game ball enters the first start port 120 are collectively referred to as special 1 hold, and the game ball enters the second start port 122. The various random numbers stored in the special figure hold storage area are collectively called special 2 hold.

The special figure reservation storage area of the main RAM 300c includes a first special figure reservation storage area and a second special figure reservation storage area. The first special figure reserved storage area and the second special figure reserved storage area each have four storage units (first to fourth storage units). Then, when the game ball enters the first start port 120, the special 1 hold is stored in order from the first storage unit of the first special figure hold storage area, and when the game ball enters the second start port 122, the special 1 hold is stored. 2 Holds are stored in order from the first storage unit of the second special figure hold storage area.

For example, when a game ball enters the first starting port 120, if the hold is not stored in any of the first to fourth storage units of the first special figure hold storage area, the first storage unit is used. Special 1 Hold is memorized. Further, for example, when a game ball enters the first starting port 120 in a state where the special 1 hold is stored in the first storage unit to the third storage unit, the special 1 hold is set to the fourth storage unit. Remember. Further, even when the game ball enters the second starting port 122, the special 2 hold is stored in the 1st to 4th storage units of the 2nd special figure hold storage area in the same manner as described above. Special 2 hold is stored in the storage unit with the smallest number (ordinal number).

However, the number of special 1 hold (X1) and the number of special 2 hold (X2) that can be stored in the first special figure hold storage area and the second special figure hold storage area are set to four, respectively. Therefore, for example, when the game ball enters the first starting port 120, if four special 1 holdings are already stored in the first special figure holding storage area, the first starting port 120 is entered. No new special 1 hold is memorized by entering the game ball. Similarly, when the game ball enters the second starting port 122, if four special 2 holdings are already stored in the second special figure holding storage area, the game to the second starting port 122 is played. No new special 2 hold is memorized by entering the ball.

FIG. 6 is a diagram illustrating a low probability jackpot determination random number determination table according to a reference example of simultaneous rotation. When a game ball enters the first starting port 120 or the second starting port 122, one jackpot determination random number is acquired from the range of 0 to 65535. Then, when the big win lottery is started, that is, the big hit determination random number determination table is selected according to the game state when the big hit is determined, and the selected jackpot determination random number determination table and the acquired jackpot determination random number are used. A big role lottery will be held.

In the low-probability gaming state, when starting the big win lottery for the special 1 hold and the special 2 hold, the low probability big hit determination random number determination table is referred to. Here, in the simultaneous rotation reference example, six levels of set values having different degrees of advantage are provided, and a low probability jackpot determination random number determination table is provided for each set value. During the game, the set value is set to one of the six stages, and the low probability jackpot determination random number judgment corresponding to the currently set set value (registered set value stored in the set value buffer) A big role lottery is held with reference to the table.

In the low-probability gaming state, when the set value = 1 (registered set value = 1), the big win lottery is performed with reference to the low-probability jackpot determination random number determination table a shown in FIG. 6 (a). Is done. According to this low probability jackpot determination random number determination table a, when the jackpot determination random number is 10001 to 10218, it is determined to be a jackpot, and when the jackpot determination random number is 20001 to 8996, it is determined to be a small hit, and others. If it is a big hit decision random number, it is judged as a loss. Therefore, the jackpot probability in this case is about 1 / 300.6, and the small hit probability is about 1 / 3.45.

In the low-probability gaming state, when the set value = 2 (registered set value = 2), the big win lottery is performed with reference to the low-probability jackpot determination random number determination table b shown in FIG. 6 (b). Is done. According to this low probability jackpot determination random number determination table b, when the jackpot determination random number is 10001 to 10225, it is determined to be a jackpot, when the jackpot determination random number is 20001 to 8996, it is determined to be a small hit, and others. If it is a big hit decision random number, it is judged as a loss. Therefore, the jackpot probability in this case is about 1 / 291.2, and the small hit probability is about 1 / 3.45.

When the game is in a low-probability game state and the set value is set to 3 (registered set value = 3), a large winning combination lottery is made with reference to the low-probability jackpot determination random number determination table c shown in FIG. 6 (c). Is done. According to this low probability jackpot determination random number determination table c, when the jackpot determination random number is 10001 to 10232, it is determined to be a jackpot, when the jackpot determination random number is 20001 to 8996, it is determined to be a small hit, and others. If it is a big hit decision random number, it is judged as a loss. Therefore, the jackpot probability in this case is about 1 / 282.4, and the small hit probability is about 1 / 3.45.

In the low-probability gaming state, when the set value = 4 (registered set value = 4), the big win lottery is performed with reference to the low-probability jackpot determination random number determination table d shown in FIG. 6 (d). Is done. According to this low probability jackpot determination random number determination table d, when the jackpot determination random number is 10001 to 10239, it is determined to be a jackpot, when the jackpot determination random number is 20001 to 8996, it is determined to be a small hit, and others. If it is a big hit decision random number, it is judged as a loss. Therefore, the jackpot probability in this case is about 1 / 274.2, and the small hit probability is about 1 / 3.45.

When the game is in a low-probability game state and the set value is set to 5 (registered set value = 5), a large winning combination lottery is performed with reference to the low-probability jackpot determination random number determination table e shown in FIG. 6 (e). Is done. According to this low probability jackpot determination random number determination table e, when the jackpot determination random number is 10001 to 10246, it is determined to be a jackpot, and when the jackpot determination random number is 20001 to 8996, it is determined to be a small hit, and others. If it is a big hit decision random number, it is judged as a loss. Therefore, the jackpot probability in this case is about 1 / 266.4, and the small hit probability is about 1 / 3.45.

When the game is in a low-probability game state and the set value is set to 6 (registered set value = 6), a large winning combination lottery is performed with reference to the low-probability jackpot determination random number determination table f shown in FIG. 6 (f). Is done. According to the low probability jackpot determination random number determination table f, when the jackpot determination random number is 10001 to 10253, it is determined to be a jackpot, and when the jackpot determination random number is 20001 to 8996, it is determined to be a small hit, and others. If it is a big hit decision random number, it is judged as a loss. Therefore, the jackpot probability in this case is about 1 / 259.0, and the small hit probability is about 1 / 3.45.

FIG. 7 is a diagram illustrating a high-accuracy jackpot determination random number determination table according to a reference example of simultaneous rotation. In the high-probability gaming state, when starting the big win lottery for the special 1 hold and the special 2 hold, the big hit determination random number determination table at the time of high probability is referred to. The high-accuracy jackpot decision random number determination table is also provided for each set value in the same manner as the low-accuracy jackpot determination random number determination table.

When the game is in a high-probability game state and the set value is set to 1 (registered set value = 1), a large winning combination lottery is performed with reference to the high-probability jackpot determination random number determination table a shown in FIG. 7 (a). Is done. According to this high-accuracy jackpot determination random number determination table a, when the jackpot determination random number is 10001 to 10620, it is determined to be a jackpot, and when the jackpot determination random number is 20001 to 8996, it is determined to be a small hit, and others. If it is a big hit decision random number, it is judged as a loss. Therefore, the jackpot probability in this case is about 1 / 105.7, and the small hit probability is about 1 / 3.45.

Similarly, in the high-probability gaming state and the set value = 2 to 6 (registered set value = 2 to 6), the high-probability jackpot shown in FIGS. 7 (b) to 7 (f) A large winning combination lottery is performed with reference to the determined random number determination tables b to f. According to these high-accuracy jackpot-determined random number determination tables b to f, when the jackpot-determined random numbers are the values shown in the figures, it is determined to be a jackpot. Therefore, when the set value = 2 to 6, the jackpot probability is about 1 / 102.4 to 1 / 91.0, and the small hit probability is about 1 / 3.45.

As described above, the big role lottery is performed according to the registered set value. At this time, the winning probability of the jackpot differs depending on the registered set value, and it is easier to win the jackpot when the registered set value is large than when it is small. Here, it is assumed that the winning probability of the small hit does not change even if the registered setting value is different, but the winning probability of the small hit may be different for each registered setting value. In addition, the small hit is not essential, and only one of the big hit and the loss may be decided in the big win lottery.

Further, here, the winning probability of the jackpot in both the low-probability gaming state and the high-probability gaming state is different depending on the registered set value, but the jackpot in either the low-probability gaming state or the high-probability gaming state is different. Only the winning probability of is different depending on the registration setting value.

FIG. 8 is a diagram illustrating a hit symbol random number determination table and a small hit symbol random number determination table according to the simultaneous rotation reference example. When a game ball enters the first starting port 120 or the second starting port 122, one winning symbol random number is acquired from the range of 0 to 99. Then, when the determination result of "big hit" is derived by the above-mentioned big role lottery, the type of the special symbol is determined by the acquired winning symbol random number and the winning symbol random number determination table. At this time, if the "big hit" is won by the special 1 hold, the symbol random number determination table a for the special 1 is selected as shown in FIG. 8 (a), and the "big hit" is won by the special 2 hold. In that case, as shown in FIG. 8 (b), when the special 2 hit symbol random number determination table b is selected and the "small hit" is won by the special 1 hold, as shown in FIG. 8 (c). When the special 1 small hit symbol random number determination table a is selected and the special 2 hold wins the "small hit", as shown in FIG. 8 (d), the special 2 small hit symbol random number determination table b is selected. In the following, the special symbol determined by the hit symbol random number, that is, the special symbol determined when the jackpot determination result is obtained is referred to as a jackpot symbol, and is determined when the small hit determination result is obtained. A special symbol is called a small hit symbol, and a special symbol determined when a loss determination result is obtained is called a lost symbol.

According to the special 1 hit symbol random number determination table a shown in FIG. 8 (a) and the special 2 per symbol random number determination table b shown in FIG. 8 (b), according to the acquired value of the winning symbol random number, As shown in the figure, a jackpot symbol (special symbols A to J) is determined as a special symbol. Further, according to the special 1 small hit symbol random number determination table a shown in FIG. 8 (c) and the special 2 small hit symbol random number determination table b shown in FIG. 8 (d), the acquired value of the winning symbol random number. As shown in the figure, small hit symbols (special symbols Z1 to Z6) are determined as special symbols.

If the result of the big role lottery is "missing" and the lottery result is derived by holding special 1, the special symbol X is determined as the losing symbol without performing the lottery, and the lottery result is special 2. When it is derived by holding, the special symbol Y is determined as the lost symbol without performing a lottery. That is, the winning symbol random number determination table is referred only when the big winning lottery result is "big hit", and is not referred to when the big winning lottery result is "missing" or "small hit". Further, the small hit symbol random number determination table is referred to only when the large winning combination lottery result is "small hit", and is not referred to when the large winning combination lottery result is "big hit" or "missing". The special symbols Z1 to Z6, which are small hit symbols, are also collectively referred to as a special symbol Z.

FIG. 9 is a diagram for explaining the reach group determination random number determination table according to the simultaneous rotation reference example. A plurality of reach group determination random number determination tables are provided, and preset tables are selected according to the hold type, the number of holds, the game state, and the like. When the game ball enters the first starting port 120 or the second starting port 122, one reach group determination random number is acquired from the range of 0 to 10066. As described above, when the major winning combination lottery result is derived, a process of determining a variable effect pattern for notifying the major winning combination lottery result is performed. In the simultaneous rotation reference example, when the result of the large winning combination lottery is "missing", the group type is first determined by the reach group determination random number and the reach group determination random number determination table in determining the variation effect pattern.

For example, when the game state is set to the normal state, which will be described in detail later, and the big role lottery result of "loss" is derived based on the special 1 hold, the special 1 hold is held when the big role lottery is performed. If the number (hereinafter, simply referred to as “holding number”) is 0, the reach group determination random number determination table 1 is selected as shown in FIG. 9A. Similarly, when the result of the big win lottery of "Loss" is derived based on the special 1 hold when it is set to the normal state, if the number of holds when performing the big win lottery is 1 or 2. As shown in FIG. 9B, the reach group determination random number determination table 2 is selected, and if the number of reservations is 3, the reach group determination random number determination table 3 is selected as shown in FIG. 9C. NS. In FIG. 9, the group x described in the group type column indicates an arbitrary group number. Therefore, various group numbers are determined as the group type according to the acquired reach group determination random number and the type of the reach group determination random number determination table to be referred to.

In addition, although the reach group determination random number determination table referred to when the major role lottery result of "loss" is derived based on the special 1 hold in the normal state has been described here, the main ROM 300b has other than this. Also stores a large number of reach group determination random number determination tables.

If the result of the big win lottery is "big hit" or "small hit", the group type is not decided when the variable effect pattern is decided. That is, the reach group determination random number determination table is referred only when the big win lottery result is "missing", and is not referred to when the big win lottery result is "big hit" or "small hit".

FIG. 10 is a diagram illustrating a reach mode determination random number determination table according to a reference example of simultaneous rotation. This reach mode determination random number judgment table is selected when the big role lottery result is "miss", and the reach mode determination random number judgment table at the time of loss, and the big hit selected when the big role lottery result is "big hit". It is roughly divided into a time reach mode determination random number determination table and a small hit time reach mode determination random number determination table selected when the result of the big win lottery is "small hit". The reach mode determination random number determination table at the time of loss is provided for each group type determined as described above, and the reach mode determination random number determination table at the time of big hit and the reach mode determination random number determination table at the time of small hit are in the gaming state. , It is provided for each hold type.

In addition, each reach mode determination random number determination table is also provided for each game state and symbol type. Here, FIG. 10A shows an example of the reach mode determination random number determination table for group x referred to in a predetermined game state and symbol type, and an example of the reach mode determination random number determination table for special 1 jackpot. FIG. 10 (b) shows an example of the special 1 jackpot reach mode determination random number determination table, and FIG. 10 (c) shows an example of the special 1 small hit reach mode determination random number determination table. An example of the reach mode determination random number determination table for special 2 is shown in FIG. 10 (e).

When the game ball enters the first starting port 120 or the second starting port 122, one reach mode determination random number is acquired from the range of 0 to 250. Then, when the result of the above-mentioned major role lottery is "missing", as shown in FIG. 10A, a random number for determining the reach mode at the time of losing corresponding to the group type determined by the above-mentioned group type lottery. The determination table is selected, and the variable mode number is determined based on the selected reach mode determination random number determination table and the reach mode determination random number. In addition, when the result of the above-mentioned big win lottery is "big hit", as shown in FIGS. 10 (b) and 10 (c), it corresponds to the game state at the time of winning the big hit and the read hold type. The jackpot reach mode determination random number determination table is selected, and the variable mode number is determined based on the selected jackpot reach mode determination random number determination table and the reach mode determination random number.

Further, when the result of the above-mentioned large winning combination lottery is "small hit", as shown in FIGS. 10 (d) and 10 (e), the game state at the time of winning the small hit and the read hold type. The small hit reach mode determination random number determination table corresponding to is selected, and the variable mode number is determined based on the selected small hit reach mode determination random number determination table and the reach mode determination random number.

Further, in each reach mode determination random number determination table, the reach mode determination random number is associated with the variation pattern random number determination table described later together with the variation mode number, and at the same time when the variation mode number is determined, the variation pattern The random number judgment table is determined. In FIG. 10, the table x described in the column of the variation pattern random number determination table indicates an arbitrary table number. Therefore, the variation mode number and the table number of the variation pattern random number determination table are determined according to the acquired reach group determination random number and the type of the reach mode determination random number determination table to be referred to. Further, in the simultaneous rotation reference example, the fluctuation mode number and the fluctuation pattern number described later are set in hexadecimal. In the following, when a hexadecimal number is indicated, "H" is added, but what is described as XXH in FIGS. 10 to 12 indicates an arbitrary value indicated by the hexadecimal number.

As described above, when the result of the large winning combination lottery is "missing", first, the group type is determined by the reach group determination random number determination table and the reach group determination random number shown in FIG. Then, the variation mode number and the variation pattern random number determination table are determined by the reach mode determination random number determination table and the reach mode determination random number at the time of loss shown in FIG. 10A according to the determined group type and the game state.

On the other hand, if the result of the big win lottery is "big hit" or "small hit", the determined big hit symbol or small hit symbol (type of special symbol), big hit, or game state at the time of small hit winning, etc. The variation mode number and the variation pattern random number determination table are determined by referring to the corresponding jackpot reach mode determination random number determination table shown in FIG. 10 and using the reach mode determination random number.

FIG. 11 is a diagram illustrating a variation pattern random number determination table according to the simultaneous rotation reference example. Here, the variation pattern random number determination table x of a predetermined table number x is shown, but in addition to this, a large number of variation pattern random number determination tables are provided for each table number.

When the game ball enters the first starting port 120 or the second starting port 122, one variation pattern random number is acquired from the range of 0 to 238. Then, the variation pattern number is determined as shown in the figure based on the variation pattern random number determination table determined at the same time as the variation mode number and the acquired variation pattern random number.

When the big winning combination lottery is performed in this way, the variable mode number and the variable pattern number are determined according to the big winning combination lottery result, the determined symbol type, the game state, the number of holdings, the holding type, and the like. These variation mode numbers and variation pattern numbers specify the variation effect pattern, and the mode and time of the variation effect are associated with each of them.

FIG. 12 is a diagram illustrating a fluctuation time determination table according to a reference example of simultaneous rotation. As described above, when the variation mode number is determined, the variation time 1 is determined according to the variation time 1 determination table shown in FIG. 12 (a). According to this variation time 1 determination table, the variation time 1 is associated with each variation mode number, and the corresponding variation time 1 is determined according to the determined variation mode number.

Further, when the fluctuation pattern number is determined as described above, the fluctuation time 2 is determined according to the fluctuation time 2 determination table shown in FIG. 12 (b). According to the fluctuation time 2 determination table, the fluctuation time 2 is associated with each fluctuation pattern number, and the corresponding fluctuation time 2 is determined according to the determined fluctuation pattern number. The total time of the fluctuation times 1 and 2 determined in this way is the time of the fluctuation effect for notifying the result of the big winning combination lottery, that is, the fluctuation time. This fluctuation time is the time until the determined special symbol is stopped and displayed on the first special symbol display 160 or the second special symbol display 162.

As will be described in detail later, when the special symbol is determined based on the special 1 hold and the variation mode number and the variation pattern number, that is, the variation time are determined, the first special symbol is displayed over the determined variation time. The fluctuation display of the symbol is performed on the device 160, and when the fluctuation time elapses, the determined special symbol is stopped and displayed on the first special symbol display 160. Further, when the special symbol is determined based on the special 2 hold and the fluctuation pattern number, that is, the fluctuation time is determined, the fluctuation display of the symbol is displayed on the second special symbol display 162 over the determined fluctuation time. When the fluctuation time elapses, the determined special symbol is stopped and displayed on the second special symbol display 162. At this time, the lost symbol is stopped and displayed on the first special symbol display 160, so that the lost symbol is confirmed as a result of the major role lottery, the major role lottery based on the next special 1 hold becomes feasible, and the lost symbol is the second. By stopping and displaying on the special symbol display 162, the loss is confirmed as a result of the big winning combination lottery, and the big winning combination lottery based on the next special 2 hold becomes feasible. On the other hand, when the jackpot symbol is stopped and displayed on the first special symbol display 160 or the second special symbol display 162, the jackpot is confirmed as a result of the big win lottery, the big win game is executed, and the small hit symbol is the first special. When the symbol display 160 or the second special symbol display 162 is stopped and displayed, the small hit is confirmed as a result of the big winning combination lottery, and the small hit game is executed.

In this way, the fluctuation time defines the time for displaying the fluctuation of the symbol on the first special symbol display 160 or the second special symbol display 162, in other words, the time until the result of the big role lottery is confirmed. Become.

When the variation mode number is determined as described above, the variation mode command corresponding to the determined variation mode number is transmitted to the sub-control board 330, and when the variation pattern number is determined, the determined variation The variation pattern command corresponding to the pattern number is transmitted to the sub-control board 330. In the sub-control board 330, the first half mode of the variation effect is mainly determined based on the received variation mode command, and the second half aspect of the variation effect is mainly determined based on the received variation pattern command. However, the details will be described later. In the following, the variation mode number and the variation pattern number may be collectively referred to as variation information, and the variation mode command and the variation pattern command may be collectively referred to as a variation command.

FIG. 13 is a diagram for explaining the gaming state and the fluctuation time according to the simultaneous rotation reference example. As described above, the special game state and the normal game state are combined to form one game state, and the progress of the game is controlled according to the game state being set. As described above, there are two types of special gaming states, a low-probability gaming state and a high-probability gaming state, in which the winning probabilities of big hits are different. In addition, there are three types of normal game states: a non-time-saving game state, a medium-time-short game state, and a time-short-time game state in which the ease of entering the game ball into the first variable starting port 120B (ball entry frequency) is different from each other. Has been done.

Here, in a normal game, the ease of entering the game ball into the first variable starting port 120B is determined by three factors: winning probability, fluctuation time, and opening time. As will be described in detail later, in a normal game, when the game ball passes through the gate 124 or the game ball enters the normal drawing operating port 125, the normal drawing hold is stored. Then, a general drawing lottery is performed to determine whether or not to release the movable piece 120b based on the stored general drawing reservation. The result of this general drawing lottery is confirmed when a predetermined fluctuation time has elapsed. When the winning is confirmed as a result of the regular drawing lottery, the movable piece 120b is released. At this time, the winning probability in the general drawing lottery, the fluctuation time, and the opening time when opening the movable piece 120b are set for each normal game state.

In the simultaneous rotation reference example, as shown in FIG. 13A, six types of gaming states are provided depending on the combination of the special gaming state and the normal gaming state. The initial state of the gaming machine 100 is a low-probability gaming state and a non-time-saving gaming state. In the non-time saving game state, the winning probability in the normal drawing lottery is low, the fluctuation time is long, and the opening time of the movable piece 120b is short. In the simultaneous rotation reference example, the gaming state in which the low-probability gaming state and the non-time-saving gaming state are combined is called a normal state.

Further, in the simultaneous rotation reference example, the high-probability gaming state and the non-time-saving gaming state may be set, and the gaming state in which both of them are combined is called the most dominant state. In addition, this most dominant state has the highest degree of advantage among the six game states, and if the game balls are properly fired, the game balls gradually increase during the game even if the jackpot is not won. It is set to go.

Further, in the simultaneous rotation reference example, it may be set to a low-probability gaming state and a time-saving gaming state. In the time-saving game state, the winning probability in the regular drawing lottery is high, the fluctuation time is short, and the opening time of the movable piece 120b is long. In the following, a gaming state in which a low-probability gaming state and a time-saving gaming state are combined is referred to as a low-probability time-saving state.

Further, in the simultaneous rotation reference example, the high-probability gaming state and the time-saving gaming state may be set. Hereinafter, the gaming state in which the high-probability gaming state and the time-saving gaming state are combined is referred to as a high-probability time-saving state or a high-probability precursor state. The high-accuracy time-saving state and the high-accuracy precursor state will be described in detail later.

Further, in the simultaneous rotation reference example, it may be set to a high-probability gaming state and a medium-time short-time gaming state. In the medium-time short-time game state, the winning probability in the normal drawing lottery is higher than that in the non-time-saving game state and lower than that in the non-time-saving game state, the fluctuation time is short, and the opening time of the movable piece 120b is long. This gaming state can be set when an unexpected situation occurs, such as when the gaming ball is not properly launched. Hereinafter, the gaming state in which the high-probability gaming state and the medium-time and short-time gaming state are combined is referred to as a penalty state.

In the sub control board 330, an effect mode corresponding to the gaming state set in the main control board 300 is set. The effect mode defines a background image, BGM, etc. displayed on the main effect display unit 200a, and the content of the effect is different for each effect mode. That is, the player can identify the current gaming state by the effect mode.

As described above, in the simultaneous rotation reference example, six game states are provided. Then, as described above, the variation mode number and the variation pattern number, that is, the variation time are determined according to the game state, the hold type, the number of fluctuations in the game state, and the type of the symbol when the big winning combination lottery is performed. NS.

Here, in the gaming machine 100, a substantial fluctuation target is set for each gaming state. The substantive change target originally indicates the type of hold for which the major role lottery should be performed, and either the special 1 hold or the special 2 hold is set as the real change target for each game state. In the normal state, the special 1 hold is set as the target of substantial fluctuation. Further, in the normal state, since the normal game state is the non-time saving game state, the first variable start port 120B is hardly opened. Therefore, in the normal state, the player needs to launch the game ball toward the first game area 116a in order to allow the game ball to enter the first fixed start port 120A.

In the normal state, the big winning combination lottery is performed by the special 1 hold which is the actual fluctuation target, and when the lost symbol or the small hit symbol is determined, the fluctuation time is determined within the range of 3 to 100 seconds. Further, in the normal state, when the big winning combination lottery is performed by the special 1 hold and the big hit symbol is decided, the fluctuation time is decided within the range of 40 to 100 seconds.

On the other hand, in the normal state, when the big winning combination lottery is performed by the special 2 hold which is not the target of the actual fluctuation, the fluctuation time is always determined to be 10 minutes regardless of the determined symbol type. In this way, by setting the fluctuation time to a long time such as 10 minutes, in the normal state, even if the player puts the game ball into the second starting port 122, the big role lottery based on the special 2 hold There are very few execution opportunities.

Specifically, the second starting port 122 is provided in the second game area 116b, and the second starting port 122 is composed of a fixed starting port to which a game ball can always enter. Further, due to the playability of the gaming machine 100, the second starting port 122 is arranged at a position where the gaming ball enters more easily than the first starting port 120. Therefore, if the fluctuation time related to the special 2 hold is set to a short time in the normal state, the player is given an opportunity of a large role lottery more than necessary. Therefore, the fluctuation time is set to a long time such as 10 minutes in order to appropriately launch the game ball toward the first game area 116a in accordance with the original game playability in the normal state.

In the most dominant state, Special 2 Hold is set as a target for substantial fluctuation. Therefore, in the most dominant state, the player needs to launch the game ball toward the second game area 116b in order to allow the game ball to enter the second starting port 122. In the most dominant state, when the big winning combination lottery is performed by the special 1 hold that is not the target of the actual fluctuation, the fluctuation time is always determined to be 10 seconds regardless of the determined symbol type. It should be noted that the case where the big role lottery is performed by the special 1 hold which is not the actual change target in the most dominant state is more playable than the case where the big role lottery is performed by the special 2 hold which is not the real change target in the normal state. The effect is small. Therefore, in the most dominant state, the fluctuation time when the big winning combination lottery is performed by the special 1 hold, which is not the target of the actual fluctuation, is set as short as 10 seconds.

In the most dominant state, the big winning combination lottery is performed by the special 2 hold which is the actual fluctuation target, and when the lost symbol or the small hit symbol is determined, the fluctuation time is determined within the range of 1 second to 3 seconds. In addition, in the most dominant state, when a big winning combination lottery is performed by holding special 2 and the big hit symbol is decided, the fluctuation time is decided within the range of 3 seconds to 10 seconds.

In both the low-probability time-saving state and the high-probability time-saving state, the special 1 hold is set as a substantial fluctuation target. Further, in the low-accuracy time-saving state and the high-accuracy time-saving state, the normal gaming state is set to the time-saving gaming state, and the first variable starting port 120B is frequently controlled to the open state. Therefore, in these two gaming states, the player needs to launch the game ball toward the second game area 116b in order to allow the game ball to enter the first variable starting port 120B. In both of these two gaming states, the same variation pattern random number determination table is selected, but these two gaming states are common in that the normal gaming state is the time-saving gaming state. In other words, when the normal game state is the time-saving game state, the big role lottery is performed by the special 1 hold which is the actual fluctuation target, and when the lost symbol or the small hit symbol is determined, the fluctuation time of 1 second is always determined. NS. Further, in the case of the low probability time saving state and the high probability time saving state, the big winning combination lottery is performed by the special 1 hold, and when the big hit symbol is decided, the fluctuation time is always decided to be 30 seconds.

In the high-probability precursor state, the special 1 hold is set as a real fluctuation target. Further, in the high-accuracy precursor state, the normal gaming state is set to the time-saving gaming state, and the first variable starting port 120B is frequently controlled to the open state. Therefore, in the high-accuracy precursor state, the player needs to launch the game ball toward the second game area 116b in order to allow the game ball to enter the first variable starting port 120B. In the high-probability precursor state, the big role lottery is performed by the special 1 hold which is the target of the actual fluctuation, and when the lost symbol or the small hit symbol is determined, the fluctuation time is determined within the range of 3 seconds to 10 seconds. In addition, in the high probability precursor state, when the big winning combination lottery is performed by the special 1 hold and the big hit symbol is decided, the fluctuation time is always decided to be 30 seconds.

On the other hand, in the case of low probability time saving state, high probability time saving state and high probability precursor state, that is, when the normal game state is the time saving game state and the big role lottery is performed by the special 2 hold which is not the actual fluctuation target, Regardless of the determined symbol type, the fluctuation time is always determined to be 10 minutes.

In the penalty state, the special 1 hold is set as a real fluctuation target. Further, in the penalty state, the normal gaming state is set to the medium-time short-time gaming state, and the first variable starting port 120B is controlled to the open state at a constant frequency. Therefore, in the penalty state, the player needs to launch the game ball toward the second game area 116b in order to allow the game ball to enter the first variable starting port 120B. In the penalty state, the big winning combination lottery is performed by the special 1 hold which is the actual fluctuation target, and when the lost symbol or the small hit symbol is determined, the fluctuation time is determined within the range of 3 to 100 seconds. In addition, in the penalty state, when the big winning combination lottery is performed by the special 1 hold and the big hit symbol is decided, the fluctuation time is decided within the range of 40 to 100 seconds.

On the other hand, in the penalty state, when the big winning combination lottery is performed by the special 2 hold which is not the target of the actual fluctuation, the fluctuation time is always determined to be 10 minutes regardless of the determined symbol type.

As described above, the actual fluctuation target is set for each game state, and when the major winning combination lottery based on the hold type as the actual fluctuation target is performed, the fluctuation time is 100 seconds at the longest. On the other hand, when a large winning combination lottery based on a hold type that is not a target of substantial fluctuation is performed, the fluctuation time is approximately 10 minutes, so that a game contrary to the original game playability is not performed.

In the simultaneous rotation reference example, the case where the average of the fluctuation time of the high-accuracy time-shortening state is shorter than the average of the fluctuation time of the high-accuracy precursor state is described. It may be longer than the average fluctuation time of the precursory state. That is, the average of the fluctuation time in the high-accuracy time-shortening state and the average of the fluctuation time in the high-accuracy precursor state may be different.

FIG. 14 is a first diagram for explaining a special electric accessory operating ram set table according to a simultaneous turning reference example, and FIG. 15 is a diagram for explaining a special electric accessory operating ram set table according to a simultaneous turning reference example. It is a figure of 2. The special electric accessory operating ram set table stores various data for controlling the large role game or the small hit game, and the special electric accessory operating ram set is stored during the large role game and the small hit game. With reference to the table, the first prize-winning port solenoid 126c or the second prize-winning port solenoid 128c is energized and controlled. In reality, a plurality of special electric accessory operating ram set tables are provided for each type of special symbol (big hit symbol and small hit symbol), and the corresponding table plays a major role according to the determined special symbol type. It is set at the start of the game or small hit game, but here, for convenience of explanation, the control data of the special symbol is shown for each symbol type.

As shown in FIG. 14, the big winning game is composed of a plurality of round games in which the big winning opening is opened and closed a predetermined number of times, and the small hit game is executed only once. According to this special electric bonus actuating ram set table, the opening time (waiting time until the first round game is started), the maximum number of special electric bonus actuations (executed during one big role game or small hit game). Number of round games to be played), number of special electric accessory opening / closing switching (number of times of opening of the large winning opening in one round), solenoid energizing time (first large winning opening solenoid 126c or second for each number of opening of large winning opening) Energizing time of the large winning opening solenoid 128c, that is, the opening time of one large winning opening), the specified number (the maximum number of winnings that can be made to the large winning opening in one round game), the effective closing time of the large winning opening (round) Closing time of the big winning opening between games, that is, interval time), ending time (waiting time from the end of the last round game to the restart of the normal special game (variation display of the symbol described later)) However, as control data, it is stored in advance for each type of special symbol as shown in the figure.

If the jackpot is won by holding the special 1 and the special symbols A, B, and D are determined as the jackpot symbols, the major role game composed of four round games is executed. In this big role game, the first big winning opening 126 is opened only once in each of the 1st to 4th round games. In each round game, the first large winning opening 126 is opened for a maximum of 29.0 seconds, and when a specified number of game balls enter during this period or the maximum opening time (29.0 seconds) elapses, the first prize is opened. One big winning opening 126 is closed and one round game is completed.

In addition, when a jackpot is won by holding special 1 and special symbols C and E are determined as jackpot symbols, a major role game composed of 10 round games is executed. In these big role games, the first big winning opening 126 is opened only once in each of the 1st to 10th round games. In each round game, the first large winning opening 126 is opened for a maximum of 29.0 seconds, and when a specified number of game balls enter during this period or the maximum opening time (29.0 seconds) elapses, the first prize is opened. One big winning opening 126 is closed and one round game is completed.

Further, when the small hit is won by the special 1 hold and the special symbols Z1 to Z3 are determined as the small hit symbols, the small hit game composed of one round game is executed. In this small hit game, the second big winning opening 128 is opened 0.1 seconds × 1 time in one round game.

Further, as shown in FIG. 15, when a jackpot is won by holding special 2 and special symbols F, G, and I are determined as jackpot symbols, a major role game composed of four round games is executed. NS. In this big role game, the first big winning opening 126 is opened only once in each of the 1st to 4th round games. In each round game, the first large winning opening 126 is opened for a maximum of 29.0 seconds, and when a specified number of game balls enter during this period or the maximum opening time (29.0 seconds) elapses, the first prize is opened. One big winning opening 126 is closed and one round game is completed.

In addition, when a jackpot is won by holding special 2 and special symbols H and J are determined as jackpot symbols, a major role game composed of 10 round games is executed. In this big role game, the first big winning opening 126 is opened only once in each of the 1st to 10th round games. In each round game, the first large winning opening 126 is opened for a maximum of 29.0 seconds, and when a specified number of game balls enter during this period or the maximum opening time (29.0 seconds) elapses, the first prize is opened. One big winning opening 126 is closed and one round game is completed.

Further, even when a small hit is won by holding the special 2 and special symbols Z4 to Z6 are determined as the small hit symbols, the small hit game consisting of one round game is executed. Here, in the small hit game when the special symbol Z4 is determined as the small hit symbol, the second big winning opening 128 is opened 0.1 seconds × 2 times in one round game. The interval time during the round, which is the rest time between the two opening of the second prize opening 128, is set to 1.78 seconds. Since the game ball is fired at the shortest interval of 0.6 seconds, considering the opening time of the second big winning opening 128 and the firing interval of the game ball, the game ball wins the second big prize during this small hit game. The probability of entering the mouth 128 is low.

However, in the simultaneous rotation reference example, the structure is such that the game ball easily stays on the movable piece 128b that keeps the second large winning opening 128 in the closed state, and the movable piece 128b is moved to the open state. The game ball staying on the piece 128b is guided into the second large winning opening 128. Therefore, by opening the second large winning opening 128 for 0.1 seconds x 2 times, an average of 2 to 3 game balls will enter the 2nd large winning opening 128.

Further, in the small hit game when the special symbol Z5 is determined as the small hit symbol, the second big winning opening 128 is opened 0.1 seconds × 3 times in one round game. The interval time during the round in this case is set to 0.84 seconds. In this small hit game, an average of 3 to 4 game balls enter the second large winning opening 128.

Further, in the small hit game when the special symbol Z6 is determined as the small hit symbol, the second big winning opening 128 is opened 0.1 seconds × 12 times in one round game. The interval time during the round in this case is set to 0.84 seconds. In this small hit game, by continuously firing the game balls toward the second game area 116b, it is almost certain that a specified number (for example, 10) of game balls will enter the second large winning opening 128. can.

At the design stage of the gaming machine 100, it is necessary to strictly manage and adjust the firing prize ball ratio, which is the ratio between the number of launched balls of the gaming ball and the number of prize balls paid out. Therefore, in the simultaneous rotation reference example, a special symbol Z4 in which the 0.1 second opening is performed twice in the small hit game and a special symbol Z5 in which the 0.1 second opening is performed three times in the small hit game are provided. By simply changing these selection ratios, the firing prize ball ratio can be easily adjusted and changed.

FIG. 16 is a diagram illustrating a game state setting table for setting a game state after the end of the major role game according to the simultaneous rotation reference example. In the simultaneous rotation reference example, when the big role game is executed, the game state setting table is referred to according to the game state at the time of winning the big hit, the hold type, and the type of the special symbol (big hit symbol), and after the big role game is completed. Set the game state of.

When the game state at the time of winning the big hit is a normal state or a penalty state, if the big hit is won by holding the special 1 which is a real fluctuation target, the game state after the big role game is set according to the type of the big hit symbol. Specifically, when the special symbol A is determined as the jackpot symbol, it is set to the low probability time saving state (the special gaming state is the low probability gaming state, and the normal gaming state is the time saving gaming state). At this time, the number of times the time-saving game state is continued (hereinafter, referred to as "time-saving number of times") is set to 100 times. This means that the time-saving game state continues until the big role lottery is held 100 times. However, the above-mentioned number of time reductions indicates the maximum number of continuations in the time-saving game state of 1, and if a big hit is won before reaching the above number of continuations, the game state is set again. It will be. Therefore, when the time-saving game state is set after the end of the big role game, if the lottery result other than the big hit is derived 100 times without deriving the lottery result of the big hit in the time-saving game state, the non-time-saving game state The game state will be changed to (normal state).

When the special symbols B and D are determined as the jackpot symbols, the high-probability time-saving state (the special gaming state is the high-probability gaming state and the normal gaming state is the time-saving gaming state) is set. At this time, "next time" is set as the high probability number, and the high-probability gaming state continues until the next big hit is won. In addition, "next time" is set as the number of time reductions, and the time reduction game state continues until the next big hit is won. Therefore, when the special symbols B and D are determined, the high-accuracy time-saving state will continue until the next big hit is won after the big role game.

When the special symbols C and E are determined as the jackpot symbols, the high probability precursor state (the special gaming state is the high-probability gaming state and the normal gaming state is the time-saving gaming state) is set. At this time, "next time" is set as the high probability number, and the time reduction number is set to 100 times. When the special symbols C and E are determined, the high-probability gaming state continues until the next big hit is won, while the time-saving gaming state ends in 100 times. Therefore, when the special symbols C and E are determined, the game state shifts to the most dominant state when the result of the big role lottery is derived 100 times after the big role game.

In addition, when the game state at the time of winning the big hit is a normal state or a penalty state, if the big hit is won by the special 2 hold which is not a substantial fluctuation target, the game state after the big role game is set as follows. That is, when the special symbol F is determined as the jackpot symbol, it is set to the normal state (the special gaming state is the low-probability gaming state, and the normal gaming state is the non-time-saving gaming state). When the special symbols G to J are determined as the jackpot symbols, the penalty state (the special gaming state is the high-probability gaming state, and the normal gaming state is the medium-time short-time gaming state) is set. At this time, both the high accuracy number and the time reduction number are set to "next time".

In addition, when the game state at the time of winning the big hit is the most dominant state, if the big hit is won by the special 1 hold which is not the target of the actual fluctuation, the game state after the big role game is set as follows. That is, when the special symbol A is determined as the jackpot symbol, it is set to the low probability time saving state (the special gaming state is the low probability gaming state, and the normal gaming state is the time saving gaming state). At this time, the number of time reductions is set to 100 times. When the special symbols B to E are determined as the jackpot symbols, the game state after the big role game is set as in the normal state and the penalty state.

On the other hand, when the game state at the time of winning the big hit is the most dominant state, if the big hit is won by the special 2 hold which is the actual fluctuation target, the game state after the big role game is set as follows. That is, when the special symbol F is determined as the jackpot symbol, it is set to the low probability time saving state (the special gaming state is the low probability gaming state, and the normal gaming state is the time saving gaming state). At this time, the number of time reductions is set to 100 times. When the special symbols G and I are determined as the jackpot symbols, the high-probability time-saving state (the special gaming state is the high-probability gaming state and the normal gaming state is the time-saving gaming state) is set. At this time, the high accuracy number and the time reduction number are set to "next time".

When the special symbols H and J are determined as the jackpot symbols, the high probability precursor state (the special gaming state is the high-probability gaming state and the normal gaming state is the time-saving gaming state) is set. At this time, the high accuracy number is set to "next time" and the time reduction number is set to 100 times.

In addition, when the gaming state at the time of winning the jackpot is a low probability time saving state, a high probability time saving state, or a high probability precursor state, that is, when the normal gaming state is the time saving gaming state, the gaming state after the big role game is the normal state. And set in the same way as the penalty state.

FIG. 17 is a diagram illustrating a hit determination random number determination table according to the simultaneous rotation reference example. When the game ball flowing down the game area 116 passes through the gate 124 or enters the normal drawing operating port 125, it is associated with whether or not the movable piece 120b of the first variable starting port 120B is energized and controlled. Judgment processing of ordinary symbols (hereinafter referred to as "general drawing lottery") is performed.

As will be described in detail later, when the game ball passes through the gate 124 or enters the normal drawing operating port 125, one hit determination random number is acquired from the range of 0 to 99, and this disturbance Numerical values are stored in the general drawing reservation storage area of the main RAM 300c up to a maximum of four. That is, the normal figure reservation storage area includes four storage units for saving the winning decision random number. Therefore, when the game ball passes through the gate 124 or enters the normal figure operating port 125 in a state where the determined random numbers are stored in all four storage units of the normal figure reservation storage area, the game is concerned. The winning random number is not stored based on the passage of the sphere. In the following, the hit determination random number stored in the normal figure hold storage area when the game ball passes through the gate 124 or the game ball enters the normal figure operation port 125 is referred to as a normal figure hold.

When the normal drawing lottery is started when the normal game state is the non-time saving game state, the hit determination random number determination table for the non-time saving game state is referred to as shown in FIG. 17A. According to this non-time saving game state hit determination random number determination table, when the hit determination random number is 0, the hit symbol is determined as the type of the normal symbol, and when the hit determination random number is 1 to 99, A lost symbol is determined as the type of normal symbol. Therefore, the probability that the winning symbol is determined in the non-time saving game state, that is, the winning probability is 1/100. As will be described in detail later, when the winning symbol is determined in this general drawing lottery, the movable piece 120b of the first variable starting port 120B is controlled to be in the open state, and when the lost symbol is determined, the first variable starting The movable piece 120b of the mouth 120B is maintained in the closed state.

Further, when starting the normal drawing lottery in the medium-time short-time game state, as shown in FIG. 17B, the hit determination random number determination table for the medium-time short-time game state is referred to. According to the hit determination random number determination table for the medium-time short game state, when the hit determination random number is 0 to 49, the hit symbol is determined as the type of the normal symbol, and the hit determination random number is 50 to 99. In addition, the lost symbol is determined as the type of the normal symbol. Therefore, the probability that the winning symbol is determined in the medium-time short game state, that is, the winning probability is 50/100.

Further, when starting the normal drawing lottery in the time-saving game state, as shown in FIG. 17 (c), the hit determination random number determination table for the time-saving game state is referred to. According to the hit determination random number determination table for the time-saving game state, when the hit determination random number is 0 to 98, the hit symbol is determined as the type of the normal symbol, and when the hit determination random number is 99, it is normal. A lost symbol is determined as the type of symbol. Therefore, the probability that the winning symbol is determined in the time-saving game state, that is, the winning probability is 99/100.

FIG. 18A is a diagram for explaining a normal symbol fluctuation time data table according to a simultaneous rotation reference example, and FIG. 18B is a diagram for explaining an opening / closing control pattern table according to a simultaneous rotation reference example. As described above, when the general drawing lottery is performed, the fluctuation time of the normal symbol is determined. The normal symbol fluctuation time data table is referred to when the fluctuation time of the normal symbol is determined when the winning symbol or the lost symbol is determined by the ordinary symbol lottery. According to this normal symbol variation time data table, when the gaming state is set to the non-time saving gaming state and the medium-time saving gaming state, the variation time is determined to be 10 seconds, and the gaming state is set to the time-saving gaming state. If so, the fluctuation time is determined to be 1 second. When the fluctuation time is determined in this way, the normal symbol display 168 is displayed in a variable manner (blinking display) over the determined time. Then, when the winning symbol is determined, the normal symbol display 168 is turned on, and when the lost symbol is determined, the normal symbol display 168 is turned off.

Then, when the winning symbol is determined by the ordinary symbol lottery and the normal symbol display 168 is lit, the movable piece 120b of the first variable starting port 120B is opened / closed controlled as shown in FIG. 18 (b). Energization is controlled with reference to the pattern table. Actually, the open / close control pattern table is provided for each game state, and the corresponding table is set at the start of energization of the normal electric accessory solenoid 120c according to the game state when the normal symbol is determined. ..

When the winning symbol is determined, as shown in FIG. 18B, the opening / closing control of the first variable starting port 120B is controlled with reference to the opening / closing control pattern table. According to this opening / closing control pattern table, the time before opening the normal electric power (waiting time until the opening of the first variable starting port 120B is started) and the maximum number of times of switching the opening / closing of the normal electric accessory (opening of the first variable starting port 120B). Number of times), solenoid energization time (energization time of the ordinary electric accessory solenoid 120c for each opening number of the first variable start port 120B, that is, one opening time of the first variable start port 120B), specified number (first variable) The maximum number of winnings to the first variable starting port 120B while the starting port 120B is fully opened), the effective closing time of the normal electric power (the closing time between each opening of the first variable starting port 120B, that is, the pause time), the general electric power Effective state time (waiting time from the end of the last opening of the first variable start port 120B), normal power end wait time (after the normal electric power effective state time elapses, wait until the fluctuation display of the normal symbol described later is resumed. Time) is stored in advance as control data of the first variable starting port 120B for each gaming state as shown in the figure.

In this way, by setting the winning probability, the fluctuation time, and the opening time of the normal symbol, as shown in the lower part of FIG. 18B, the firing prize ball ratio (for the game ball launched in the game area 116) The number of shots in the non-time-saving game state) is the ratio of the number of prize balls that the game balls enter into the first variable start port 120B, the second start port 122, the normal drawing operation port 125, and the large prize opening and are paid out to the player. : The number of prize balls = 100: 20, the number of shots in the medium-time short game state: the number of prize balls = 100: 40, and the number of shots in the short-time game state: the number of prize balls = 100: 99.

The opening / closing condition of the first variable starting port 120B defines three elements: the winning probability of the normal symbol, the time for displaying the fluctuation of the normal symbol, and the opening time of the first variable starting port 120B. That is, by combining the three elements of the winning probability of the normal symbol, the time of the variable display of the normal symbol, and the opening time of the first variable start port 120B, in each of the non-time saving game state, the medium time saving game state, and the time saving game state, The frequency of entering the game ball into the first variable starting port 120B and the firing prize ball ratio can be set. In any case, the combination of the three elements shown here is only an example, and if the three elements are combined so that the firing prize ball ratio is higher in the time-saving game state than in the non-time-saving game state. good.

FIG. 19 is a diagram for explaining the transition of the gaming state according to the original game playability according to the simultaneous rotation reference example. With the above configuration, the gaming machine 100 realizes the following playability. Here, the case where the registration setting value is set to "1" will be described. First, in the initial state of the gaming machine 100, it is set to the normal state shown in FIG. 19A. In the normal state, since the substantially variable target is set to the special 1 hold, the player launches the game ball toward the first game area 116a in order to allow the game ball to enter the first fixed start port 120A. Since the first game area 116a is located on the left side of the game board 108, the player performs a so-called "left-handed" in a normal state.

When the game ball enters the first fixed start port 120A, the special 1 hold is stored in the first special figure hold storage area. The special 1 hold stored in the first special figure hold storage area is sequentially read out when the start condition is satisfied, and a large winning combination lottery is performed based on the read special 1 hold. At this time, the winning probability of the jackpot is set to about 1 / 300.6. In the normal state, in the big role lottery based on this special 1 hold, the game is played for the purpose of winning the big hit. The firing prize ball ratio when the game ball is launched toward the first game area 116a is set to 100:20, and the number of game balls decreases during the game.

Then, in the normal state, if a big hit is won in the big role lottery by holding the special 1, the big role game is executed. In this big role game, a round game in which the first big winning opening 126 is opened is executed four or ten times, and the player can win a prize ball for four or ten rounds. Then, when the jackpot is won by holding the special 1, one of the special symbols A to E is determined as the jackpot symbol.

In the normal state, when the jackpot symbol stopped and displayed on the first special symbol display 160 is the special symbol A, the gaming state after the big role game is the low probability time saving state shown in FIG. 19 (b). If the jackpot is won with the special 1 hold, the probability that the special symbol A will be determined as the jackpot symbol is 30%. Therefore, if a jackpot is won in the normal state, there is a 30% chance that the gaming state will shift to the low probability time saving state. In the low-probability time-saving state, the actual fluctuation target is set to the special 1 hold, but since the normal game state is the time-saving game state, the player has to put the game ball into the first variable starting port 120B. 2 Right-handed aiming at the game area 116b will be performed.

That is, in this low probability time saving state, as in the normal state, the game is played for the purpose of winning the big hit in the big role lottery based on the special 1 hold. In the low probability time saving state, the winning probability of the jackpot is about 1 / 300.6, but since the normal gaming state is the time saving gaming state, the movable piece 120b is frequently opened. Therefore, the launch prize ball ratio is 100:99, and the player can aim for a big hit while reducing the consumption of the game ball.

In addition, when shifting to the low probability time saving state, the number of time saving times is set to 100 times, and if the big hit is not won in the 100 times big role lottery, the gaming state will shift to the normal state again (time saving omission). ).

Further, in the normal state, when the jackpot symbols stopped and displayed on the first special symbol display 160 are the special symbols B and D, the gaming state after the big role game is the high accuracy time reduction shown in FIG. 19 (c). It becomes a state. If the jackpot is won with the special 1 hold, the probability that the special symbols B and D will be determined as the jackpot symbols is 35%. Therefore, if a jackpot is won in the normal state, there is a 35% probability that the gaming state will shift to the high-accuracy time-saving state. In the high-accuracy time-saving state, the actual fluctuation target is set to the special 1 hold, but since the normal game state is the time-saving game state, the player has to put the game ball into the first variable start port 120B. 2 Right-handed aiming at the game area 116b will be performed.

That is, in this high-accuracy time-saving state, as in the normal state, the game is played for the purpose of winning the big hit in the big role lottery based on the special 1 hold. In the high-accuracy time-saving state, the winning probability of the jackpot is about 1 / 105.7, and since the normal game state is the time-saving game state, the movable piece 120b is frequently opened. Therefore, the ratio of the launch prize balls is 100:99, and the player can perform the big role lottery while reducing the consumption of the game balls. Therefore, in the high-accuracy time-saving state, it can be said that the next big hit is virtually guaranteed.

Further, in the normal state, when the jackpot symbols stopped and displayed on the first special symbol display 160 are the special symbols C and E, the gaming state after the major role game is a highly accurate precursor shown in FIG. 19 (d). It becomes a state. If the jackpot is won with the special 1 hold, the probability that the special symbols C and E will be determined as the jackpot symbols is 35%. Therefore, if a jackpot is won in the normal state, there is a 35% probability that the gaming state will shift to the high-probability precursor state. In the high-accuracy precursor state, the actual fluctuation target is set to the special 1 hold, but since the normal game state is the time-saving game state, the player has to put the game ball into the first variable start port 120B. 2 Right-handed aiming at the game area 116b will be performed.

When the special symbols C and E are determined, the high probability precursor state is set and the number of time reductions is set to 100 times. At this time, when the number of fluctuations after the big role game reaches 100 times, the time-saving game state ends, and the normal game state becomes the non-time-saving game state. As a result, the gaming state shifts to the most dominant state shown in FIG. 19 (e) due to the time saving omission. As will be described in detail later, in the most dominant state, the number of game balls can be increased simply by continuously firing the game balls toward the second game area 116b. Therefore, in the high-accuracy precursor state, the goal of the game is not to win the jackpot, but to skip the time without winning the jackpot.

According to the special 1 hold of the actual fluctuation target in the high-accuracy precursor state, the high-accuracy time-shortening state, and the low-accuracy time-saving state, when the jackpot is won, the special symbols A to E are determined as the jackpot symbols. When the special symbol A is determined, four round games are executed in the big role game, and the game state after the big role game becomes the low probability time saving state shown in FIG. 19 (b). Further, when the special symbols B and D are determined, the round game is executed 4 times or 10 times in the big role game, and the game state after the big role game becomes a highly accurate time saving state. Further, when the special symbols C and E are determined, the round game is executed 4 times or 10 times in the big role game, and the game state after the big role game becomes a high probability precursor state.

In the most dominant state, when the game ball enters the second starting port 122, the special 2 hold is stored in the second special figure hold storage area. The special 2 hold stored in the second special figure hold storage area is sequentially read when the start condition is satisfied, and a large winning combination lottery is performed based on the read special 2 hold. At this time, the winning probability of the big hit is set to about 1 / 105.7, and the winning probability of the small hit is set to about 1 / 3.45. In the most dominant state, in the big role lottery based on this special 2 hold, winning a small hit is the main purpose of the game.

Specifically, when a game ball is launched into the second game area 116b, the ratio of the prize balls paid out by entering the game ball into the second starting port 122 with respect to the number of launched balls is 100: 60 to 80. It is set to the degree. Then, in the most dominant state, in the large winning combination lottery by holding the special 2, the small hit game is frequently performed because the small hit is won with a probability of about 1 / 3.45. Here, when the small hit is won by the special 2 hold, the small hit symbols Z4 to Z6 are determined. As described above, in the small hit game when the small hit symbol Z4 is stopped and displayed on the second special symbol display 162, an average of 2 to 3 game balls enter the second large winning opening 128. In the small hit game when the small hit symbol Z5 is stopped and displayed on the second special symbol display 162, an average of 3 to 4 game balls enter the second large winning opening 128. Further, in the small hit game when the small hit symbol Z6 is stopped and displayed on the second special symbol display 162, a substantially specified number of game balls enter the second large winning opening 128.

When a game ball enters the second prize opening 128, for example, 15 prize balls are paid out for each game ball. As a result, in the most dominant state, the ratio of all prize balls to the number of shot balls is 100: 120, and the game balls are simply fired toward the second game area 116b. Can be increased.

In this most dominant state, the normal gaming state is the non-time saving gaming state, and the movable piece 120b is rarely opened. Further, in the most dominant state, the special gaming state is a high-probability gaming state, and the winning probability of the jackpot in the most dominant state is about 1 / 105.7. It can be said that the jackpot winning is guaranteed.

According to the special 2 hold of the real fluctuation target in this most dominant state, when the jackpot is won, the special symbols F to J are determined as the jackpot symbols. When the special symbol F is determined, four round games are executed in the big role game, and the game state after the big role game becomes the low probability time saving state shown in FIG. 19 (b). Further, when the special symbols G and I are determined, the round game is executed 4 times or 10 times in the big role game, and the game state after the big role game becomes a highly accurate time saving state. Further, when the special symbols H and J are determined, the round game is executed 4 times or 10 times in the big role game, and the game state after the big role game becomes a high probability precursor state.

Since the most dominant state has an extremely high degree of advantage as compared with other gaming states, the greatest purpose of the game in the gaming machine 100 is to shift the gaming state to the most dominant state. As described above, the game is first started in the normal state, but does not shift from this normal state to the most dominant state at once. Therefore, the transition route to the most dominant state via the high-accuracy precursor state becomes the transition route to the most dominant state in the gaming machine 100.

Further, in the simultaneous rotation reference example, it is set as a condition for transition from the high probability precursor state to the highest advantage state to win a specific small hit symbol, apart from the time saving omission in the high probability precursor state. Specifically, when a small hit is won by holding special 1 which is a real fluctuation target in a high probability precursor state, the special symbol Z1 is 1%, the special symbol Z2 is 69%, and the special symbol Z3 is 30 as small hit symbols. It is determined with a probability of% (see FIG. 8 (c)).

At this time, if the special symbol Z1 is determined as the small hit symbol, the time-saving game state ends with the end of the small hit game, and as a result, the game state shifts to the most dominant state.

In this way, since the player shifts to the most dominant state by winning a specific small hit, the player is compared to the case where the player shifts to the most dominant state only when the number of fluctuations reaches the specified number of times (100 times). Therefore, a feeling of expectation and a feeling of tension are always given.

In the above-mentioned high-probability precursor state, high-probability time-saving state, and low-probability time-saving state, a small hit is won with a probability of about 1 / 3.45. Therefore, even in the high-accuracy precursor state, the high-accuracy time-saving state, and the low-accuracy time-saving state, the small hit game is frequently executed as in the most dominant state. However, in the high-accuracy precursor state, the high-accuracy time-saving state, and the low-accuracy time-saving state, the normal gaming state is the time-saving gaming state. Further, as will be described in detail later, the normal game state is maintained in the time-saving game state even during the small hit game. Therefore, although the second big winning opening 128 is opened during the small hit game, the first variable starting opening 120B is also opened during this time.

As described above, the first variable starting port 120B is provided above the second large winning opening 128, and in the time-saving gaming state, the opening time of the first variable starting opening 120B is the second large winning prize. It is much longer than the opening time of the mouth 128. Therefore, in the high-accuracy precursor state, the high-accuracy time-saving state, and the low-accuracy time-saving state, most of the game balls flowing down the second game area 116b enter the first variable starting port 120B and enter the second large winning opening 128. Almost no game ball enters. As a result, in the high-accuracy precursor state, the high-accuracy time-saving state, and the low-accuracy time-saving state, unlike the most dominant state, even if a right-handed hit is made during the game, the number of game balls gradually decreases.

As described above, when the game progresses according to the actual fluctuation target according to the original game performance, when the big hit is won, the game state after the big role game is the low probability time saving state, the high probability time saving state, and the high probability precursor state. Set to either. In the high-probability time-saving state and the high-probability precursor state, it is common that the special gaming state is the high-probability gaming state and the normal gaming state is the time-saving gaming state. On the other hand, the high-accuracy time-saving state continues until the next big hit is won, while the high-accuracy precursor state is a game by winning a specific small hit (special symbol Z1) or skipping the time. The difference is that the state is transferred to the most dominant state.

Further, in the high-accuracy time-shortening state, the fluctuation time at the time of small hit and loss is set to 1 second, whereas in the high-accuracy precursor state, the fluctuation time at the time of small hit and loss is 3 to 10 seconds. It differs in that it is set within the range (see FIG. 13 (b)). That is, the average of the fluctuation time in the high-accuracy time-shortening state is set shorter than the average of the fluctuation time in the high-accuracy precursor state.

Therefore, in the high-accuracy time-shortening state, the fluctuation time at the time of small hit and at the time of loss is relatively short, so that the actual fluctuation target can be digested at high speed until the big hit is won. Although detailed description will be omitted, in the variation time of the special symbol, the variation display of the effect symbols 210a, 210b, 210c is performed on the sub-control board 330. In the high-accuracy time-saving state, the variation display of the effect symbols 210a, 210b, 210c is also relatively short. Therefore, in the high-accuracy time-saving state, as long as the special 1 hold continues to be memorized, the special 1 hold (variable display of the effect symbols 210a, 210b, 210c) will continue to be digested at high speed, and the time until the jackpot is won will be reduced. It can be shortened, and the player can play the game until the next big hit without making the player feel stress (reduced).

On the other hand, in the high-accuracy precursor state, the fluctuation time at the time of small hit and at the time of loss is relatively long, but in the sub-control board 330, an effect of whether or not to shift to the most dominant state is performed. Therefore, the player can play the game while expecting that the player will shift to the highest superior state.

In this way, in the high-accuracy time-shortening state, even if a specific small hit (special symbol Z1) is won, it does not shift to the most dominant state, but by setting the average fluctuation time short, the next big hit The time to win the prize can be shortened, and the stress on the player can be reduced. In addition, in the high-accuracy precursor state, the average fluctuation time is set longer than in the high-accuracy time-shortening state, but the fluctuation time can be used to produce an effect as to whether or not to shift to the most dominant state. It is possible to give a person a sense of anticipation and a sense of tension.

As described above, the high-probability time-saving state and the high-probability precursor state, which are common in that the special gaming state is the high-probability gaming state and the normal gaming state is the time-saving gaming state, are provided, and the fluctuation of the high-probability time-saving state is provided. By making the average of time shorter than the average of the fluctuation time of the high-probability precursor state, it is possible to provide new playability.

FIG. 20 is a diagram for explaining the transition of the game state when the game is not properly performed according to the simultaneous rotation reference example. As described above, in the gaming machine 100, the variation display of the symbol on the first special symbol display 160 and the variation display of the symbol on the second special symbol display 162 are simultaneously performed in parallel. At this time, if there is a possibility that the player may be disadvantaged as a result of the large winning combination lottery being held due to a hold other than the actual fluctuation target, the fluctuation time is set to a long time such as 10 minutes. However, after the big win lottery is performed by the hold other than the real change target, for example, as a result of interrupting the game, the big hit by the hold other than the real change target may be confirmed. In this case, the gaming state changes as shown in FIG.

The main processing of the main control board 300 for realizing the above-mentioned playability will be described below.

FIG. 21 is a diagram illustrating a gaming machine state flag according to a reference example of simultaneous rotation. In the main control board 300, whether or not the game can proceed is managed by the game machine state flag. One of six types of flag values from 00H to 05H is set in the gaming machine status flag. The flag value = 00H of the gaming machine status flag indicates a game-enabled state, and when the gaming machine status flag is 00H, the game progress is controlled, and when the gaming machine status flag is other than 00H, the game is played. It will be stopped.

The flag value = 01H of the gaming machine status flag indicates the setting change state, and when the gaming machine status flag is 01H, the registered setting value can be changed. The flag value of the gaming machine status flag = 02H indicates the setting confirmation status, and when the gaming machine status flag is 02H, the registered setting value is displayed on the performance display monitor 184, and the registered setting value is set. It becomes possible to confirm. The flag value = 03H of the gaming machine status flag indicates an abnormal setting state, and when the gaming machine status flag is 03H, the game is stopped because the registered setting value is abnormal. The flag value = 04H of the gaming machine status flag indicates a RAM abnormal state, and when the gaming machine status flag is 04H, the game is stopped. The flag value = 05H of the gaming machine status flag indicates a checksum abnormal state, and when the gaming machine status flag is 05H, the game is stopped. When the power is turned on, the gaming machine status flag is set to one of the flag values, and processing is performed according to the gaming machine status flag.

(CPU initialization process of main control board 300)
FIG. 22 is a first flowchart for explaining the CPU initialization process in the main control board 300 according to the simultaneous rotation reference example, and FIG. 23 explains the CPU initialization process in the main control board 300 according to the simultaneous rotation reference example. It is a second flowchart to be done.

When power is supplied from the power supply board, a system reset occurs in the main CPU 300a, and the main CPU 300a performs the following CPU initialization process (S100).

(Step S100-1)
When the power is turned on, the main CPU 300a reads a boot program from the main ROM 300b as an initial setting process, and performs setting processes necessary for executing various processes.

(Step S100-3)
The main CPU 300a sets the wait processing time in the timer counter.

(Step S100-5)
The main CPU 300a determines whether or not the power supply cutoff warning signal is detected. The main control board 300 is provided with a power supply cutoff detection circuit, and when the power supply voltage becomes equal to or lower than a predetermined value, a power supply cutoff warning signal is output from the power supply cutoff detection circuit. If the power off warning signal is detected, the process is moved to step S100-3, and if the power off warning signal is not detected, the process is moved to step S100-7.

(Step S100-7)
The main CPU 300a determines whether or not the wait time set in step S100-3 has elapsed. As a result, if it is determined that the wait time has elapsed, the process is transferred to step S100-9, and if it is determined that the wait time has not elapsed, the process is transferred to step S100-5.

(Step S100-9)
The main CPU 300a executes a process necessary for permitting access to the main RAM 300c.

(Step S100-11)
The main CPU 300a loads the flag value of the gaming machine state flag before the power is turned off into the D register.

(Step S100-13)
The main CPU 300a calculates the checksum and determines whether the calculated checksum matches the checksum saved when the power is turned off (normal) and whether the backup flag is normal. As a result, if it is determined that the backup flag and checksum are normal, the process is transferred to step S100-15, and if it is determined that either or both are not normal, the process is transferred to step S100-25. ..

(Step S100-15)
The main CPU 300a sets an address that does not include the set value and the gaming machine status flag at the start address of the main RAM 300c to be cleared.

(Step S100-17)
The main CPU 300a determines whether the RAM clear operation signal is input from the RAM clear switch 182s (whether the RAM clear button is pressed). As a result, if it is determined that the RAM clear operation signal has been input, the process is transferred to step S100-31, and if it is determined that the RAM clear operation signal has not been input, the process is transferred to step S100-19. ..

(Step S100-19)
The main CPU 300a determines whether the flag value of the gaming machine status flag loaded in step S100-11 is 00H (gamable state), the setting change switch 180s is on, and the middle frame 104 is open. judge. As a result, if it is determined that all three conditions are satisfied, the process is transferred to step S100-21, and if it is determined that even one of the three conditions is not satisfied, the process is transferred to step S100-23.

(Step S100-21)
The main CPU 300a sets 02H (setting confirmation state) in the gaming machine status flag. That is, when the middle frame 104 is open, the setting change switch 180s is on, and the power is normally turned on while the RAM clear button is not pressed, the setting confirmation state is set.

(Step S100-23)
The main CPU 300a executes an initialization process for clearing the clear target at the time of power recovery, which is an area after the start address set in step S100-15 of the main RAM 300c, and shifts the process to step S100-49.

(Step S100-25)
The main CPU 300a sets 05H (checksum abnormal state) in the D register.

(Step S100-27)
The main CPU 300a performs an out-of-area read / write check process for checking and clearing the read / write memory in the out-of-use area.

(Step S100-29)
The main CPU 300a sets the address including the set value and the gaming machine status flag at the start address of the main RAM 300c to be cleared.

(Step S100-31)
The main CPU 300a checks and clears the read / write memory of the used area.

(Step S100-33)
The main CPU 300a determines whether the check result of the read / write memory in the step S100-31 is normal. As a result, if it is determined that the process is normal, the process is transferred to step S100-37, and if it is determined that the process is not normal, the process is transferred to step S100-35.

(Step S100-35)
The main CPU 300a sets 04H (RAM abnormal state) in the D register and shifts the processing to steps S100-45.

(Step S100-37)
The main CPU 300a determines whether 02H (setting confirmation state) is set in the D register. As a result, if it is determined that 02H is set, the process is transferred to step S100-39, and if it is determined that 02H is not set, the process is transferred to step S100-41.

(Step S100-39)
The main CPU 300a sets 00H (playable state) in the D register.

(Step S100-41)
The main CPU 300a determines whether or not the setting change condition is satisfied. As a result, if it is determined that the setting change condition is satisfied, the process is transferred to step S100-43, and if it is determined that the setting change condition is not satisfied, the process is transferred to step S100-45. Here, at least, the setting change condition is that the setting change switch 180s is turned on, the middle frame 104 is open, and the RAM clear operation signal is input from the RAM clear switch 182s. included.

(Step S100-43)
The main CPU 300a sets 01H (setting change state) in the D register.

(Step S100-45)
The main CPU 300a saves the value set in the D register in the gaming machine status flag.

(Step S100-47)
The main CPU 300a executes an initialization process for clearing the clear target at the time of clearing the RAM in the main RAM 300c, and shifts the process to steps S100-49.

(Step S100-49)
The main CPU 300a performs a transmission process (storing the RAM clear designation command in the transmission buffer) of a payout command (RAM clear designation command) for transmitting to the payout control board 310 that the main RAM 300c has been cleared.

(Step S100-51)
The main CPU 300a loads the gaming machine status flag.

(Step S100-53)
The main CPU 300a determines whether the gaming machine status flag loaded in step S100-51 is 00H (gamable state). As a result, if it is determined that it is 00H, the process is transferred to step S110, and if it is determined that it is not 00H, the process is transferred to steps S100-55.

(Step S110)
The main CPU 300a performs subcommand group set processing. The subcommand group set processing will be described later.

(Step S100-55)
The main CPU 300a performs a subcommand set process for transmitting a predetermined command to the subcontrol board 330.

(Step S100-57)
The main CPU 300a sets the timer interrupt cycle.

(Step S100-59)
The main CPU 300a performs a process for disabling interrupts.

(Step S100-61)
The main CPU 300a updates the initial value update random number for the winning symbol random number. The initial value update random number for the winning symbol random number is for determining the initial value and the ending value of the winning symbol random number. That is, when the hit symbol random number goes around from the initial value update random number for the hit symbol random number to the initial value update random number -1 for the hit symbol random number by the update process of the hit symbol random number described later, the hit symbol random number is obtained at that time. It will be updated to the initial value update random number for the winning symbol random number.

(Step S100-63)
The main CPU 300a analyzes the received data (main command) received from the payout control board 310 and executes various processes according to the received data.

(Step S100-65)
The main CPU 300a performs a process for transmitting a subcommand stored in the transmission buffer to the sub-control board 330.

(Step S100-67)
The main CPU 300a performs a process for permitting an interrupt.

(Step S100-69)
The main CPU 300a updates the reach group determination random number, the reach mode determination random number, and the variation pattern random number, and thereafter repeats the process from step S100-59. In the following, the reach group determination random number, the reach mode determination random number, and the variation pattern random number for determining the variation effect pattern are collectively referred to as a variation effect random number.

FIG. 24 is a flowchart illustrating a subcommand group set process (S110) in the main control board 300 according to the simultaneous rotation reference example.

(Step S110-1)
The main CPU 300a loads the flag value of the gaming machine status flag.

(Step S110-3)
The main CPU 300a performs a subcommand set process for transmitting a predetermined command to the subcontrol board 330.

(Step S110-5)
The main CPU 300a performs a model command setting process for setting a model command indicating the model information of the gaming machine 100 in the transmission buffer.

(Step S110-7)
The main CPU 300a performs a setting value specification command setting process for setting a setting value specification command indicating a registration setting value in the transmission buffer.

(Step S110-9)
The main CPU 300a performs a special figure 1 hold designation command setting process for setting a special figure 1 hold designation command indicating the number of special 1 hold in the transmission buffer.

(Step S110-11)
The main CPU 300a performs a special figure 2 hold designation command setting process for setting a special figure 2 hold designation command indicating the number of special 2 hold designations in the transmission buffer.

(Step S110-13)
The main CPU 300a performs a number-of-times command setting process for setting a number-of-times command indicating the remaining number of times in the time-saving game state in the transmission buffer.

(Step S110-15)
The main CPU 300a performs a variation pattern selection state specification command setting process for setting a variation pattern selection state specification command indicating the variation pattern selection state in the transmission buffer.

(Step S110-17)
The main CPU 300a performs a special figure phase designation command setting process for setting a special figure phase designation command indicating the special game management phase in the transmission buffer. The special game management phase will be described later.

(Step S110-19)
The main CPU 300a determines whether the special game management phase is in the special symbol change waiting state. As a result, if it is determined that the state is in the special symbol change waiting state, the process is shifted to step S110-21, and if it is determined that the state is not in the special symbol change waiting state, the subcommand group set process is terminated.

(Step S110-21)
The main CPU 300a sets the customer waiting designation command in the transmission buffer, and ends the subcommand group set process.

Next, interrupt processing on the main control board 300 will be described. Here, the save process (XINT interrupt process) and the timer interrupt process when the power is turned off will be described.

(Evacuation processing when the power of the main control board 300 is turned off (XINT interrupt processing))
FIG. 25 is a flowchart illustrating an evacuation process (XINT interrupt process) when the power is turned off in the main control board 300 according to the simultaneous rotation reference example. The main CPU 300a monitors the power supply cutoff detection circuit, and when the power supply voltage becomes equal to or less than a predetermined value, it interrupts the CPU initialization process and executes the power failure saver process.

(Step S300-1)
When the power cutoff warning signal is input, the main CPU 300a saves the register.

(Step S300-3)
The main CPU 300a checks the power off warning signal.

(Step S300-5)
The main CPU 300a determines whether or not the power supply cutoff warning signal is detected. As a result, if it is determined that the power off warning signal has been detected, the process is transferred to step S300-11, and if it is determined that the power off warning signal has not been detected, the process is transferred to step S300-7. ..

(Step S300-7)
The main CPU 300a restores the register.

(Step S300-9)
The main CPU 300a performs a process for permitting an interrupt, and ends the save process when the power is turned off.

(Step S300-11)
The main CPU 300a executes an output port clearing process for stopping the output of the output port.

(Step S300-13)
The main CPU 300a executes a checksum setting process for calculating and saving the checksum.

(Step S300-15)
The main CPU 300a executes the RAM protection setting process necessary for prohibiting access to the main RAM 300c.

(Step S300-17)
The main CPU 300a sets a predetermined number of times of power failure detection signal detection to the counter value of the loop counter in order to set the power failure occurrence monitoring time.

(Step S300-19)
The main CPU 300a checks the power off warning signal.

(Step S300-21)
The main CPU 300a determines whether or not the power supply cutoff warning signal is detected. As a result, if it is determined that the power off warning signal has been detected, the process is transferred to step S300-17, and if it is determined that the power off warning signal has not been detected, the process is transferred to step S300-23. ..

(Step S300-23)
The main CPU 300a subtracts 1 from the value of the loop counter set in step S300-17.

(Step S300-25)
The main CPU 300a determines whether the counter value of the loop counter is not 0. As a result, if it is determined that the counter value is not 0, the process proceeds to step S300-19, and if it is determined that the counter value is 0, the process proceeds to the CPU initialization process (step S100) described above.

When the power is actually cut off, the operation of the gaming machine 100 is stopped while looping steps S300-17 to S300-25.

(Timer interrupt processing of main control board 300)
FIG. 26 is a flowchart illustrating timer interrupt processing in the main control board 300 according to the simultaneous rotation reference example. The main control board 300 is provided with a reset clock pulse generation circuit that generates a clock pulse at a predetermined cycle (4 milliseconds in the simultaneous rotation reference example, hereinafter referred to as “4 ms”). Then, when a clock pulse is generated by the reset clock pulse generation circuit, the CPU initialization process (step S100) is interrupted and the following timer interrupt process is executed.

(Step S400-1)
The main CPU 300a saves the register.

(Step S400-3)
The main CPU 300a performs a process for permitting an interrupt.

(Step S400-5)
The main CPU 300a outputs the common data set in the common output buffer to the output port, and outputs the first special symbol display 160, the second special symbol display 162, the first special symbol hold display 164, and the second special symbol display. A dynamic port output process for lighting control of the display 166, the normal symbol display 168, the normal symbol hold display 170, the right-handed notification display 172, and the performance display monitor 184 is executed.

(Step S400-7)
The main CPU 300a reads various input port information and executes a port input process for accurately acquiring the latest switch state.

(Step S400-9)
The main CPU 300a loads the flag value of the gaming machine status flag.

(Step S400-11)
The main CPU 300a determines whether the flag value loaded in step S400-9 is 00H (gamable state). As a result, if it is determined that it is 00H, the process is transferred to step S400-15, and if it is determined that it is not 00H, the process is transferred to step S400-13.

(Step S400-13)
The main CPU 300a determines whether the flag value loaded in step S400-9 is 03H (setting abnormality state) or more. As a result, if it is determined that it is 03H or more, the process is transferred to step S400-29, and if it is determined that it is not 03H or more, the process is transferred to step S450.

(Step S450)
The main CPU 300a executes the setting-related processing and shifts the processing to steps S400-29. The setting-related processing will be described later.

(Step S400-15)
The main CPU 300a performs a timer update process for updating various timer counters. Here, the various timer counters are subtracted each time the timer interrupt process of the main control board 300 is performed, and the subtraction is stopped when it reaches 0, unless otherwise specified.

(Step S400-17)
Similar to step S100-61, the main CPU 300a executes the update process of the initial value update random number for the winning symbol random number.

(Step S400-19)
The main CPU 300a performs a process of updating the winning symbol random number. Specifically, the random number counter is added and updated by 1, and when the added result exceeds the maximum value of the random number range, the random number counter is returned to 0, and when the random number counter makes one round, at that time. Update the initial value for the winning symbol random number Update the random number from the value of the random number.

Although detailed description is omitted, in the simultaneous rotation reference example, the hardware random number updated by the hardware random number generator built in the main control board 300 is used as the jackpot determination random number and the hit determination random number. The hardware random number generator updates both the jackpot random number and the hit random number according to a certain rule, automatically changes the random number sequence each time the random number sequence goes around, and sets the start value every time the system is reset. I'm changing.

(Step S500)
The main CPU 300a includes a first fixed start port detection switch 120As, a first variable start port detection switch 120Bs, a second start port detection switch 122s, a gate detection switch 124s, a normal figure operation port detection switch 125s, and a first grand prize opening detection switch. In 126s, the switch management process for determining whether or not a signal is input from the second large winning opening detection switch 128s is executed. The details of this switch management process will be described later.

(Step S600)
The main CPU 300a executes a special game management process for controlling the progress of the variable display of the special symbol based on the special 2 hold of the special games. The details of this special game management process will be described later.

(Step S600)
The main CPU 300a executes a special game management process for controlling the progress of the variable display of the special symbol based on the special 1 hold of the special games. Here, the same program (module) as the special game management process for controlling the progress of the variable display of the special symbol based on the special 2 hold is read out, and the variable display of the special symbol based on the special 1 hold is advanced. A special game management process for controlling will be executed.

(Step S700)
The main CPU 300a executes a special electric accessory game management process for controlling the progress of the large role game and the small hit game in the special game. The details of this special electric accessory game management process will be described later.

(Step S800)
The main CPU 300a executes a normal game management process for controlling the progress of the normal game. The details of this normal game management process will be described later.

(Step S400-21)
The main CPU 300a executes error management processing for determining various errors and making settings according to the error determination results.

(Step S400-23)
The main CPU 300a checks the general winning opening detection switch 118s, the first starting opening detection switch 120s, the second starting opening detection switch 122s, the first major winning opening detection switch 126s, and the second major winning opening detection switch 128s, and corresponds to the above. The winning opening switch process for adding the counter for controlling the winning ball to be performed is executed.

(Step S400-25)
The main CPU 300a executes a payout control management process for creating and transmitting a payout command based on the counter value of the prize ball control counter set in step S400-23.

(Step S400-27)
The main CPU 300a launches a game ball to transmit a launch position designation command indicating which of the first game area 116a and the second game area 116b to launch the game ball to the sub-control board 330. Execute the position specification management process.

(Step S400-29)
The main CPU 300a executes an external information management process for setting output data for external information to be output from the game information output terminal plate 312 to the outside.

(Step S400-31)
The main CPU 300a includes a first special symbol display 160, a second special symbol display 162, a first special symbol hold indicator 164, a second special symbol hold indicator 166, a normal symbol display 168, and a normal symbol hold indicator 170. , The LED display setting process for setting the display data for lighting control of various indicators (LEDs) such as the right-handed notification indicator 172 in the output buffer corresponding to each common is executed.

(Step S400-33)
The main CPU 300a synthesizes the solenoid output images of the ordinary electric accessory solenoid 120c, the first winning opening solenoid 126c, and the second winning opening solenoid 128c, and executes a solenoid output image compositing process for storing in the output port buffer. ..

(Step S400-35)
The main CPU 300a executes a port output process for outputting the value of the common output buffer stored in each output port buffer to the output port.

(Step S400-37)
The main CPU 300a performs a process for disabling interrupts.

(Step S400-39)
The main CPU 300a uses the unused area of the main RAM 300c to perform processing for calculating the base ratio to be displayed on the performance display monitor 184, and common data for displaying the calculated base ratio on the performance display monitor 184 is common. Executes the performance display monitor control process to be set in the output buffer. In the performance display monitor control process, the base ratio is calculated for each predetermined period. Here, the performance display monitor 184 may switch and display the base ratio of the current period and the base ratio of the period before that at predetermined time intervals. Further, the base ratio displayed on the performance display monitor 184 may be switched according to a predetermined operation.

(Step S400-41)
The main CPU 300a returns the register and ends the timer interrupt process.

FIG. 27 is a flowchart illustrating the setting-related process (S450) according to the simultaneous rotation reference example.

(Step S450-1)
The main CPU 300a determines whether the flag value of the gaming machine state flag is 01H (setting change state). As a result, if it is determined that it is 01H, the process is transferred to step S450-3, and if it is determined that it is not 01H, the process is transferred to step S450-15.

(Step S450-3)
The main CPU 300a loads the registered set value stored in the set value buffer into a predetermined processing area.

(Step S450-5)
The main CPU 300a determines whether the RAM clear switch 182s is pressed (whether the RAM clear operation signal is input). As a result, if it is determined that the RAM clear switch 182s is pressed, the process is transferred to step S450-7, and if it is determined that the RAM clear switch 182s is not pressed, the process is transferred to step S450-9. ..

(Step S450-7)
The main CPU 300a adds 1 to the set value of the processing area.

(Step S450-9)
The main CPU 300a determines whether the set value of the processing area is in the range of 1 to 6. As a result, if it is determined that the set value is in the range of 1 to 6, the process is transferred to step S450-13, and if it is determined that the set value is not in the range of 1 to 6, the process is performed in step S450-11. To move.

(Step S450-11)
The main CPU 300a sets the set value of the processing area to 1.

(Step S450-13)
The main CPU 300a sets the set value of the processing area in the set value buffer.

(Step S450-15)
The main CPU 300a determines whether the setting change switch 180s is on. As a result, when it is determined that the setting change switch 180s is turned on, the setting-related process is terminated, and when it is determined that the setting change switch 180s is not turned on, the process is moved to step S450-17.

(Step S450-17)
The main CPU 300a sets a setting-related end specification command indicating the end of the setting-related processing in the transmission buffer.

(Step S110)
The main CPU 300a executes the subcommand group set process shown in FIG. 24. That is, when the setting-related processing is executed, at the end of the execution, the model command, the setting value specification command, the special figure 1 hold designation command, the special figure 2 hold designation command, the number of times command, the variation pattern selection state specification command, and the special figure phase. The designated command and the customer waiting designated command will be transmitted to the sub-control board 330.

(Step S450-19)
The main CPU 300a sets 00H (gamable state) in the gaming machine status flag, and ends the setting-related processing.

As described above, according to the simultaneous rotation reference example, when the power is turned on normally with the middle frame 104 opened, the setting change switch 180s turned on, and the RAM clear button pressed, the CPU is initially initialized. In the conversion process (FIG. 22), 01H (setting change state) is set in the game machine state flag. After that, the timer interrupt process is executed, but since 01H (setting change state) is set in the game machine status flag, all the processes related to the progress of the game (steps S400-15 to S400-27 in FIG. 26). ) Is stopped and the setting related processing is executed.

The setting-related processing is repeatedly executed while the setting change switch 180s is on, and during this setting-related processing, the operation of pressing the RAM clear button is accepted as the setting change operation of the registered setting value. That is, during the setting change process (S450-1 to S450-13) for accepting the setting change operation, the registered setting value stored in the setting value buffer is one of the setting values provided in a plurality of stages according to the setting change operation. Can be switched to.

Then, when the setting change switch 180s is switched off while the gaming machine status flag is set to 01H (setting change status), the setting change processing is completed and the gaming machine status flag is set to 00H (gaming possible state). It is set. As a result, the process related to the progress of the game can be executed from the next timer interrupt process.

Here, in the setting-related processing of the simultaneous rotation reference example, the setting value corresponding to the registration setting value is specified in the subcommand group set processing after the RAM clear button pressing operation, that is, the acceptance of the registration setting value setting change operation is completed. The command is sent to the sub-control board 330. On the other hand, while the setting change operation is being accepted, the setting value designation command is not transmitted to the sub-control board 330. In this way, while the setting change operation is being accepted, the setting value specification command is transmitted when the acceptance of the setting change operation is completed and the game progresses to a state in which the setting value specification command is not transmitted. By doing so, it is possible to reduce the risk that the registered setting value is illegally acquired.

Further, in the simultaneous rotation reference example, a plurality of flag values including at least 01H (setting change state) can be switched. Then, when 01H (setting change state) is set in the game machine state flag, the setting-related processing can be executed and the progress of the game is stopped. In this way, since the setting-related processing is not executed while the game is in progress, the setting value specification command is not transmitted while the game is in progress, and the risk of illegal acquisition of the registered setting value is reduced. Will be done.

Next, among the timer interrupt processes described above, the switch management process in step S500, the special game management process in step S600, the special electric accessory game management process in step S700, and the normal game management process in step S800 will be described in detail. ..

FIG. 28 is a flowchart illustrating a switch management process (step S500) in the main control board 300 according to the simultaneous rotation reference example.

(Step S500-1)
The main CPU 300a determines whether the gate detection switch is on, that is, whether the game ball has passed through the gate 124 and the detection signal from the gate detection switch 124s is turned on. As a result, if it is determined that the gate detection switch-on is detected, the process is transferred to step S510, and if it is determined that the gate detection switch-on is not detected, the process is transferred to step S500-7.

(Step S510)
The main CPU 300a executes the gate passage process based on the passage of the game ball to the gate 124. The details of this gate passing process will be described later.

(Step S500-3)
The main CPU 300a determines whether the normal figure operating port detection switch is on, that is, whether the game ball enters the normal drawing operating port 125 and the detection signal from the normal drawing operating port detection switch 125s is turned on. .. As a result, if it is determined that the normal figure operation port detection switch-on is detected, the process is moved to step S510, and if it is determined that the normal figure operation port detection switch-on is not detected, the process is performed in step S500-5. To move.

(Step S510)
The main CPU 300a executes the gate passing process based on the entry of the game ball into the normal drawing operating port 125.

(Step S500-5)
The main CPU 300a determines whether the first fixed start port detection switch is on, that is, whether the game ball enters the first fixed start port 120A and the detection signal is input from the first fixed start port detection switch 120As. judge. As a result, if it is determined that the first fixed start port detection switch-on is detected, the process is shifted to step S520, and if it is determined that the first fixed start port detection switch-on is not detected, step S500-7 is performed. Move the process to.

(Step S520)
The main CPU 300a executes the first starting port passing process based on the entry of the game ball into the first fixed starting port 120A. The details of the process of passing through the first starting port will be described later.

(Step S500-7)
The main CPU 300a determines whether the first variable start port detection switch is on, that is, whether the game ball enters the first variable start port 120B and the detection signal is input from the first variable start port detection switch 120Bs. judge. As a result, if it is determined that the first variable start port detection switch-on is detected, the process is shifted to step S520, and if it is determined that the first variable start port detection switch-on is not detected, step S500-11 is performed. Move the process to.

(Step S520)
The main CPU 300a executes the first start port passing process based on the entry of the game ball into the first variable start port 120B. The details of the process of passing through the first starting port will be described later.

(Step S500-9)
The main CPU 300a determines whether or not the game ball has been properly entered into the first variable starting port 120B, and if it is determined that the game ball has not been properly entered, the first An ordinary electric accessory winning confirmation process for transmitting a command for specifying an illegal winning error of a general electric machine indicating an illegal entry of a game ball into the variable starting port 120B to the sub-control board 330 is executed.

(Step S500-11)
The main CPU 300a determines whether the second start port detection switch is on, that is, whether the game ball has entered the second start port 122 and the detection signal has been input from the second start port detection switch 122s. As a result, if it is determined that the second start port detection switch-on is detected, the process is transferred to step S530, and if it is determined that the second start port detection switch-on is not detected, the process is performed in step S500-13. To move.

(Step S530)
The main CPU 300a executes the second starting port passing process based on the entry of the game ball into the second starting port 122. The details of this second starting port passing process will be described later.

(Step S500-13)
The main CPU 300a is at the time of detecting the large winning opening detection switch on, that is, the game ball enters the first large winning opening 126 or the second large winning opening 128, and the first large winning opening detection switch 126s or the second It is determined whether or not the detection signal is input from the large winning opening detection switch 128s. As a result, if it is determined that the large winning opening detection switch-on is detected, the process is shifted to step S540, and if it is determined that the large winning opening detection switch-on is not detected, the switch management process is terminated.

(Step S540)
When the main CPU 300a determines whether or not the game ball has been properly entered into the first large winning opening 126 or the second large winning opening 128, and determines that the game ball has been properly entered. Is to execute a large winning opening passing process for transmitting a large winning opening entry command indicating the entry of a game ball into the first large winning opening 126 or the second large winning opening 128 to the sub-control board 330. The details of this large winning opening passing process will be described later.

FIG. 29 is a flowchart illustrating a gate passing process (step S510) in the main control board 300 according to the simultaneous rotation reference example.

(Step S510-1)
The main CPU 300a loads the hit determination random number updated by the hardware random number generator.

(Step S510-3)
The main CPU 300a determines whether the counter value of the normal symbol reserved ball number counter is the maximum value or more, that is, whether the counter value of the normal symbol reserved ball number counter is 4 or more. As a result, when it is determined that the counter value of the normal symbol reserved ball count counter is equal to or higher than the maximum value, the gate passing process is terminated, and when it is determined that the normal symbol reserved ball number counter is not equal to or higher than the maximum value. The process is transferred to step S510-5.

(Step S510-5)
The main CPU 300a updates the counter value of the normal symbol reserved ball count counter to a value obtained by adding "1" to the current counter value.

(Step S510-7)
The main CPU 300a calculates the target storage unit for saving the acquired hit determination random number among the four storage units in the normal figure reservation storage area.

(Step S510-9)
The main CPU 300a saves the winning determination random number acquired in step S510-1 in the target storage unit calculated in step S510-7.

(Step S510-11)
The main CPU 300a sets the normal figure hold designation command indicating the number of normal figure hold stored in the normal figure hold storage area in the transmission buffer, and ends the gate passing process.

FIG. 30 is a flowchart illustrating a first starting port passing process (step S520) in the main control board 300 according to the simultaneous rotation reference example.

(Step S520-1)
The main CPU 300a sets "00H" as a special symbol identification value. The special symbol identification value is for identifying whether the hold type is special 1 hold or special 2 hold, and the special symbol identification value (00H) indicates special 1 hold, and the special symbol identification value ( 01H) indicates special 2 hold.

(Step S520-3)
The main CPU 300a sets the address of the special symbol 1 reserved ball number counter.

(Step S535)
The main CPU 300a executes the special symbol random number acquisition process and ends the first start port passing process. The special symbol random number acquisition process is executed by using a module common to the second start port passing process (step S530). Therefore, the details of the special symbol random number acquisition process will be described after the description of the second start port passing process.

FIG. 31 is a flowchart illustrating a second starting port passing process (step S530) in the main control board 300 according to the simultaneous rotation reference example.

(Step S530-1)
The main CPU 300a sets "01H" as a special symbol identification value.

(Step S530-3)
The main CPU 300a sets the address of the special symbol 2 reserved ball number counter.

(Step S535)
The main CPU 300a executes a special symbol random number acquisition process described later, and ends the second start port passage process.

FIG. 32 is a flowchart illustrating a special symbol random number acquisition process (step S535) in the main control board 300 according to the simultaneous rotation reference example. This special symbol random number acquisition process is executed by using a common module in the first start port passage process (step S520) and the second start port passage process (step S530) described above.

(Step S535-1)
The main CPU 300a loads the special symbol identification value set in step S520-1 or step S530-1.

(Step S535-3)
The main CPU 300a loads the number of target special symbol reserved balls. Here, if the special symbol identification value loaded in step S535-1 is "00H", the counter value of the special symbol 1 reserved ball count counter, that is, the special 1 reserved number is loaded. If the special symbol identification value loaded in step S535-1 is "01H", the counter value of the special symbol 2 reserved ball number counter, that is, the special 2 reserved number is loaded.

(Step S535-5)
The main CPU 300a loads the jackpot determination random number updated by the hardware random number generator.

(Step S535-7)
The main CPU 300a determines whether or not the number of target special symbol reserved balls loaded in step S535-3 is equal to or greater than the upper limit value. As a result, if it is determined that the value is equal to or higher than the upper limit value, the special symbol random number acquisition process is terminated, and if it is determined that the value is not equal to or higher than the upper limit value, the process proceeds to step S535-9.

(Step S535-9)
The main CPU 300a updates the counter value of the target special symbol reserved ball count counter to a value obtained by adding "1" to the current counter value.

(Step S535-11)
The main CPU 300a calculates the target storage unit for saving the acquired jackpot determination random number among the storage units in the special figure reservation storage area.

(Step S535-13)
The main CPU 300a acquires the jackpot determination random number loaded in step S535-5, the hit symbol random number updated in step S400-19, and the variation pattern random number updated in step S100-69, and obtains the variation pattern random number updated in step S100-69. Store in the target storage unit calculated in.

(Step S535-15)
The main CPU 300a loads the counter values of the special symbol 1 reserved ball number counter and the special symbol 2 reserved ball number counter.

(Step S535-17)
The main CPU 300a sets the special figure hold designation command in the transmission buffer based on the counter value loaded in step S535-15. Here, the special figure 1 hold designation command is set based on the counter value (special 1 hold number) of the special symbol 1 hold ball number counter, and based on the counter value (special 2 hold number) of the special symbol 2 hold ball number counter. Set the special figure 2 hold designation command. As a result, each time the special 1 hold or the special 2 hold is stored, the special 1 hold number and the special 2 hold number are transmitted to the sub-control board 330.

(Step S536)
The main CPU 300a performs an effect determination process at the time of acquisition, and ends the special symbol random number acquisition process. In this acquisition-time effect determination process, the result of the large winning combination lottery, the variation pattern number, and the like are tentatively determined, and a look-ahead designation command according to the tentative determination result is transmitted to the sub-control board 330. The acquisition-time effect determination process will be described with reference to FIG. 33.

FIG. 33 is a flowchart illustrating the acquisition-time effect determination process (step S536) in the main control board 300 according to the simultaneous rotation reference example.

(Step S536-1)
The main CPU 300a selects the corresponding jackpot determination random number determination table based on the set value being set. Specifically, the corresponding jackpot determination random number determination table is selected based on the current game state and the set value being set. Then, based on the selected table and the jackpot determination random number stored in the target storage unit in step S535-13, a special symbol hit provisional determination process for provisionally determining any of jackpot, small hit, and loss is performed.

(Step S536-3)
The main CPU 300a executes a special symbol symbol provisional determination process for provisionally determining the special symbol. Here, if the result of the provisional large winning combination lottery in step S536-1 (the result derived by the provisional determination process for special symbol hits) is a big hit or a small hit, it is stored in the target storage unit in step S535-13. Load the winning symbol random number, winning type (big hit or small hit), and hold type, select the corresponding winning symbol random number judgment table, extract the special symbol judgment data, and extract the special symbol judgment data. Save (type of big hit symbol or small hit symbol). Further, when the result of the provisional large role lottery in step S536-1 is a loss, the special symbol determination data (type of the lost symbol) for a predetermined loss is saved.

(Step S536-5)
The main CPU 300a sets the look-ahead symbol type designation command (look-ahead designation command) corresponding to the special symbol determination data saved in step S536-3 in the transmission buffer.

(Step S536-7)
The main CPU 300a determines whether the result derived by the special symbol hit provisional determination process in step S536-1 is a big hit or a small hit. As a result, if it is determined that it is a big hit or a small hit, the process is transferred to step S536-9, and if it is determined that it is not a big hit or a small hit (it is a loss), the process is transferred to step S536-11.

(Step S536-9)
The main CPU 300a sets the jackpot reach mode determination random number determination table (see FIGS. 10B and 10) or the small hit reach mode determination random number determination table (FIGS. 10D and e), and steps. The process is transferred to S536-19.

(Step S536-11)
The main CPU 300a loads the reach group determination random number stored in the target storage unit in step S535-13.

(Step S536-13)
The main CPU 300a determines whether the reach group determination random number loaded in step S536-11 has a fixed value (9000 or more). Here, the group type is determined with reference to the reach group determination random number determination table, and this reach group determination random number determination table is selected according to the stored number of reservations. At this time, the reach group determination random number is acquired from the range of 0 to 10066, and if the value of the reach group determination random number is 9000 or more, the same reach group determination random number determination table is selected regardless of the number of reservations, and the reach is reached. If the value of the group determination random number is less than 9000, a different reach group determination random number determination table is selected according to the number of holds. In the following, among the reach group determination random numbers, the value in the range of 0 to 8999 in which different reach group determination random number determination tables are selected according to the number of reservations is set as an indefinite value, and the same reach group determination random number determination is performed regardless of the number of reservations. A value in the range of 9000 to 10006 from which the table is selected is called a fixed value. If it is determined that the reach group determination random number loaded in step S536-11 has a fixed value (9000 or more), the process is transferred to step S536-15, and the reach group determination random number loaded in step S536-11 is fixed. If it is determined that the value is not (9000 or more), the process is moved to step S536-27.

(Step S536-15)
The main CPU 300a sets a reach group determination random number determination table (see FIG. 9). A plurality of types of reach group determination random number determination tables are provided according to the number of holdings, but here, the table used when the number of holdings is 0 is selected. Then, the reach group (group type) is tentatively determined based on the set reach group determination random number determination table and the reach group determination random number stored in the target storage unit in step S535-13.

(Step S536-17)
The main CPU 300a sets a random number determination table for determining the reach mode at the time of loss (see FIG. 10A) corresponding to the group type provisionally determined in step S536-15, and shifts the process to step S536-19.

(Step S536-19)
The main CPU 300a has a variable mode number based on the reach mode determination random number determination table set in step S536-9 or step S536-17 and the reach mode determination random number stored in the target storage unit in step S535-13. Is tentatively decided. Further, here, the fluctuation pattern random number determination table is tentatively determined together with the fluctuation mode number.

(Step S536-21)
The main CPU 300a sets the look-ahead designation variable mode command (look-ahead designation command) corresponding to the variable mode number tentatively determined in step S536-19 in the transmission buffer.

(Step S536-23)
The main CPU 300a tentatively determines the variation pattern number based on the variation pattern random number determination table tentatively determined in step S536-19 and the variation pattern random number stored in the target storage unit in step S535-13.

(Step S536-25)
The main CPU 300a sets the look-ahead designation variation pattern command (look-ahead designation command) corresponding to the variation pattern number tentatively determined in step S536-23 in the transmission buffer, and ends the acquisition-time effect determination process.

(Step S536-27)
The main CPU 300a is an indefinite value command (look-ahead) indicating that the group type, that is, the variation effect pattern changes according to the number of holds when the hold is read, for the hold newly stored in the target storage unit. The designated variation mode command and the look-ahead specified variation pattern command = 7FH) are set in the transmission buffer, and the effect determination process at the time of acquisition is terminated.

FIG. 34 is a flowchart illustrating a large winning opening passing process (step S540) in the main control board 300 according to the simultaneous rotation reference example.

(Step S540-1)
When the main CPU 300a determines in step S500-13 that it is the time when the large winning opening detection switch-on is detected, the main CPU 300a loads the special electric accessory game management phase described in detail later. As will be described in detail later, the special electric accessory game management phase indicates the stage of execution processing of the large role game or the small hit game, that is, the progress of the large role game or the small hit game, and indicates the progress of the large role game or the small hit game. It is updated according to the stage of the execution process of the winning game.

(Step S540-3)
The main CPU 300a determines whether the special electric accessory game management phase loaded in step S540-1 indicates a stage of execution processing equal to or higher than the pre-processing for opening the large winning opening. The special electric accessory game management phase is provided with nine stages from 00H to 08H, of which 01H to 08H corresponds to the execution processing stage equal to or higher than the pre-opening of the large winning opening. Since the big role game or the small hit game is executed when the special electric accessory game management phase is 01H to 08H, here, it is determined whether the big role game or the small hit game is currently in progress. Become. If it is determined that the special electric accessory game management phase indicates the stage of execution processing equal to or higher than the pre-processing for opening the large winning opening, the processing is moved to step S540-5, and the special electric accessory game management phase is set. If it is determined that it does not indicate the stage of execution processing higher than the pre-processing for opening the large winning opening, the processing is moved to step S540-7.

(Step S540-5)
The main CPU 300a sets a large winning opening command indicating that the game ball has properly entered the first large winning opening 126 or the second large winning opening 128 in the transmission buffer, and ends the large winning opening passing process. ..

(Step S540-7)
The main CPU 300a executes a predetermined error process on the assumption that the ball of the game ball is improperly entered into the first special winning opening 126 or the second special winning opening 128, and ends the large winning opening passing process.

FIG. 35 is a diagram illustrating a special game management phase according to the simultaneous rotation reference example. As already explained, in the simultaneous turning reference example, a special game triggered by the entry of the game ball into the first start port 120 or the second start port 122, and the passage of the game ball to the gate 124 or the normal drawing operation port A normal game triggered by the entry of the game ball into 125 proceeds in parallel at the same time. The processing related to the special game is executed stepwise and repeatedly, and the main control board 300 manages each processing related to the special game by the special game management phase and the special electric accessory game management phase. ..

As shown in FIG. 35, a plurality of special game control modules for executing and controlling the variation display of the special symbol in the special game are stored in the main ROM 300b, and the special game is stored for each of these special game control modules. Management phases are associated. Specifically, when the special game management phase is "00H", the module for executing the "special symbol change waiting process" is called, and when the special game management phase is "01H", the module is called. The module for executing the "special symbol changing process" is called, and when the special game management phase is "02H", the module for executing the "special symbol stop symbol display process" is called.

Further, the main ROM 300b stores a plurality of special electric accessory game control modules for executing and controlling the large role game and the small hit game among the special games, and each of these special electric accessory game control modules is stored. A special electric accessory game management phase is associated with it. Specifically, when the special electric accessory game management phase is "01H" or "05H", the module for executing the "pre-processing for opening the large winning opening" is called, and the special electric accessory game management is performed. When the phase is "02H" or "06H", the module for executing the "large winning opening opening control process" is called, and the special electric accessory game management phase is "03H" or "07H". In that case, the module for executing the "large winning opening closing effective processing" is called, and when the special electric accessory game management phase is "04H" or "08H", the "large winning opening end wait processing" is performed. The module to execute "is called. When the special electric accessory game management phase is "00H", none of the special electric accessory game control modules is called.

FIG. 36 is a flowchart illustrating a special game management process (step S600) in the main control board 300 according to the simultaneous rotation reference example.

(Step S600-1)
The main CPU 300a loads the special electric accessory game management phase.

(Step S600-3)
The main CPU 300a determines whether the special electric accessory game management phase loaded in step S600-1 is other than "00H". That is, here, it is determined whether the player is currently in the big role game or the small hit game. If it is determined that the special electric accessory game management phase is other than "00H", the special game management process is terminated, and if it is determined that the special electric accessory game management phase is not other than "00H", step S600 Move the process to -5.

(Step S600-5)
The main CPU 300a loads the special game special symbol determination flag. The special game special symbol determination flag is for determining whether the hold type to be the target of the special game management process is special 1 hold or special 2 hold, and the special game special symbol determination flag (00H). ) Indicates Special 1 hold, and the special game special symbol determination flag (01H) indicates Special 2 hold.

(Step S600-7)
The main CPU 300a inverts the special game special symbol determination flag loaded in step S600-5. Here, when the special game special symbol determination flag is "00H", it is inverted to "01H", and when the special game special symbol determination flag is "01H", it is inverted to "00H". Since the initial value of the special game special symbol determination flag is set to "00H", among the two special game management processes S600 shown in FIG. 26, the first special game management process S600 determines the special game special symbol. The flag is set to "01H", the subsequent processing is executed for the special 2 hold, the special game special symbol determination flag is set to "00H" in the second special game management process S600, and the subsequent processing is executed for the special 1 hold. Will be done. That is, the special 2 hold is processed with priority.

(Step S600-9)
The main CPU 300a saves the special game special symbol determination flag inverted in step S600-7.

(Step S600-11)
The main CPU 300a loads the special game management phase.

(Step S600-13)
The main CPU 300a selects the special game control module corresponding to the special game management phase loaded in step S600-11.

(Step S600-15)
The main CPU 300a calls the special game control module selected in step S600-13 to start the process.

(Step S600-17)
The main CPU 300a loads a special game timer that manages the control time of the special game, and ends the special game management process.

FIG. 37 is a flowchart illustrating a special symbol change waiting process in the main control board 300 according to the simultaneous rotation reference example. This special symbol change waiting process is executed when the special game management phase is "00H".

(Step S610-1)
The main CPU 300a determines whether or not the number of special symbol hold balls of the hold (special 1 hold or special 2 hold, hereinafter referred to as target hold) subject to the special game management process is 1 or more. As a result, if it is determined that the number of special symbol reserved balls is 1 or more, the process is shifted to step S610-3, and if it is determined that the number of special symbol reserved balls is not 1 or more, the special symbol change waiting process is performed. To finish.

(Step S610-3)
In the main CPU 300a, a special symbol (hereinafter referred to as a non-target special symbol) based on a hold (special 2 hold or special 1 hold, hereinafter referred to as a non-target hold) that is not subject to the special game management process is being determined. Determine if there is. As a result, if it is determined that the non-target special symbol is being determined, the process is shifted to step S610-5, and if it is determined that the special symbol based on the non-target special symbol is not being determined, step S610-9 is performed. Move the process to.

(Step S610-5)
The main CPU 300a determines whether the non-target special symbol is a jackpot symbol. As a result, if it is determined that the symbol is a jackpot symbol, the special symbol change waiting process is terminated, and if it is determined that the symbol is not a jackpot symbol, the process is moved to step S610-7.

(Step S610-7)
The main CPU 300a determines whether the non-target special symbol is a small hit symbol. As a result, if it is determined that the symbol is a small hit symbol, the special symbol change waiting process is terminated, and if it is determined that the symbol is not a small hit symbol, the process is moved to step S610-9.

(Step S610-9)
The main CPU 300a blocks-transfers the target hold stored in the first to fourth storage units of the special figure hold storage area corresponding to the target hold to a storage unit having a smaller ordinal number. Specifically, the object hold stored in the second storage unit to the fourth storage unit is transferred to the first storage unit to the third storage unit. Further, the main RAM 300c is provided with a 0th storage unit to be processed, and the target hold stored in the 1st storage unit is block-transferred to the 0th storage unit. In this special symbol storage area shift process, the counter value of the target special symbol hold ball count counter corresponding to the target hold is subtracted by "1", and the hold decrease indicates that the target hold is subtracted by "1". Set the specified command in the send buffer.

(Step S611)
The main CPU 300a executes a special symbol hit determination process for performing a large winning combination lottery. This special symbol hit detection process will be described later.

(Step S610-11)
The main CPU 300a executes a special symbol symbol determination process for determining the special symbol. Here, when the result of the big winning combination lottery in step S611 is a big hit or a small hit, the winning symbol random number and the hold type transferred to the 0th storage unit are loaded, and the corresponding winning symbol random number determination table or the small hit symbol is loaded. Select the random number judgment table, extract the special symbol judgment data, and save the extracted special symbol judgment data (type of jackpot symbol). If the result of the big winning combination lottery in step S611 is a loss, the special symbol determination data for the loss is saved. Then, after saving the special symbol determination data, the symbol type designation command corresponding to the special symbol determination data is set in the transmission buffer.

(Step S610-13)
The main CPU 300a saves the special symbol stop symbol number corresponding to the special symbol determination data extracted in step S610-11. The first special symbol display 160 and the second special symbol display 162 are each composed of 7 segments, and each segment constituting the 7 segments is associated with a number (counter value). The special symbol stop symbol number determined here indicates the number (counter value) of the segment that is finally lit.

(Step S612)
The main CPU 300a executes a special symbol variation number determination process for determining the variation mode number and the variation pattern number. The details of this special symbol variation number determination process will be described later.

(Step S610-15)
The main CPU 300a loads the fluctuation mode number and the fluctuation pattern number determined in step S612, and determines the fluctuation time 1 and the fluctuation time 2 with reference to the fluctuation time determination table. Then, the total time of the determined fluctuation times 1 and 2 is set in the special symbol fluctuation timer.

(Step S610-17)
The main CPU 300a determines whether or not the result of the big win lottery is a big hit, and if it is a big hit, loads the special symbol determination data saved in step S610-11 and confirms the type of the big hit symbol. do. Then, with reference to the game state setting table and the current game state, the game state, the high probability number, and the time reduction number set after the end of the big role game are determined, and the determination result is used as the special symbol probability state reserve flag and the time reduction state reserve. Save to the flag, high-probability number-cutting spare counter, and time-saving number-cutting spare counter. If the lost symbol is saved, the process proceeds to the next process without executing the process.

(Step S610-19)
The main CPU 300a executes a process of setting a special symbol display symbol counter in the first special symbol display 160 or the second special symbol display 162 in order to start the variable display of the special symbol. A counter value is associated with each segment of the 7-segments constituting the first special symbol display 160 and the second special symbol display 162, and the segment corresponding to the counter value set in the special symbol display symbol counter is Lighting is controlled. Here, the counter value corresponding to the segment to be turned on at the start of the variable display of the special symbol is set in the special symbol display symbol counter. The special symbol display symbol counter is provided separately with a special symbol 1 display symbol counter corresponding to the first special symbol display 160 and a special symbol 2 display symbol counter corresponding to the second special symbol display 162. Here, the counter value is set in the counter corresponding to the hold type.

(Step S613)
The main CPU 300a executes the count-cutting management process. Here, processing is performed to end the time-saving game state according to the number of fluctuations. This number-cutting management process will be described later.

(Step S610-21)
The main CPU 300a sets a number-of-times command indicating the remaining number of times (actual remaining number of times) until the high-accuracy number of times and the time-saving number of times become 0 in the transmission buffer.

(Step S610-23)
The main CPU 300a sets in the transmission buffer a game state change designation command indicating the game state at the start of the variation display of the special symbol.

(Step S610-25)
The main CPU 300a updates the special game management phase to "01H" and ends the special symbol change waiting process.

FIG. 38 is a flowchart illustrating the special symbol collision determination process (S611) according to the simultaneous rotation reference example.

(Step S611-1)
The main CPU 300a loads the special symbol probability state flag.

(Step S611-3)
The main CPU 300a loads the registered set value of the set value buffer.

(Step S611-5)
The main CPU 300a determines whether the registration set value loaded in step S611-3 is within the normal range. As a result, if it is determined that the value is within the normal range, the process is transferred to step S611-11, and if it is determined that the value is not within the normal range, the process is transferred to step S611-7.

(Step S611-7)
The main CPU 300a sets 03H (setting abnormal state) in the gaming machine status flag.

(Step S611-9)
The main CPU 300a sets the setting abnormality state command (subcommand) in the transmission buffer, and ends the special symbol hit determination process. When this setting abnormality state command is transmitted to the sub-control board 330, a notification indicating that the setting is abnormal is made.

(Step S611-11)
The main CPU 300a refers to the jackpot determination random number determination table corresponding to the information loaded in step S611-1 and step S611-3, and sets the lower limit value and the upper limit value when determining the jackpot or the small hit, respectively.

(Step S611-13)
The main CPU 300a compares the big hit determination random number transferred to the 0th storage unit with the above lower limit value and upper limit value, and performs a determination process (big win lottery) for determining whether or not a big hit or a small hit has been won.

(Step S611-15)
The main CPU 300a determines whether the non-target special symbol is a jackpot symbol. As a result, if it is determined that the symbol is a jackpot symbol, the process is transferred to step S611-17, and if it is determined that the symbol is not a jackpot symbol, the process is transferred to step S611-21.

(Step S611-17)
The main CPU 300a determines whether the large winning combination lottery result in step S611-13 is a small hit or a loss. As a result, if it is determined that there is a small hit or a loss, the process is transferred to step S611-21, and if it is determined that there is no small hit or loss, the process is transferred to step S611-19.

(Step S611-19)
The main CPU 300a changes the result of the large winning combination lottery in step S611-13 to a loss.

(Step S611-21)
The main CPU 300a sets the result of the determination process in step S611-13 or the result changed in step S611-19 as determination information, and ends the special symbol hit detection process.

FIG. 39 is a flowchart illustrating a special symbol variation number determination process (step S612) in the main control board 300 according to the simultaneous rotation reference example.

(Step S612-1)
The main CPU 300a determines whether the result of the big winning combination lottery in step S611 is a big hit or a small hit. As a result, if it is determined that it is a big hit or a small hit, the process is moved to step S612-3, and if it is determined that it is neither a big hit nor a small hit (it is a loss), the process is performed in step S612-5. Transfer.

(Step S612-3)
The main CPU 300a sets a reach mode determination random number determination table corresponding to the current gaming state and the hold type.

(Step S612-5)
The main CPU 300a confirms the counter value of the special symbol 2 hold ball count counter when the hold type of the read hold is the special 2 hold, and when the hold type of the read hold is the special 1 hold, the main CPU 300a confirms the counter value. Special symbol 1 Check the counter value of the reserved ball count counter.

(Step S612-7)
The main CPU 300a sets the corresponding reach group determination random number determination table based on the current gaming state, the number of holds confirmed in step S612-5, and the hold type. Then, the reach group (group type) is determined based on the set reach group determination random number determination table and the reach group determination random number transferred to the 0th storage unit in step S610-9.

(Step S612-9)
The main CPU 300a sets a random number determination table for determining the reach mode at the time of loss corresponding to the group type determined in step S612-7.

(Step S612-11)
The main CPU 300a has a variable mode based on the reach mode determination random number determination table set in step S612-3 or step S612-9 and the reach mode determination random number transferred to the 0th storage unit in step S610-9. Determine the number. Further, here, the fluctuation pattern random number determination table is determined together with the fluctuation mode number.

(Step S612-13)
The main CPU 300a sets the variable mode command corresponding to the variable mode number determined in step S612-11 in the transmission buffer.

(Step S612-15)
The main CPU 300a determines the variation pattern number based on the variation pattern random number determination table determined in step S612-11 and the variation pattern random number transferred to the 0th storage unit in step S610-9.

(Step S612-17)
The main CPU 300a sets the variation pattern command corresponding to the variation pattern number determined in step S612-15 in the transmission buffer, and ends the special symbol variation number determination process.

FIG. 40 is a flowchart illustrating a number-of-times cutting management process (step S613) in the main control board 300 according to the simultaneous rotation reference example.

(Step S613-1)
The main CPU 300a determines whether the number of time reductions, that is, the counter value of the time reduction count cut counter is larger than 0. As a result, if it is determined that the number of time reductions is larger than 0, the process is moved to step S613-3, and if it is determined that the number of time reductions is 0, the number cut management process is terminated.

(Step S613-3)
The main CPU 300a decrements the time reduction counter.

(Step S613-5)
The main CPU 300a determines in step S613-3 whether the counter value (number of time reductions) has been updated to 0. As a result, if it is determined that the number of time reductions is 0, the process is moved to step S613-7, and if it is determined that the number of time reductions is not 0, the number cut management process is terminated.

(Step S613-7)
The main CPU 300a sets the time saving state flag in order to set the normal gaming state to the non-time saving gaming state. As a result, after the normal game state is set to the time-saving game state, the normal game state is changed to the non-time-saving game state at the start of the fluctuation when the number of fluctuations reaches the time-saving number of times (50 times or 100 times in this case). The Rukoto. For example, if it is set to the high probability precursor state, it will be set to the highest advantage state.

(Step S613-9)
The main CPU 300a turns on the time saving end flag and ends the number-of-times cut management process.

FIG. 41 is a flowchart illustrating a process during special symbol change in the main control board 300 according to the simultaneous rotation reference example.

(Step S620-1)
The main CPU 300a determines whether the suspended flag is on. As will be described in detail later, in the simultaneous rotation reference example, the small hit symbol may be stopped and displayed on the second special symbol display 162 during the variable display of the symbol on the first special symbol display 160. In this case, when the small hit symbol is stopped and displayed on the second special symbol display 162, the small hit game is executed, but during this time, the subtraction of the fluctuation time of the special symbol on the first special symbol display 160 is interrupted. After the small hit game is completed, the variable display of the symbol on the first special symbol display 160 is restarted. The suspended flag is turned on when the small hit symbol is stopped and displayed on the second special symbol display 162 and the symbol is being displayed on the first special symbol display 160. Here, if it is determined that the suspended flag is on, the processing during the special symbol change is terminated, and if it is determined that the suspended flag is not on, the process is moved to step S620-3.

(Step S620-3)
The main CPU 300a executes a process of updating the special symbol fluctuation base counter. The counter value of the special symbol fluctuation base counter is set so as to make one round in a predetermined cycle (for example, 100 ms). Specifically, when the counter value of the special symbol fluctuation base counter is "0", a predetermined counter value (for example, 25) is set, and when the counter value is "1" or more, it is set. The counter value is updated to the value obtained by subtracting "1" from the current counter value.

(Step S620-5)
The main CPU 300a determines whether the counter value of the special symbol variation base counter updated in step S620-3 is "0". As a result, if the counter value is "0", the process is transferred to step S620-7, and if the counter value is not "0", the process is transferred to step S620-11.

(Step S620-7)
The main CPU 300a performs a special symbol variation timer update process of subtracting a predetermined value from the timer value of the special symbol variation timer set in step S610-15.

(Step S620-9)
The main CPU 300a determines whether the timer value of the special symbol variation timer updated in step S620-7 is "0". As a result, if the timer value is "0", the process is transferred to step S620-17, and if the timer value is not "0", the process is transferred to step S620-11.

(Step S620-11)
The main CPU 300a updates the special symbol display timer that measures the lighting time of each segment of the 7-segments constituting the first special symbol display 160 and the second special symbol display 162. Specifically, when the timer value of the special symbol display timer is "0", a predetermined timer value is set, and when the timer value is "1" or more, the current timer value is used. "1" Updates the timer value to the subtracted value.

(Step S620-13)
The main CPU 300a determines whether the timer value of the special symbol display timer is "0". As a result, when it is determined that the timer value of the special symbol display timer is "0", the process is shifted to step S620-15, and when it is determined that the timer value of the special symbol display timer is not "0", the process is concerned. Ends processing during special symbol change.

(Step S620-15)
The main CPU 300a updates the counter value of the special symbol display symbol counter to be updated, and ends the processing during the special symbol change. As a result, each segment constituting the 7-segment is turned on in sequence at predetermined time intervals.

(Step S620-17)
The main CPU 300a determines whether or not the non-target special symbol is being displayed in a variable manner. As a result, when it is determined that the non-target special symbol is in the variable display, the process is transferred to step S621, and when it is determined that the non-target special symbol is not in the variable display, the process is transferred to step S620-19.

(Step S621)
The main CPU 300a executes the symbol forced stop process. This symbol forced stop processing will be described later with reference to FIG. 42.

(Step S620-19)
The main CPU 300a updates the special game management phase to "02H".

(Step S620-21)
The main CPU 300a saves the special symbol stop symbol number (counter value) determined in step S610-13 in the target special symbol display symbol counter. As a result, the determined special symbol is stopped and displayed on the first special symbol display 160 or the second special symbol display 162.

(Step S620-23)
The main CPU 300a sets in the transmission buffer a special symbol stop designation command indicating that the special symbol has been stopped and displayed on the first special symbol display 160 or the second special symbol display 162.

(Step S620-25)
The main CPU 300a sets the special symbol change stop time, which is the time for stopping and displaying the special symbol, in the special game timer, and ends the processing during the special symbol change.

FIG. 42 is a flowchart illustrating a symbol forced stop process (step S621) in the main control board 300 according to the simultaneous rotation reference example.

(Step S621-1)
The main CPU 300a determines whether the special symbol during the stop display (corresponding) is a small hit symbol. As a result, if it is determined that the symbol is a small hit symbol, the process is transferred to step S621-3, and if it is determined that the symbol is not a small hit symbol, the process is transferred to step S621-11.

(Step S621-3)
The main CPU 300a determines whether the special game special symbol determination flag is 00H, that is, whether the small hit symbol is stopped and displayed on the first special symbol display 160. As a result, if it is determined that the special game special symbol determination flag is 00H, the process is shifted to step S621-11, and if it is determined that the special game special symbol determination flag is not 00H, the process is performed in step S621-5. To move.

(Step S621-5)
The main CPU 300a determines whether the special symbol in the variable display (the other) is a jackpot symbol. As a result, if it is determined that the symbol is a jackpot symbol, the process is transferred to step S621-11, and if it is determined that the symbol is not a jackpot symbol, the process is transferred to step S621-7.

(Step S621-7)
The main CPU 300a turns on the suspended flag.

(Step S621-9)
The main CPU 300a executes a fluctuation interruption process for interrupting the variation display of the special symbol, and ends the symbol forced stop process. Here, a process is performed in which the remaining time of the fluctuation time and the information related to the special symbol are temporarily saved in a predetermined storage area.

(Step S621-11)
The main CPU 300a forcibly stops the lost symbol on the first special symbol display 160 or the second special symbol display 162 on which the symbol is displayed in a variable manner, and forcibly terminates the remaining variable time. The process of turning on the stop flag is performed, and the process of forcibly stopping the symbol is terminated.

By the above processing, when the small hit symbol is stopped and displayed on the first special symbol display 160, the lost symbol is forcibly stopped and displayed on the second special symbol display 162. Further, when the small hit symbol is stopped and displayed on the second special symbol display 162, the first special symbol is displayed if the big hit symbol is finally stopped and displayed on the first special symbol display 160 during the variable display. A lost symbol is forcibly stopped and displayed on the vessel 160. On the other hand, when the small hit symbol is stopped and displayed on the second special symbol display 162, the small hit symbol or the lost symbol is finally stopped and displayed on the first special symbol display 160. 1 The variable display on the special symbol display 160 will be temporarily interrupted.

FIG. 43 is a flowchart illustrating a special symbol stop symbol display process on the main control board 300 according to the simultaneous rotation reference example.

(Step S630-1)
The main CPU 300a determines whether the timer value of the special game timer set in step S620-25 is not "0". As a result, when it is determined that the timer value of the special game timer is not "0", the special symbol stop symbol display process is terminated, and when it is determined that the timer value of the special game timer is "0", the special symbol stop symbol display process is terminated. The process is transferred to step S630-3.

(Step S630-3)
The main CPU 300a determines whether the variable time special stop flag is on. As a result, if it is determined that the variable time special stop flag is on, the process is moved to step S630-5, and if it is determined that the variable time special stop flag is not on, the special symbol stop symbol display process is terminated. do.

(Step S630-5)
The main CPU 300a confirms the result of the big winning combination lottery.

(Step S630-7)
The main CPU 300a determines whether the result of the big winning combination lottery is a loss. As a result, if it is determined that there is a loss, the process is transferred to step S630-27, and if it is determined that there is no loss, the process is transferred to step S630-9.

(Step S630-9)
The main CPU 300a performs a game state update process for updating the game state. Here, the game state is set to the initial state when the special symbol displayed in the stop display is the jackpot symbol, and when the special symbol displayed in the stop display is the small hit symbol, the process proceeds to the next process as it is.

(Step S630-11)
The main CPU 300a sets the data of the special electric accessory operating ram set table according to the type of the determined special symbol. The main CPU 300a is turned off when the variable time special stop flag is on.

(Step S630-13)
The main CPU 300a performs a process of setting the maximum number of operations of the special electric accessory. Specifically, referring to the data set in step S630-11, a predetermined number (counter value corresponding to the type of special symbol = number of rounds) is set as a counter value in the special electric accessory maximum operation count counter. .. It should be noted that this special electric accessory maximum operation number counter indicates the number of rounds that can be executed in the large role game to be started from now on. On the other hand, the main RAM 300c is provided with a counter for the number of continuous operations of the special electric accessory, and by adding "1" to the counter value of the counter for the number of continuous operations of the special electric accessory at the start of each round game, the current number of times of continuous operation of the special electric accessory is added. The number of round games is managed. Here, a process of resetting (updating to "0") the counter value of the special electric accessory continuous operation number counter is also executed with the start of the big role game.

(Step S630-15)
The main CPU 300a refers to the data set in step S630-11, and saves a predetermined opening time as a timer value in the special electric accessory game timer.

(Step S630-17)
The main CPU 300a sets an opening designation command for transmitting the start of the major game to the sub-control board 330 in the transmission buffer.

(Step S630-19)
The main CPU 300a updates the special electric accessory game management phase to "01H" when starting a large role game, and updates the special electric accessory game management phase to "05H" when starting a small hit game. ..

(Step S630-21)
The main CPU 300a updates the special game management phase to "00H".

(Step S630-23)
The main CPU 300a determines whether the special electric accessory game management phase updated in step S630-19 is "01H", that is, whether it is a big hit. As a result, when it is determined that the special electric accessory game management phase is "01H", the process is moved to step S630-25, and when it is determined that the special electric accessory game management phase is not "01H", the process is transferred to step S630-25. , Step S630-27.

(Step S630-25)
The main CPU 300a performs a jackpot signal output start process for outputting a jackpot signal from the game information output terminal plate 312, and ends the special symbol stop symbol display process. By this processing, a big hit signal is output with the start of the big role game (opening). Although a plurality of signals output from the game information output terminal board 312 are provided, only a predetermined jackpot signal will be described here.

(Step S630-27)
The main CPU 300a sets in the transmission buffer a command for confirming the game state when the special symbol is confirmed, which indicates the game state when the special symbol is confirmed.

(Step S630-29)
The main CPU 300a determines whether the time saving end flag is turned on. As described above, the time saving end flag is turned on in step S613-9 of FIG. 40 at the start of the fluctuation when the time saving gaming state is changed to the non-time saving gaming state. That is, when the time saving end flag is turned on here, the normal gaming state is changed from the time saving gaming state to the non-time saving gaming state due to the time saving omission at the start of the 50th or 100th fluctuation in the high probability precursor state. If it is done. That is, here, it is determined that the time reduction end flag is turned on only when the fluctuation at the time reduction is completed. If it is determined that the time reduction end flag is on, the process is transferred to step S630-31, and if it is determined that the time reduction end flag is not turned on, the process is transferred to step S630-35.

(Step S630-31)
The main CPU 300a performs a jackpot signal output stop process for stopping the jackpot signal output from the game information output terminal plate 312. That is, the jackpot signal is output during the big role game or the time-saving game state.

(Step S630-33)
The main CPU 300a turns off the time saving end flag.

(Step S630-35)
The main CPU 300a updates the special game management phase to "00H" and ends the special symbol stop symbol display process.

FIG. 44 is a flowchart illustrating a special electric accessory game management process (step S700) on the main control board 300 according to the simultaneous rotation reference example.

(Step S700-1)
The main CPU 300a loads the special electric accessory game management phase.

(Step S700-3)
The main CPU 300a determines whether the special electric accessory game management phase loaded in step S700-1 is "00H". That is, here, it is determined whether or not the player is currently in the big role game and the small hit game. If it is determined that the special electric accessory game management phase is "00H", the special electric accessory game management process is terminated, and if it is determined that the special electric accessory game management phase is not "00H", a step is taken. The process is transferred to S700-5.

(Step S700-5)
The main CPU 300a selects the special electric accessory game control module corresponding to the special electric accessory game management phase loaded in step S700-1.

(Step S700-7)
The main CPU 300a calls the special electric accessory game control module selected in step S700-5 to start the process.

(Step S700-9)
The main CPU 300a loads a special electric accessory game timer that manages the control time of the special electric accessory game, and ends the special electric accessory game management process.

FIG. 45 is a flowchart illustrating the pre-processing for opening the large winning opening in the main control board 300 according to the simultaneous rotation reference example. This large winning opening pre-opening process is executed when the special electric accessory game management phase is "01H" or "05H".

(Step S710-1)
The main CPU 300a determines whether the timer value of the special electric accessory game timer set in step S630-15 or the like is "0". As a result, when it is determined that the timer value of the special electric accessory game timer is not "0", the pre-processing for opening the large winning opening is terminated, and the timer value of the special electric accessory game timer is "0". If it is determined, the process is moved to step S710-3.

(Step S710-3)
The main CPU 300a updates the counter value of the special electric accessory continuous operation count counter to a value obtained by adding "1" to the current counter value.

(Step S710-5)
The main CPU 300a sets in the transmission buffer a command for designating the opening of the large winning opening to transmit the opening start of the large winning opening (start of the round game) to the sub-control board 330.

(Step S711)
The main CPU 300a executes a large winning opening opening / closing switching process. This large winning opening opening / closing switching process will be described later.

(Step S710-7)
The main CPU 300a updates the special electric accessory game management phase to a value obtained by adding 01H to the current value (“02H” or “06H”), and ends the pre-processing for opening the large winning opening.

FIG. 46 is a flowchart illustrating a large winning opening opening / closing switching process (S711) in the main control board 300 according to the simultaneous rotation reference example.

(Step S711-1)
The main CPU 300a determines whether the counter value of the special electric accessory opening / closing switching count counter is the upper limit value of the special electric accessory opening / closing switching count (the number of opening / closing of the large winning opening during one round game). As a result, when it is determined that the counter value is the upper limit value, the large winning opening opening / closing switching process is terminated, and when it is determined that the counter value is not the upper limit value, the process is moved to step S711-3.

(Step S711-3)
The main CPU 300a energizes the first special winning opening solenoid 126c and the second winning opening solenoid 128c based on the counter value of the special electric accessory opening / closing switching count counter with reference to the data of the special electric accessory operating ram set table. The solenoid control data for control and the timer data which is the energization time or the energization stop time are extracted.

(Step S711-5)
Based on the solenoid control data extracted in step S711-3, the main CPU 300a starts or stops energization of the first special winning opening solenoid 126c or the second special winning opening solenoid 128c. Executes the winning port solenoid energization control process. By executing the large winning opening solenoid energization control process, the energization start or energization stop of the first special winning opening solenoid 126c or the second special winning opening solenoid 128c is controlled in steps S400-33 and S400-35. It will be.

(Step S711-7)
The main CPU 300a saves the timer value based on the timer data extracted in step S711-3 in the special electric accessory game timer. It should be noted that the timer value saved in the special electric accessory game timer here is the maximum opening time of one large winning opening.

(Step S711-9)
The main CPU 300a is in the energization start state of the first special winning opening solenoid 126c or the second special winning opening solenoid 128c, that is, in step S711-5, the first special winning opening solenoid 126c or the second special winning opening solenoid 128c Determine if the control process to start energization has been performed. As a result, if it is determined that the energization start state is determined, the process is moved to step S711-11, and if it is determined that the energization start state is not present, the large winning opening opening / closing switching process is terminated.

(Step S711-11)
The main CPU 300a updates the counter value of the special electric accessory opening / closing switching count counter to a value obtained by adding "1" to the current counter value, and ends the large winning opening opening / closing switching process.

FIG. 47 is a flowchart illustrating a large winning opening opening control process in the main control board 300 according to the simultaneous rotation reference example. This large winning opening opening control process is executed when the special electric accessory game management phase is "02H" or "06H".

(Step S720-1)
The main CPU 300a determines whether the timer value of the special electric accessory game timer saved in step S711-7 is "0". As a result, if it is determined that the timer value of the special electric accessory game timer is not "0", the process is shifted to step S720-5, and it is determined that the timer value of the special electric accessory game timer is "0". If so, the process is moved to step S720-3.

(Step S720-3)
The main CPU 300a determines whether the counter value of the special electric accessory opening / closing switching number counter is the upper limit value of the special electric accessory opening / closing switching number. As a result, when it is determined that the counter value is the upper limit value, the process is transferred to step S720-7, and when it is determined that the counter value is not the upper limit value, the process is transferred to step S711.

(Step S711)
If it is determined in step S720-3 that the counter value of the special electric accessory opening / closing switching count is not the upper limit of the number of special electric accessory opening / closing switching, the main CPU 300a executes the process of step S711. do.

(Step S720-5)
In the main CPU 300a, the counter value of the large winning opening winning ball number counter updated in step S500-9 has not reached the specified number, that is, the number of large winning openings is the same as the maximum number of winning balls in one round. It is determined whether or not the game ball of is entered. As a result, if it is determined that the specified number has not been reached, the large winning opening opening control process is terminated, and if it is determined that the specified number has been reached, the process is moved to step S720-7.

(Step S720-7)
The main CPU 300a executes the large winning opening closing process necessary for stopping the energization of the first large winning opening solenoid 126c or the second special winning opening solenoid 128c to close the large winning opening. As a result, the big prize opening is closed.

(Step S720-9)
The main CPU 300a saves the winning opening closing effective time (interval time) in the special electric accessory game timer.

(Step S720-11)
The main CPU 300a updates the special electric accessory game management phase to a value (“03H” or “07H”) obtained by adding 01H to the current value.

(Step S720-13)
The main CPU 300a sets a command for designating the closing of the winning opening to indicate that the winning opening has been closed in the transmission buffer, and ends the large winning opening opening control process.

FIG. 48 is a flowchart illustrating a large winning opening closing effective process in the main control board 300 according to the simultaneous rotation reference example. This large winning opening closing effective process is executed when the special electric accessory game management phase is "03H" or "07H".

(Step S730-1)
The main CPU 300a determines whether the timer value of the special electric accessory game timer saved in step S720-9 is not "0". As a result, when it is determined that the timer value of the special electric accessory game timer is not "0", the large winning opening closing effective process is terminated, and the timer value of the special electric accessory game timer is "0". If it is determined, the process is moved to step S730-3.

(Step S730-3)
The main CPU 300a determines whether the counter value of the special electric accessory continuous operation count counter matches the counter value of the special electric accessory maximum operation count counter, that is, whether the round game of a preset number of times is completed. .. As a result, when it is determined that the counter value of the special electric accessory continuous operation count counter matches the counter value of the special electric accessory maximum operation count counter, the process is transferred to step S730-9, and when it is determined that they do not match. The process is transferred to step S730-5.

(Step S730-5)
The main CPU 300a updates the special electric accessory game management phase to "01H". When the special electric accessory game management phase is 07H, that is, during the control of the small hit game, the number of round games of the small hit game is "1", so that the answer is always YES in step S730-3. It is determined and the process does not shift to the step.

(Step S730-7)
The main CPU 300a saves a predetermined large winning opening closing time in the special game timer, and ends the large winning opening closing valid process. As a result, the next round game will be started.

(Step S730-9)
The main CPU 300a executes an ending time setting process for saving the ending time in the special electric accessory game timer.

(Step S730-11)
The main CPU 300a updates the special electric accessory game management phase to a value (“04H” or “08H”) obtained by adding 01H to the current value.

(Step S730-13)
The main CPU 300a sets an ending designation command indicating the start of the ending in the transmission buffer, and ends the large winning opening closing valid processing.

FIG. 49 is a flowchart illustrating a large winning opening end wait process in the main control board 300 according to the simultaneous rotation reference example. This large winning opening end wait process is executed when the special electric accessory game management phase is "04H" or "08H".

(Step S740-1)
The main CPU 300a determines whether the timer value of the special electric accessory game timer saved in step S730-9 is not "0". As a result, when it is determined that the timer value of the special electric accessory game timer is not "0", the large winning opening end wait process is terminated, and the timer value of the special electric accessory game timer is "0". If it is determined, the process is moved to step S740-3.

(Step S740-3)
The main CPU 300a determines whether the special electric accessory game management phase is "08H", that is, whether the small hit game is completed. As a result, when it is determined that the special electric accessory game management phase is "08H", the process is moved to step S740-11, and when it is determined that the special electric accessory game management phase is not "08H", the process is transferred to step S740-11. The process is transferred to step S740-5.

(Step S740-5)
The main CPU 300a executes a state setting process for setting a game state after the end of the major game. Here, the game state, the high probability number, and the time reduction number set in the spare area in step S610-17 are loaded, and each flag is set and the counter value is set as the game state after the big role game.

(Step S740-7)
In step S740-5, the main CPU 300a determines whether the normal gaming state is set to the non-time saving gaming state. As a result, if it is determined that the non-time saving game state is set, the process is transferred to step S740-9, and if it is determined that the non-time saving game state is not set, the process is transferred to step S740-21.

(Step S740-9)
The main CPU 300a performs a jackpot signal output stop process for stopping the jackpot signal output from the game information output terminal plate 312. That is, when the maximum advantage state is set after the big role game, the output of the big hit signal is stopped at the end of the big role game.

(Step S740-11)
The main CPU 300a determines whether the current gaming state is a high-probability precursor state (high-probability gaming state and time-saving gaming state). As a result, if it is determined that the state is a high probability precursor state, the process is transferred to step S740-13, and if it is determined that the state is not a high probability precursor state, the process is transferred to step S740-21.

(Step S740-13)
The main CPU 300a determines whether the stop-displayed small hit symbol is the special symbol Z1. As a result, if it is determined that it is the special symbol Z1, the process is transferred to step S740-15, and if it is determined that it is not the special symbol Z1, the process is transferred to step S740-21.

(Step S740-15)
The main CPU 300a sets the time saving state flag in order to change the normal gaming state to the non-time saving gaming state. As a result, when the special symbol Z1 is determined in the high probability precursor state, the game state is changed to the most dominant state at the end of the small hit game.

(Step S740-17)
The main CPU 300a performs a counter reset process for resetting the time reduction counter.

(Step S740-19)
The main CPU 300a performs a jackpot signal output stop process for stopping the jackpot signal output from the game information output terminal plate 312. That is, when the special symbol Z1 is won and the most dominant state is set after the small hit game, the output of the big hit signal is stopped at the end of the small hit game.

(Step S740-21)
The main CPU 300a sets in the transmission buffer a game state change designation command for transmitting a game state set after the end of the major game.

(Step S740-23)
The main CPU 300a sets the number-of-times commands corresponding to the high-accuracy number of times and the time-saving number of times in the transmission buffer.

(Step S740-25)
The main CPU 300a updates the special electric accessory game management phase to "00H" and ends the special winning opening end wait process. As a result, when the special 1 hold or the special 2 hold is stored, the variable display of the symbol is restarted.

FIG. 50 is a diagram illustrating a normal game management phase according to a reference example of simultaneous rotation. As described above, in the simultaneous rotation reference example, the process related to the normal game triggered by the passage of the game ball through the gate 124 or the entry of the game ball into the normal drawing operating port 125 is repeated stepwise and repeatedly. Although it is executed, the main control board 300 manages each process related to such a normal game by the normal game management phase.

As shown in FIG. 50, a plurality of normal game control modules for executing and controlling normal games are stored in the main ROM 300b, and a normal game management phase is associated with each of these normal game control modules. .. Specifically, when the normal game management phase is "00H", the module for executing the "normal symbol change waiting process" is called, and when the normal game management phase is "01H", the module is called. When the module for executing "normal symbol change processing" is called and the normal game management phase is "02H", the module for executing "normal symbol stop symbol display processing" is called and normal. When the game management phase is "03H", the module for executing "pre-processing for opening the winning opening of the normal electric accessory" is called, and when the normal game management phase is "04H", "normal". When the module for executing the "electric accessory winning opening opening control process" is called and the normal game management phase is "05H", the module for executing the "normal electric accessory winning opening closing effective processing" Is called, and when the normal game management phase is "06H", the module for executing the "normal electric accessory winning opening end wait process" is called.

FIG. 51 is a flowchart illustrating a normal game management process (step S800) on the main control board 300 according to the simultaneous rotation reference example.

(Step S800-1)
The main CPU 300a loads the normal game management phase.

(Step S800-3)
The main CPU 300a selects the normal game control module corresponding to the normal game management phase loaded in step S800-1.

(Step S800-5)
The main CPU 300a calls the normal game control module selected in step S800-3 to start the process.

(Step S800-7)
The main CPU 300a loads a normal game timer that manages the control time of the normal game.

FIG. 52 is a flowchart illustrating a normal symbol change waiting process in the main control board 300 according to the simultaneous rotation reference example. This normal symbol change waiting process is executed when the normal game management phase is "00H".

(Step S810-1)
The main CPU 300a loads the counter value of the normal symbol hold ball number counter, and determines whether the counter value is "0", that is, whether the normal symbol hold is "0". As a result, when it is determined that the counter value is "0", the normal symbol change waiting process is terminated, and when it is determined that the counter value is not "0", the process is moved to step S810-3.

(Step S810-3)
The main CPU 300a blocks-transfers the normal-figure hold (hit-determined random number) stored in the first to fourth storage units of the normal-figure hold storage area to a storage unit having a smaller ordinal number. Specifically, the normal figure hold stored in the second storage unit to the fourth storage unit is transferred to the first storage unit to the third storage unit. Further, the main RAM 300c is provided with a 0th storage unit to be processed, and the normal drawing hold stored in the 1st storage unit is transferred to the 0th storage unit. In this normal symbol storage area shift process, the counter value of the normal symbol hold ball counter is subtracted by "1", and a normal symbol hold reduction specification command indicating that the normal symbol hold is subtracted by "1" is transmitted. Set in the buffer.

(Step S810-5)
The main CPU 300a loads the hit determination random number transferred to the 0th storage unit, selects the hit determination random number determination table corresponding to the current gaming state, performs a general drawing lottery, and stores the lottery result. Execute the judgment process.

(Step S810-7)
The main CPU 300a saves the normal symbol stop symbol number corresponding to the result of the normal symbol lottery in step S810-5. In the simultaneous rotation reference example, the normal symbol display 168 is composed of one LED lamp, and the normal symbol display 168 is turned on in the case of a hit, and the normal symbol display 168 is turned off in the case of a loss. Let me. The normal symbol stop symbol number determined here indicates whether or not to finally turn on the normal symbol display 168. For example, if a winner is won, the normal symbol stop symbol number is "0". Is determined, and in the case of loss, "1" is determined as the normal symbol stop symbol number.

(Step S810-9)
The main CPU 300a confirms the current gaming state, selects and sets the corresponding normal symbol variation time data table.

(Step S810-11)
The main CPU 300a determines the normal symbol fluctuation time based on the hit determination random number transferred to the 0th storage unit in step S810-3 and the normal symbol fluctuation time data table set in step S810-9.

(Step S810-13)
The main CPU 300a saves the normal symbol fluctuation time determined in step S810-11 in the normal game timer.

(Step S810-15)
The main CPU 300a executes a process of setting a normal symbol display symbol counter in the normal symbol display 168 in order to start a variable display of the normal symbol. When, for example, "0" is set as the counter value in the normal symbol display symbol counter, the normal symbol display 168 is lit and controlled, and when "1" is set as the counter value, the normal symbol display is displayed. The device 168 is turned off. Here, a predetermined counter value is set in the normal symbol display symbol counter at the start of the fluctuation display of the normal symbol.

(Step S810-17)
The main CPU 300a sets in the transmission buffer a command for designating the hold of the normal figure, which indicates the number of hold of the normal figure stored in the hold storage area of the normal figure.

(Step S810-19)
The main CPU 300a transmits a normal symbol designation command based on the normal symbol stop symbol number determined in step S810-7, that is, the symbol type (win symbol or lost symbol) determined by the normal symbol hit determination process. Set to.

(Step S810-21)
The main CPU 300a updates the normal game management phase to "01H" and ends the normal symbol change waiting process.

FIG. 53 is a flowchart illustrating a process during normal symbol variation in the main control board 300 according to the simultaneous rotation reference example. This normal symbol change processing is executed when the normal game management phase is "01H".

(Step S820-1)
The main CPU 300a determines whether the timer value of the normal game timer saved in step S810-13 is "0". As a result, if the timer value is "0", the process is transferred to step S820-9, and if the timer value is not "0", the process is transferred to step S820-3.

(Step S820-3)
The main CPU 300a updates the normal symbol display timer that measures the lighting time and the extinguishing time of the normal symbol display 168. Specifically, when the timer value of the normal symbol display timer is "0", a predetermined timer value is set, and when the timer value is "1" or more, the current timer value is used. "1" Updates the timer value to the subtracted value.

(Step S820-5)
The main CPU 300a determines whether the timer value of the normal symbol display timer is "0". As a result, when it is determined that the timer value of the normal symbol display timer is "0", the process is shifted to step S820-7, and when it is determined that the timer value of the normal symbol display timer is not "0", the process is concerned. Ends processing during normal symbol change.

(Step S820-7)
The main CPU 300a updates the counter value of the normal symbol display symbol counter. Here, if the counter value of the normal symbol display symbol counter is a counter value indicating that the normal symbol display 168 is turned off, the counter value indicating lighting is updated, and the counter value indicating lighting of the normal symbol display 168 is updated. If is, the counter value indicating that the light is turned off is updated, and the processing during the change of the normal symbol is terminated. As a result, the normal symbol display 168 repeatedly turns on and off (blinks) at predetermined time intervals over the normal symbol fluctuation time.

(Step S820-9)
The main CPU 300a saves the normal symbol stop symbol number (counter value) determined in step S810-7 above in the normal symbol display symbol counter. As a result, the normal symbol display 168 is finally controlled to be turned on or off, and the result of the normal symbol lottery is notified.

(Step S820-11)
The main CPU 300a sets the normal symbol fluctuation stop time, which is the time for stopping and displaying the normal symbol, in the normal game timer.

(Step S820-13)
The main CPU 300a sets in the transmission buffer a command for specifying the stop of the normal symbol, which indicates that the stop display of the normal symbol has started.

(Step S820-15)
The main CPU 300a updates the normal game management phase to "02H" and ends the normal symbol changing process.

FIG. 54 is a flowchart illustrating a normal symbol stop symbol display process on the main control board 300 according to the simultaneous rotation reference example. This normal symbol stop symbol display process is executed when the normal game management phase is "02H".

(Step S830-1)
The main CPU 300a determines whether the timer value of the normal game timer set in step S820-11 is "0". As a result, when it is determined that the timer value of the normal game timer is not "0", the normal symbol stop symbol display process is terminated, and when it is determined that the timer value of the normal game timer is "0", the timer value is determined to be "0". The process is transferred to step S830-3.

(Step S830-3)
The main CPU 300a confirms the result of the drawing lottery.

(Step S830-5)
The main CPU 300a determines whether or not the result of the general drawing lottery is a hit. As a result, if it is determined that it is a hit, the process is transferred to step S830-9, and if it is determined that it is not a hit (it is a loss), the process is transferred to step S830-7.

(Step S830-7)
The main CPU 300a updates the normal game management phase to "00H" and ends the normal symbol stop symbol display process. As a result, when the normal game management process based on the normal figure hold of 1 is completed and the normal figure hold is stored, the process for starting the variable display of the normal symbol based on the next hold is performed. It becomes.

(Step S830-9)
The main CPU 300a refers to the data in the open / close control pattern table, and saves the time before the opening of the normal power as a timer value in the normal game timer.

(Step S830-11)
The main CPU 300a updates the normal game management phase to "03H" and ends the normal symbol stop symbol display process. As a result, the opening / closing control of the first variable starting port 120B is started.

FIG. 55 is a flowchart illustrating the pre-opening process of the winning opening of the ordinary electric accessory in the main control board 300 according to the simultaneous rotation reference example. This pre-processing for opening the winning opening of the ordinary electric accessory is executed when the ordinary game management phase is "03H".

(Step S840-1)
The main CPU 300a determines whether the timer value of the normal game timer set in step S830-9 is not "0". As a result, when it is determined that the timer value of the normal game timer is not "0", the pre-processing for opening the winning opening of the normal electric accessory is terminated, and it is determined that the timer value of the normal game timer is "0". In that case, the process is transferred to step S841.

(Step S841)
The main CPU 300a executes a normal electric accessory winning opening opening / closing switching process. This ordinary electric accessory winning opening opening / closing switching process will be described later.

(Step S840-3)
The main CPU 300a updates the normal game management phase to "04H" and ends the pre-opening process of the normal electric accessory winning opening.

FIG. 56 is a flowchart illustrating a process of switching the opening / closing of the winning opening of the ordinary electric accessory in the main control board 300 according to the simultaneous rotation reference example.

(Step S841-1)
In the main CPU 300a, the counter value of the normal electric accessory opening / closing switching count counter is the upper limit of the normal electric accessory opening / closing switching count (the number of times the movable piece 120b of the first variable starting port 120B is opened / closed during one opening / closing control). Determine if there is. As a result, when it is determined that the counter value is the upper limit value, the opening / closing switching process of the ordinary electric accessory winning opening is terminated, and when it is determined that the counter value is not the upper limit value, the process is performed in step S841-3. Transfer.

(Step S841-3)
The main CPU 300a refers to the data in the open / close control pattern table, and based on the counter value of the normal electric accessory opening / closing switching count counter, the solenoid control data (energization control data or energization control data) for energizing the ordinary electric accessory solenoid 120c. Stop control data) and timer data that is the energization time (solenoid energization time) or energization stop time (normal power closing effective time = pause time) of the ordinary electric accessory solenoid 120c are extracted.

(Step S841-5)
The main CPU 300a starts energizing the ordinary electric accessory solenoid 120c based on the solenoid control data extracted in step S841-3, or stops energization of the ordinary electric accessory solenoid 120c. The object solenoid energization control process is executed. By executing this ordinary electric accessory solenoid energization control process, the energization start or energization stop of the ordinary electric accessory solenoid 120c is controlled in steps S400-33 and S400-35.

(Step S841-7)
The main CPU 300a saves the timer value based on the timer data extracted in step S841-3 in the normal game timer. The timer value saved in the normal game timer here is the maximum opening time of the first variable start port 120B once.

(Step S841-9)
The main CPU 300a determines whether the energization start state of the ordinary electric accessory solenoid 120c is performed, that is, whether the control process for starting the energization of the ordinary electric accessory solenoid 120c is performed in step S841-5. As a result, if it is determined that the energization start state is determined, the process is shifted to step S841-11, and if it is determined that the energization start state is not present, the normal electric accessory winning opening opening / closing switching process is terminated.

(Step S841-11)
The main CPU 300a updates the counter value of the normal electric accessory opening / closing switching count counter to a value obtained by adding "1" to the current counter value.

FIG. 57 is a flowchart illustrating a normal electric accessory winning opening opening control process in the main control board 300 according to the simultaneous rotation reference example. This ordinary electric accessory winning opening opening control process is executed when the ordinary game management phase is "04H".

(Step S850-1)
The main CPU 300a determines whether the timer value of the normal game timer saved in step S841-7 is "0". As a result, if it is determined that the timer value of the normal game timer is not "0", the process is shifted to step S850-5, and if it is determined that the timer value of the normal game timer is "0", step S850 Move the process to -3.

(Step S850-3)
The main CPU 300a determines whether the counter value of the normal electric accessory opening / closing switching number counter is the upper limit value of the normal electric accessory opening / closing switching number. As a result, when it is determined that the counter value is the upper limit value, the process is transferred to step S850-7, and when it is determined that the counter value is not the upper limit value, the process is transferred to step S841.

(Step S841)
If it is determined in step S850-3 that the counter value of the normal electric accessory opening / closing switching count is not the upper limit of the normal electric accessory opening / closing switching count, the main CPU 300a executes the process of step S841. do.

(Step S850-5)
The main CPU 300a has not reached the specified number of counter values of the ordinary electric accessory winning ball number counter updated in step S530-9, that is, the first variable starting port 120B is being controlled to open and close once. It is determined whether or not the same number of game balls as the maximum number of winning balls can be entered. As a result, if it is determined that the specified number has not been reached, the normal electric accessory winning opening opening control process is terminated, and if it is determined that the specified number has been reached, the process is moved to step S850-7.

(Step S850-7)
The main CPU 300a executes the ordinary electric accessory closing process necessary for stopping the energization of the ordinary electric accessory solenoid 120c and closing the first variable starting port 120B. As a result, the first variable starting port 120B is closed.

(Step S850-9)
The main CPU 300a saves the normal power effective state time in the normal game timer.

(Step S850-11)
The main CPU 300a updates the normal game management phase to "05H" and ends the normal electric accessory winning opening opening control process.

FIG. 58 is a flowchart illustrating an ordinary electric accessory winning opening closing effective process in the main control board 300 according to the simultaneous rotation reference example. This normal electric accessory winning opening closing effective process is executed when the normal game management phase is "05H".

(Step S860-1)
The main CPU 300a determines whether the timer value of the normal game timer saved in step S850-9 is not "0". As a result, when it is determined that the timer value of the normal game timer is not "0", the normal electric accessory winning opening closing effective processing is terminated, and it is determined that the timer value of the normal game timer is "0". In the case, the process is moved to step S860-3.

(Step S860-3)
The main CPU 300a saves the normal game end wait time in the normal game timer.

(Step S860-5)
The main CPU 300a updates the normal game management phase to "06H" and ends the normal electric accessory winning opening closing effective process.

FIG. 59 is a flowchart illustrating a normal electric accessory winning opening end wait process in the main control board 300 according to the simultaneous rotation reference example. This ordinary electric accessory winning opening end wait process is executed when the ordinary game management phase is "06H".

(Step S870-1)
The main CPU 300a determines whether the timer value of the normal game timer saved in step S860-3 is not "0". As a result, when it is determined that the timer value of the normal game timer is not "0", the normal electric accessory winning opening end wait process is terminated, and it is determined that the timer value of the normal game timer is "0". In the case, the process is moved to step S870-3.

(Step S870-3)
The main CPU 300a updates the normal game management phase to "00H" and ends the normal electric accessory winning opening end wait process. As a result, when the normal symbol hold is stored, the variable display of the normal symbol is restarted. Next, as a production reference example, a specific production that can be executed by the above-mentioned type 1 gaming machine, type 2 gaming machine, and a simultaneous turning machine, and specific processing related to the production will be described.

<Reference example of production>
FIG. 60 is a diagram illustrating an example of a variation effect of a reachless variation pattern according to an effect reference example. As described above, when the big winning combination lottery is performed on the main control board 300, the variable effect of notifying the result of the big winning combination lottery is executed during the variable display of the special symbol, that is, over the variable time of the special symbol. In this variable effect, various background images are displayed on the main effect display unit 200a, and the effect symbols 210a, 210b, and 210c are displayed superimposed on the background image. During the variable effect, the sound is output from the sound output device 206 along with the image displayed on the main effect display unit 200a, the effect lighting device 204 is lit, and the effect accessory device 202 is used. Although it is movably controlled, detailed description thereof will be omitted here.

The variation effect according to the production reference example is roughly classified into a reach-less variation pattern and a reach variation pattern. In the variation effect of the non-reach variation pattern, a background image (not shown) is displayed on the main effect display unit 200a, and the effect symbols 210a, 210b, 210c are superimposed and displayed on the background image. For example, as shown in FIG. 60A, it is assumed that the effect symbols 210a, 210b, and 210c are stopped and displayed in a combination indicating that the result of the large winning combination lottery was lost. In this state, when a new variable display of the special symbol is performed, the three effect symbols 210a, 210b, and 210c are variablely displayed as shown in FIG. 60 (b) with the start of the variable display of the special symbol. Start (scroll display). The downward white arrows in the figure indicate that the effect symbols 210a, 210b, and 210c are scrolled in the height direction.

Then, as shown in FIG. 60 (c), the effect symbol 210a is first stopped and displayed, and then, as shown in FIG. 60 (d), the effect symbol 210c different from the effect symbol 210a is stopped and displayed. Then, as shown in FIG. 60 (e), at substantially the same timing as when the variable display of the special symbol is completed and the special symbol is stopped and displayed on the first special symbol display 160 or the second special symbol display 162. , The effect symbol 210b is stopped and displayed, and the player is notified of the big winning combination lottery result by the final stop display mode of the three effect symbols 210a, 210b, 210c at this time.

FIG. 61 is a diagram illustrating an example of a variation effect of the normal reach variation pattern according to the effect reference example. In the production reference example, the reach fluctuation pattern is roughly classified into a normal reach fluctuation pattern, a development reach fluctuation pattern, and a pseudo continuous reach fluctuation pattern. Similar to the variation effect of the non-reach variation pattern, the variation effect of the normal reach variation pattern starts the variation display of the effect symbols 210a, 210b, 210c with the start of the variation display of the special symbol. As shown, the effect symbol 210a is first stopped and displayed. After that, as shown in FIG. 61 (b), the same effect symbol 210c as the effect symbol 210a is stopped and displayed.

In this way, when the same effect symbols 210a and 210c are displayed in the reach mode in which the same effect symbols 210a and 210c are stopped and displayed on the main effect display unit 200a, as shown in FIG. 61 (c), the effect symbols are displayed on the main effect display unit 200a. "Reach" is displayed by superimposing on 210a and 210c. In addition, a plurality of types of reach modes are provided, and the same effect symbols 210a and 210c on which any number of "1" to "9" is written are stopped and displayed. After that, as shown in FIG. 61 (d), the shape of the effect symbols 210a and 210c is changed from the one before the reach mode, and the variable display is continued. Then, as shown in FIG. 61 (e), finally, the effect symbols 210b different from the effect symbols 210a and 210c are stopped and displayed, and the player is notified that the result of the big role lottery is lost.

FIG. 62 is a diagram illustrating an example of a variation effect of the development reach fluctuation pattern at the time of loss according to the production reference example, and FIG. 63 is an example of a variation effect of the development reach variation pattern at the time of a jackpot according to the production reference example. It is a figure explaining. As shown in FIGS. 62 (a) to 62 (d) and 63 (a) to (d), the variation effect of the development reach variation pattern is displayed on the main effect display unit 200a in the same manner as the variation effect of the normal reach variation pattern. The reach development effect is executed in which the effect symbols 210a and 210c are displayed in the reach mode, and then a predetermined development image (moving image) is reproduced and displayed. In this reach development effect, for example, as shown in FIGS. 62 (e) and 63 (e), the mission is displayed on the main effect display unit 200a, and FIGS. 62 (f), (g) and 63 (g) As shown in f) and (g), an image for accomplishing the mission is displayed.

Here, the development image for the reach development production is roughly divided into a loss pattern and a jackpot pattern, and in the development image of the loss pattern, as shown in FIG. 62 (h), the image showing the failure of the mission is finally obtained. After that, as shown in FIG. 62 (i), the effect symbols 210a, 210b, 210c are stopped and displayed in a combination for notifying the loss. On the other hand, in the developed image of the jackpot pattern, as shown in FIG. 63 (h), an image showing the success of the mission is finally displayed, and then, as shown in FIG. 63 (i), the effect symbols 210a, 210b, The 210c is stopped and displayed in a combination that notifies the jackpot.

As described above, the reach development effect includes, for example, a mission effect in which a development image of the content that challenges the mission is displayed, and a battle effect in which a development image in which a ally character and an enemy character compete against each other is displayed. Has been done. The mission production is provided with a plurality of execution patterns having different mission contents, and the battle production is provided with a plurality of execution patterns having different appearance characters and battle methods. In addition, as described above, the execution pattern of the mission production is roughly divided into a jackpot pattern that achieves the mission and a loss pattern that fails the mission. Similarly, in the execution pattern of the battle production, the ally character is the enemy character. It is roughly divided into a jackpot pattern that wins the game and a loss pattern that the ally character loses to the enemy character.

The jackpot pattern and the loss pattern are composed of the same contents until the end of the production, and differ in that the ally character wins or loses in the end, or whether or not the mission is completed. .. Therefore, during the reach development production, the player cannot identify the result of the big role lottery until the end of the fluctuation production, and the player is given a feeling of expectation of a big hit.

The jackpot pattern is selected only when the result of the big win lottery is a big hit, and the loss pattern is selected only when the result of the big win lottery is a loss. However, in one variable effect, the reach development effect may be executed twice. In this case, the first reach development effect is executed in a loss pattern, and the second reach development effect is a loss pattern. Or it is executed in the jackpot pattern. The flow of the effect when the reach development effect is executed twice in one variable effect will be described below.

FIG. 64 is a diagram illustrating an example of a variable effect when the reach development effect according to the effect reference example is executed twice. For example, it is assumed that after the effect symbols 210a and 210c are displayed in the reach mode, the mission effect is executed as shown in FIGS. 64 (a) and 64 (b). Up to this point, there is no difference from the case where the reach development effect is executed only once in one variable effect, but as shown in FIG. 64 (c) immediately after being notified that the mission could not be achieved. , "REACH UP" is displayed on the main effect display unit 200a.

After that, as shown in FIG. 64 (d), the development image for the battle effect is displayed on the main effect display unit 200a, and the second reach development effect is started. In the development image for this battle production, the ally character and the enemy character play against each other, and when the jackpot is won, as shown in FIG. 64 (e), the ally character finally wins the enemy character and at the same time. , As shown in FIG. 64 (f), the effect symbols 210a, 210b, 210c are stopped and displayed in a combination that notifies the jackpot. On the other hand, at the time of loss, as shown in FIG. 64 (g), the ally character is finally defeated by the enemy character, and as shown in FIG. 64 (h), the effect symbols 210a, 210b, 210c notify the loss. Stop display is displayed in combination.

FIG. 65 is a diagram illustrating an example of a variation effect of a pseudo continuous reach variation pattern according to an effect reference example. As shown in FIG. 65 (a), when the variation display of the effect symbols 210a, 210b, 210c is started, the variation effect of the pseudo continuous reach variation pattern is shown in the effect symbols 210a, as shown in FIG. 65 (b). The 210b and 210c are temporarily stopped and displayed in any of a plurality of types of pseudo modes provided in advance. In this pseudo mode, for example, the same effect symbols 210a and 210b and the effect symbols 210c on which a number "2" larger than these effect symbols 210a and 210b are temporarily stopped and displayed.

When the effect symbols 210a, 210b, 210c are temporarily stopped and displayed in a pseudo manner, the variable display of the effect symbols 210a, 210b, 210c is restarted as shown in FIG. 65 (c). That is, it can be said that the pseudo mode shows the re-variation display of the effect symbols 210a, 210b, 210c. After that, as shown in FIG. 65 (d), the effect symbols 210a, 210b, 210c are temporarily stopped and displayed again in a pseudo manner.

Then, as shown in FIG. 65 (e), when the variable display of the effect symbols 210a, 210b, 210c is resumed, the effect symbols 210a, 210c are displayed in the reach mode as shown in FIG. 65 (f). After that, as shown in FIGS. 65 (g) to 65 (i), the reach development effect is executed in the same manner as the development reach fluctuation pattern, and the result of the big role lottery is notified to the player.

As described above, in the variation effect of the pseudo continuous reach variation pattern, the content until the effect symbols 210a and 210c are in the reach mode is different from the variation effect of the development reach variation pattern, and after the effect pattern is in the reach mode, it is developed. The fluctuation effect will proceed in the same way as the reach fluctuation pattern.

In the pseudo continuous reach variation pattern, a plurality of variation display patterns of the effect symbols 210a, 210b, 210c until the reach mode is reached are provided, and the effect symbols 210a, 210b, 210c are temporarily stopped for each variation display pattern. The number of times of display, in other words, the number of times of variable display of the effect symbols 210a, 210b, 210c is different. This variation display pattern is determined by the variation mode command, and as the number of temporary stop displays (variation display) of the effect symbols 210a, 210b, 210c increases, there is a possibility that the winning of the jackpot will be finally notified (hereinafter, "reliability"). The selection ratio of the variable mode command at the time of winning a big hit and at the time of losing is set so that the degree) becomes high.

Specifically, when the result of the big role lottery is a big hit, the selection ratio of the variable mode command with a large number of variable impressions is set higher than the selection ratio of the variable mode command with a small number of variable impressions. If the result of the big win lottery is lost, the selection ratio of the variable mode command with a small number of variable display times is set higher than the selection ratio of the variable mode command with a large number of variable display times.

Further, in the main control board 300, the reliability of the pseudo continuous reach variation pattern is set to be higher than the reliability of the development reach variation pattern. Therefore, the reliability is suggested by the number of temporary stop displays (variable display) of the effect symbols 210a, 210b, 210c, and the player has more temporary stop displays (variable display) of the effect symbols 210a, 210b, 210c. While expecting that it will be done, we will watch over the whereabouts of the production.

The execution pattern of the above-mentioned variation effect is determined and executed and controlled on the sub-control board 330 based on the variation command determined on the main control board 300. That is, it can be said that the execution pattern of the variation effect is determined in cooperation with the main control board 300 and the sub control board 330.

FIG. 66 is a diagram for explaining the variation effect determination table according to the effect reference example, FIG. 66 (a) shows the first half variation effect determination table, and FIG. 66 (b) shows the second half variation effect determination table. As described above, when the major winning combination lottery is performed on the main control board 300, variable commands are determined based on the result of the major winning combination lottery, and each determined command is transmitted to the sub-control board 330. When the sub-control board 330 receives the variation mode command, it acquires an effect random number of 1 from the range of 0 to 249, and also refers to the first half variation effect determination table to obtain the acquired effect random number and the received variation mode command. Based on the above, the execution pattern of the variation effect in the first half is determined. Further, when the variation pattern command is received, 1 effect random number is acquired from the range of 0 to 249, and the latter half variation effect determination table is referred to, based on the acquired effect random number and the received variation pattern command. Determine the execution pattern of the fluctuation effect in the latter half. In FIG. 66, only a part of the first half variation effect determination table and the second half variation effect determination table is extracted and shown.

As shown in FIG. 66, according to the first half variation effect determination table, the selection ratio for the execution pattern of the first half variation effect is set for each variation mode number (variation mode command), and the latter half variation effect determination table is used. For example, for each variation pattern number (variation pattern command), a selection ratio for the execution pattern of the variation effect in the latter half is set. Then, by executing the determined execution patterns of the first half and the second half of the variation effect in combination, one variation effect is executed.

As the execution pattern of the first half of the variation pattern without reach, "None" indicating that the variation effect of the first half is not executed is determined, and as the execution pattern of the second half, "Normal loss 1" corresponding to the variation pattern without reach. , "Normal loss 2", "Special loss 1", "Special loss 2" is executed when it is determined. For example, upon receiving the variation mode command corresponding to the variation mode number of "01H" indicating that the variation effect of the first half is not executed, the sub-control board 330 always determines "none" as the execution pattern of the first half. Further, at this time, as the fluctuation pattern command that can be received at the same time, only one of "normal loss 1", "normal loss 2", "special loss 1", and "special loss 2" is determined in the latter half. The selection ratio is set in the variable effect determination table. Therefore, "None" is determined as the execution pattern in the first half, and "Normal loss 1", "Normal loss 2", "Special loss 1", and "Special loss 2" are determined as the execution patterns in the second half. The execution pattern of the effect is determined by the above-mentioned non-reach variation pattern.

On the other hand, as the variation effect of the reach variation pattern, other than "None" was determined as the execution pattern in the first half, and one of the reach development effects (indicated by developments 1 to 5 in the figure) was determined as the execution pattern in the second half. If executed. In other words, when the variation effect of the reach variation pattern is executed in the main effect display unit 200a, the variation mode command corresponding to the variation mode number other than the variation mode number = 01H is always received and developed. It means that the variation pattern command corresponding to the variation pattern number in which any of 1 to 5 is determined is received.

Here, in FIG. 66A, in the first half execution patterns such as "normal reach 1" and "normal reach 2", among the variation effects of the normal reach variation pattern, the effect symbols 210a, 210b, 210c are the reach modes, respectively. More specifically, the background image displayed on the main effect display unit 200a and the variable display patterns of the effect symbols 210a, 210b, 210c until the reach development effect is started are shown. These image patterns are pre-designed to match the time of the variation display of the special symbol associated with the variation mode number. For example, when "normal reach 1" is determined, FIGS. 61 (a) to 61 (a). The image shown in (d) is displayed on the main effect display unit 200a.

Further, in FIG. 66A, the “pseudo 2a” or the like in the execution pattern of the first half is displayed on the main effect display unit 200a until the reach development effect is started among the variation effects of the pseudo continuous reach variation pattern. The display pattern of the main variation effect image, that is, the execution pattern of the symbol display effect in which the effect symbols 210a, 210b, and 210c are variablely displayed is shown. For example, "pseudo 2a" is a pseudo continuous reach fluctuation pattern of "pseudo 2" in which the number of fluctuation display times of the effect symbols 210a, 210b, 210c is two, and the main variation effect image is the display pattern a. Shown. Further, the "pseudo 3b" is a pseudo continuous reach fluctuation pattern of the "pseudo 3" in which the number of fluctuation display times of the effect symbols 210a, 210b, 210c is three, and the main variation effect image is the display pattern b. Shown.

In the first half variation effect determination table and the second half variation effect determination table shown in FIG. 66, the variation effect of the non-reach variation pattern and the normal reach variation pattern is executed only when the result of the big role lottery is lost. , The selection ratio is set. In addition, the development reach fluctuation pattern and the pseudo continuous reach fluctuation pattern are determined at both the time of loss and the jackpot, but the development reach fluctuation pattern has a higher selection ratio at the time of loss than the pseudo continuous reach fluctuation pattern and is a jackpot. The time selection ratio is set low. In this way, by setting the selection ratio between the time of loss and the time of big hit, the pseudo continuous reach fluctuation pattern is set to have higher reliability than the development reach fluctuation pattern.

Furthermore, among the pseudo continuous reach fluctuation patterns, the higher the number of pseudos, the higher the selection ratio at the time of jackpot, and the lower the selection ratio at the time of loss, and the greater the number of pseudos, the higher the reliability. Has been made.

As described above, the rough flow of the variable effect is determined by the variable effect determination table, but at the start of the variable effect, various elemental effects that compose the variable effect are based on the variable mode command or the variable pattern command. Executability and execution pattern are further determined. Here, the element effect is, for example, as described above, a variable display of the effect symbols 210a, 210b, 210c on the main effect display unit 200a, or a development image displayed on the main effect display unit 200a in the reach development effect. Furthermore, it refers to all the effects that constitute the variable effect, such as the effect of moving the effect accessory device 202. In the embodiment, the advance notice effect (suggestion effect) is executed at various timings during the variation effect as the element effect that constitutes the variation effect.

This notice effect is the main effect display unit 200a at the start of the variation effect, at the time of re-variation display of the effect symbols 210a, 210b, 210c in the variation effect of the pseudo continuous reach variation pattern, and during the reach development effect. It is an effect of displaying a predetermined image on the screen or moving the effect accessory device 202 at a predetermined timing, and whether or not the effect can be executed and an execution pattern are determined for each advance notice effect. Each notice effect is provided with a plurality of types of execution patterns, and for each of the plurality of types of execution patterns, a selection ratio is set for each variation pattern command or variation mode command, in other words, for each jackpot winning or not. The expected value is set for each execution pattern according to the selection ratio.

As described above, when the sub-control board 330 receives the variation command, the execution pattern of the variation effect, whether or not each element effect can be executed, and the execution pattern are determined, and the variation effect is executed during the variation display of the special symbol. The Rukoto. As described above, the variation effect is performed once for each variation display of the special symbol, but in the embodiment, the effect straddling the variation display of the special symbol is also executed a plurality of times.

FIG. 67 is a diagram illustrating an example of a hold display effect according to an effect reference example. A hold display area 211 is provided below the main effect display unit 200a. Although not shown in FIGS. 60 to 65, the hold display area 211 is always displayed on the main effect display unit 200a even during the variation effect or the standby of the game. Then, during the variable effect, the hold display effect is performed in the hold display area 211. In the hold display effect, the hold display 212a indicating the hold read in the processing area (0th storage unit) at the time of the large winning combination lottery is stored in the 1st to 4th storage units of the 1st special figure hold storage area. The first hold display 212b, the second hold display 212c, the third hold display 212d, and the fourth hold display 212e, which indicate the hold being held, are displayed in the hold display area 211. In the following, the hold display 212a and the first hold display 212b to the fourth hold display 212e are collectively referred to as the hold display 212.

For example, when the special symbol is being displayed in a variable manner and the main RAM 300c stores four special 1 hold, as shown in FIG. 67 (a), the hold display 212a and the first hold display are displayed. A total of five hold displays 212, 212b to the fourth hold display 212e, are displayed in the hold display area 211. Then, from this state, the variable display of the special symbol is completed, the special 1 hold stored in the first storage unit is read out to the processing area (0th storage unit), a large winning combination lottery is performed, and the main RAM 300c is performed. When the hold shift process of is executed, as shown in FIG. 67 (b), the hold display 212a is erased, and the first hold display 212b to the fourth hold display 212e are moved and displayed one to the left. .. Further, when the next special 1 hold is read from this state, each hold display 212 is further moved and displayed as shown in FIG. 67 (c). As described above, the hold display effect is an effect of notifying the player of the special 1 hold number stored in the main RAM 300c.

Further, a plurality of display patterns of the hold display 212 are provided, and the display color is different for each display pattern. In the main control board 300, the acquisition-time effect determination process (step S536) is executed when the hold is stored, and the variation information determined when the newly stored hold is read out to the 0th storage unit. A look-ahead designation command indicating is transmitted to the sub-control board 330. When the sub-control board 330 receives the look-ahead designation command, the display pattern of the hold display 212 corresponding to the newly stored hold is determined based on the receive command. At this time, the selection ratio of each display pattern is set for each look-ahead designation command, that is, for each fluctuation information determined when the newly stored hold is read by the large winning combination lottery. That is, since the selection ratio of each display pattern is set according to whether or not the jackpot can be won and the execution pattern of the variable effect, the display pattern of the hold display 212 suggests the reliability (expected value) of the jackpot. It will be.

FIG. 68 (a) is a diagram for explaining the final hold display pattern determination table, and FIG. 68 (b) is a diagram for explaining the previous hold display pattern determination table. As described above, in the acquisition-time effect determination process on the main control board 300, the sub-control board 330 issues a look-ahead designation command indicating the fluctuation mode number and the fluctuation pattern number determined when the newly stored hold is read. Send to. That is, the look-ahead designation command is a command that transmits the variation mode number and the variation pattern number determined when the hold is read to the sub-control board 330. According to the final hold display pattern determination table, the selection ratio of the display pattern of the hold display 212 is set for each look-ahead designation command (variable pattern number), and when the look-ahead designation command is received, the final hold display 212 is set. The display pattern, that is, the final display pattern of the hold display 212a is determined.

According to the final hold display pattern determination table shown in FIG. 68 (a), "default (white)", "blinking", "blue", "yellow", "green", "black", "red", and "premier (premier) One of the eight types of display patterns of "rainbow)" is determined. Then, when the final display pattern of the hold display 212a is determined, the display pattern of the hold display 212 displayed before that is referred to the previous hold display pattern determination table shown in FIG. 68 (b). Will be decided. According to the previous hold display pattern determination table, the selection ratio of the display pattern of the hold display 212 to be displayed before the movement display is set for each display pattern of the hold display 212.

For example, in the main control board 300, when the hold is stored in the second storage unit of the first special figure hold storage area, the final display pattern of the hold display 212a is referred to by referring to the final hold display pattern determination table. Is decided. In this case, next, the display pattern of the first hold display 212b is determined with reference to the previous hold display pattern determination table. At this time, the display pattern of the first hold display 212b is determined based on the final display pattern of the hold display 212a determined earlier. For example, when the final display pattern of the hold display 212a is "blue", according to the previous hold display pattern determination table, "blinking" is 200/250 as the display pattern of the first hold display 212b. Is determined by the probability of, and "blue" is determined by the probability of 50/250.

When the display pattern of the first hold display 212b is determined in this way, the previous hold display pattern determination table is again set based on the previously determined display pattern of the first hold display 212b. With reference to this, the display pattern of the second hold display 212c is determined.

As described above, when the hold is stored, the final display pattern of the hold display 212a is first determined, and then the first hold is determined based on the determined final display pattern of the hold display 212a. The display patterns are sequentially determined so that the display order is traced back in the reverse direction, such as the display pattern of the display 212b being determined. According to the previous hold display pattern determination table, the selection ratio is set so that only the display pattern that is the same as the previously determined display pattern of the hold display 212 or has low reliability is determined. Has been done.

As described above, in the hold display effect, the hold display 212 is provided with a plurality of display patterns having different expected values for granting a predetermined game profit. Then, the hold display 212 may be displayed in the display pattern of 1 from the time when it is first displayed on the main effect display unit 200a until it is finally erased, or the display pattern changes during the display period. In some cases.

In the production reference example, the timing at which the display pattern of the hold display 212 changes is displayed by moving the newly stored special 1 hold (hereinafter, also referred to as the target hold) to the first hold display 212b to the third hold display 212d. It is roughly divided into the timing when the target is changed and the target change effect related to the target hold.

Next, the processing on the sub-control board 330 for executing the above-mentioned variation effect will be described. In the following, among the processes on the sub-control board 330, the processes that are not related to the fluctuation effect will not be described.

(Sub CPU initialization process of sub control board 330)
FIG. 69 is a flowchart illustrating a sub CPU initialization process (S1000) of the sub control board 330 according to the production reference example.

(Step S1000-1)
When the power is turned on, the sub CPU 330a reads the CPU initialization processing program from the sub ROM 330b, and also initializes and sets the flags stored in the sub RAM 330c.

(Step S1000-3)
Next, the sub CPU 330a performs a process of updating each effect random number, and thereafter repeats the process of step S1000-3 until the interrupt process is performed. It should be noted that a plurality of types of effect random numbers are provided, and here, each effect random number is updated asynchronously.

(Subtimer interrupt processing of subcontrol board 330)
FIG. 70 is a flowchart illustrating the sub-timer interrupt processing (S1100) of the sub-control board 330 according to the production reference example. The sub-control board 330 is provided with a reset clock pulse generation circuit (not shown) that generates a clock pulse at a predetermined cycle (30 times per second). Then, due to the generation of the clock pulse by the reset clock pulse generation circuit, the sub CPU 330a reads the timer interrupt processing program and starts the sub timer interrupt processing.

(Step S1100-1)
The sub CPU 330a saves the register.

(Step S1100-3)
The sub CPU 330a performs a process for permitting an interrupt.

(Step S1100-5)
The sub CPU 330a updates various timer counters used in the sub control board 330. Here, the various timer counters are subtracted by 1 each time the sub-timer interrupt processing of the sub-control board 330 is performed, and the subtraction is stopped when it reaches 0, unless otherwise specified.

(Step S1200)
The sub CPU 330a analyzes the command stored in the reception buffer of the sub RAM 330c and performs various processes according to the received command. In the sub-control board 330, when a command is transmitted from the main control board 300, command reception interrupt processing is performed, and the command transmitted from the main control board 300 is stored in the reception buffer. Here, the command stored in the receive buffer is analyzed by the command reception interrupt process.

(Step S1100-7)
The sub CPU 330a refers to the time table and performs a time schedule management process for executing the process corresponding to the corresponding time stored in the time table. Here, based on the time data set in the timetable, various flags are turned on and off, or commands are sent to each production device to perform variable production and major role production. It will control the execution of the production.

(Step S1100-9)
The sub CPU 330a returns the register and ends the sub timer interrupt process.

FIG. 71 is a flowchart illustrating a look-ahead designation command reception process according to an effect reference example executed when a look-ahead designation command is received among the above command analysis processes. As described above, the look-ahead designation command (look-ahead designation variation pattern command) is set in the main control board 300 in the acquisition-time effect determination process (step S536-21, step S536-25, step S536-27 in FIG. 33). After that, it is transmitted to the sub-control board 330 by the sub-command transmission process (step S100-65 in FIG. 23).

(Step S1210-1)
The sub CPU 330a first analyzes the received look-ahead designation command.

(Step S1210-3)
The sub CPU 330a stores the preliminary determination information based on the analysis result in step S1210-1. The sub RAM 330c of the sub control board 330 includes a first pre-determination information storage unit corresponding to the first special figure reservation storage area of the main control board 300 and a second pre-determination corresponding to the second special figure reservation storage area. An information storage unit is provided. The first predetermined information storage unit includes four storage units, a first storage unit to a fourth storage unit. The first storage unit to the fourth storage unit of the first pre-determination information storage unit correspond to the first storage unit to the fourth storage unit of the first special figure reservation storage area, respectively. Similarly, the second pre-determined information storage unit includes four storage units, a first storage unit to a fourth storage unit, and the first storage unit to the fourth storage unit of the second pre-determination information storage unit include the first storage unit to the fourth storage unit. The second special figure corresponds to the first storage unit to the fourth storage unit of the reserved storage area, respectively. Here, among the first to fourth storage units of the first special figure reserved storage area or the second special figure reserved storage area of the main control board 300, the storage unit corresponding to the storage unit in which the hold is newly stored. Pre-judgment information is stored in.

(Step S1210-5)
The sub CPU 330a performs a final hold display pattern determination process for determining the final display pattern of the hold display 212. Here, the final display pattern of the hold display 212a is determined and stored by referring to the final hold display pattern determination table (FIG. 68 (a)) based on the received look-ahead designation command.

(Step S1210-7)
The sub CPU 330a derives the number of times the display pattern of the hold display 212 is determined based on the storage unit in which the hold is stored, that is, the change timing of the hold display 212, and the number of times the hold display 212 is derived is the number of times the previous hold display pattern determination table is determined. (FIG. 68 (b)), the display pattern of the hold display 212 is determined. Then, the determined display pattern information of the hold display 212 is stored in a predetermined storage unit, and the process is transferred to step S1210-9.

(Step S1210-9)
Based on the determinations in steps S1210-5 and S1210-7, the sub CPU 330a performs a hold display start process for starting the display of the hold display 212, and ends the look-ahead designation command reception process. As a result, when the hold is stored, the display of the corresponding hold display 212 is started.

FIG. 72 is a flowchart illustrating a variable command reception process executed when a variable command is received among the above command analysis processes according to the production reference example. As described above, the variation command is set in the special symbol variation number determination process (steps S612-13 and S612-17 in FIG. 39) on the main control board 300, and then the subcommand transmission process (step S100- in FIG. 23). It is transmitted to the sub-control board 330 by 65).

(Step S1220-1)
Upon receiving the variation command, the sub CPU 330a first analyzes and stores the received variation pattern command.

(Step S1220-3)
The sub CPU 330a acquires the effect random numbers (0 to 249) updated in step S1000-3, and based on the acquired effect random numbers and the analysis result in step S1220-1, performs the execution pattern of the variation effect in the latter half. Decide and remember.

(Step S1220-5)
The sub CPU 330a analyzes and stores the received variable mode command.

(Step S1220-7)
The sub CPU 330a acquires the effect random numbers (0 to 249) updated in step S1000-3, and based on the acquired effect random numbers and the analysis result in step S1220-5, performs the execution pattern of the variation effect in the first half. Decide and remember.

(Step S1220-9)
The sub CPU 330a acquires the effect random numbers (0 to 249) updated in step S1000-3 for each advance notice effect, and is based on the acquired effect random numbers and the analysis results in steps S1220-1 and S1220-5. , Each notice effect determination table is referred to, and whether or not each advance notice effect is executed and the execution pattern are determined and stored.

(Step S1220-11)
The sub CPU 330a executes a shift process for shifting the pre-determination information stored in the pre-determination information storage unit. Here, when starting the variation effect based on the special 1 hold, the pre-determination information stored in the 4th storage unit to the 2nd storage unit of the 1st pre-determination information storage unit is stored in the 1st pre-determination information, respectively. When shifting to the third storage unit to the first storage unit of the storage unit and starting the variation effect based on the special 2 hold, the storage unit is stored in the fourth storage unit to the second storage unit of the second predetermination information storage unit. The pre-determined information is shifted to the third storage unit to the first storage unit of the second pre-determination information storage unit, respectively.

(Step S1220-13)
The sub CPU 330a performs a hold display shift process for moving and displaying the hold display 212. Further, here, when the display pattern of the hold display 212 changes, the execution data for changing the display pattern is set at a predetermined timing.

(Step S1220-15)
The sub CPU 330a sets the time data of the time table based on the determination of each of the above steps, and ends the variable command reception process. In addition, based on the timetable set here, in step S1100-7, the process of displaying the image for the variable effect on the main effect display unit 200a, the audio output process, the lighting control process of the effect lighting device 204, etc. The production execution control will be performed.

<Slot machine 400>
As shown in the external views of FIGS. 73 and 74, the slot machine 400 as a gaming machine has a housing 402 having an open front surface and a front surface rotatably arranged vertically on one end of the front surface of the housing 402. An upper door 404 and a front lower door 406 are provided. A colorless and transparent design display window 408 made of a glass plate, a transparent resin plate, or the like is provided in the lower center of the front upper door 404, and is located in the housing 402 at a position corresponding to the design display window 408. Three reels 410 (left reel 410a, middle reel 410b, right reel 410c) are provided independently and rotatably. As shown in the symbol arrangement of FIG. 75 (a), a plurality of types of symbols are arranged in each region equally divided into 20 on the outer peripheral surfaces of the left reel 410a, the middle reel 410b, and the right reel 410c. Through the symbol display window 408, the player can visually recognize three consecutive symbols of the left reel 410a, the middle reel 410b, and the right reel 410c, which are located in the upper, middle, and lower stages, for a total of nine symbols.

An operation unit installation table 412 is formed on the upper part of the front lower door 406, and the operation unit installation table 412 is provided with a medal insertion unit 414, a bet switch 416, a start switch 418, a stop switch 420, an effect switch 422, and the like. There is. The medal insertion unit 414 accepts the insertion of medals as a game value through the medal insertion slot 414a. The bet switch 416 inserts (bets) a specified number of medals required for one game among the medals electrically stored inside the slot machine 400 (hereinafter, simply referred to as credits).

The start switch 418 is composed of, for example, a lever capable of detecting a tilting operation, and detects a game start operation by a player. The stop switch 420 (stop switch 420a, stop switch 420b, stop switch 420c) is provided corresponding to each of the left reel 410a, the middle reel 410b, and the right reel 410c, and detects the player's stop operation. The first stop operation of any of the stop switch 420a, the stop switch 420b, and the stop switch 420c by the player while the stop switch 420 can be stopped is called the first stop, and the first stop is performed. After that, the stop operation of any of the two stop switches 420 that have not been stopped is called the second stop, and the stop operation of the last remaining stop switch 420 after the second stop is called the third stop. .. The effect switch 422 is composed of, for example, a pressing switch and a jog dial switch rotatably arranged around the pressing switch, and detects a player's pressing operation or rotation operation.

A liquid crystal display unit 424 for displaying various images accompanying the effect is provided at substantially the center of the upper part of the front upper door 404. Further, on the upper part and the left and right of the front upper door 404, for example, an effect lamp 426 composed of a high-intensity light emitting diode (LED) is provided. Further, at the left and right positions of the liquid crystal display unit 424 on the back surface of the front upper door 404 and at the left and right positions on the back surface of the front lower door 406, speakers 428 that produce an auditory effect by sound effects, musical sounds, or the like are provided.

The operation unit installation table 412 is provided with a main credit display unit 430 and a main payout display unit 432. Further, a sub-credit display unit 434 and a sub-payout display unit 436 are provided between the symbol display window 408 and the operation unit installation table 412. The number of medals credited (number of credits) is displayed on the main credit display unit 430 and the sub credit display unit 434, and the number of medals paid out is displayed on the main payout display unit 432 and the sub payout display unit 436. ..

Below the reel 410 in the housing 402, a medal payout device (medal hopper) 442 for paying out medals from the medal discharge port 440a is provided. Further, in the lower part of the front surface of the front lower door 406, a saucer portion 440 for storing medals paid out from the medal discharge port 440a is provided. Further, a power switch 444 is provided in the housing 402. The power switch 444 is operated by an administrator who manages the slot machine 400, and is used to switch between two states, a power off state and a power on state.

Further, in the housing 402, a setting key (not shown) and a setting change switch (collectively referred to as a setting value setting means) are provided on the main control board 500, which will be described later. In the slot machine 400, when a predetermined key (operation key) is inserted into the setting key and the power is turned on via the power switch 444 while being rotated from the OFF position to the ON position, the slot machine 400 shifts to the setting change mode. , The setting value can be changed (also simply called setting change). The set value indicates the degree of advantage of the player (machine discount) in stages. For example, the set value is expressed in 6 stages from 1 to 6, and in general, the larger the value of the set value, the higher the degree of advantage of the game as a whole. It is set to be high (the expected number of acquisitions is high). Then, each time the setting change switch is pressed in a state where the setting can be changed, the setting value is added by 1, for example, the setting value is changed to one of the 6-step setting values, and the start switch 418 is operated. Then, the set value is fixed, and by returning the setting key to the original position (OFF position), the setting change mode ends and the game becomes possible. The setting can be changed only for a certain period after the power switch 444 is operated and the power is turned on.

In the slot machine 400, the game can be started, and when a specified number of medals are bet, the effective line A is activated and the operation on the start switch 418 is effective. Here, as for the bet, the case where the credited medal is inserted through the operation of the bet switch 416 and the case where the medal is inserted through the medal insertion unit 414, and the replay combination described in detail later is displayed on the effective line A. Including the case where medals are automatically inserted based on the above. Further, the effective line A is a line for determining the winning combination of the winning combination, and is one in the present embodiment. As shown in FIG. 75 (b), the effective line A is the middle stage of the left reel 410a and the middle stage of the middle reel 410b among the nine symbols (3 reels x 3 stages of upper, middle and lower) facing the symbol display window 408. It is set to a line connecting the positions corresponding to the symbols that stop at the upper stage of the right reel 410c. The invalid line is used for the winning judgment of the winning combination, which displays another symbol combination that makes it easy to grasp the winning combination when it is difficult to grasp the winning combination only by the symbol combination displayed on the valid line A. It is a line other than the valid line A, and in this embodiment, five invalid lines B1, B2, B3, C1 and C2 shown in FIG. 75 (b) are assumed.

Then, when the start switch 418 is operated by the player, the game is started, the left reel 410a, the middle reel 410b, and the right reel 410c are rotated, and a winning type lottery or the like is executed. After that, the corresponding left reel 410a, middle reel 410b, and right reel 410c are stopped according to the operation of the stop switches 420a, 420b, and 420c, respectively. Then, depending on the combination of the lottery result of the winning type lottery and the symbol displayed on the valid line A, if the winning combination that can receive the medal payout wins, the medal payout is executed and the winning type that can receive the medal payout. If the player is unsuccessful, or if he / she wins but does not win, the game ends when the left reel 410a, the middle reel 410b, and the right reel 410c all stop.

In the present embodiment, in the above one game, a medal insertion through the medal insertion unit 414, a credited medal insertion through the operation of the bet switch 416, or a replay combination is displayed on the effective line A. After any of the automatic medals are inserted based on the above, the left reel 410a, the middle reel 410b, and the right reel 410c are rotationally controlled and the winning type lottery is executed according to the operation of the start switch 418 by the player. The left reel 410a, middle reel 410b, and right reel corresponding to the operated stop switches 420a, 420b, 420c according to the lottery result of the winning type lottery and the operation of the plurality of stop switches 420a, 420b, 420c by the player. When each of the 410c is stopped and controlled and the winning combination that can receive the medal payout wins, it means the game until the medal payout is executed. In addition, if the winning type that can receive the payout of medals is not won, or if the winning is not won, one game ends when the left reel 410a, the middle reel 410b, and the right reel 410c all stop. However, the start of one game may be read as the operation of the start switch 418 by the player instead of inserting the above-mentioned medal or winning the replay combination. Further, the number of times such one game is repeated is defined as the number of games.

FIG. 76 is a block diagram showing a schematic electrical configuration of the slot machine 400. As shown in FIG. 76, the slot machine 400 includes a main control board 500 (main control unit) that controls the progress of the game and a sub control board 502 (sub control unit) that controls the effect according to the progress of the game. A control board including the control board is provided. Further, the transmission of electrical signals between the main control board 500 and the sub control board 502 is limited to only one direction from the main control board 500 to the sub control board 502 from the viewpoint of fraud prevention and the like.

(Main control board 500)
The main control board 500 has a semiconductor integrated circuit including a main CPU 500a which is a central processing unit, a main ROM 500b in which programs and the like are stored, a main RAM 500c which functions as a work area, and the like, and controls the entire slot machine 400 in an integrated manner. .. Even when the power is turned off, the main RAM 500c is retained without being erased unless the settings are changed and the RAM is cleared.

Further, the main control board 500 functions by the main CPU 500a cooperating with the main RAM 500c based on the program stored in the main ROM 500b, the initialization means 600, the betting means 602, the winning type lottery means 604, and the reel control means. It has functional units such as 606, determination means 608, payout control means 610, game state control means 612, effect state control means 614, and command transmission means 616.

The main control board 500 receives various detection signals from the insertion medal detection unit 414b, the bet switch 416, the start switch 418, and the stop switches 420a, 420b, 420c for detecting the insertion of medals into the medal insertion port 414a. The main CPU 500a executes various processes based on the received detection signal.

The initialization means 600 executes the initialization process on the main control board 500. The betting means 602 bets medals for use in the game. Based on the operation of the start switch 418, the winning type lottery means 604 performs a winning type lottery for determining the winning or not of the winning combination, and more specifically, the winning or not of the winning type including the winning combination, as will be described later.

The reel control means 606 controls the rotation of the left reel 410a, the middle reel 410b, and the right reel 410c according to the operation of the start switch 418, and corresponds to the rotating left reel 410a, middle reel 410b, and right reel 410c, respectively. The corresponding left reel 410a, middle reel 410b, and right reel 410c are stopped and controlled according to the operation of the stop switches 420a, 420b, and 420c. Further, the reel control means 606 is operated by the player in order to display the lottery result of the winning type lottery after enabling the operation of the stop switches 420a, 420b, 420c in the previous game in response to the operation of the start switch 418. The time until the operation of the stop switches 420a, 420b, 420c is enabled (disabled by the completion of the operation of the stop switches 420a, 420b, 420c in the previous game) is extended from the specified time, and the reel 410a is in the meantime. , 410b, 410c may be rotated in various modes to perform a reel effect (freeze effect). In the reel effect, an arbitrary switch that should be originally enabled is not enabled for a predetermined time, a process that should be originally executed is held for a predetermined time, or a signal of an arbitrary switch that should be originally transmitted / received is transmitted or received for a predetermined time. It can be realized by not having it.

Further, a reel drive control unit 450 is connected to the main control board 500. The reel drive control unit 450 drives the stepping motor 452 based on the rotation start signals of the left reel 410a, the middle reel 410b, and the right reel 410c transmitted from the reel control means 606 in response to the operation signal of the start switch 418. do. Further, the reel drive control unit 450 detects the stop signals and the rotation position detection circuits 454 of the left reel 410a, the middle reel 410b, and the right reel 410c, which are transmitted from the reel control means 606 in response to the operation signal of the stop switch 420. The drive of the stepping motor 452 is stopped based on the signal.

The determination means 608 determines whether or not the symbol combination corresponding to the winning combination is displayed on the effective line A. Here, displaying the symbol combination corresponding to the winning combination on the valid line A may be simply referred to as winning. The payout control means 610 pays out medals by the number (value amount) corresponding to the winning combination based on the fact that the symbol combination corresponding to the winning combination is displayed on the valid line A (winning). Further, a medal payout device 442 is connected to the main control board 500, and the payout control means 610 discharges medals while counting the number of medals to be paid out.

The game state control means 612 refers to the result of the winning type lottery and the determination result of the determination means 608, and shifts the game state to any of a plurality of types of game states. Further, the effect state control means 614 refers to the result of the winning type lottery, the determination result of the determination unit 608, and the transition information of the game state, and shifts the effect state to any of a plurality of types of effect states.

The command transmitting means 616 is a command related to the game associated with the operation of the betting means 602, the winning type lottery means 604, the reel control means 606, the determination means 608, the payout control means 610, the game state control means 612, the effect state control means 614, and the like. Are sequentially determined, and the determined commands are sequentially transmitted to the sub-control board 502.

Further, the main control board 500 is provided with a random number generator (random number generation means) 500d. The random number generator 500d sequentially increments the count value, loops it within a predetermined numerical range, and extracts the count value at a predetermined time point to obtain a random number. The random numbers generated by the random number generator 500d of the main control board 500 (hereinafter referred to as the winning type lottery random numbers) are used for the game profit given to the player, for example, the winning type lottery means 604 for determining the winning type. ..

(Sub-control board 502)
Further, the sub-control board 502 has various semiconductor integrated circuits including a sub CPU 502a which is a central processing device, a sub ROM 502b in which programs and the like are stored, a sub RAM 502c which functions as a work area, and the like, like the main control board 500. , In particular, the effect is controlled based on the command from the main control board 500. Further, like the main RAM 500c, a backup power supply (not shown) is connected to the sub RAM 502c, and even when the power supply is turned off, the data is retained without being erased. Similar to the main control board 500, the sub control board 502 is also provided with a random number generator (random number generation means) 502d, and the random numbers generated by the random number generator 502d (hereinafter referred to as effect lottery random numbers) are mainly used. It is used to determine the mode of production.

Further, in the sub control board 502, the sub CPU 502a functions by cooperating with the sub RAM 502c based on the program stored in the sub ROM 502b, such as the initialization determination means 630, the command receiving means 632, and the effect control means 634. It has a functional part.

The initialization determining means 630 executes the initialization process on the sub-control board 502. The command receiving means 632 receives a command from another control board such as the main control board 500, and processes the command. The effect control means 634 receives the detection signal from the effect switch 422, and determines the effect of the game performed by each device of the liquid crystal display unit 424, the speaker 428, and the effect lamp 426 based on the received command. Specifically, the effect control means 634 is used to display image data on the liquid crystal display unit 424 and to produce an electric effect through an illumination device such as an effect lamp 426, a sub credit display unit 434, and a sub payout display unit 436. In addition to determining the decoration data, the audio data constituting the audio to be output from the speaker 428 is determined. Then, the effect control means 634 executes the effect of the determined game. The production also includes an auxiliary production. The auxiliary effect is the correct answer of the stop switches 420a, 420b, 420c, which is the winning condition for the correct answer when the correct answer (specific role) and the incorrect answer are duplicated in the winning type lottery. It is an effect of notifying the operation mode. With such an auxiliary effect, the player can easily display the symbol combination corresponding to the correct answer combination on the effective line A. The effect state in which such an auxiliary effect is executed is called an AT (assist time) effect state. In addition, a so-called ART game state in which the AT effect state and the RT (replay time) game state in which the winning probability of the replay combination is high is advanced in parallel may be used.

In the following, the notification managed by a board other than the main control board 500 including the sub control board 502 such as the liquid crystal display unit 424, the effect lamp 426, the speaker 428, the sub credit display unit 434, and the sub payout display unit 436. The means may be referred to as another notification means. On the other hand, the notification means managed by the main control board 500, such as the main credit display unit 430 and the main payout display unit 432, may be referred to as a main notification means (instruction monitor). In addition, the main notification means and other notification means capable of executing the auxiliary effect may be collectively referred to as the auxiliary effect execution means. The effect state control means 614 causes the auxiliary effect execution means to execute the auxiliary effect in the AT effect state.

(Table used in the main control board 500)
77 is an explanatory diagram for explaining the winning combination, and FIGS. 78 and 79 are explanatory diagrams for explaining the winning type lottery table.

In the slot machine 400, as will be described in detail later, a plurality of types of game states and effect states are provided, and the game state and effect state are shifted according to the progress of the game. Then, in the main control board 500, a plurality of winning type lottery tables and the like corresponding to the game states managed and controlled by the game state control means 612 are stored in the main ROM 500b. The winning type lottery means 604 sets the corresponding winning type lottery table in the main ROM 500b according to the current set value (indicating the easiness of obtaining the game profit stepwise) stored in the main RAM 500c and the current game state. Based on the winning type lottery table extracted from, it is determined which winning type in the winning type lottery table the winning type lottery random number acquired in response to the operation signal of the start switch 418 corresponds to.

Here, the winning combination that constitutes the winning type extracted in the winning type lottery table includes a replay combination, a small combination, and a bonus combination. The replay combination is a combination in which when the symbol combination corresponding to the replay combination is displayed on the effective line A, the game can be executed again without making a new bet of the medal by the player. The small winning combination is a combination in which a predetermined number of medals can be paid out according to the symbol combination by displaying the symbol combination corresponding to the small winning combination on the effective line A. Further, as for the bonus combination, the symbol combination corresponding to the bonus combination is displayed on the effective line A, so that the gaming state managed by the gaming state control means 612 is changed to the bonus gaming state (the gaming state during RBB operation, which will be described later). It is a role that can be transferred to.

As shown in FIG. 77, the winning combinations in the present embodiment are provided with winning combinations "Replay 1" to "Replay 7" as replay combinations. In addition, as small wins, winning wins "small win 1" to "small win 39" are provided. In addition, a winning combination "RBB" is provided as a bonus combination. In FIG. 77, one or a plurality of symbols constituting each winning combination are associated with each of the left reel 410a, the middle reel 410b, and the right reel 410c.

Here, in the present embodiment, when the stop switch 420 is operated by the player, if the symbols constituting the symbol combination corresponding to the winning combination that can be won are on the effective line A, the reel control means. By 606, stop control is performed so that the symbol stops on the effective line A. Further, when the stop switch 420 is operated, there are no symbols on the effective line A that constitute a symbol combination corresponding to the winning combination that can be won, but four symbols in the direction opposite to the rotation direction of the reel 410. When it exists within the range corresponding to the minute (pull-in range), the number of distant symbols becomes the number of sliding frames by the reel control means 606, and the symbols constituting the symbol combination corresponding to the winning combination are effective. The stop control is performed so as to stop after maintaining the rotation for the number of sliding frames so as to be pulled onto the line A. In addition, if there are a plurality of symbols in the reel 410 corresponding to the winning combination that can be won, and all of them are within the pull-in range of the reel 410, any of the symbols is valid line A according to a predetermined priority. It is determined whether to pull it upward, and stop control is performed so that the priority symbol is pulled onto the effective line A and the rotation is maintained for the number of sliding frames and then stopped. When the stop switch 420 is pressed, if there is a symbol on the effective line A that constitutes a symbol combination corresponding to the winning combination other than the winning combination, the symbol is controlled by the reel control means 606. The so-called kicking process is also executed in parallel so as not to stop the reel on the effective line A. Further, as will be described later, when an operation mode (operation order or operation timing) is set as a winning condition for the winning combination included in the winning type, the reel control means 606 will perform the winning combination according to the operation mode of the player. The symbol combination corresponding to is stopped and controlled so that it can be displayed on the effective line A.

Then, for example, the symbols constituting the symbol combinations corresponding to the winning combinations "Replay 1" to "Replay 4", the winning combinations "Small role 1" to "Small role 6", and "Small role 35" to "Small role 39". Are arranged in each reel 410 so that they can always be displayed on the effective line A by the above-mentioned stop control. Such a winning combination may be expressed as PB = 1. On the other hand, for example, the symbols constituting the symbol combinations corresponding to the winning combinations "Replay 5" to "Replay 7", the winning combinations "small combination 7" to "small combination 34", and the winning combination "RBB" are in each reel 410. Because the stop control is not necessarily arranged so that it can be displayed on the effective line A, so-called omission may occur. Such a winning combination may be expressed as PB ≠ 1.

As shown in FIGS. 78 and 79, in the winning type lottery table, a plurality of winning areas are divided, and the winning type to be the target of the lottery differs depending on each game state, and the presence or absence of unwinning (loss) differs. Or something. In FIGS. 78 and 79, the winning area assigned to each gaming state (non-internal gaming state (non-internal), RBB internal medium gaming state (RBB internal), RBB operating gaming state (RBB operating)). The winning type) is represented by "◎" or "○", but in reality, the winning type lottery table corresponding to each of the plurality of gaming states is stored in the main ROM 500b. In addition, "◎" indicates that the lottery for the advantageous section can be performed, and "○" indicates that the lottery for the advantageous section cannot be performed. It indicates that it is a winning type.

In the winning type lottery table, each of the compartmentalized winning areas is associated with a predetermined number (winning range value), which is a numerical value indicating the winning range, and the winning type, and all assigned to each gaming state. The total number of winning areas is the total number of winning type lottery random numbers (65536). Therefore, the probability that each winning type is determined is a value obtained by dividing the number of places associated with the winning area by the total number of winning type lottery random numbers. Based on the game state at that time, the winning type lottery means 604 sequentially acquires the number of the winning areas from the plurality of winning areas in the winning type lottery table, and determines the number of the winning number by the winning type lottery random number. When the value after subtraction becomes less than 0 by subtracting from, the winning type associated with the winning area at that time is used as the lottery result of the winning type lottery. In addition, if the number of winning areas in the winning area 1 or higher is subtracted from the winning type lottery random numbers and the value after subtraction is 0 or more, the winning type "loss" in the winning area 0 is the winning type lottery. Will be the result of the lottery.

Here, the winning combination "RBB" constituting the winning type "RBB" will be supplemented. The predetermined first-class special accessory RB is an accessory that increases the number of combinations of symbols related to winning for each specified number, or increases the probability that the condition device for winning for each specified number operates, and is predetermined. It operates when it is played, and can continue to operate until the result of the game is obtained no more than 12 times. Here, the condition device is a device whose operation is a necessary condition for displaying a winning combination, a replay, a combination of symbols related to the operation of the accessory or the accessory continuous operation device, and is a winning type lottery (winning type lottery). It means the one that operates when the lottery by the computer performed in the game machine) is won, that is, the winning flag. The accessory continuous operation device (winning combination "RBB") related to the first-class special accessory that constitutes the winning type "RBB" is a device that can continuously operate the first-class special accessory RB. Yes, it operates when a specific combination of symbols is displayed, and ends the operation when a predetermined combination is displayed.

According to the winning type lottery table of FIG. 78, for example, the winning type "loss" is associated with the winning area 0, and when the winning type is won, the symbol corresponding to any of the winning combinations shown in FIG. 77 is obtained. The combination is not displayed on the valid line A, and the medal is not paid out. However, as will be described later, when the RBB internal winning flag is carried over to the next game, the symbol combination corresponding to the winning combination "RBB" may be displayed on the effective line A by winning the winning type "Loss". It will be possible.

Further, the winning area 1 is associated with the winning type "small combination ALL" in which the winning combinations "small combination 1" to "small combination 39" are duplicated, and the winning combination "small combination ALL" is associated with the winning area 2. The winning type "1 piece ALLA" in which "small winning combination 11" to "small winning combination 39" are duplicated is associated, and the winning combination "small winning combination 12" to "small winning combination 27" is associated with the winning area 3. The winning type "1 sheet ALLB" that is included in duplicate is associated. Further, the winning area 4 is associated with the winning type "choice 1 sheet 1" in which the winning combination "small combination 12" and the "small combination 20" are duplicated, and the winning combination "small" is associated with the winning area 5. The winning type "choice 1 sheet 2" in which the winning combination "13" and "small winning combination 21" are duplicated is associated, and the winning winning combination "small winning combination 14" and "small winning combination 22" are duplicated in the winning area 6. The winning type "choice 1 piece 3" is associated with the winning type "choice 1 piece 3", and the winning type "choice 1 piece 4" in which the winning combination "small winning combination 15" and "small winning combination 23" are duplicated is included in the winning area 7. It is associated. Further, the winning area 8 is associated with the winning type "weak cherry" in which the winning combination "small combination 35" and the "small combination 36" are duplicated, and the winning area 9 is associated with the winning combination "small combination 37". The winning type "strong cherry" in which "small winning combination 39" is duplicated is associated, and the winning winning combination "small winning combination 7", "small winning combination 8", and "small winning combination 11" are associated with each other. The winning type "watermelon A" that is duplicated is associated, and the winning area 11 is associated with the winning type "watermelon B" that includes the winning combinations "small winning combination 7" to "small winning combination 10". The winning area 12 is associated with a winning type "strong bell" in which the winning combination "small combination 1", "small combination 3", and "small combination 5" are duplicated. Further, the winning area 13 is associated with the winning type "common bell A" in which the winning combinations "small combination 1" to "small combination 6" are duplicated, and the winning combination "small combination" is associated with the winning area 14. The winning type "common bell B" in which "1" to "small winning combination 6" and "small winning combination 11" are duplicated is associated.

In the winning areas 15 to 26, there are 11 correct batting orders (winning batting orders "small winning combination 1" to "small winning combination 6") and incorrect batting orders with one payout number (winning winning combination "small winning combination"). The selected winning types (winning types "batting order bell 1A" to "batting order bell 6A", "batting order bell 1B" to "batting order bell 6B") in which the winning combination 12 "to" small winning combination 34 ") are duplicated are associated with each other. Has been done.

Further, according to the winning type lottery table of FIG. 79, the winning types "symbol replay A1" to "symbol replay A7" in which the winning combinations "replay 1" to "replay 7" are duplicated are included in the winning areas 27 to 39. , "Symbol Replay B1" to "Symbol Replay B6" are associated with each other. Further, the winning area 40 is associated with a winning type "normal replay" in which the winning combinations "replay 1" and "replay 2" are duplicated.

Further, the winning areas 41 to 46 are associated with winning types "RBB1" to "RBB6" in which the winning combination "RBB" is included alone or in combination with other small combinations.

Then, when a winning combination including a plurality of winning combinations is won in duplicate, a winning condition regarding which of the winning combinations the symbol combination corresponding to the winning combination is preferentially displayed on the effective line A, for example, a stop The order in which the switches 420a, 420b, and 420c are operated is set.

In the following description, the operation of the stop switches 420a, 420b, 420c for stopping the reels in the order of the left reel 410a, the middle reel 410b, and the right reel 410c is defined as "stroke order 1", and the left reel 410a, the right reel 410c, and the middle reel 410b The operation of the stop switches 420a, 420b, 420c that stop the reels in order is set to "striking order 2", and the operation of the stop switches 420a, 420b, 420c that stop the reels in the order of the middle reel 410b, the left reel 410a, and the right reel 410c is "striking order". 3 ”, the operation of the stop switches 420a, 420b, 420c that stop the reels in the order of the middle reel 410b, the right reel 410c, and the left reel 410a is set to“ striking order 4 ”, and the right reel 410c, the left reel 410a, and the middle reel 410b are in that order. The operation of the stop switches 420a, 420b, 420c for stopping the reels is set to "striking order 5", and the operation of the stop switches 420a, 420b, 420c for stopping the reels in the order of the right reel 410c, the middle reel 410b, and the left reel 410a is "striking order 6". ".

For example, in the non-internal gaming state, when the winning type "batting order bell 1A" in the winning area 15 is won and the operation is performed according to the correct answer operation mode (batting order 1), the winning combination with 11 payouts is the correct answering combination. Stop control is performed so that the symbol combination corresponding to "small winning combination 1" is preferentially displayed on the effective line A. In addition, when the operation is performed in batting order 2, the stop control is performed so that the symbol combination corresponding to the winning combination "small combination 28", which is an incorrect answer of one payout number, is preferentially displayed on the effective line A. When the operation is performed in the batting order 3 or 4, the symbol combination corresponding to the winning combination "small combination 12", which is an incorrect answer of one payout number, is preferentially 1/4 on the effective line A. When stop control is performed so that it is displayed with a probability and operations are performed in batting orders 5 and 6, the symbol combination corresponding to the winning combination "small combination 16", which is an incorrect answering of one payout number, is effective line A. Stop control is performed so that it is preferentially displayed on the top with a probability of 1/4.

The winning probabilities (numbers) of each winning type in the winning areas 15 to 26 are set to be equal. Since the player cannot usually know which winning type is won, it is difficult to win the correct answer by providing the winning areas 15 to 26 as described above. Further, as described above, even if the stop switches 420a, 420b, and 420c are operated in the batting order in which the incorrect answer is preferentially displayed, the symbol combination corresponding to the incorrect answer is not necessarily displayed on the effective line A. Therefore, depending on the operation mode, omission may occur (PB ≠ 1).

When any of the above-mentioned winning types is won, the internal winning flag corresponding to each winning type is established (ON), and the stop control of each reel 410 is performed according to the establishment status of the internal winning flag. The Rukoto. At this time, if the winning type including the small winning combination is won, but the symbol combination corresponding to these winning combination cannot be displayed on the valid line A in the game, after the game is completed. The internal winning flag is turned off. That is, the right to win a small winning combination is limited to the game in which the small winning combination is included in the winning type, and the right cannot be carried over to the next game. On the other hand, when the winning type including the winning combination "RBB" is won, the RBB internal winning flag is established (ON), and the symbol combination corresponding to the winning combination "RBB" is on the valid line A. The RBB internal winning flag is carried over across the game until it is displayed. If the internal winning flag corresponding to the winning type including the replay combination is established, the symbol combination corresponding to any of the replay combinations included in the winning type is always on the valid line A. It is displayed, and after the processing necessary for performing the next game without requiring a medal is performed, the internal winning flag is turned off.

(Transition of game state)
Here, the transition of the gaming state will be described with reference to FIG. 80. Here, a plurality of gaming states such as a non-internal gaming state, an RBB internal medium gaming state, and an RBB operating gaming state are prepared. As will be described later, each game state is changed according to the winning of the bonus combination, the winning (operation), and the end.

The non-internal gaming state is a gaming state corresponding to the initial state in a plurality of gaming states. In such a non-internal gaming state, the winning probability of the replay combination is set to about 1 / 7.3. Further, in the non-internal gaming state, the winning combination "RBB" is determined with a predetermined probability (for example, about 1/30).

The game state control means 612 shifts the game state according to the winning of the winning combination “RBB”. For example, in the game in which the winning combination "RBB" is won, when the symbol combination corresponding to the winning combination "RBB" is displayed on the effective line A, the game state control means 612 changes the game state to the game state during RBB operation. Make the transition (1).

In the gaming state during RBB operation, the winning probability of the replay combination is set to 0. In the gaming state during the RBB operation, the winning type "small role ALL" is in the winning area 1, and the winning types "1 piece ALLA" and "1 piece ALLB" are in the winning areas 2 and 3. It is set. If you win the winning type "Small role ALL", the symbol combination corresponding to any of the winning combination "Small role 1" to "Small role 39" is displayed on the valid line A, and you win the winning type "1 piece ALL". Then, the stop control is performed so that the symbol combination corresponding to any of the winning combinations "small combination 11" to "small combination 39" is displayed on the effective line A. Here, the expected number of cards to be acquired per unit game in the game state during RBB operation is lowered due to the configuration of such a small winning combination.

When the end condition of the gaming state during RBB operation is satisfied, that is, when the acquired number reaches a predetermined number, the gaming state control means 612 shifts the gaming state to the non-internal gaming state (2).

On the other hand, in the game in which the winning combination "RBB" is won, if the symbol combination corresponding to the winning combination "RBB" cannot be displayed on the effective line A, the game state control means 612 displays the game state inside the RBB. Shift to the medium gaming state (special gaming state) (3).

In the RBB internal medium game state, the winning probability of the replay combination is set to about 1 / 5.9. In addition, in the game state inside the RBB, the winning type "Loss" will not be won. In other words, if the symbol combination corresponding to the winning combination "RBB" cannot be displayed on the valid line A in the winning game of the winning combination "RBB", after that, a smaller role or a smaller role than the winning combination "RBB" Since the replay combination is preferentially stopped and controlled on the effective line A, the symbol combination corresponding to the winning combination "RBB" cannot be displayed on the effective line A. Therefore, once the gaming state shifts to the RBB internal medium gaming state, the RBB internal medium gaming state is maintained without the subsequent transition of the gaming state. Here, while maintaining the RBB internal medium gaming state, the AT effect state is realized in the RBB internal medium gaming state.

Here, in the RBB internal medium game state, since a plurality of types of correct answer combinations are won without overlapping each other, it is possible to increase the chances that the correct answer combination can be won, and as a result, for example, the RBB internal medium game. AT effect in the state By performing the auxiliary effect in the state, it is possible to easily obtain a medal. On the other hand, in the game state during RBB operation, since multiple types of correct answer combinations are won in duplicate, there are few chances that the correct answer combination can be won, so the correct answer combination is won more than the AT production state in other game states. The chances of being able to do it are reduced, making it difficult for players to increase the number of medals they own. Therefore, while having the function of the RBB operating game state in which the winning probability of the winning combination is higher than the RBB internal medium game state, the RBB internal game state is changed to the RBB internal medium game state in terms of medal acquisition performance. It is possible to realize a specification that is inferior (accelerator RBB).

(Transition of production state)
FIG. 81 is an explanatory diagram for explaining the transition of the effect state. Hereinafter, the effect state (non-AT effect state, AT effect state) transitioned by the effect state control means 614 on the main control board 500 will be described in detail. In the following, a case where the gaming state is the RBB internal middle gaming state will be described.

Here, in order to comprehensively and uniformly determine whether or not the game state in which the medal acquisition performance is high is biased, a game section having performance related to the instruction function, that is, an auxiliary effect (instruction function) is executed. A game section that is advantageous to the player, including a game section, is defined as an advantageous section (specific section). In the advantageous section, for example, when the auxiliary effect is activated as a result of drawing a lottery related to the operation of the auxiliary effect on the main control board 500, the main control board 500 can identify the content of the instruction. It is a game section in which instruction information may be transmitted to a peripheral board such as a sub-control board 502 only when it is displayed on the means. In addition, a game section different from the advantageous section is defined as a non-advantageous section. Therefore, the plurality of effect states (non-AT effect state, AT effect state) belong to either the advantageous section or the non-advantageous section which is the game section. In the present embodiment, almost all the effect states belong to the advantageous section, and the non-advantageous section is realized in a part of the non-AT effect state (here, the non-advantageous effect state).

In addition, in the winning mode in which the correct answer role is missed if there is no auxiliary effect in the advantageous section, the assistance to assist the winning of the correct answer role in the selected winning type in which the payout of the correct answer role is the maximum (here, 11 cards). When performing an effect (an auxiliary effect that can obtain the maximum number of payouts), for example, the section indicator 160 must be turned on to notify the effect.

Further, in the non-advantageous section, it is possible to make the winning probability of the winning type different for each set value, but the probability of determining the transition to the effect state (AT effect state) accompanied by the auxiliary effect in the same winning type. Must not be different for each set value. On the other hand, in the advantageous section, if both the winning probability of the winning type and the probability of determining the transition (or addition) to the effect state (AT effect state) accompanied by the auxiliary effect in the same winning type are different for each set value. It is possible to make it.

Therefore, the effect state control means 614 manages the transition between the non-advantageous section and the advantageous section in addition to the management of the transition of the effect state. In addition, the advantageous section is forcibly terminated by satisfying the following termination conditions regardless of such management. For example, based on the fact that the value counted in the advantageous section reaches a predetermined value (for example, the number of staying games (number of game executions) reaches 1500 games, or the number of acquired games (net increase number) exceeds 2400). And forcibly terminate. In any case, the effect state control means 614 resets all the information updated in the advantageous section (all variables affecting the performance related to the instruction function) by shifting from the advantageous section to the non-advantageous section. ..

(Non-AT production state, AT production state)
In the non-AT effect state, the execution frequency of the auxiliary effect is extremely low and the auxiliary effect is hardly performed as compared with the AT effect state, so that the number of medals that can be obtained is limited. Here, as the non-AT effect state, six effect states such as a normal effect state, a non-advantageous effect state, a preparatory effect state, a first interval effect state, a continuous lottery effect state, and a second interval effect state are provided.

In the AT effect state, it is possible to obtain a large number of medals while suppressing the consumption of medals by causing the auxiliary effect execution means to execute the auxiliary effect at the time of winning all the selected winning types. Therefore, the player can advance the game advantageously by shifting to the AT effect state as compared with the non-AT effect state. Here, a pseudo bonus effect state is provided as the AT effect state. Hereinafter, each effect state (normal effect state, pseudo bonus effect state, non-advantageous effect state, preparatory effect state, first interval effect state, continuous lottery effect state, second interval effect state) will be described individually.

(Each production state)
The normal effect state is an effect state corresponding to the initial state among the plurality of effect states. The effect state control means 614 performs an AT lottery in a normal effect state. The AT lottery is a lottery that determines the transition to the AT effect state, and the effect state control means 614 performs the AT lottery with a different probability for each winning type determined by the winning type lottery. Then, when the AT lottery is won, the effect state control means 614 shifts the effect state to the pseudo bonus effect state, which is the AT effect state, after the predetermined number of precursor games has elapsed (1). Further, when a predetermined ceiling condition (for example, the normal effect state is continuously consumed by a predetermined number of games) is satisfied in the normal effect state without shifting to the pseudo bonus effect state (so-called ceiling arrival), the effect state control means 614 Shifts the production state to the pseudo-bonus production state (1).

In the pseudo-bonus effect state, the auxiliary effect is executed until a predetermined end condition (for example, the number of digested games reaches the predetermined number of games) is satisfied, and the player obtains, for example, expectation in the pseudo-bonus effect state. The number of sheets can be 3.5. In the pseudo-bonus effect state, mainly two end conditions are prepared. For example, when the end condition is that the number of digested games reaches a predetermined number of games, the predetermined number of games is provided in two stages of 30 and 80, and one of them is determined by lottery. In the pseudo-bonus effect state, of course, the larger the number of games digested, the more game profits the player will get. Therefore, the player wants the predetermined number of games to be 80 instead of 30. However, even if 30 is determined as the predetermined number of games, a promotion lottery for increasing the predetermined number of auxiliary effects from 30 to 80 is also performed during the digestion. Here, as an end condition of the pseudo-bonus effect state, it is illustrated that the number of digested games has reached the predetermined number of games, but instead, the number of auxiliary effects that can obtain the maximum number of payouts is predetermined. It may be adopted that the number is reached or the number of acquired sheets (net increase number) reaches a predetermined number.

Then, when a predetermined end condition is satisfied in the pseudo bonus effect state, the effect state control means 614 may shift the effect state to the non-advantageous effect state (2). At this time, the effect state control means 614 temporarily shifts the advantageous section to the non-advantageous section, and resets all the information updated in the advantageous section. For example, if the pseudo-bonus effect state in the previous stage is the first pseudo-bonus effect state, that is, if the pseudo-bonus effect state immediately after the transition from the normal effect state, the effect state control means 614 has a disadvantageous effect on the effect state. At the same time as shifting to the production state, the advantageous section is temporarily shifted to the non-advantageous section. Further, even when the pseudo bonus effect state in the previous stage is a pseudo bonus effect state that is a multiple of 3 (3, 6, ...) That does not go through the normal effect state, the effect state control means 614 temporarily sets the advantageous section. , The advantageous section is temporarily shifted to the non-advantageous section while shifting to the non-advantageous section.

Then, the effect state control means 614 draws a lottery for the transition to the advantageous section with a high probability (for example, 1/2), and after digesting several games, returns to the advantageous section and shifts the effect state to the preparatory effect state (for example). 3). This is to prevent the pseudo-bonus effect state from being forcibly terminated when the value counted in the advantageous section reaches a predetermined value.

On the other hand, if the pseudo-bonus effect state in the previous stage is not the first time, or is not the pseudo-bonus effect state that is a multiple of 3 that does not go through the normal effect state, the effect state control means 614 shifts the effect state to the non-advantageous effect state. Without doing so, it directly shifts to the preparatory production state (4). This is because the pseudo-bonus effect state is not forcibly terminated when the value counted in the advantageous section reaches a predetermined value, and the advantageous section is not terminated unnecessarily.

In the preparatory effect state, the effect state control means 614 draws a lottery for the transition to the first interval effect state with a high probability (for example, 1/2), and based on the determination of the transition to the first interval effect state, the effect state. Shifts to the first interval production state (5).

The first interval effect state continues until a predetermined end condition (for example, digestion of 40 games) is satisfied, during which the continuous lottery of the pseudo bonus effect state is executed. Unlike the pseudo-bonus effect state, the first interval effect state has a small expected number of acquisitions per unit game and may have a negative value. In the present embodiment, when the advantageous section is won in the non-advantageous section, the effect state is set to be the first interval effect state without fail. Therefore, after the end of the pseudo-bonus effect state, even if the advantageous section continues or, as described above, even if the section once shifts to the non-advantageous section, the state shifts to the first interval effect state. It becomes. Then, when a predetermined end condition in the first interval effect state is satisfied, the effect state control means 614 shifts the effect state to the continuous lottery effect state (6).

The continuous lottery effect state continues until a predetermined end condition (for example, digestion of 5 games) is satisfied, and finally, the result of the continuous lottery in the pseudo bonus effect state in the first interval effect state is notified. Unlike the pseudo-bonus effect state, the continuous lottery effect state also has a small expected number of acquisitions per unit game, and may have a negative value. If the transition (continuation) to the pseudo-bonus effect state is determined in the first interval effect state, the effect state control means 614 shifts the effect state to the pseudo-bonus effect state (7), and the pseudo-bonus effect state. If the transition to the effect state is not determined, the effect state control means 614 returns the effect state to the normal effect state (8).

As described above, in the present embodiment, once the pseudo-bonus effect state is entered, the pseudo-bonus effect state → the preparation effect state → the first interval effect state → the continuous lottery effect state unless the continuous lottery in the continuous lottery effect state is omitted. By repeating the transition of, the player can accumulate medals.

In the preparatory effect state, the effect state control means 614 also performs a transition lottery to the second interval effect state in addition to the transition lottery to the first interval effect state. However, the transition probability to the second interval effect state (for example, 1/20) is set smaller than the transition probability to the first interval effect state (for example, 1/2). If the transition to the second interval effect state is determined before the transition to the first interval effect state is determined in the preparatory effect state, the effect state control means 614 determines the transition to the second interval effect state. Based on the above, the effect state is shifted to the second interval effect state (9). In addition, although the example of performing the transition lottery to the second interval effect state in the preparatory effect state is given here, similarly, the transition lottery to the second interval effect state may be performed in the non-advantageous effect state.

Like the first interval effect state, the second interval effect state continues until a predetermined end condition (for example, digestion of 40 games) is satisfied, and during that time, a continuous lottery of the pseudo bonus effect state is executed. Similar to the first interval effect state, the second interval effect state is different from the pseudo bonus effect state, and the expected number of acquired cards per unit game is small and may be a negative value.

However, in the second interval effect state, the pseudo bonus effect state is determined with a higher probability than in the first interval effect state. For example, in the first interval effect state, the pseudo bonus effect state is determined at 1/58 of each game for 40 games (winning probability 50%), and in the second interval effect state, the pseudo bonus effect state is determined for 40 games. Is determined by every game 1/25 (winning probability 80%). Then, when the predetermined end condition is satisfied, the effect state control means 614 shifts the effect state to the continuous lottery effect state (10). Once the transition to the second interval effect state is determined, the process does not shift to the non-advantageous effect state, the preparatory effect state, or the first interval effect state until the continuous lottery effect state is leaked. The pseudo-bonus effect state only shifts to the second interval effect state (11). Therefore, the player can always receive a continuous lottery with a high probability. Further, once the transition to the second interval effect state is determined, the effect state control means 614 immediately changes the effect state even if the transition to the pseudo bonus effect state is not determined in the continuous lottery effect state. It shifts to the non-advantageous production state without returning to the normal production state (12). Therefore, if the transition to the pseudo bonus effect state is not determined in the continuous lottery effect state, the pseudo bonus effect state → the preparation effect state → the first interval effect state → continue until the continuous lottery in the continuous lottery effect state is leaked again. The transition of the lottery effect state can be repeated. In this way, once the transition to the second interval effect state is made, the transition of the pseudo bonus effect state → the second interval effect state → the continuous lottery effect state can be repeated with high probability, and further, the pseudo in the continuous lottery effect state. Even if the transition to the bonus effect state is not decided, at least the transition of the pseudo bonus effect state → the preparation effect state → the first interval effect state → the continuous lottery effect state can be repeated, so that the number of players is larger. It is possible to accumulate medals. That is, it can be said that the second interval effect state is more advantageous than the first interval effect state.

Further, as described above, when the effect state control means 614 shifts from the pseudo bonus effect state to the second interval effect state, it may shift to a non-advantageous section unlike the transition to the first interval effect state. No. In the present embodiment, when the pseudo-bonus effect state is the first pseudo-bonus effect state, the effect state control means 614 does not shift to the second interval effect state, and temporarily shifts the advantageous section to the non-advantageous section. To shift to, be sure to shift to the first interval production state. Then, the advantageous section is once reset. Therefore, even if the advantageous section is not reset when shifting to the second interval effect state, the pseudo-bonus effect state via the second interval effect state does not end in a short period due to the limitation of the advantageous section, and the player , Pseudo-bonus effect state → 2nd interval effect state → Continuous lottery effect state loop, many medals can be obtained.

Hereinafter, specific processing in the main control board 500 and the sub control board 502 will be described with reference to the flowchart.

(CPU initialization process of main control board 500)
FIG. 82 is a flowchart illustrating the CPU initialization process in the main control board 500. When power is supplied from the power supply board, a system reset occurs in the main CPU 500a, and the main CPU 500a performs the following CPU initialization process (S2000).

(Step S2000-1)
The main CPU 500a reads the boot program from the main ROM 500b as the initial setting process in response to the power-on, and also performs the setting process necessary for executing various processes.

(Step S2000-3)
The main CPU 500a sets the wait processing time in the timer counter.

(Step S2000-5)
The main CPU 500a determines whether or not the power supply cutoff warning signal is detected. The main control board 500 is provided with a power supply cutoff detection circuit, and when the power supply voltage becomes equal to or lower than a predetermined value, a power supply cutoff warning signal is output from the power supply cutoff detection circuit. If the power off warning signal is detected, the process is transferred to step S2000-3, and if the power off warning signal is not detected, the process is transferred to step S2000-7.

(Step S2000-7)
The main CPU 500a determines whether or not the wait processing time set in step S2000-3 has elapsed. As a result, if it is determined that the wait processing time has elapsed, the process is transferred to step S2000-9, and if it is determined that the wait time has not elapsed, the process is transferred to step S2000-5.

(Step S2000-9)
The main CPU 500a executes a process necessary for permitting access to the main RAM 500c.

(Step S2000-11)
The main CPU 500a executes the checksum confirmation process. Here, the main CPU 500a calculates a check sum, and determines whether the calculated check sum does not match (abnormal) the check sum saved when the power is turned off, and whether the backup is abnormal. Then, when the main CPU 500a determines that either one or both of the backup and the checksum are abnormal, the backup error flag is turned on, and when it is determined that both the backup and the checksum are not abnormal, the backup error flag is set. Turn off.

(Step S2000-13)
The main CPU 500a determines whether the backup error flag is on. As a result, if it is determined that the backup error flag is on, the process is transferred to step S2010, and if it is determined that the backup error flag is not on, the process is transferred to step S2020.

(Step S2010)
The main CPU 500a executes a cold start process. The cold start process will be described later.

(Step S2020)
The main CPU 500a executes a set value switching process for switching the set value. The setting value switching process will be described later.

(Step S2030)
The main CPU 500a executes a state return process for returning to the state immediately before the power is turned off. The state return processing will be described later.

FIG. 83 is a flowchart illustrating a cold start process (S2010) in the main control board 500.

(Step S2010-1)
The main CPU 500a clears the used area in the main RAM 500c and executes a used area RAM check process for detecting an abnormality in the used area.

(Step S2010-3)
The main CPU 500a clears another area (unused area) in the main RAM 500c, and executes another area RAM check process for detecting an abnormality in the other area. When an abnormality is detected in another area in the other area RAM check process, the main CPU 500a turns on the RAM read / write error flag.

(Step S2010-5)
The main CPU 500a sets an error code "EA" indicating an abnormality in the main RAM 500c.

(Step S2010-7)
The main CPU 500a determines whether or not an abnormality has been detected in step S2010-1. As a result, if it is determined that an abnormality has been detected in step S2010-1, the process is shifted to step S2011, and if it is determined that no abnormality has been detected in step S2010-1, the process proceeds to step S2010-9. Move the process.

(Step S2010-9)
The main CPU 500a acquires a RAM read / write error flag that is turned on when an abnormality is detected in step S2010-3.

(Step S2010-11)
The main CPU 500a determines whether the RAM read / write error flag is on. As a result, if it is determined that the RAM read / write error flag is on, the process is transferred to step S2011, and if it is determined that the RAM read / write error flag is not on, the process is transferred to step S2020.

(Step S2020)
The main CPU 500a executes a set value switching process for switching the set value. The setting value switching process will be described later.

(Step S2010-13)
The main CPU 500a sets an error code "E7" indicating that it is a backup error.

(Step S2011)
The main CPU 500a executes an error stop process for stopping the progress of the game due to an error. The error stop processing will be described later.

FIG. 84 is a flowchart illustrating an error stop process (S2011) in the main control board 500.

(Step S2011-1)
The main CPU 500a sets the initial stack pointer value as the address of the stack pointer.

(Step S2011-3)
The main CPU 500a executes an error setting process for displaying an error and setting a warning sound.

(Step S2011-5)
The main CPU 500a sets the external signals 1 to 3 output bit off, which turns off the output image of the bits corresponding to the external signals 1 to 3.

(Step S2011-7)
The main CPU 500a executes an output port image set process for updating the output image for the bits set in step S2011-5.

(Step S2011-9)
The main CPU 500a shifts to an endless loop. As a result, the progress of the game is stopped.

FIG. 85 is a flowchart illustrating a set value switching process (S2020) in the main control board 500.

(Step S2020-1)
The main CPU 500a acquires the signal of the input port 1 and determines whether or not the set value switching condition is satisfied based on the acquired signal of the input port 1. As a result, if it is determined that the set value switching condition is not satisfied, the set value switching process is terminated, and if it is determined that the set value switching condition is satisfied, the process is moved to step S2020-3. .. Here, the signal of the input port 1 includes a signal indicating whether or not the front upper door 404 and the front lower door 406 are open, and a signal indicating whether or not the setting key is turned on. Then, here, when the signal indicating that the front upper door 404 and the front lower door 406 are open and the signal indicating that the setting key is turned on are acquired, the setting value switching condition is set. It is judged that it is established.

(Step S2020-3)
The main CPU 500a executes a RAM clearing process for clearing the used area to be cleared when the setting is changed in the main RAM 500c.

(Step S2020-5)
The main CPU 500a executes a table content set process for transferring the table data of the data table at the time of switching the set value to the main RAM 500c.

(Step S2020-7)
The main CPU 500a sets a setting change start command indicating that the setting value change is started in the transmission buffer.

(Step S2020-9)
The main CPU 500a executes an edge check process for detecting the rising edge (on-edge) and falling edge (off-edge) of the signal of the input port.

(Step S2020-11)
The main CPU 500a acquires the set value data indicating the current set value.

(Step S2020-13)
The main CPU 500a determines whether or not the on-edge of the setting change switch is detected in step S2020-9. As a result, if it is determined that the on-edge of the setting change switch has not been detected, the process is transferred to step S2020-17, and if it is determined that the on-edge of the setting change switch has been detected, the process is transferred to step S2020-15. ..

(Step S2020-15)
The main CPU 500a increments the set value data by 1.

(Step S2020-17)
The main CPU 500a determines whether the set value data is within the range (1 to 6) that can be set as the set value. As a result, if it is determined that the set value data is within the range, the process is transferred to step S2020-21, and if it is determined that the set value data is not within the range, the process is transferred to step S2020-19.

(Step S2020-19)
The main CPU 500a sets the set value data to 0.

(Step S2020-21)
The main CPU 500a updates the set value data to the value incremented or set in step S2020-15 or step S2020-19.

(Step S2020-23)
The main CPU 500a executes a display data conversion process for displaying the set value on the main credit display unit 430.

(Step S2020-25)
The main CPU 500a determines whether or not the on-edge of the setting change switch is detected. As a result, if it is determined that the on-edge of the setting change switch has not been detected, the process is transferred to step S2020-31, and if it is determined that the on-edge of the setting change switch has been detected, the process is performed in step S2020-27. To move.

(Step S2020-27)
The main CPU 500a determines whether the setting change switch is on. As a result, if it is determined that the setting change switch is on, the process is transferred to step S2020-27, and if it is determined that the setting change switch is not on, the process is transferred to step S2020-29.

(Step S2020-29)
The main CPU 500a sets a set value change switch interval timer.

(Step S2020-31)
The main CPU 500a executes a timer wait process that waits until the setting change switch interval timer becomes 0.

(Step S2020-33)
The main CPU 500a determines whether or not the on-edge of the start switch 418 is detected. As a result, if it is determined that the on-edge of the start switch 418 is not detected, the process is transferred to step S2020-9, and if it is determined that the on-edge of the start switch 418 is detected, the process is performed in step S2020-35. To move.

(Step S2020-35)
The main CPU 500a determines whether the setting key is off. As a result, if it is determined that the setting key is off, the process is transferred to step S2020-35, and if it is determined that the setting key is not off, the process is transferred to step S2020-37.

(Step S2020-37)
The main CPU 500a determines whether the setting key is on. As a result, if it is determined that the setting key is on, the process is transferred to step S2020-37, and if it is determined that the setting key is not on, the process is transferred to step S2021.

(Step S2021)
The main CPU 500a executes an initialization start process for starting the initialization start. The initialization start process will be described later.

FIG. 86 is a flowchart illustrating the initialization start process (S2021) in the main control board 500.

(Step S2021-1)
The main CPU 500a sets a setting change end command indicating that the setting value change is completed in the transmission buffer.

(Step S2021-3)
The main CPU 500a sets in the transmission buffer a setting change status command indicating a status when the change of the set value is completed.

(Step S2021-5)
The main CPU 500a sets a wait timer at the start of initialization.

(Step S2021-7)
The main CPU 500a executes a timer wait process that waits until the wait timer at the start of initialization becomes 0.

(Step S2021-9)
The main CPU 500a executes a RAM clearing process at the time of setting change to clear another area of the main RAM 500c.

(Step S2021-11)
The main CPU 500a executes a RAM clearing process for clearing the used area to be cleared when the setting is changed in the main RAM 500c.

(Step S2021-13)
The main CPU 500a sets a game state command indicating the current game state in the transmission buffer.

(Step S2100)
The main CPU 500a executes a game start process for starting the game. The game start process will be described later.

FIG. 87 is a flowchart illustrating a state return process (S2030) in the main control board 500.

(Step S2030-1)
The main CPU 500a returns the stack pointer.

(Step S2030-3)
The main CPU 500a executes an unused area clearing process for clearing an unused area in the main RAM 500c.

(Step S2030-5)
The main CPU 500a clears the stack pointer storage buffer.

(Step S2030-7)
The main CPU 500a sets (turns on) the flag after the power is turned off and on.

(Step S2030-9)
The main CPU 500a executes a port input process for updating the image of the input port.

(Step S2030-11)
The main CPU 500a executes an operation target bit extraction process for extracting information on the operation target bit based on the image of the input port updated in step S2030-9.

(Step S2030-13)
The main CPU 500a sets the operation target bit extracted in step S2030-11 as the operation target bit in the previous state.

(Step S2030-15)
The main CPU 500a acquires the motor phases of the reels 410a, 410b, 410c. Here, the motor phase is set as the state of the reels 410a, 410b, 410c. The motor phase indicates the operating state of the reels 410a, 410b, 410c, that is, during acceleration, steady rotation, stop, and standby. Specifically, the 1-byte (storage unit) variable assigned to the motor phase is accelerating = 3, steady rotation = 2, stopped = 1, waiting =, depending on the operating state of the stepping motor 452. It changes to a value such as 0.

(Step S2030-17)
Based on the motor phase acquired in step S2030-15, the main CPU 500a determines whether any of the reels 410a, 410b, and 410c is in steady rotation and acceleration. As a result, when it is determined that none of the reels 410a, 410b, 410c is in steady rotation and acceleration, the process is transferred to step S2030-21, and any of the reels 410a, 410b, 410c is in steady rotation or acceleration. If it is determined to be inside, the process is moved to step S2030-19.

(Step S2030-19)
The main CPU 500a executes a rotation error process for setting the reels 410a, 410b, 410c at the time of error detection.

(Step S2030-21)
The main CPU 500a restores the saved register group.

(Step S2030-23)
The main CPU 500a permits interrupts and ends the state return process. As a result, the main CPU 500a returns to the state immediately before the power is turned off.

FIG. 88 is a flowchart illustrating the game start process (S2100) on the main control board 500.

(Step S2100-1)
The main CPU 500a executes a re-game state identification signal output setting process for outputting a re-game state identification signal indicating whether or not the game is re-game.

(Step S2100-3)
The main CPU 500a sets the inserted number indicator output bit off for turning off (turning off) the bit corresponding to the inserted number indicator that displays the inserted number of medals (the number of bets).

(Step S2100-5)
The main CPU 500a executes an output port image set process for updating the output image for the bits set in step S2100-3.

(Step S2100-7)
The main CPU 500a sets a game start wait timer.

(Step S2100-9)
The main CPU 500a executes a timer wait process that waits until the game start wait timer becomes 0.

(Step S2100-11)
The main CPU 500a executes a one-game RAM clearing process that clears an area to be cleared for each game among the areas used in the main RAM 500c.

(Step S2100-13)
The main CPU 500a executes a bonus signal setting process for setting a bonus signal.

(Step S2100-15)
The main CPU 500a executes an edge clearing process for clearing the edge information of the input port image.

(Step S2200)
The main CPU 500a executes a game medal insertion process for accepting the insertion of medals. The game medal insertion process will be described later.

FIG. 89 is a flowchart illustrating a game medal insertion process (S2200) on the main control board 500.

(Step S2200-1)
The main CPU 500a executes an error confirmation process for confirming the detection results of various errors.

(Step S2200-3)
The main CPU 500a executes an edge check process for detecting the rising edge (on-edge) and falling edge (off-edge) of the signal of the input port.

(Step S2200-5)
The main CPU 500a acquires a door opening error detection flag in which 1 is set when the front upper door 404 or the front lower door 406 is opened.

(Step S2200-7)
The main CPU 500a determines whether the front upper door 404 and the front lower door 406 are closed based on the door opening error detection flag acquired in step S2200-5. As a result, when it is determined that the front upper door 404 and the front lower door 406 are closed, the process is transferred to step S2200-17, and at least one of the front upper door 404 or the front lower door 406 is not closed. If it is determined, the process is moved to step S2200-9.

(Step S2200-9)
The main CPU 500a sets an error code "E8" indicating that at least one of the front upper door 404 and the front lower door 406 is open.

(Step S2200-11)
The main CPU 500a executes an error display, an error sound request, and an error wait process for waiting for error recovery.

(Step S2200-13)
The main CPU 500a executes a set value confirmation process for confirming the set value.

(Step S2200-15)
The main CPU 500a executes an edge clearing process for clearing the edge information of the input port image.

(Step S2200-17)
The main CPU 500a executes a credit button check process for refunding stored medals when a credit switch (not shown) for refunding stored medals is pressed.

(Step S2200-19)
The main CPU 500a executes a game medal insertion button-related process for betting medals. Here, when the bet switch 416 is pressed, the stored (credit) medals are bet up to a specified number, and the stored number is subtracted by the number of bets. Further, when medals are inserted through the medal insertion slot 414a, medals are bet up to a specified number, and when more medals are inserted than the specified number, the number of medals is added to the stored number.

(Step S2200-21)
The main CPU 500a executes a game medal acquisition process for confirming whether or not the number of inserted cards is a specified number.

(Step S2200-23)
The main CPU 500a determines whether or not the number of input sheets is not the specified number based on the confirmation result in step S2200-21. As a result, when it is determined that the number of inserted sheets is not the specified number, the process is transferred to step S2200-1, and when it is determined that the number of inserted sheets is the specified number, the process is transferred to step S2200-25.

(Step S2200-25)
The main CPU 500a sets a start indicator output bit for turning on (lights) the start indicator (not shown) indicating whether or not the operation of the start switch 418 is enabled.

(Step S2200-27)
The main CPU 500a determines whether or not the falling edge (pressing) of the start switch 418 is detected. As a result, if it is determined that the falling edge of the start switch 418 has not been detected, the process is shifted to step S2200-1. If it is determined that the falling edge of the start switch 418 has been detected, step S2200 is performed. Move the process to -29.

(Step S2200-29)
The main CPU 500a clears the main payout display unit buffer in order to clear the display of the main payout display unit 432.

(Step S2200-31)
The main CPU 500a executes a re-game state identification signal clearing process for clearing the re-game state identification signal.

(Step S2200-33)
The main CPU 500a executes a blocker blockage preprocessing for turning off (turning off) the start indicator.

(Step S2200-35)
The main CPU 500a sets a lever pressing command indicating that the start switch 418 has been pressed in the transmission buffer.

(Step S2300)
The main CPU 500a executes an internal lottery process for performing a winning type lottery. The internal lottery process will be described later.

FIG. 90 is a flowchart illustrating the internal lottery process (S2300) in the main control board 500.

(Step S2300-1)
The main CPU 500a acquires the set value data.

(Step S2300-3)
The main CPU 500a sets an error code "EC" indicating a set value abnormality error.

(Step S2300-5)
The main CPU 500a determines whether the set value data acquired in step S2300-1 is abnormal. As a result, if it is determined that the set value data is abnormal, the process is transferred to step S2011, and if it is determined that the set value data is not abnormal, the process is transferred to step S2300-7.

(Step S2300-7)
The main CPU 500a acquires a winning type lottery random number updated by the random number generator 500d.

(Step S2300-9)
The main CPU 500a executes a state offset acquisition process for acquiring an offset value related to the game state.

(Step S2300-11)
The main CPU 500a sets the address of the internal lottery area definition table (winning type lottery table).

(Step S2300-13)
The main CPU 500a sets the value indicated by the address obtained by adding the offset value acquired in step S2300-9 to the address set in step S2300-11 as the initial value of the winning area. Here, the first winning area in the winning type lottery table in the current gaming state is set as the initial value.

(Step S2300-15)
The main CPU 500a acquires lottery data which is a numerical value indicating a winning range of the winning area, and executes a lottery data acquisition process of shifting the winning area by one.

(Step S2300-17)
The main CPU 500a determines whether or not to perform the winning type lottery. As a result, if it is determined that the winning type lottery is not performed, the process is transferred to step S2300-21, and if it is determined that the winning type lottery is performed, the process is transferred to step S2300-19.

(Step S2300-19)
The main CPU 500a subtracts the lottery data from the random number value.

(Step S2300-21)
The main CPU 500a determines whether the subtraction result in step S2300-19 is negative, that is, whether the winning area is won by the winning type lottery. As a result, if it is determined that the lottery for the winning type has been won, the process is transferred to step S2400, and if it is determined that the lottery for the winning type has not been won, the process is transferred to step S2300-23.

(Step S2300-23)
The main CPU 500a determines whether or not the winning type lottery has ended. As a result, if it is determined that the winning type lottery is not completed, the process is transferred to step S2300-15, and if it is determined that the winning type lottery is completed, the process is transferred to step S2300-25.

(Step S2300-25)
The main CPU 500a clears the trigger combination type.

(Step S2400)
The main CPU 500a executes a symbol code setting process for setting a symbol code based on the winning area and the game state. The symbol code setting process will be described later.

FIG. 91 is a flowchart illustrating a symbol code setting process (S2400) on the main control board 500.

(Step S2400-1)
The main CPU 500a acquires the winning area won in step S2300, and executes a game state setting process for setting the game state to the internal middle game state when the acquired winning area includes a bonus combination.

(Step S2400-3)
The main CPU 500a sets the winning area acquired in step S2400-1 as the stop control number.

(Step S2400-5)
The main CPU 500a determines (sets) the winning type based on the winning area acquired in step S2400-1.

(Step S2400-7)
Based on the stop control number set in step S2400-3, the main CPU 500a executes a symbol code initial setting process for setting a symbol that can be displayed and a symbol code that indicates a symbol to be pulled in.

(Step S2400-9)
The main CPU 500a executes a display symbol bit initial value setting process for setting the display symbol bit.

(Step S2400-11)
The main CPU 500a executes an execution flag setting process that sets an execution flag, performs various processes related to the effect state, processes related to the auxiliary effect, and the like.

(Step S2400-13)
The main CPU 500a sets the effect command, which is a command related to the advantageous section, in the transmission buffer.

(Step S2400-15)
The main CPU 500a sets a winning information command indicating a winning type in the transmission buffer.

(Step S2400-17)
The main CPU 500a confirms the timer between one game.

(Step S2400-19)
The main CPU 500a sets a pre-rotation command indicating that the reels 410a, 410b, 410c are before rotation in the transmission buffer.

(Step S2400-21)
The main CPU 500a executes an excitation release waiting process that waits for the excitation release of the stepping motor 452.

(Step S2400-23)
The main CPU 500a determines whether the timer for one game is not 0. As a result, if it is determined that the 1-game timer is not 0, the process is transferred to step S2400-23, and if it is determined that the 1-game timer is 0, the process is transferred to step S2400-25.

(Step S2400-25)
The main CPU 500a executes a spinning start process for starting the rotation of the reels 410a, 410b, 410c. Here, the motor phases of the reels 410a, 410b, and 410c are set during acceleration to start the rotation of each reel, or the timer between games is set to a value corresponding to 4.1 seconds.

(Step S2400-27)
The main CPU 500a sets a rotation start command indicating that the rotation of the reels 410a, 410b, 410c has started in the transmission buffer.

(Step S2500)
The main CPU 500a executes a process during rotation of the reels 410a, 410b, 410c, which is a process during rotation of the reels 410a, 410b, 410c. The processing during rotation of the rotating cylinder will be described later.

FIG. 92 is a flowchart illustrating the processing during rotation (S2500) in the main control board 500.

(Step S2500-1)
The main CPU 500a sets the stop indicator output bit off (output image) in order to turn off (turn off) the bits corresponding to the indicators (not shown) of the stop switches 420a, 420b, 420c. Here, the stop indicator output bit is composed of a 3-bit bit string, and each bit is associated with the emission color of the three stop switches 420a, 420b, and 420c, respectively, and is represented by blue = 1 and red = 0. Will be done.

(Step S2500-3)
The main CPU 500a executes an output port image set process for updating the output image for the bits set in step S2500-1.

(Step S2500-5)
The main CPU 500a executes an error confirmation process for confirming the detection results of various errors.

(Step S2500-7)
The main CPU 500a refers to the index flag and acquires the indexes of the rotating reels 410a, 410b, 410c. The index flag is set only after the reels 410a, 410b, 410c have reached the constant speed rotation speed. In other words, the fact that the index flag is set means that the reels 410a, 410b, 410c rotate at a constant speed. It also indicates that the speed has been reached.

(Step S2500-9)
The main CPU 500a determines whether or not the index flags of all the reels 410a, 410b, and 410c have been detected. As a result, if it is determined that all the index flags have not been detected, the process is transferred to step S2500-1, and if it is determined that all the index flags have been detected, the process is transferred to step S2500-11.

(Step S2500-11)
The main CPU 500a acquires a stop rotation bit indicating the reels 410a, 410b, 410c that have stopped or started to stop. Here, the stop rotation bit is composed of a bit string of 3 bits, and each bit is associated with any of the three reels 410a, 410b, 410c, and the constant speed state = 1, acceleration state, and deceleration state. Or it is represented by the stopped state = 0.

(Step S2500-13)
The main CPU 500a saves the stop rotating bit acquired in step S2500-11 as a rotating rotating flag.

(Step S2500-15)
The main CPU 500a sets the stop indicator output bit on (output image) in order to turn on (turn off) the bits corresponding to the indicators (not shown) of the stop switches 420a, 420b, 420c.

(Step S2500-17)
The main CPU 500a acquires an image of the input port 0 and executes an operation target bit extraction process for extracting an operation target bit from the acquired image. Here, the operation target bit is composed of a 3-bit bit string, and each bit is associated with any of the three stop switches 420a, 420b, and 420c, and is operated = 1, not operated. It is represented by = 0.

(Step S2500-19)
The main CPU 500a calculates the logical product of the rotating cylinder rotating flag acquired in step S2500-13 and the operation target bit extracted in step S2500-17. Here, if the reel 410 is rotating and the stop switch 420 corresponding to the reel is operated, that is, if the operated stop switch 420 corresponds to the reel 410 that is effectively rotating. , The logical product is 1.

(Step S2500-21)
The main CPU 500a determines whether the logical product calculated in step S2500-19 is 0, that is, whether the stop switch 420 corresponding to the rotating reel 410 is not operated. As a result, when it is determined that the stop switch 420 corresponding to the rotating reel 410 is not operated, the process is transferred to step S2500-3, and the stop switch 420 corresponding to the rotating reel 410 is operated. If it is determined that the process is performed, the process is moved to step S2500-23.

(Step S2500-23)
The main CPU 500a acquires an output image including the stop indicator output bit, and calculates the logical product of the acquired output image and the logical product calculated in step S2500-19. Here, when the operated stop switch 420 is lit in red, the bit of the logical product is 0, and when it is lit in blue, the bit of the logical product is 1.

(Step S2500-25)
The main CPU 500a determines whether the logical product calculated in step S2500-23 is 0, that is, whether the operated stop switch 420 is lit in red. As a result, if it is determined that the operated stop switch 420 is lit in red, the process is transferred to step S2500-1, and if it is determined that the operated stop switch 420 is not lit in red, step S2500-. The process is transferred to 27.

(Step S2500-27)
The main CPU 500a determines whether the operated stop switch 420 is not valid. As a result, if it is determined that the operated stop switch 420 is not valid, the process is transferred to step S2500-1, and if it is determined that the operated stop switch 420 is valid, the process is performed in step S2500-29. Transfer. Here, it is determined whether or not there is only one operated stop switch 420. Then, when it is determined that the number of operated stop switches 420 is one, the process is transferred to step S2500-29, and when it is determined that the number of operated stop switches 420 is not one, that is, two or more. The process is transferred to step S2500-1.

(Step S2500-29)
The main CPU 500a executes a stop control rotation cylinder setting process for acquiring various parameters for stopping the reel 410 corresponding to the operated stop switch 420.

(Step S2500-31)
The main CPU 500a disables interrupts.

(Step S2500-33)
The main CPU 500a executes a pressing reference position acquisition process for deriving the symbol number of the symbol located on the effective line A as the pressing reference position.

(Step S2500-35)
The main CPU 500a executes a sliding frame number acquisition process for determining the number of sliding frames of the reel 410.

(Step S2600)
The main CPU 500a executes a spinning stop process for stopping the reel 410 corresponding to the operated stop switch 420. The rotation stop processing will be described later.

FIG. 93 is a flowchart illustrating the rotation stop processing (S2600) in the main control board 500.

(Step S2600-1)
The main CPU 500a acquires the pressing reference position derived in step S2500-35.

(Step S2600-3)
The main CPU 500a calculates the stop request number by correcting the number of sliding frames determined in step S2500-37 with respect to the pressing reference position acquired in step S2600-1.

(Step S2600-5)
The main CPU 500a sets (sets to 1) the stop request flag. The stop request flag is a flag for requesting the stop processing of the target reel 410 from the programs operating in parallel, and by setting the stop request flag to 1, the symbol corresponding to the stop request number is valid. It is possible to stop on line A. The stop request flag and the above stop request number are read by a program operating in parallel, and the reel 410 is stopped. When the stop processing is completed, the stop request flag is reset to 0 (OFF) by the program.

(Step S2600-7)
The main CPU 500a allows interrupts.

(Step S2600-9)
The main CPU 500a sets a stop information command indicating the stop order of the reels 410 in the transmission buffer.

(Step S2600-11)
The main CPU 500a sets the stop indicator output bit off (output image) in order to turn off (turn off) the bit corresponding to the indicator (not shown) of the stop switch 420.

(Step S2600-13)
The main CPU 500a executes an output port image set process for updating the output image for the bits set in step S2600-11.

(Step S2600-15)
The main CPU 500a executes a display symbol bit setting process for setting the display symbol bit.

(Step S2600-17)
The main CPU 500a executes the next reel setting preprocessing for stopping the next reel 410.

(Step S2600-19)
The main CPU 500a determines whether the stop processing of all reels 410 has been completed. As a result, if it is determined that the stop processing of all reels 410 has not been completed, the process is transferred to step S2500, and if it is determined that the stop processing of all reels 410 has been completed, the process proceeds to step S2600-21. Move the process.

(Step S2600-21)
The main CPU 500a determines whether the stop request flag is on for any of the reels 410, that is, whether all the reels 410 have been stopped. As a result, if it is determined that all the reels 410 have not been stopped, the process is transferred to step S2600-21, and if it is determined that all the reels 410 have been stopped, the process is transferred to step S2600-23.

(Step S2600-23)
The main CPU 500a executes an error confirmation process for confirming the detection results of various errors.

(Step S2600-25)
The main CPU 500a executes an operation target bit extraction process for extracting information on the operation target bit.

(Step S2600-27)
The main CPU 500a determines whether or not the stop switch 420 is pressed based on the operation target bit acquired in step S2600-25. As a result, if it is determined that the stop switch 420 is pressed, the process is transferred to step S2600-23, and if it is determined that the stop switch 420 is not pressed, the process is transferred to step S2700.

(Step S2700)
The main CPU 500a executes a display determination process for determining a winning combination. The display determination process will be described later.

FIG. 94 is a flowchart illustrating the display determination process (S2700) on the main control board 500.

(Step S2700-1)
The main CPU 500a clears the buffer of the main payout display unit 432.

(Step S2700-3)
The main CPU 500a determines whether or not a display determination abnormality has occurred depending on whether or not the symbol combination displayed on the effective line A and the symbol combination permitted to be displayed on the effective line A match. Execute the detection process.

(Step S2700-5)
The main CPU 500a sets an error code "EE" indicating that the display determination is abnormal (error).

(Step S2700-7)
The main CPU 500a determines whether or not the display determination is abnormal based on the determination result in step S2700-3. As a result, if it is determined that the display determination is abnormal, the process is transferred to step S2011, and if it is determined that the display determination is not abnormal, the process is transferred to step S2700-9.

(Step S2700-9)
The main CPU 500a executes a display symbol identification generation process for determining a winning combination based on the symbol combination stopped (displayed) on the valid line A.

(Step S2700-11)
The main CPU 500a sets 0 as the initial value of the number of payouts.

(Step S2700-13)
The main CPU 500a determines whether or not the small winning combination has won. As a result, if it is determined that the small winning combination has won, the process is transferred to step S2700-15, and if it is determined that the small winning combination has not won, the processing is transferred to step S2700-35.

(Step S2700-15)
The main CPU 500a turns on the winning flag indicating that the small winning combination has won.

(Step S2700-17)
The main CPU 500a executes a payout number setting process for setting the payout number according to the winning small winning combination.

(Step S2700-19)
The main CPU 500a determines whether or not it is an advantageous section. As a result, if it is determined that the section is not advantageous, the process is transferred to step S2800, and if it is determined that the section is advantageous, the process is transferred to step S2700-21.

(Step S2700-21)
The main CPU 500a acquires the value of the advantageous section MY counter that counts the net increase in the number of sheets in the advantageous section.

(Step S2700-23)
The main CPU 500a adds the number of payouts to the value of the advantageous section MY counter acquired in step S2700-23.

(Step S2700-25)
The main CPU 500a acquires the number of input sheets of the game.

(Step S2700-27)
The main CPU 500a subtracts the number of input sheets from the value added in step S2700-23.

(Step S2700-29)
The main CPU 500a determines whether the subtraction result in step S2700-27 is not negative. As a result, if it is determined that the subtraction result is not negative, the process is transferred to step S2700-33, and if it is determined that the subtraction result is negative, the process is transferred to step S2700-31.

(Step S2700-31)
The main CPU 500a clears (sets to 0) the value of the advantageous section MY counter.

(Step S2700-33)
The main CPU 500a updates the value of the advantageous section MY counter to the value subtracted in the step S2700-27 or the value cleared in the step S2700-31.

(Step S2700-35)
The main CPU 500a determines whether or not the replay combination has won a prize. As a result, if it is determined that the replay combination has not won a prize, the process is transferred to step S2800, and if it is determined that the replay combination has won a prize, the process is transferred to steps S2700-37.

(Step S2700-37)
The main CPU 500a sets the number of input sheets to the number of payout sheets.

(Step S2700-39)
The main CPU 500a turns on the flag during re-game operation.

(Step S2700-41)
The main CPU 500a sets the number of automatically input sheets.

(Step S2800)
The main CPU 500a executes a payout process for paying out medals. The payout process will be described later.

FIG. 95 is a flowchart illustrating the payout process (S2800) in the main control board 500.

(Step S280-1)
The main CPU 500a acquires the re-game operation flag.

(Step S2800-3)
The main CPU 500a sets a payout start command indicating that the payout of medals has started in the transmission buffer.

(Step S2800-5)
The main CPU 500a determines whether or not the replay combination has won a prize based on the replay operating flag acquired in step S280-1. As a result, if it is determined that the replay combination has won a prize, the process is transferred to step S2800-41, and if it is determined that the replay combination has not won a prize, the process is transferred to step S2800-7.

(Step S2800-7)
The main CPU 500a executes a main display display process for displaying 0 on the main payout display unit 432.

(Step S2800-9)
The main CPU 500a determines that there is no payout (the number of payouts is 0). As a result, if it is determined that there is no payout, the process is transferred to step S2800-35, and if it is determined that there is a payout, the process is transferred to step S2800-11.

(Step S2800-11)
The main CPU 500a determines whether the number of stored sheets is 50 or more. As a result, when it is determined that the number of stored sheets is 50 or more, the process is transferred to step S2800-13, and when it is determined that the number of stored sheets is not 50 or more, the process is transferred to step S2800-15.

(Step S2800-13)
The main CPU 500a executes a medal payout device control process for paying out one medal from the medal payout device 442, and shifts the process to step S2800-23.

(Step S2800-15)
The main CPU 500a sets a payout start interval timer.

(Step S2800-17)
The main CPU 500a determines whether the payout start timer is not 0, that is, at the time of the first payout. As a result, if it is determined that it is the first payout, the process is transferred to step S2800-21, and if it is determined that it is not the first payout, the process is transferred to step S2800-19.

(Step S2800-19)
The main CPU 500a executes a timer wait process that waits until the payout start interval timer becomes 0.

(Step S2800-21)
The main CPU 500a increments the number of stored sheets by one.

(Step S2800-23)
The main CPU 500a sets a payout execution command indicating that one medal has been paid out in the transmission buffer.

(Step S2800-25)
The main CPU 500a executes a main display pre-display processing for displaying the number of payouts already paid out on the main payout display unit 432.

(Step S2800-27)
The main CPU 500a determines whether or not it is in the bonus game state. As a result, if it is determined that the game is not in the bonus game state, the process is transferred to step S2800-31, and if it is determined that the game is in the bonus game state, the process is transferred to step S2800-29.

(Step S2800-29)
The main CPU 500a increments the number of medals acquired during the bonus operation, which is the number of medals paid out in the bonus game state.

(Step S2800-31)
The main CPU 500a determines whether or not the payout of the number of medals to be paid out has been completed. As a result, if it is determined that the payout has not been completed, the process is transferred to step S2800-11, and if it is determined that the payout has been completed, the process is transferred to step S2800-33.

(Step S2800-33)
The main CPU 500a executes a payout end process for ending the payout of medals.

(Step S2800-35)
The main CPU 500a determines whether an over error has been detected. As a result, if it is determined that no over error has been detected, the process is transferred to step S2800-41, and if it is determined that an over error has been detected, the process is transferred to step S2800-37.

(Step S2800-37)
The main CPU 500a sets an error code "E5" indicating an over error.

(Step S2800-39)
The main CPU 500a executes an error display, an error sound request, and an error wait process for waiting for error recovery.

(Step S2800-41)
The main CPU 500a sets a payout end command indicating that the payout of medals has been completed in the transmission buffer.

(Step S2900)
The main CPU 500a executes a game transition process that performs a game state transition, a process of managing an advantageous section, and the like. The game transition process will be described later.

FIG. 96 is a flowchart illustrating the game transition process (S2900) in the main control board 500.

(Step S2900-1)
The main CPU 500a acquires the re-game operating flag, and based on the acquired re-game operating flag, turns on or off the bit corresponding to the replay display (not shown) indicating that the next game is the re-game. Therefore, the stop indicator output bit off (output image) is set, and the replay indicator control process that updates the output bit of the set output image is executed.

(Step S2900-3)
When the bonus combination is won, the main CPU 500a executes a bonus operation symbol display process for setting various parameters for controlling the bonus game state.

(Step S2900-5)
In the bonus game state, the main CPU 500a executes a bonus operation end process for shifting the game state to the non-internal game state when the number of acquired cards during the bonus operation reaches a predetermined number.

(Step S2900-7)
The main CPU 500a executes the advantageous section update process for managing the advantageous section.

(Step S2900-9)
The main CPU 500a determines whether or not the next game is in the AT effect state. As a result, if it is determined that the next game is not in the AT effect state, the process is transferred to step S2900-15, and if it is determined that the next game is in the AT effect state, the process is transferred to step S2900-11.

(Step S2900-11)
The main CPU 500a determines whether or not it is in the bonus game state. As a result, if it is determined that the game is not in the bonus game state, the process is transferred to step S2900-15, and if it is determined that the game is in the bonus game state, the process is transferred to step S2900-13.

(Step S2900-13)
The main CPU 500a sets the advantage lamp flag for lighting the section indicator 160 on.

(Step S2900-15)
The main CPU 500a executes an effect command setting process for setting an effect command, which is a command related to an advantageous section, in the transmission buffer.

(Step S2900-17)
The main CPU 500a sets a game end command indicating that one game has ended in the transmission buffer.

(Step S2900-19)
The main CPU 500a executes a terminal board signal output process for outputting an external signal.

(Step S2900-21)
The main CPU 500a determines whether or not the effect wait timer set when the advantageous section is terminated in step S2900-7 is not 0. As a result, if it is determined that the effect wait timer is not 0, the process is transferred to step S2900-21, and if it is determined that the effect wait timer is 0, the process is transferred to step S2900-23.

(Step S2900-23)
The main CPU 500a sets a game state command indicating the game state in the transmission buffer.

(Step S2900-25)
The main CPU 500a sets a game start command indicating the start of the next game in the transmission buffer, and shifts the process to step S2100.

One game is executed through a series of processes from step S2100 to step S2900. After that, steps S2100 to S2900 will be repeated.

Next, the evacuation process when the power is turned off and the timer interrupt process in the main control board 500 will be described.

(Evacuation processing when the power of the main control board 500 is turned off)
FIG. 97 is a flowchart illustrating the evacuation process when the power is turned off in the main control board 500. The main CPU 500a monitors the power supply cutoff detection circuit, and when the power supply voltage becomes equal to or less than a predetermined value, it interrupts and executes the power failure save processing.

(Step S3000-1)
When the power cutoff warning signal is input, the main CPU 500a saves the register.

(Step S3000-3)
The main CPU 500a checks the power off warning signal.

(Step S3000-5)
The main CPU 500a determines whether or not the power supply cutoff warning signal is detected. As a result, if it is determined that the power off warning signal has been detected, the process is transferred to step S3000-11, and if it is determined that the power off warning signal has not been detected, the process is transferred to step S3000-7. ..

(Step S3000-7)
The main CPU 500a restores the register.

(Step S3000-9)
The main CPU 500a performs a process for permitting an interrupt, and ends the save process when the power is turned off.

(Step S3000-11)
The main CPU 500a executes an output port clearing process for stopping the output of the output port.

(Step S3000-13)
The main CPU 500a executes an evacuation process when the power is turned off for another area.

(Step S3000-15)
The main CPU 500a executes the RAM protection setting process necessary for prohibiting access to the main RAM 300c.

(Step S3000-17)
The main CPU 500a sets a predetermined number of times of power failure detection signal detection to the counter value of the loop counter in order to set the power failure occurrence monitoring time.

(Step S3000-19)
The main CPU 500a subtracts 1 from the value of the loop counter set in step S3000-17.

(Step S3000-21)
The main CPU 500a determines whether the counter value of the loop counter is not 0. As a result, if it is determined that the counter value is not 0, the process proceeds to step S3000-19, and if it is determined that the counter value is 0, the process proceeds to the CPU initialization process (step S1000) described above.

When the power is actually cut off, the operation of the slot machine 400 is stopped while looping from step S3000-19 to step S3000-21.

(Timer interrupt processing of main control board 500)
FIG. 98 is a flowchart illustrating timer interrupt processing on the main control board 500. The main control board 500 is provided with a reset clock pulse generation circuit that generates a clock pulse at a predetermined cycle (1.49 ms in the simultaneous rotation reference example, hereinafter referred to as “1.49 ms”). Then, when a clock pulse is generated by the reset clock pulse generation circuit, it interrupts and the following timer interrupt processing is executed.

(Step S3100-1)
The main CPU 500a saves the register.

(Step S3100-3)
The main CPU 500a clears the interrupt flag.

(Step S3100-5)
The main CPU 500a reads various input port images and executes port input processing for accurately acquiring the latest switch state.

(Step S3100-7)
The main CPU 500a outputs the set output image to the output port, and displays the main credit display unit 430, the main payout display unit 432, the number of input sheets display, the start display, the stop switches 420a, 420b, and 420c, and the replay display. The dynamic port output process for controlling the lighting of the device and the section indicator 160 is executed.

(Step S3100-9)
The main CPU 500a updates the timer interrupt phase. The timer interrupt phase is any of 0 to 3, and here, 1 is added when the timer interrupt phase is 0, 1, and 2, and 0 when the timer interrupt phase is 3. Be changed.

(Step S3100-11)
The main CPU 500a performs a subcommand transmission process for transmitting the command stored in the transmission buffer to the subcontrol board 502.

(Step S3100-13)
The main CPU 500a executes a stepping motor control process for controlling the stepping motor 452.

(Step S3100-15)
The main CPU 500a executes an output port image output process for outputting an output image to be output to the medal payout device 442.

(Step S3100-17)
The main CPU 500a executes a random number update process for updating various random numbers.

(Step S3100-19)
The main CPU 500a executes an fraud monitoring process for detecting an error in order to output an external signal (external signals 4, 5) corresponding to the error to the outside.

(Step S3100-21)
The main CPU 500a executes a module (subroutine) corresponding to the timer interrupt processing phase updated in step S3100-9. Here, the timer interrupt processing phase is set to any of 0 to 3, and one module corresponding to each of the timer interrupt processing phases 0 to 3 is provided (four in total), and 1 One module will be executed once every four times (every 5.96 ms) of timer interrupt processing. For example, a module that executes time monitoring processing for subtracting various timers is associated with one timer interrupt processing phase.

(Step S3100-23)
The main CPU 500a executes a test signal output process for outputting a test signal to the outside.

(Step S3100-25)
The main CPU 500a reads various input port images and executes port input processing for accurately acquiring the latest switch state.

(Step S3100-27)
The main CPU 500a restores the register.

(Step S3100-29)
The main CPU 300a permits interrupts and ends the timer interrupt process.

Further, in the above-described embodiment, the main control board 500 and the sub control board 502 are arranged so as to share the functional part for advancing the game, but the functional part of the main control board 500 is assigned to the sub control board 502. Alternatively, the functional parts of the sub-control board 502 may be arranged on the main control board 500, or all the functional parts may be arranged together on one control board.

Further, in the above-described embodiment, only one type of AT effect state is provided, but for example, a plurality of types of AT effect states are provided, such as a special zone for adding the number of continuous games in the AT effect state. May be good.

Further, in the above-described embodiment, the game is performed using medals as the game value, but the game value may be electrical information (so-called medalless). In this case, when the winning combination wins, the amount of value corresponding to the winning combination may be given to the player by electrical information.

Further, each process performed by the main control board 500 and the sub control board 502 described above does not necessarily have to be processed in chronological order in the order described in the flowchart, and may include parallel or subroutine processing.

Further, each process performed by the main control board 500 and the sub control board 502 described above does not necessarily have to be processed in chronological order in the order described in the flowchart, and may include parallel or subroutine processing.

<Configuration around the CPU of the main control board>
FIG. 99 is a diagram for explaining the electrical connection around the main CPU 300a. The main CPU 300a includes a CPU core 700 and a bus controller 702. The CPU core 700 controls the bus controller 702 through a bus control signal (Bus Cont) output from the BC terminal, reads data from the main ROM 300b, the main RAM 300c, or the input / output unit 704, or reads data to the main RAM 300c. Write. Here, as the CPU 300a, a microprocessor sold by LETech, which is based on a Z80 series CPU, is used. Here, the main CPU 300a, main, ROM 300b, and main RAM 300c of the pachinko machine will be described, but it goes without saying that the main CPU 500a, main, ROM 500b, and main RAM 500c of the slot machine 400 can be replaced.

For example, when reading data from the main ROM 300b, the main RAM 300c, or the input / output unit 704, the bus controller 702 outputs a 16-bit address (A [16]) signal, and the main ROM 300b, through the decoders 706a, 706b, and 706c, While specifying either the main RAM 300c or the input / output unit 704, the read (RD) signal is controlled to read the data (D [8]) signal from the main ROM 300b, the main RAM 300c, or the input / output unit 704. .. When writing data to the main RAM 300c or the input / output unit 704, the bus controller 702 outputs an address (A [16]) signal and a data (D [8]) signal, and outputs the main RAM 300c through the decoders 706b and 706c. , Or the input / output unit 704 is specified, and the write (WR) signal is controlled to write a data (D [8]) signal to the main RAM 300c or the input / output unit 704.

Here, as will be described later, the address space of the input / output unit 704 is integrated with the address space of the main ROM 300b and the main RAM 300c. Therefore, conventionally, the memory request (MRQ) terminal and the I / O request (IORQ) terminal for outputting a signal for specifying which of the memory and the I / O to access are not provided. By reassigning these two terminals to any other signal, the degree of freedom in program development can be increased.

Further, in the CPU core 700, an interrupt / wait (INT / WAIT) signal that triggers the start of interrupt processing, an unmaskable interrupt (NMI) signal that can execute interrupt processing with the highest priority, and a bus signal are set to high impedance. An external signal such as a transitionable bus request (BUSRQ) signal is also input.

FIG. 100 is a block diagram showing an internal configuration of the CPU core 700. The CPU core 700 includes an external input unit 710, a state control unit 712, a central control unit 714, a register unit 716, and an arithmetic logic unit (ALU) 718. The external input unit 710 receives an external signal and outputs control information based on the external signal to the state control unit 712 and the central control unit 714.

The state control unit 712 manages and transitions the internal state (RESET, instruction fetch, instruction decode, operation, memory load, memory store, HALT, etc.) to determine the operating state of the CPU core 700, and is based on the internal state. The control information is output to the central control unit 714.

The central control unit 714 extracts an operation code (instruction) from the input data (DI [8]) input via the bus controller 702, and controls the ALU718 based on the command decoded by the instruction decoder. Further, the central control unit 714 acquires necessary information from each register of the register unit 716 or updates each register by a decoded command.

The register unit 716 includes selector ports 722a, 722b, 722c, input side bank selector 724, first register bank 726, second register bank 728, output side bank selector 730, address port 732, and individual register 734. In the individual register 734, a 16-bit program counter (PC) indicating the address of the program to be executed next, an 8-bit interrupt (I) register used in the interrupt mode, and an operation code fetch cycle are counted. It includes a bit refresh (R) register and an 8-bit interrupt permission (IFF) register that controls interrupt permission / prohibition.

Further, the register unit 716 generates random numbers for acquiring various random number values (big hit determination random number, hit symbol random number, reach group determination random number, reach mode determination random number, fluctuation pattern random number, hit determination random number) related to the big win lottery. A device (not shown) is associated with each other, and a random number value latched via an input port (FE73h to FE9Ch) is acquired.

The random number generator operates with a system clock (a clock obtained by dividing the external input by two) and generates a random number less than a predetermined maximum value. The random number generator is a random number generator that can set the maximum value of random numbers. As a maximum value setting random number generator, a maximum value of 16 bits can be set, and a maximum value of 4 channels and 8 bits can be set. Eight channels of possible random number generation are prepared. Here, the 16-bit maximum value setting random number generator can be selected with a random number update cycle in the range of 32 to 47 clocks, and the maximum value setting range can be set in the range of 256 to 65535. In addition, the 8-bit maximum value setting random number generator can select the random number update cycle in the range of 16 to 31 clocks, the maximum value setting range can be set in the range of 16 to 255 in 4 channels, and in the other 4 channels. It can be set in the range of 64 to 255. In addition, as a maximum value fixed random number generator that is a random number generator with a fixed maximum value of random numbers, there are 4 channels of random number generation that can set the maximum value of 16 bits, and random number generation that can set the maximum value of 8 bits. 8 channels are prepared. Here, the 16-bit maximum value fixed random number generator has a random number update cycle fixed to 1 clock and a maximum value fixed to 65535. Further, the 8-bit maximum value fixed random number generator has a random number update cycle fixed at 1 clock and a maximum value fixed at 255.

If there are not enough types of random numbers, the random number value obtained from the hardware random number generator (random number generator) is multiplied by a predetermined number in the program and divided to generate another random number (software). Random number generator) is also possible.

FIG. 101 is a diagram illustrating a register configuration. The first register bank 726 and the second register bank 728 both have 8-bit registers (Q, U, A, F, B, C, D, E, H, L) and 16-bit registers (IX, IY, SP) is provided. Further, the registers of the first register bank 726 and the second register bank 728 include a front register and a back register. The CPUs 300a and 500a can access only the front register of the register bank indicated by the register bank designation register RB in the F register, and cannot access the back register.

Of the registers shown in FIG. 101, the Q register is an 8-bit dedicated register with extended specifications for gaming machines. The Q register is fixed at F0h and is used for accessing the main RAM 300c of F000h to F0FFh. The U register is an 8-bit dedicated register with extended specifications for gaming machines. The U register is fixed to FEh and is used for accessing built-in devices (timer, random number generator, external input / output circuit, etc.) connected to the input / output unit 704 of FE00h to FEFFh. The A register is used for arithmetic processing and data transfer. The F register is an 8-bit flag register that holds various calculation results. Here, each bit of the F register is the most significant bit (MSB:) as shown in FIG. 101. From Most Significant Bit) to the least significant bit (LSB: Least Significant Bit), S is a sign flag set to 1 when the operation result is negative, and Z is 1 when all bits are 0 as a result of the operation. It is a zero flag (first zero flag) set to, and TZ is an extended specification for gaming machines that is set to 1 (changes in value) when all bits are 0 by executing a data transfer instruction (LD; load). It is a specific bit flag (second zero flag) and is sometimes called a timer flag. H is a half-carry flag that the programmer cannot participate in, and RB is the current register bank (first register bank 726 = 0, th). 2 Register bank monitor indicating register bank 728 = 1), P / V is a parity overflow flag, N is an addition / subtraction flag that the programmer cannot participate in, and C is a carry or borrow as a result of the operation. It is a carry flag in which 1 is sometimes set. The F register constitutes the A register and the pair register AF.

The B register, C register, D register, E register, H register, and L register are 8-bit general-purpose registers, and each constitutes a 16-bit pair register BC, DE, and HL whose combination is predetermined. .. The IX register and the IY register are 16-bit dedicated registers for index addressing. The SP (stack pointer) register is 16 bits and stores an address that serves as a stack pointer. Q'register, A'register, F'register, B'register, C'register, D'register, E'register, H'register, L'register, IX'register, IY'register are Q register, A register , F register, B register, C register, D register, E register, H register, L register, IX register, IY register. And F'registers make up pair register AF', B'register and C'register make up pair register BC', D'register and E'register make up pair register DE', H'register and L'register. The'registers make up the pair register HL'. The back register can be used by selecting and exchanging either register with the front register by a replacement instruction or the like. On the other hand, the register U and the register SP are single registers having no back register. In this way, the back register functions as a stack area of the front register when the interrupt process occurs.

By the way, as described above, in the main control boards 300 and 500, the main CPU 300a controls the progress of the game in cooperation with the main RAM 300c based on the program stored in the main ROM 300b. The program for executing these functional units is arranged in a predetermined area (used area) of the main ROM 300b and the main RAM 300c.

FIG. 102 is an explanatory diagram showing a memory map. Since the memory map in the pachinko machine has already been described with reference to FIG. 5, the memory map of the slot machine 400 will be described here. A memory space of 0000h to 3FFFh (12kbyte) is allocated to the main ROM 500b, a memory space of F000h to F3FFh (1kbyte) is allocated to the main RAM 500c, and the input / output unit 704 is allocated to the input / output unit 704 of FE00h to FEFFh (256byte). Memory space is allocated. The instruction code of the program is written in assembler language. Here, the program is composed of an instruction code, is read by a computer, and can realize a predetermined process in cooperation with data and a work area.

A used area is allocated to the memory space of the main ROM 500b from 0000h to 1DF3h. The used area is an area for storing programs and data for executing a game control process that controls the progress of the game. Specifically, in the memory space (control area) limited to 0000h to 11FFh (4.5kbyte), the initialization means 600, the betting means 602, the winning type lottery means 604, the reel control means 606, the determination means 608, and the payout control. The instruction code of the program for executing the game control process for controlling the progress of the game by operating the means 610, the game state control means 612, the effect state control means 614, and the command transmission means 616 is stored, and 1200h to 1DF3h (3). Data used in the game control processing program is stored in the memory space (data area) limited to (0.0 kbyte). A comment area is allocated to the memory space of 1E00h to 1FFFh, and a program management area is allocated to the memory space of 3FC0h to 3FFFh. Further, another area (unused area) is allocated to the memory space of 2000h to 3FBFh. As will be described later, another area is an area for storing programs and data that are not defined to be stored in the used area. Specifically, in the memory space of 2000h to 3FBFh, instruction codes and program data of a program that executes a part or all of the game machine test processing and security-related processing that do not affect the progress of the game are stored. It is stored. The test process for a game machine is a test process for the slot machine 400 described in the connection specifications (fourth edition) of the test machine for a rotating game machine. The security-related process is a process for identifying an abnormal state for the purpose of preventing fraud by a third party or finding a defect, and includes, for example, the determination of the backup flag and the execution of the checksum described above. There is no limitation on the storage capacity in another area, and in the example of FIG. 102, it can be freely allocated to a storage area other than the used area, the comment area, and the program management area.

As described above, the main CPU 500a may perform not only game control processing but also game machine test processing and security-related processing. However, the storage capacity of the used area is predetermined. For example, as shown in FIG. 102, the control area is limited to 4.5 kbytes and the data area is limited to 3.0 kbytes. Therefore, if not only the game control process but also the program and data of the game machine test process and the security-related process are arranged in the used area, the storage area for performing the game control process is limited accordingly. Here, the program (program used) and data for executing the game control process must be stored in the used area, but do not affect the progress of the game other than the game control process (not directly related). Programs (separate programs) and data for executing processing (test processing for gaming machines, security-related processing, etc.) can be stored in both the used area and the other area. Therefore, at least a part of the program or data for executing the backup flag determination process and the checksum execution process, which are the processes corresponding to the security-related process, is stored in a storage area different from the used area (other than the used area). It is described in another area that is a part of it.

When the process executed in the used area (here, the game control process) and the process that does not necessarily have to be performed in the used area (here, the security-related process) are mixed in this way, the game control process To store the program (program used) and data for executing the game in the used area, and to execute the process (security-related process) that does not affect the progress of the game other than the game control process, which does not have to be performed in the used area. It is desirable to store the program (separate program) and data in another area. By dividing the storage area into a plurality of storage areas in this way, a margin is created in the storage area (capacity) of the used area by the amount of the program moved to another area. Therefore, the used area can be allocated to the game control process (used program) accordingly.

However, even when the storage area is divided into the used area and another area as described above, the fairness of the gaming machine must be guaranteed. Therefore, the following conditions (1) to (6) are stipulated in order to appropriately divide the roles between the used area and another area while ensuring the fairness of the gaming machine.

Condition (1), programs placed in different areas are used for the purpose of signal output (test processing for gaming machines) and fraud prevention (security-related processing) necessary for testing gaming machines, which impairs the fairness of the game. It should not be (damaged). Condition (2), the control area and the data area, which are different from the used area, should be placed in an explicitly distinguished area. Condition (3), the program to be placed in another area (another program) must be statically called from the program in the used area (used program) and then executed. In addition, the callee address must be clearly stated in the program list at that time. Condition (4), the program to be placed in another area should be modularized for each function, and when called, the contents of all registers used in the used area should be protected. Condition (5), access to RAM in each other's area from the used area or another area can only be referenced, and cannot be updated. Condition (6), it is not possible to call a subroutine in the control area of the used area from the control area of another area. Since a subroutine that performs interrupt processing is provided in the used area, it is necessary to prohibit interrupts when using a control area in another area. In order to properly execute the game control process, the time from the interrupt prohibition to the release of the interrupt prohibition must be within the interval (for example, 1.49 msec) of the interrupt process in the game control process. Must be. Therefore, when a subroutine that uses a control area of another area is called, the total time required for one call is set so as to be within the interrupt processing interval of the game control processing.

Further, a used area is allocated to the memory spaces of F000h to F1FFh of the main RAM 500c. Specifically, the work area for the game control process is allocated to the memory spaces of F000h to F13Fh, and is used for managing variables such as timers, counters, and flags. The stack area of the game control process is allocated to the memory spaces of F1C0h to F1FFh. Further, another area is allocated to the memory spaces of F200h to F3FFh of the main RAM 500c. Specifically, a work area for a part or all of the security-related processes is allocated to the memory space of F210h to F22Fh, and is used for variable management of timers, counters, flags, and the like. A stack area for a part or all of the security-related processes is allocated to the memory spaces of F230h to F246h.

Further, the input / output unit 704 is assigned to the memory spaces of FE00h to FEFFh. Conventionally, in order to access the device corresponding to the input / output unit 704, a 256-byte I / O space is provided independently of the memory space. On the other hand, in the present embodiment, the MRQ and IORQ signals are eliminated, and the memory and the input / output unit 704 are commonly accessed by the RD and WR signals. Further, a U register is provided as hardware for designating the address of the upper 8 bits for accessing the device connected to the input / output unit 704, and the upper address of the 8 bits is specified in advance here. As a result, the I / O space provided independently of the memory space is integrated into the memory space to form one address space, and when the IN instruction and OUT instruction are executed, the input / output unit 704 assigned to the memory space is executed. On the other hand, the upper 8 bits are specified by the U register, and the lower 8 bits are accessible by using the lower 8 bits specified by the operands of the IN instruction and the OUT instruction.

In this embodiment, the LDQ instruction uses the Q register to access the memory space (mainly the data area and work area), and the IN instruction and the OUT instruction use the U register to access the device (timer, random number generator, external input / output). You will be able to write programs to access the I / O of circuits, etc.). With such a configuration, it becomes easy to grasp the program at the time of design. In addition, the memory and I / O specified by the 16-bit address can be accessed by the lower 8-bit operand, and the program capacity can be compressed. Furthermore, by having a Q register, a Q'register, a U register, and a plurality of upper designated registers, the number of replacements due to reuse of the upper register is smaller than when there is only one upper register, and the program capacity is further compressed. be able to.

In the above example, the memory space corresponding to the I / O space is accessed by the IN instruction and the OUT instruction, but the memory space may be directly accessed by the IN instruction and the OUT instruction. This means that, for example, when accessing three 256-byte areas on the memory, the upper 8 bits of each are specified in the Q register, the Q'register, and the U register, and the LDQ instruction and the IN instruction OUT instruction each area. It can be realized by accessing.

<Description of modules and commands>
Hereinafter, for each of the above-mentioned processes (modules), specific instruction codes (command groups) for realizing them will be described in command units mainly used in the module.

<Command "ADDALD">
The BYTESEL module is a byte data selection process, that is, a general-purpose module for offsetting a selected address and reading a 1-byte value stored at the offset address. A general-purpose module is a subroutine of the same processing used in executing a program, and indicates a module that is frequently called by another module. The general-purpose module is often located near the lowest address 0000H on the memory map shown in FIG. 5 (or FIG. 102). This is because by arranging a general-purpose module that is frequently called in the vicinity of 0000H, it can be called by using not only the command "CALL" used for the call but also another command "RST". Here, an example of arranging the BYTESEL module at 0008H on the memory map will be described.

Here, the command "RST" is an address having a low numerical value near 0000H in the memory map, and is any of a plurality of addresses (0008H, 0010H, 0018H, 0020H, 0028H, 0030H, 0038H, 0040H) separated by 8 bytes. Is a command that can be called. The command "RST" has the same execution cycle as the normal command "CALL" used for calling at "4", but the command size of the normal command "CALL" is "3", whereas the command "RST" The command size of is "1". Therefore, the program can be shortened by using the command "RST".

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls a BYTESEL module as a subroutine in an arbitrary process, and executes the BYTESEL module. The BYTESEL module offsets the selected address by a predetermined value and holds the 1-byte value stored in the offset address. In this way, the value corresponding to the offset can be set.

FIG. 103 is a flowchart showing a specific process of the BYTESEL module. Here, as an arbitrary process, a part of the LED_PRC module that executes the LED display setting process shown in S400-31 of FIG. 26 will be described. The numerical value of step S in such a figure will be used only in the description of this figure. Further, in the description of the BYTESEL module, the first register is the HL register and the second register is the A register.

As shown in FIG. 103A, the main CPU 300a sets the offset in the A register (S1) and sets the start address of the address group to be read in the HL register in an arbitrary process (S2). Then, the BYTESEL module is called as a subroutine (S3).

As shown in FIG. 103B, the main CPU 300a updates the HL register by adding the value of the A register to the value of the HL register in the BYTESEL module, and at the same time, a 1-byte value stored at the address indicated by the HL register. To the A register (S4). Subsequently, the main CPU 300a sets a zero flag (first zero flag) according to whether or not the value of the A register is 0 (zero) (S5). Then, the BYTESEL module is terminated and the process returns to the routine one step higher (S6).

104 and 105 are explanatory diagrams for explaining an example of a command for realizing the BYTESEL module. Of these, FIG. 104 (a) shows a command group of arbitrary processing for calling the BYTESEL module, FIG. 104 (b) shows a command group of the BYTESEL module, and FIG. 104 (c) shows program data of the main ROM 300b. The arrangement of the 1-byte data group in. The flowchart shown in FIG. 103 is realized by, for example, the program shown in FIG. 104.

By the command "LDQ A, (LOW R_TZ1_DSP)" on the first line of FIG. 104 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_TZ1_DSP" is set to the lower 1 byte of the address. Then, the value stored at that address (counter value of the special symbol 1 display symbol counter) is read out to the A register. The command on the first line corresponds to step S1 in FIG. 103 (a). By the command "LD HL, D_DSP_TZ" on the second line, the start address "D_DSP_TZ" of the data group of the special symbol display LED output data table to be read out is set in the HL register. The command on the second line corresponds to step S2 in FIG. 103 (a). Then, the BYTESEL module is called as a subroutine by the command "RST BYTESEL" on the third line. The command on the third line corresponds to step S3 in FIG. 103 (a).

The index “BYTESEL:” in the first line of FIG. 104 (b) indicates the start address of the BYTESEL module. The command "ADDWB HL, A" on the second line adds the value of the A register to the value of the HL register and updates the value of the HL register. Then, the command "LDA, (HL)" on the third line reads the 1-byte value stored in the address indicated by the HL register into the A register. The commands on the second and third lines correspond to step S4 in FIG. 103 (b). The command "OR A, A" on the fourth line calculates the logical sum of the value of the A register and the value of the A register. In such a command "OR A, A", the value of the A register does not change because it is the logical sum of the values of the A register. On the other hand, the zero flag (first zero flag and second zero flag) can be changed by the logical sum. That is, in such a BYTESEL module, it is possible to determine whether or not the value of the read A register is zero by the zero flag. The command on the fourth line corresponds to step S5 in FIG. 103 (b). Then, the command "RET" on the fifth line returns to the routine one step higher. The command on the fifth line corresponds to step S6 in FIG. 103 (b).

The table starting from the index "D_DSP_TZ" in FIG. 104 (c) shows, for example, information on the special 1 jackpot symbol and the special 2 jackpot symbol. For example, when the variable "R_TZ1_DSP", that is, the counter value of the special symbol 1 display symbol counter is "02H", as shown in FIG. 105, the tables (2AH, A2H, A8H) described in the program data of the main ROM 300b , 36H ... 5DH, FDH), the value (A8H) stored in the address (third address from the lowest) obtained by adding the value of the A register (for example, 02H) to the selected address (for example, 1250H) is set in the A register. Can be read. As described above, here, it is possible to acquire a desired 1-byte value in a table in which a plurality of values having the same byte length are continuously juxtaposed.

The BYTESEL module is called as a subroutine from a plurality of modules. For example, in the SBCMDST module that executes the subcommand set process shown in step S100-53 of FIG. 23, the LED_PRC module that executes the LED display setting process shown in step S400-31 of FIG. 26, and step S400-33 of FIG. 26. The SOL_SET module that executes the indicated solenoid data setting process (solnel output image composition process), and the MEM_DAT module that executes the hold ball number bit data composition process that is the subroutine of the LED display setting process shown in step S400-31 of FIG. 26. The TDN_PAS module that executes the count switch passing process (second starting port passing process, large winning opening passing process) shown in steps S530 and S540 of FIG. 34, and the special symbol stop symbol display process shown in step S630 of FIG. 43 is executed. The TZ_STP module, the TD_OPN module that executes the large winning opening control process shown in step S720 of FIG. 47, and the normal symbol fluctuation time setting process (normal symbol fluctuation time determination process) shown in step S810-11 of FIG. 52. The FSPNTMR module to be executed, the THPTSEL module that executes the special symbol variation pattern determination process (special symbol variation number determination process) shown in step S612 of FIG. 39, and the preliminary area setting process shown in step S610-17 of FIG. 37 are executed. TRSVSEL module, TENDTMR module that executes the ending time setting process shown in step S730-9 of FIG. 48, symbol offset acquisition process executed in step S630-13 (special electric accessory maximum operation number setting process) of FIG. 43. It is called from the ZUGOFFS module that executes (not shown), the RGETCHK module that executes the acquisition-time effect determination process shown in step S536 of FIG. 33, and the like.

As described above, the total command size of the commands of the BYTESEL module shown in FIG. 104 (b) is 1 byte of the command "ADDWB HL, A" on the 2nd line + 1 byte of the command "LD A, (HL)" on the 3rd line. + 4th line command "OR A, A" 1 byte + 5th line command "RET" 1 byte = 4 bytes, and the total execution cycle is 2nd line 1 cycle + 3rd line 2 cycles + 4th line 1 cycle + 5 lines 3 cycles = 7 cycles. By providing such a BYTESEL module, it is possible to cover with the command "RST BYTESEL" having a command size of 1 byte without performing the byte data selection process in each module described above. Therefore, the command can be shortened and the game control process can be performed. It is possible to secure the capacity of the control area for performing the above.

FIG. 106 is an explanatory diagram for explaining another example of the command for realizing the BYTESEL module. Here, the command group of the BYTESEL module of FIG. 104 (b) is replaced with the command group of the BYTESEL module of FIG. 106 (b), and another command group of arbitrary processing for calling the BYTESEL module of FIG. 104 (a). , And the 1-byte data group in the program data of the main ROM 300b of FIG. 104 (c) is used as it is as FIGS. 106 (a) and 106 (c). Here, as shown in FIGS. 106 (a) and 106 (c), the description of the processing substantially equivalent to that of FIGS. 104 (a) and 104 (c) is omitted, and FIG. 106 (b) is different. Only the processing will be described.

The index “BYTESEL:” in the first line of FIG. 106 (b) indicates the start address of the BYTESEL module. The command "ADDAL D A, (HL)" on the second line adds the value of the A register to the value of the HL register, and the 1-byte value stored at the address indicated by the added HL register is read into the A register. .. The command on the second line corresponds to step S4 in FIG. 103 (b). The command "OR A, A" on the third line calculates the logical sum of the value of the A register and the value of the A register. The zero flag (first zero flag and second zero flag) can be changed by such a logical sum. That is, in the BYTESEL module, it is possible to determine whether or not the value of the read A register is zero by the zero flag. The command on the third line corresponds to step S5 in FIG. 103 (b). Then, the command "RET" on the fourth line returns to the routine one step higher. The command on the fourth line corresponds to step S6 in FIG. 103 (b).

Here, the command "ADDALD A, (HL)" adds the value of the A register to the value of the HL register to update the HL register, and reads the value stored at the address indicated by the HL register into the A register. It is a command. The command size of such a command is "1" and the execution cycle is "3".

The total command size of the BYTESEL module commands in FIG. 106 (b) is the command "ADDALD A, (HL)" on the second line, 1 byte + the command "OR A, A" on the third line, and the command "OR A, A" on the 4th line. "RET" 1 byte = 3 bytes, and the total execution cycle is 3 cycles in the 2nd line + 1 cycle in the 3rd line + 3 cycles in the 4th line = 7 cycles. Therefore, it can be understood that the total command size is reduced by 1 byte as compared with the case of FIG. 104 (b). With such a BYTESEL module, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

Further, in order to be able to understand by comparing FIG. 104 (b) and FIG. 106 (b), the command group that occupied the second line (second and third lines) in FIG. 104 (b) is shown in FIG. 106 (b). In b), it can be represented by one line (second line), and it is possible to reduce the number of commands themselves and the design load.

FIG. 107 is an explanatory diagram for explaining still another example of the command for realizing the BYTESEL module. Here, the command group of the arbitrary process for calling the BYTESEL module of FIG. 106 (a) and the command group of the BYTESEL module of FIG. 106 (b) are replaced with the command group of the arbitrary process of FIG. 107 (a). The other 1-byte data group in the program data of the main ROM 300b of FIG. 106 (c) is used as it is as FIG. 107 (b). Here, the description of the process substantially the same as that of FIG. 106 (c) as shown in FIG. 107 (b) will be omitted, and only the different processes of FIG. 107 (a) will be described.

By the command "LDQ A, (LOW R_TZ1_DSP)" on the first line of FIG. 107 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_TZ1_DSP" is set to the lower 1 byte of the address. Then, the value stored at that address is read into the A register. The command on the first line corresponds to step S1 in FIG. 103 (a). The command "LD HL, D_DSP_TZ" on the second line sets the start address "D_DSP_TZ" of the 1-byte data group to be read from in the HL register. The command on the second line corresponds to step S2 in FIG. 103 (a). Then, by the command "ADDALD A, (HL)" on the third line, the value of the A register is added to the value of the HL register, and the 1-byte value stored at the address indicated by the added HL register is added to the A register. Read out. The command on the third line corresponds to step S4 in FIG. 103 (b).

In the example of FIG. 107, the command “RST BYTESEL” corresponding to step S3 of FIG. 103 (a), the command “OR A, A” corresponding to step S5 of FIG. 103 (b), and the command “OR A, A” of FIG. 103 (b). The command "RET" corresponding to step S6 is omitted.

The total command size of the command group for arbitrary processing in FIG. 107 (a) is the command "LDQ A, (LOW R_TZ1_DSP)" on the first line, 2 bytes + the command "LD HL, D_DSP_TZ" on the second line, 3 bytes + the third line. Command "ADDAL D A, (HL)" 1 byte = 6 bytes, and the total execution cycle is 1st line 2 cycles + 2nd line 3 cycles + 3rd line 3 cycles = 8 cycles.

On the other hand, the total command size of the arbitrary processing of FIGS. 106 (a) and 106 (b) and the command of the BYTESEL module is the command "LDQ A, (LOW R_TZ1_DSP)" on the first line of FIG. 106 (a). 2 bytes + 2nd line command "LD HL, D_DSP_TZ" 3 bytes + 3rd line command "RST BYTESEL" 1 byte + 2nd line command "ADDALD A, (HL)" 1 byte + 3 lines in FIG. 106 (b) The first command "OR A, A" 1 byte + the 4th line command "RET" 1 byte = 9 bytes, and the total execution cycle is the 1st line 2 cycles + 2nd line 3 cycles + 3rd line in FIG. 106 (a). 4 cycles + 3 cycles in the 2nd row of FIG. 106 (b) + 1 cycle in the 3rd row + 3 cycles in the 4th row = 16 cycles. Therefore, in the example of FIG. 107, the total command size is reduced by 3 bytes and the total execution cycle is reduced by 8 cycles as compared with the case of FIG. 106. By embedding the BYTESEL module itself as a command in an arbitrary process in this way, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control process. ..

Further, as can be understood by comparing FIG. 106 and FIG. 107, it is no longer necessary to describe the command group that occupied the 4th line (1st to 4th lines) in FIG. 106 (b) in FIG. 107. Therefore, it is possible to reduce the number of commands themselves and the design load.

Further, the BYTESEL module is a general-purpose module as a target of the command "RST", but by omitting such a general-purpose module, a valuable general-purpose module area can be vacated and other modules can be arranged in the area. .. In this way, resources can be effectively used.

However, in the example of FIG. 107, the first zero flag cannot be changed by omitting the command “OR A, A”. That is, it becomes impossible to determine whether or not the read A register value is zero by the first zero flag. However, if it is not necessary to determine whether or not the value of the A register is zero after the byte data selection process, this function is not required in the first place. Further, the command "ADDAL D A, (HL)" can change the second zero flag only by executing the command. Therefore, when it is necessary to determine whether or not the value of the A register is zero, it is possible to determine whether or not the value of the A register is zero by referring to the second zero flag.

The BYTESEL module is used not only in pachinko machines but also in slot machines, for example, for modules for executing register addition processing.

<Command "ADDALDW">
The WORDSEL module is a word data selection process, that is, a general-purpose module for offsetting a selected address and setting a 2-byte value stored in the offset address. Here, an example of arranging the WORDSEL module at 0018H on the memory map will be described.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls the WORDSEL module as a subroutine in an arbitrary process, and executes the WORDSEL module. In the WORDSEL module, the selected address is offset by a predetermined value, and the 2-byte value stored in the offset address is retained. In this way, the value corresponding to the offset can be set.

FIG. 108 is a flowchart showing a specific process of the WORDSEL module. Here, as an arbitrary process, a part of the FUT_PRC module that executes the normal game management process shown in step S800 of FIG. 51 will be described. The numerical value of step S in such a figure will be used only in the description of this figure. Further, in the description of the WORDSEL module, the first register is the HL register and the second register is the A register.

As shown in FIG. 108A, the main CPU 300a sets the offset in the A register (S1) and sets the start address of the address group to be read in the HL register in an arbitrary process (S2). Then, the WORDSEL module is called as a subroutine (S3).

As shown in FIG. 108 (b), the main CPU 300a adds the value of the A register twice to the value of the HL register or adds the value obtained by doubling the value of the A register to the HL register in the WORDSEL module. It is updated (S4) and the 2-byte value stored in the address indicated by the HL register is read into the HL register (S5). Subsequently, the main CPU 300a sets the value of the L register in the A register (S6). Then, the WORDSEL module is terminated and the routine returns to the next higher routine (S7).

When a 2-byte value is set in the HL register by the WORDSEL module, the main CPU 300a performs various processes using the value of the HL register. For example, here, as shown in FIG. 108 (a), the address indicated by the HL register is called as a subroutine (S8).

FIGS. 109 and 110 are explanatory diagrams for explaining an example of a command for realizing the WORDSEL module. Of these, FIG. 109 (a) shows a command group of arbitrary processing for calling the WORDSEL module, FIG. 109 (b) shows a command group of the WORDSEL module, and FIG. 109 (c) shows program data of the main ROM 300b. The arrangement of the 2-byte data group in. The flowchart shown in FIG. 108 is realized by, for example, the program shown in FIG. 109.

By the command "LDQ A, (LOW R_FUT_PHS)" on the first line of FIG. 109 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_TZ1_DSP" is set to the lower 1 byte of the address. Then, the value stored at that address is read into the A register. The command on the first line corresponds to step S1 in FIG. 108 (a). The command "LD HL, J_JMP_FUT" on the second line sets the start address "J_JMP_FUT" of the 2-byte data group as the read source in the HL register. The command on the second line corresponds to step S2 in FIG. 108 (a). Then, the WORDSEL module is called as a subroutine by the command "RST WORDSEL" on the third line. The command on the third line corresponds to step S3 in FIG. 108 (a).

The index “WORDSEL:” in the first line of FIG. 109 (b) indicates the start address of the WORDSEL module. The command "ADDWB HL, A" on the second line adds the value of the A register to the value of the HL register and updates the HL register. Further, the command "ADDWB HL, A" on the third line adds the value of the A register to the value of the HL register, and updates the HL register. Here, the value of the A register is added to the HL register twice because the value of the read source is a 2-byte value. That is, since the data is assigned to the table in units of 2 bytes, it is necessary to offset the addresses by 2 in order to read the data. Here, by executing the command "ADDWB HL, A" twice, the value of the A register is added to the HL register twice, but instead of the command "ADDWB HL, A" on the second line, It can also be realized by using the command "ADD A, A" to double the value of the A register in advance and then adding it to the HL register. The commands on the second and third lines correspond to step S4 in FIG. 108 (b).

Then, the command "LD HL, (HL)" on the fourth line of FIG. 109 (b) reads the 2-byte value stored at the address indicated by the HL register into the HL register. The command on the fourth line corresponds to step S5 in FIG. 108 (b). The value of the L register among the HL registers is set in the A register by the command "LD A, L" on the fifth line. In this way, the lower 1 byte of the value of the HL register is set in the A register in advance. The command on the fifth line corresponds to step S6 in FIG. 108 (b). Then, the command "RET" on the 6th line returns to the routine one step higher. The command on the sixth line corresponds to step S7 in FIG. 108 (b).

The table starting from the index "J_JMP_FUT" in FIG. 109 (c) shows, for example, an address indicating the state of a normal game. For example, when the variable "R_FUT_PHS", that is, the value of the normal game management phase is "02H", as shown in FIG. 110, the tables (FZ_STA, FZ_SPN, FZ_STP, FD_PRE,) described in the program data of the main ROM 300b, In FD_OPN, FD_END), the value stored in the selected address (for example, 1270H) plus the value obtained by doubling the value of the A register (for example, 04H) (the fifth and sixth addresses from the lowest), here. Then, 0832H (FZ_STP) can be held in the HL register. As described above, here, it is possible to acquire a desired 2-byte value in a table in which a plurality of values having the same byte length are continuously juxtaposed.

Here, FZ_STA indicates the address value of the normal symbol change waiting process shown in step S810 of FIG. 52, FZ_SPN indicates the address value of the normal symbol change process during step S820 of FIG. 53, and FZ_STP indicates the address value of the normal symbol change process. The address value of the normal symbol stop symbol display process shown in step S830 of FIG. 54 is shown, FD_PRE shows the address value of the normal electric accessory winning opening pre-opening process shown in step S840 of FIG. 55, and FD_OPN is the figure. The address value of the ordinary electric accessory winning opening opening control process shown in step S850 of 57 is shown, FD_CLS shows the address value of the ordinary electric accessory winning opening closing effective process shown in step S860 of FIG. 58, and FD_END is , The address value of the normal electric accessory winning opening end wait process shown in step S870 of FIG. 59 is shown.

Subsequently, the acquired 2-byte value, that is, the address value according to the state of the normal game is called by the command "CALL (HL)" on the fourth line of FIG. 109 (a). For example, as described above, when 0832H (FZ_STP) is read into the HL register in the table, the address indicated by "FZ_STP" is called by the command "CALL (HL)", and the normal symbol stop symbol display process is executed. It becomes. The command on the fourth line corresponds to step S8 in FIG. 108 (a).

The WORDSEL module is called as a subroutine from a plurality of modules. For example, a DBLBYTE module that executes a double byte selection process (not shown) executed in the special symbol stop symbol display process shown in step S630 of FIG. 43, and subcommand transmission shown in step S100-65 of FIG. SBC_OUT module that executes processing, DYM_OUT module that executes dynamic port output processing shown in step S400-5 of FIG. 26, FUT_PRC module that executes normal game management processing shown in step S800 of FIG. 51, step S600 of FIG. The TOK_PRC module that executes the special game management process shown in FIG. 44, the TDN_PRC module that executes the special electric accessory game management process in step S700 of FIG. 44, and the STA_PAS module that executes the start port passage process shown in step S530 of FIG. The TDN_PAS module that executes the count switch passing process (large winning opening passing process) shown in step S540 of FIG. 34, the TZ_RGET module that executes the special symbol random number acquisition process shown in step S535 of FIG. 32, and the normal symbol variation time setting process. The FSPNTMR module that executes the FSPNTMR module that executes the normal electric accessory winning opening opening / closing switching process shown in step S841 of FIG. 56, and the TMEMSFT module that executes the special symbol storage area shift process shown in step S610-9 of FIG. 37. , The THPTSEL module that executes the special symbol variation pattern determination process shown in step S612 of FIG. 39, and executes the special symbol variation time setting process shown in step S610-15 of the special symbol variation waiting process shown in step S610 of FIG. 37. TSPNTM module, TSTATMR module that executes the opening time setting process in step S630-15 of FIG. 43, TDNCHG module that executes the large winning opening opening / closing switching process shown in step S711 of FIG. 46, shown in step S730-7 of FIG. The TCLSTMR module that executes the large winning opening closing time setting process, the TENDTMR module that executes the ending time setting process shown in step S730-9 of FIG. 48, and the variation pattern selection 2 process (variation) shown in S612-15 of FIG. 39. HPT_MOD module that executes the pattern number determination process), HPT_PAT module that executes the variation pattern selection 3 process (variation pattern number determination process) shown in S612-15 of FIG. 39, step S810-5 of FIG. The WORDJDG module that executes the word data determination process (not shown) executed in the module, the RGETCHK module that executes the acquisition-time effect determination process shown in step S536 of FIG. 33, and the large module shown in step S720-9 of FIG. 47. It is called from the TEF_SEL module or the like that executes the large winning opening closing valid time selection process, which is a subroutine of the winning opening closing valid time setting process.

As described above, the total command size of the WORDSEL module command shown in FIG. 109 (b) is 1 byte of the command "ADDWB HL, A" on the 2nd line + 1 byte + 4 lines of the command "ADDWB HL, A" on the 3rd line. First command "LD HL, (HL)" 2 bytes + 5th line command "LD A, L" 1 byte + 6th line command "RET" 1 byte = 6 bytes, total execution cycle is 2nd line 1 Cycle + 3rd row 1 cycle + 4th row 4 cycles + 5th row 1 cycle + 6th row 3 cycles = 10 cycles. By providing such a WORDSEL module, it is possible to cover with the command "RST WORDSEL" having a command size of 1 byte without performing the word data selection process in each module described above. Therefore, the command can be shortened and the game control process can be performed. It is possible to secure the capacity of the control area for performing the above.

FIG. 111 is an explanatory diagram for explaining another example of the command for realizing the WORDSEL module. Here, the command group of the WORDSEL module of FIG. 109 (b) is replaced with the command group of the WORDSEL module of FIG. 111 (b), and another command group of arbitrary processing for calling the WORDSEL module of FIG. 109 (a). , And the 2-byte data group in the program data of the main ROM 300b of FIG. 109 (c) is used as it is as FIGS. 111 (a) and 111 (c). Here, as shown in FIGS. 111 (a) and 111 (c), the description of the processing substantially equivalent to that of FIGS. 109 (a) and 109 (c) is omitted, and FIG. 111 (b) is different. Only the processing will be described.

The index “WORDSEL:” in the first line of FIG. 111B indicates the start address of the WORDSEL module. The command "ADDALDW HL, (HL)" on the second line adds the value of the A register to the value of the HL register twice, and the 2-byte value stored at the address indicated by the HL register after addition is added to the HL register. Read out. The command on the second line corresponds to steps S4 and S5 in FIG. 108 (b). The value of the L register among the HL registers is set in the A register by the command "LD A, L" on the third line. In this way, the lower 1 byte of the value of the HL register is set in the A register in advance. The command on the third line corresponds to step S6 in FIG. 108 (b). Then, the command "RET" on the fourth line returns to the routine one step higher. The command on the sixth line corresponds to step S7 in FIG. 108 (b).

Here, the command "ADDALDW HL, (HL)" updates the HL register by adding the value of the A register to the value of the HL register twice, and also adds the value stored in the address indicated by the added HL register. This is a command to read to the HL register. The command size of such a command is "2" and the execution cycle is "6".

Subsequently, the acquired 2-byte value, that is, the address value according to the state of the normal game is called by the command "CALL (HL)" on the fourth line of FIG. 111 (a). The command on the fourth line corresponds to step S8 in FIG. 108 (a).

The total command size of the WORDSEL module command in FIG. 111 (b) is the command "ADDALDW HL, (HL)" on the second line, 2 bytes + the command "LD A, L" on the third line, and the command "LD A, L" on the fourth line. "RET" 1 byte = 4 bytes, and the total execution cycle is 6 cycles in the 2nd line + 1 cycle in the 3rd line + 3 cycles in the 4th line = 10 cycles. Therefore, the total command size is reduced by 2 bytes as compared with the case of FIG. 109 (b). With such a WORDSEL module, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

Further, in order to be able to understand by comparing FIG. 109 (b) with FIG. 111 (b), the command group occupying the third line (second, third, fourth line) in FIG. 109 (b) is shown in FIG. In 111 (b), it can be represented by one line (second line), and it is possible to reduce the number of commands themselves and the design load.

FIG. 112 is an explanatory diagram for explaining still another example of the command for realizing the WORDSEL module. Here, the command group of arbitrary processing for calling the WORDSEL module of FIG. 111 (a) and the command group of the WORDSEL module of FIG. 111 (b) are replaced with the command group of arbitrary processing of FIG. 112 (a). The other 2-byte data group in the program data of the main ROM 300b of FIG. 111 (c) is used as it is as FIG. 112 (b). Here, the description of the process substantially the same as that of FIG. 111 (c) as shown in FIG. 112 (b) will be omitted, and only the different processes of FIG. 112 (a) will be described.

By the command "LDQ A, (LOW R_FUT_PHS)" on the first line of FIG. 112 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_FUT_PHS" is set to the lower 1 byte of the address. Then, the value stored at that address is read into the A register. The command on the first line corresponds to step S1 in FIG. 108 (a). Second line command "LD HL
, J_JMP_FUT "sets the start address" J_JMP_FUT "of the 1-byte data group to be read from in the HL register. The command on the second line corresponds to step S2 in FIG. 108 (a). Then, by the command "ADDALDW HL, (HL)" on the third line, the value of the A register is added twice to the value of the HL register, and the 2-byte value stored in the address indicated by the added HL register is HL. Read to register. The command on the third line corresponds to steps S4 and 5 in FIG. 108 (b). The command "CALL (HL)" on the fourth line calls the acquired 2-byte value, that is, the address value according to the state of the normal game. The command on the fourth line corresponds to step S8 in FIG. 108 (a).

In the example of FIG. 112, the command “RST WORDSEL” corresponding to step S3 of FIG. 108 (a), the command “LD A, L” corresponding to step S6 of FIG. 108 (b), and FIG. 108 (b). The command "RET" corresponding to step S7 is omitted.

The total command size of the arbitrary processing in FIG. 112 (a) and the command of the WORDSEL module is the command "LDQ A, (LOW R_FUT_PHS)" on the first line 2 bytes + the command "LD HL, J_JMP_FUT" 3 bytes + 3 on the second line. The command "ADDALDW HL, (HL)" on the first line is 2 bytes + the command "CALL (HL)" on the 4th line is 2 bytes = 9 bytes, and the total execution cycle is 2 cycles on the 1st line + 3 cycles on the 2nd line + 3rd line. 6 cycles + 4th line 5 cycles = 16 cycles.

On the other hand, the total command size of the arbitrary processing of FIGS. 111 (a) and 111 (b) and the command of the WORDSEL module is the command "LDQ A, (LOW R_FUT_PHS)" on the first line of FIG. 111 (a). 2 bytes + 2nd line command "LD HL, J_JMP_FUT" 3 bytes + 3rd line command "RST WORDSEL" 1 byte + 4th line command "CALL (HL)" 2 bytes + 2nd line of FIG. 111 (b) Command "ADDALDW HL, (HL)" 2 bytes + 3rd line command "LD A, L" 1 byte + 4th line command "RET" 1 byte = 12 bytes, and the total execution cycle is shown in FIG. 111 (a). 1st row 2 cycles + 2nd row 3 cycles + 3rd row 4 cycles + 4th row 5 cycles + 2nd row 6 cycles in FIG. 111 (b) + 3rd row 1 cycle + 4th row 3 cycles = 24 cycles. Therefore, in the example of FIG. 112, the total command size is reduced by 3 bytes and the total execution cycle is reduced by 8 cycles as compared with the case of FIG. 111. By embedding the WORDSEL module itself as a command in an arbitrary process in this way, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control process. ..

Further, in order to be able to understand by comparing FIG. 111 and FIG. 112, it is no longer necessary to describe the command group that occupied the 4th line (1st to 4th lines) in FIG. 111 (b) in FIG. 112. Therefore, it is possible to reduce the number of commands themselves and the design load.

Further, the WORDSEL module is a general-purpose module as a target of the command "RST", but by omitting such a general-purpose module, a valuable general-purpose module area can be vacated and other modules can be arranged in the area. .. In this way, resources can be effectively used.

However, in the example of FIG. 112, the commands “LD A, L” are omitted. Therefore, when it is necessary to set the value of the L register in the A register, it is necessary to add the command "LDA, L" separately. However, since the command "LDA, L" has a command size of "1" and an execution cycle of "1", the effect of adding such a command is small.

The WORDSEL module is transferred not only from the pachinko machine but also from the CAL_MOD module for executing the state-specific module execution process shown in step S3100-21 of FIG. 98 and the CAL_MOD module thereof in the slot machine. It is used in the HID_JUG module for executing this precursor start determination process.

FIG. 113 is an explanatory diagram for explaining the CAL_MOD module. The CAL_MOD module shown in FIG. 113 executes a state-specific module execution process, that is, a module corresponding to a state.

At the stage of executing the CAL_MOD module, the offset value is already held in a predetermined register (for example, the A register). The index “CAL_MOD:” in the first line of FIG. 113A indicates the start address of the CAL_MOD module. The command "LD HL, T_INT_PHASE" on the second line sets the start address "T_INT_PHASE" of the 2-byte data group as the read source in the HL register. The command "ADD A, A" on the third line adds the value of the A register to the value of the A register, and doubles the value of the A register. Here, the value of the A register is doubled because the value of the read source is a 2-byte value. That is, since the data is assigned to the table in units of 2 bytes, it is necessary to offset the addresses by 2 in order to read the data. The command "ADDWB HL, A" on the fourth line adds the value of the A register to the value of the HL register, and updates the HL register.

Then, the command "LD HL, (HL)" on the fifth line of FIG. 113A reads the 2-byte value stored at the address indicated by the HL register into the HL register. The command "JP (HL)" on the 6th line moves to the address indicated by the HL address.

Here, by replacing with the command "ADDALDW", the command group in FIG. 113 (a) can be changed as shown in FIG. 113 (b). The index “CAL_MOD:” in the first line of FIG. 113B indicates the start address of the CAL_MOD module. The command "LD HL, T_INT_PHASE" on the second line sets the start address "T_INT_PHASE" of the 2-byte data group as the read source in the HL register. The command "ADDALDW HL, (HL)" on the third line adds the value of the A register to the value of the HL register twice, and the 2-byte value stored at the address indicated by the HL register after addition is added to the HL register. Read out. Then, the command "JP (HL)" on the fourth line moves to the address indicated by the HL address.

Here, the total command size of the commands of the CAL_MOD module shown in FIG. 113A is the command "LD HL, T_INT_PHASE" on the second line, 3 bytes + the command "ADD A, A" on the third line, 1 byte + 4th line. Command "ADDWB HL, A" 1 byte + 5th line command "LD HL, (HL)" 2 bytes + 6th line command "JP (HL)" 2 bytes = 9 bytes, total execution cycle is 2 lines 3rd row 1 cycle + 3rd row 1 cycle + 4th row 1 cycle + 5th row 4 cycles + 6th row 2 cycles = 11 cycles. On the other hand, the total command size of the commands of the CAL_MOD module shown in FIG. 113 (b) is the command "LD HL, T_INT_PHASE" on the second line 3 bytes + the command "ADDALDW HL, (HL)" on the third line 2 bytes + 4 lines. The second command "JP (HL)" is 2 bytes = 7 bytes, and the total execution cycle is 3 cycles in the 2nd line + 6 cycles in the 3rd line + 2 cycles in the 4th line = 11 cycles. Therefore, by replacing the command group of FIG. 113 (a) with the command group of FIG. 113 (b), the total command size is reduced by 2 bytes. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 114 is an explanatory diagram for explaining the HID_JUG module. The HID_JUG module shown in FIG. 114 executes the present precursor start determination process.

The index “HID_JUG:” in the first line of FIG. 114 (a) indicates the start address of the HID_JUG module. By the command "LDQ A, (LOW_NMD_KND)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_NMD_KND" is set to the lower 1 byte of the address and stored in that address. The value (normal mode type) is read into the A register. The command "LD HL, T_DAT_PGM-2" on the third line sets the start address (value obtained by subtracting 2 from "T_DAT_PGM") of the 2-byte data group to be read from the HL register. The command "ADD A, A" on the fourth line adds the value of the A register to the value of the A register, and doubles the value of the A register. Here, the value of the A register is doubled because the value of the read source is a 2-byte value. That is, since the data is assigned to the table in units of 2 bytes, it is necessary to offset the addresses by 2 in order to read the data. The command "ADDWB HL, A" on the fifth line adds the value of the A register to the value of the HL register, and updates the HL register. Then, the command "LD HL, (HL)" on the sixth line of FIG. 114 (a) reads the 2-byte value stored at the address indicated by the HL register into the HL register.

Here, by replacing with the command "ADDALDW", the command group of FIG. 114 (a) can be changed as shown in FIG. 114 (b). The index “HID_JUG:” in the first line of FIG. 114 (b) indicates the start address of the HID_JUG module. By the command "LDQ A, (LOW_NMD_KND)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_NMD_KND" is set to the lower 1 byte of the address and stored in that address. The value (normal mode type) is read into the A register. The command "LD HL, T_DAT_PGM-2" on the third line sets the start address (value obtained by subtracting 2 from "T_DAT_PGM") of the 2-byte data group to be read from the HL register. The command "ADDALDW HL, (HL)" on the 4th line adds the value of the A register to the value of the HL register twice, and the 2-byte value stored at the address indicated by the HL register after addition is added to the HL register. Read out.

Here, the total command size of the commands of the HID_JUG module shown in FIG. 114 (a) is the command "LDQ A, (LOW_NMD_KND)" on the second line + the command "LD HL, T_DAT_PGM-2" on the third line. 3 bytes + 4th line command "ADD A, A" 1 byte + 5th line command "ADDWB HL, A" 1 byte + 6th line command "LD HL, (HL)" 2 bytes = 9 bytes, total execution The cycle is 2nd row 2 cycles + 3rd row 3 cycles + 4th row 1 cycle + 5th row 1 cycle + 6th row 4 cycles = 11 cycles. On the other hand, the total command size of the commands of the HID_JUG module shown in FIG. 114 (b) is the command "LDQ A, (LOW_NMD_KND)" on the second line + the command "LD HL, T_DAT_PGM-2" 3 on the third line. Bytes + command "ADDALDW HL, (HL)" on the 4th line 2 bytes = 7 bytes, and the total execution cycle is 2 cycles on the 2nd line + 3 cycles on the 3rd line + 6 cycles on the 4th line = 11 cycles. Therefore, by replacing the command group of FIG. 114 (a) with the command group of FIG. 114 (b), the total command size is reduced by 2 bytes. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

<Commands "INLD", "INLDTQR">
The RAMSET module is a general-purpose module for ram set processing, that is, for setting a predetermined value (initial value) in a variable of the main RAM 300c. Here, an example of arranging the RAMSET module at 0020H on the memory map will be described.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls a RAMSET module as a subroutine in an arbitrary process, and executes the RAMSET module. In the RAMSET module, a plurality of 1-byte values described in the program data of the main ROM 300b are transferred to an area holding a plurality of data treated as variables in the work area of the main RAM 300c. In this way, the values of a plurality of variables are set. Here, the number of data to be transferred is simply referred to as the number of data.

FIG. 115 is a flowchart showing a specific process of the RAMSET module. Here, as an arbitrary process, a part of the CPUINIT module that executes the CPU initialization process shown in step S100 of FIG. 22 will be described. The numerical value of step S in such a figure will be used only in the description of this figure. Further, in the description of the RAMSET module, the first register is the B register, the second register is the HL register, the first value is "1", and the second value is "2". Needless to say, the first value and the second value can be set arbitrarily.

As shown in FIG. 115A, the main CPU 300a sets the start address of the 1-byte data group as the transfer source in the HL register in an arbitrary process (S1). Then, the RAMSET module is called as a subroutine (S2).

As shown in FIG. 115 (b), the main CPU 300a reads the 1-byte value stored in the address indicated by the HL register into the B register in the RAMSET module (S3). Such a 1-byte value indicates the number of data. Subsequently, the main CPU 300a is stored in the address specified by the value stored in the address indicated by the value obtained by adding "1" to the HL register, and at the address indicated by the value obtained by adding "2" to the HL register. Transfer the value, add "2" to the value of the HL register, and set the address to be transferred next (S4). Subsequently, the main CPU 300a decrements (subtracts “1”) the value of the B register, and determines whether or not the decrement result is 0 (S5). Here, if the decremented result is not 0 (NO in S5), the process from step S4 is repeated, and if the decremented result is 0 (YES in S5), the RAMSET module is terminated and one step higher. Return to the routine (S6).

116 and 117 are explanatory diagrams for explaining an example of a command for realizing the RAMSET module. Of these, FIG. 116 (a) shows a command group of arbitrary processing for calling the RAMSET module, FIG. 116 (b) shows a command group of the RAMSET module, and FIG. 116 (c) shows program data of the main ROM 300b. The arrangement of the 1-byte data group in the above is shown, and FIG. 116 (d) shows the arrangement of the 1-byte data group in the work area of the main RAM 300c. The flowchart shown in FIG. 115 is realized by, for example, the program shown in FIG. 116.

The start address "D_RAM_RST_INI" of the 1-byte data group as the transfer source is set in the HL register by the command "LD HL, D_RAM_RST_INI" on the first line of FIG. 116 (a). The command on the first line corresponds to step S1 in FIG. 115 (a). Then, the RAMSET module is called as a subroutine by the command "RST RAMSET" on the second line. The command on the second line corresponds to step S2 in FIG. 115 (a).

The index “RAMSET:” in the first line of FIG. 116B indicates the start address of the RAMSET module. The command "LD B, (HL)" on the second line reads the 1-byte value stored at the address indicated by the HL register into the B register. At this time, the address "D_RAM_RST_INI" is set in the HL register as shown in FIG. 116 (a). Therefore, the 1-byte value "(@ D_RAM_RST_INI-D_RAM_RST_INI-1) / 2" on the second line of FIG. 116 (c) is read into the B register as the number of data (number of repeated transfers). Since "@D_RAM_RST_INI" is the address next to the final address of the 1-byte data group that is the transfer source, and D_RAM_RST_INI is the start address of the 1-byte data group that is the transfer source, the value of @D_RAM_RST_INI-D_RAM_RST_INI-1 ( The value of 1-byte value indicating the number of data) becomes the total number of bytes of the 1-byte value, and the number of data is derived by dividing the value by 2, which is the number of combinations of the address and the value. In the example of FIG. 116 (c), the number of data is (11-1) / 2 = 5. The command on the second line of FIG. 116 (b) corresponds to step S3 of FIG. 115 (b).

The index “RAMSET_10:” on the third line of FIG. 116 (b) indicates the start address of the iterative process. Specified by the value stored in the address indicated by the value obtained by adding "1" to the HL register by the command "INLD AC, (HL)" on the 4th line and the command "LDQ (C), A" on the 5th line. The value stored in the address indicated by the value obtained by adding "2" to the HL register is stored in the address to be performed, and "2" is added to the value of the HL register to set the address to be transferred next. The commands on the 4th and 5th lines correspond to step S4 in FIG. 115 (b).

Here, the command "INLD AC, (HL)" stores the value stored in the address indicated by the value obtained by adding "1" to the HL register in the C register, and adds "2" to the HL register. This command updates the value of the HL register by storing the value stored at the address indicated by in the A register and adding "2" to the value of the HL register. The command size of such a command is "2" and the execution cycle is "4".

For example, when the HL register is the value of the address "D_RAM_RST_INI", the lower 1-byte value of the 2-byte variable "R_TZ1_STP" in the third line of FIG. The value of "@DSP_HAZ" in the third line is stored in the A register.

Further, in the command "LDQ (C), A" on the fifth line of FIG. 116 (b), the value of the Q register is set to the upper 1 byte of the address, the value of the C register is set to the lower 1 byte of the address, and the address is set to that address. , A command to store the value of the register. The command size of such a command is "2" and the execution cycle is "3".

For example, the value of the C register, that is, the value of the lower 1 byte of "R_TZ1_STP" is set as the lower 1 byte of the address, and the value of the A register, that is, the value of "@DSP_HAZ" is stored in the address.

Here, in FIGS. 116 (c) and 116 (d), the variable "R_TZ1_STP" indicates the special symbol 1 stop symbol number, the variable "R_TZ2_STP" indicates the special symbol 2 stop symbol number, and the variable "R_TZ1_DSP". Indicates the counter value of the special symbol 1 display symbol counter, the variable "R_TZ2_DSP" indicates the counter value of the special symbol 2 display symbol counter, and the variable "R_EXT_SEC_TMR" indicates the security external signal timer value. The arrangement of the variables shown in FIG. 116 (d) does not have to be continuous as shown in the figure, and may be separated.

Subsequently, the command "DJNZ RAMSET_10" on the sixth line of FIG. 116 (b) decrements (subtracts "1") the value of the B register, and if the decremented result is not 0, it moves to the address "RAMSET_10". If the result of decrementing is 0, the process is moved to the command next to the command. Here, since the number of data is "5", the value of the B register becomes 0 when the process from "RAMSET_10" is repeated 5 times. The command on the sixth line corresponds to step S5 in FIG. 115 (b). Then, the command "RET" on the 7th line returns to the routine one step higher. The command on the seventh line corresponds to step S6 in FIG. 115 (b).

In this way, as shown in FIG. 117, the plurality of 1-byte values (55H, 77H, 66H, 22H, AAH) described in the program data of the main ROM 300b are set to the variables (“R_TZ1_STP” and “R_TZ2_STP”) in the work area of the main RAM 300c. , "R_TZ1_DSP", "R_TZ2_DSP", "R_EXT_SEC_TMR")).

The RAMSET module is called as a subroutine from a plurality of modules. For example, the CPUINIT module that executes the CPU initialization process shown in step S100 of FIG. 22, the SEC_SET module that executes the security setting process, and the state management process (error management process) shown in step S400-21 of FIG. 26 are executed. The STC_PRC module, the FZ_STA module that executes the normal symbol change waiting process shown in step S810 of FIG. 52, the FZ_SPN module that executes the normal symbol change process shown in step S820 of FIG. 53, and the normal symbol shown in step S830 of FIG. The FZ_STP module that executes the symbol stop symbol display process, the FD_PRE module that executes the pre-opening process of the ordinary electric accessory winning opening shown in step S840 of FIG. 55, and the ordinary electric accessory winning opening opening control shown in step S850 of FIG. 57. The FD_OPN module that executes the process, the TZ_STA module that executes the special symbol change waiting process shown in step S610 of FIG. 37, the TZ_SPN module that executes the special symbol change process shown in step S620 of FIG. 41, and the step S630 of FIG. 43. The TZ_STP module that executes the special symbol stop symbol display process shown in FIG. 45, the TD_PRE module that executes the large winning opening pre-opening process shown in step S710 of FIG. 45, and the large winning opening opening control process shown in step S720 of FIG. 47. TD_OPN module to be executed, TD_EFF module to execute the large winning opening closing effective processing shown in step S730 of FIG. 48, TD_END module to execute the large winning opening end wait processing shown in step 740 of FIG. 49, step S630 of FIG. The TOKZERO module that executes the special symbol change waiting state transition process (not shown) executed in the above, the CHGSTS module that executes the number-cutting management process shown in step S613 of FIG. 40, and step S450 of FIG. 27. It is called from the RNK_PRC module or the like that executes setting-related processing.

As described above, the total command size of the RAMSET module commands shown in FIG. 116 (b) is the command "LD B, (HL)" on the second line + the command "INLD AC, (HL)" on the fourth line. 2 bytes + 5th line command "LDQ (C), A" 2 bytes + 6th line command "DJNZ RAMSET_10" 2 bytes + 7th line command "RET" 1 byte = 8 bytes, total execution cycle is 2 lines 2nd cycle + 4th row 4 cycles + 5th row 3 cycles + 6th row 3 cycles (or 2 cycles) + 7th row 3 cycles = 15 cycles (or 14 cycles). The number of cycles in parentheses indicates the execution cycle when the command "DJNZ RAMSET_10" does not move. By providing such a RAMSET module, it is possible to cover with the command "RST RAMSET" having a command size of 1 byte without performing the ram set processing in each module described above, so that the command can be shortened and the game control processing can be performed. It is possible to secure the capacity of the control area for performing.

FIG. 118 is an explanatory diagram for explaining another example of the command for realizing the RAMSET module. Here, the command group of the RAMSET module of FIG. 116 (b) is replaced with the command group of the RAMSET module of FIG. 118 (b), and another command group of arbitrary processing for calling the RAMSET module of FIG. 116 (a). The 1-byte data group in the program data of the main ROM 300b of FIG. 116 (c) and the 1-byte data group of the work area of the main RAM 300c of FIG. 116 (d) are shown in FIGS. 118 (a) and 118 (c). As shown in FIG. 118 (d), it is used as it is. Here, as shown in FIGS. 118 (a), 118 (c), and 118 (d), the processing substantially equivalent to that of FIGS. 116 (a), 116 (c), and 116 (d) is the same. The description will be omitted, and only the different processes shown in FIG. 118 (b) will be described.

The index “RAMSET:” in the first line of FIG. 118 (b) indicates the start address of the RAMSET module. The command "LD B, (HL)" on the second line reads the 1-byte value stored at the address indicated by the HL register into the B register. At this time, the address "D_RAM_RST_INI" is set in the HL register as shown in FIG. 118 (a). Therefore, the 1-byte value "(@ D_RAM_RST_INI-D_RAM_RST_INI-1) / 2" in the second line of FIG. 118 (c) is read into the B register as the number of data. The command on the second line of FIG. 118 (b) corresponds to step S3 of FIG. 115 (b).

By the command "INLDTQR AC, (HL)" on the third line of FIG. 118 (b), the address specified by the value stored in the address indicated by the value obtained by adding "1" to the HL register is added to the HL register. The value stored in the address indicated by the value obtained by adding "2" is transferred, the address to be transferred next is set by adding "2" to the value of the HL register, and the value of the B register is decremented ("1"). The process is repeated until the result of decrementing is 0. The command on the third line corresponds to steps S4 and S5 in FIG. 115 (b).

Here, the command "INLDTQR AC, (HL)" sets the value of the Q register as the upper 1 byte of the address, and sets the value stored in the address indicated by the value obtained by adding "1" to the HL register as the lower 1 of the address. As a byte, transfer the value stored in the address indicated by the value obtained by adding "2" to the HL register to that address, add "2" to the value of the HL register, update the value of the HL register, and B. This command repeats the transfer of values until the register value is decremented (subtracted by "1") and the decremented result becomes 0. The command size of such a command is "2" and the execution cycle is "5".

For example, when the HL register is the value of the address "D_RAM_RST_INI", the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of "R_TZ1_STP" in the third line of FIG. 118 (c) is the value of the address. The lower 1 byte is set, the value of "@DSP_HAZ" in the third line of FIG. 118 (c) is transferred to that address, "2" is added to the value of the HL register, and the value of the B register is decremented ("1"). The transfer is repeated until the decrement result becomes 0, that is, 5 times.

Then, the command "RET" on the fourth line of FIG. 118 (b) returns to the routine one step higher. The command on the fourth line corresponds to step S6 in FIG. 115 (b).

The total command size of the RAMSET module command in FIG. 118 (b) is 1 byte of the command "LD B, (HL)" on the 2nd line + 2 bytes of the command "INLDTQR AC, (HL)" on the 3rd line + 4th line. The command "RET" is 1 byte = 4 bytes, and the total execution cycle is 2 cycles in the 2nd line + 5 cycles in the 3rd line + 3 cycles in the 4th line = 10 cycles. Therefore, as compared with the case of FIG. 116 (b), the total command size is reduced by 4 bytes, and the total execution cycle is also reduced by at least 4 cycles. In particular, in the example of FIG. 116 (b), if the value of the B register in the command "DJNZ RAMSET_10" is 2 or more, the value is 10 cycles (4 cycles in the 4th line + 3 cycles in the 5th line + 3 cycles in the 6th line). Since the total execution cycle increases by the amount multiplied by, the reduction amount of the total execution cycle in FIG. 118 (b) also increases. With such a RAMSET module, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, here, the A register and the C register are not used as compared with the example of FIG. 116. Therefore, the value of the A register and the value of the C register are not unintentionally updated. Further, in the example of FIG. 116, when the A register and the C register are already used, it is necessary to stack and save the values of the A register and the C register. However, here, the A register and the C register are used. Since it does not, stack processing is not required. In this way, resources can be effectively used.

Further, in order to be able to understand by comparing FIG. 116 (b) with FIG. 118 (b), the command group occupying the 4th line (3rd to 6th lines) in FIG. 116 (b) is shown in FIG. In 118 (b), it can be represented by one line (third line), and it is possible to reduce the number of commands themselves and the design load.

The RAMSET module is used not only in pachinko machines but also in slot machines as a TABLEST module (general-purpose module) that executes a table set process for setting a predetermined value (initial value) in a variable of the main RAM 500c. ing.

FIG. 119 is an explanatory diagram for explaining an example of a command for realizing the TABLEST module. Of these, FIG. 119 (a) shows a command group of arbitrary processing for calling the TABLEST module, FIG. 119 (b) shows a command group of the TABLEST module, and FIG. 119 (c) shows program data of the main ROM 500b. 119 (d) shows the arrangement of the 1-byte data group in the work area of the main RAM 500c.

Here, as an arbitrary process, the error wait process shown in step S2200-11 of FIG. 89 and step S2800-39 of FIG. 95, that is, the error display, the warning sound request, and the error recovery wait are executed in the ERRWAY module. Some are listed.

The command "LD HL, T_ERR_RCV" on the first line of FIG. 119 (a) sets the start address "T_ERR_RCV" of the 1-byte data group as the transfer source in the HL register. Then, the TABLEST module is called as a subroutine by the command "RST TABLEST" on the second line.

The index "TABLSET:" in the first line of FIG. 119 (b) indicates the start address of the TABLSET module. The value of the BC register is saved in the stack area by the command "PUSH BC" on the second line. Interruption is prohibited by the command "DI" on the third line.

The command "LD B, (HL)" on the fourth line of FIG. 119 (b) reads the 1-byte value stored at the address indicated by the HL register into the B register. At this time, the address "T_ERR_RCV" is set in the HL register as shown in FIG. 119 (a). Therefore, the 1-byte value "(T_ERR_RCV_-T_ERR_RCV) / 2" in the second line of FIG. 119 (c) is read into the B register as the number of data (number of repeated transfers). Since "T_ERR_RCV_" is the address next to the final address of the 1-byte data group that is the transfer source and T_ERR_RCV is the start address of the 1-byte data group that is the transfer source, the value of T_ERR_RCV_-T_ERR_RCV (indicates the number of data). The value of 1-byte value) becomes the total number of bytes of the 1-byte value, and the number of data is derived by dividing the value by 2, which is the number of combinations of the address and the value. In the example of FIG. 119 (c), the number of data is 9/2 = 4.

The index “TABLEST10:” on the fifth line of FIG. 119 (b) indicates the start address of the iterative process. Specified by the value stored in the address indicated by the value obtained by adding "1" to the HL register by the command "INLD AC, (HL)" on the 6th line and the command "LDQ (C), A" on the 7th line. The value stored in the address indicated by the value obtained by adding "2" to the HL register is stored in the address to be performed, "2" is added to the value of the HL register, and the address to be transferred next is set.

For example, when the HL register is the value of the address "T_ERR_RCV", the lower 1-byte value of the 2-byte variable "_ERR_NUM" in the third line of FIG. 119 (c) is stored in the C register, and the lower 1-byte value of FIG. 119 (c) is stored. The value of "0" in the third line is stored in the A register.

Further, in the command "LDQ (C), A" on the 7th line of FIG. 119 (b), the value of the Q register is set to the upper 1 byte of the address, the value of the C register is set to the lower 1 byte of the address, and the address is set to that address. , A command to store the value of the register.

For example, the value of the C register, that is, the value of the lower 1 byte of "_ERR_NUM" is set as the lower 1 byte of the address, and the value of the A register, that is, the value of "0" is stored in the address.

Here, in FIGS. 119 (c) and 119 (d), the variable "_ERR_NUM" indicates an error number, the variable "_CRE_TMR" indicates a credit button detection timer, and the variable "_CRE_FLG" indicates a credit button detection flag. The variable "_SNS_OLD" indicates the previous state of the medal passing sensor bit. The arrangement of the variables shown in FIG. 119 (d) does not have to be continuous as shown in the figure, and may be separated.

Subsequently, the value of the B register is decremented (subtracted by "1") by the command "DJNZ TABLEST10" on the 8th line of FIG. If the result of decrementing is 0, the process is moved to the command next to the command. Here, since the number of data is "4", the value of the B register becomes 0 when the process from "TABLSET10" is repeated four times.

Interruption is permitted by the command "EI" on the 9th line of FIG. 119 (b). The data saved in the stack area is returned to the BC register by the command "POP BC" on the 10th line. Then, the command "RET" on the 11th line returns to the routine one step higher.

Here, if the command "INLDTQR" is replaced, the command group can be described as follows.

FIG. 120 is an explanatory diagram for explaining another example of the command for realizing the TABLEST module. Here, the command group of the TABLEST module of FIG. 119 (b) is replaced with the command group of the TABLEST module of FIG. 120 (b), and other commands of arbitrary processing for calling the TABLEST module of FIG. 119 (a) are replaced. The group, the 1-byte data group in the program data of the main ROM 500b of FIG. 119 (c), and the 1-byte data group in the work area of the main RAM 500c of FIG. 119 (d) are shown in FIGS. 120 (a) and 120 (c). , FIG. 120 (d) is used as it is. Here, as shown in FIGS. 120 (a), 120 (c), and 120 (d), the processing substantially equivalent to that of FIGS. 119 (a), 119 (c), and 119 (d) is the same. The description will be omitted, and only the different processes shown in FIG. 120 (b) will be described.

The index “TABLSET:” in the first line of FIG. 120 (b) indicates the start address of the TABLSET module. The value of the BC register is saved in the stack area by the command "PUSH BC" on the second line. Interruption is prohibited by the command "DI" on the third line.

The 1-byte value stored at the address indicated by the HL register is read into the B register by the command "LD B, (HL)" on the fourth line of FIG. 120 (b). At this time, the address "T_ERR_RCV" is set in the HL register as shown in FIG. 120 (a). Therefore, the 1-byte value "(T_ERR_RCV_-T_ERR_RCV) / 2" in the second line of FIG. 120 (c) is read into the B register as the number of data (number of repeated transfers). In the example of FIG. 120 (c), the number of data is 4.

By the command "INLDTQR (HL)" on the fifth line of FIG. 120 (b), the address specified by the value stored in the address indicated by the value obtained by adding "1" to the HL register is set to "2" in the HL register. The value stored in the address indicated by the value obtained by adding "" is transferred, the address to be transferred next is set by adding "2" to the value of the HL register, and the value of the B register is decremented (subtracted by "1"). The process is repeated until the decremented result becomes 0.

Subsequently, the interrupt is permitted by the command "EI" on the sixth line of FIG. 120 (b). The data saved in the stack area is returned to the BC register by the command "POP BC" on the 7th line. Then, the command "RET" on the 8th line returns to the routine one step higher.

Here, the total command size of the commands of the TABLEST module shown in FIG. 119 (b) is the command "PUSH BC" on the second line + the command "DI" on the third line + the command "LD B" on the fourth line. , (HL) "1 byte + 6th line command" INLD AC, (HL) "2 bytes + 7th line command" LDQ (C), A "2 bytes + 8th line command" DJNZ TABLEST10 "2 bytes + 9 lines 1st line command "EI" 1 byte + 10th line command "POP BC" 1 byte + 11th line command "RET" 1 byte = 12 bytes, total execution cycle is 2nd line 3 cycles + 3rd line 1 cycle + 4 Line 2 cycles + 6th line 4 cycles + 7th line 3 cycles + 8th line 3 cycles (or 2 cycles) + 9th line 1 cycle + 10th line 3 cycles + 11th line 3 cycles = 23 cycles (or 22 cycles). On the other hand, the total command size of the commands of the TABLEST module shown in FIG. 120 (b) is the command "PUSH BC" on the second line + 1 byte on the third line + the command "DI" on the third line + the command "LD B," on the fourth line. (HL) "1 byte + 5th line command" INLDTQR (HL) "2 bytes + 6th line command" EI "1 byte + 7th line command" POP BC "1 byte + 8th line command" RET "1 byte = 8 bytes, and the total execution cycle is 2nd row 3 cycles + 3rd row 1 cycle + 4th row 2 cycles + 5th row 5 cycles + 6th row 1 cycle + 7th row 3 cycles + 8th row 3 cycles = 18 cycles. .. Therefore, as compared with the case of FIG. 119 (b), the total command size is reduced by 4 bytes, and the total execution cycle is also reduced by at least 5 cycles. In particular, in the example of FIG. 119 (b), if the value of the B register in the command "DJNZ TABLEST10" is 2 or more, the value is 10 cycles (6th line 4 cycles + 7th line 3 cycles + 8th line 3 cycles). Since the total execution cycle is increased by the amount multiplied by, the reduction amount of the total execution cycle in FIG. 120 (b) is also increased. With such a TABLEST module, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, here, the A register and the C register are not used as compared with the example of FIG. 119. Therefore, the value of the A register and the value of the C register are not unintentionally updated. Further, in the example of FIG. 119, when the A register and the C register are already used, it is necessary to stack and save the values of the A register and the C register. However, here, the A register and the C register are used. Since it does not, stack processing is not required. In this way, resources can be effectively used.

Further, in order to be able to understand by comparing FIG. 119 (b) and FIG. 120 (b), the command group that occupied the 4th line (5th to 8th lines) in FIG. 119 (b) is shown in FIG. In 120 (b), it can be represented by one line (fifth line), and it is possible to reduce the number of commands themselves and the design load.

The TABLEST module is called as a subroutine not only from the ERRWAY module but also from a plurality of modules. For example, in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, the module selectively shifts according to the game state and the effect state, and the present precursor processing (AT state = "3") is executed. HID_LOT module to be executed, EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. The FIN_LOT module that executes the above, and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. ), And the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, selectively shifts according to the game state and the effect state, and performs REG processing (AT state = "6". The REG_LOT module that executes () and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91 selectively shift according to the game state and the effect state, and perform BIG processing (AT state = "AT state" 7 ”), the BIG_LOT module that executes the set value switching process shown in step S2020 of FIG. 85, the FGSET UP module that executes the symbol code setting process shown in step S2400 of FIG. 91, and step S2900 of FIG. 96. It is called from the GAMESET module that executes the game transition process shown in FIG. 96, the JCGMSET module that executes the accessory operation symbol display process shown in step S2900-3 of FIG. 96, and the like.

<Commands "DECM", "DECWM">
The BYTEDEC module is a byte counter subtraction process, that is, a general-purpose module for decrementing only one 1-byte variable of the main RAM 300c. In the BYTEDEC module, not only the decrement but also the zero flag and the carry flag are set as a result of the decrement.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls the BYTEDEC module as a subroutine in an arbitrary process, and executes the BYTEDEC module. The BYTEDEC module decrements the 1-byte value held in the main RAM 300c.

FIG. 121 is a flowchart showing a specific process of the BYTEDEC module. Here, as an arbitrary process, a part of the TZ_STP module that executes the special symbol stop symbol display process shown in step S630 of FIG. 43 will be described. The numerical value of step S in such a figure will be used only in the description of this figure. Further, in the description of the BYTEDEC module, the predetermined register is the HL register.

The main CPU 300a executes an arbitrary process as shown in FIG. 121 (a). First, the main CPU 300a sets the address of the variable to be decremented in the HL register (S1). Then, the BYTEDEC module is called as a subroutine (S2).

As shown in FIG. 121B, the main CPU 300a decrements the 1-byte value stored in the address indicated by the HL register by 1 in the BYTEDEC module, and sets the zero flag and the carry flag (S3). Then, the BYTEDEC module is terminated and the process returns to the routine one step higher (S4). Hereinafter, the decrement mode and the setting of the flag will be described in detail.

FIG. 122 is an explanatory diagram for explaining the decrement mode and the setting of the zero flag and the carry flag in the BYTEDEC module. Here, if the value before decrement is 1 or more (1 or 2 or more), the value is decremented by 1 after decrement. However, if it was 0 before the decrement, it does not become -1 after the decrement, but becomes 0. That is, the lower limit value is 0 and does not become a negative value. Such maintenance of 0 may be realized by decrementing and further incrementing or forcibly reading 0 when it was 0 before decrementing, or by not performing decrementing.

Also, if it is 2 or more before decrement, it will be 1 or more after decrement, so the zero flag will not be set and it will be 0, but if it is 1 or 0 before decrement, it will be 0 after decrement, so the zero flag will be set. Becomes 1. Further, in the BYTEDEC module, if the value before the decrement is 1, it becomes 0 after the decrement, and in that case, the carry flag is set to 1. Then, if the value before decrement is 2 or more or 0, the carry flag is not set and the value is set to 0.

Returning to FIG. 121 (a), when the zero flag and the carry flag are set by the BYTEDEC module, the main CPU 300a performs various processes using the values of the flags. For example, here, it is determined that the decrement is not a process of subtracting 1 to make it 0 (S5), and as a result, if it is not a process of subtracting 1 to make it 0 (YES in S5), a special symbol hit. If the process moves to a predetermined address (TZ_STP_10) for performing the flag check process (S6) and subtracts 1 to make it 0 (NO in S5), the next process is executed without moving.

FIG. 123 is an explanatory diagram for explaining an example of a command for realizing the BYTEDEC module. Of these, FIG. 123 (a) shows a command group of arbitrary processing for calling the BYTEDEC module, and FIG. 123 (b) shows a command group of the BYTEDEC module. The flowchart shown in FIG. 121 is realized by, for example, the program shown in FIG. 123.

The command "LDQ HL, LOW R_EXT_HCT" on the first line of FIG. 123 (a) reads the value of the Q register into the H register and the value of the lower 1 byte of the address "R_EXT_HCT" into the L register. The command on the first line corresponds to step S1 in FIG. 121 (a). Then, the BYTEDEC module is called as a subroutine by the command "CALLF BYTEDEC" on the second line. The command on the second line corresponds to step S2 in FIG. 121 (a).

Here, the command "CALLF BYTEDEC" is a command that can call only the range of 0000H to 11FFH in the memory map. The command "CALLF" used for calling has the same execution cycle as the normal command "CALL" with "4", but the command size of the normal command "CALL" is "3", whereas the command size of the command "CALLF" The command size is "2". Therefore, the program can be shortened. Instead of the command "CALLF BYTEDEC", the BYTEDEC module may be called by "RST BYTEDEC" as in the general-purpose module described above. By doing so, the command size can be set to "1".

The index "BYTEDEC:" in the first line of FIG. 123 (b) indicates the start address of the BYTEDEC module. The command "LDA, (HL)" on the second line reads the 1-byte value stored at the address indicated by the HL register into the A register. In such a command "LDA, (HL)", the second zero flag is changed by its execution. Then, the command "RT Z, A" on the third line returns to the routine one step higher if the value of the A register is 0 (if the second zero flag is 1). At this time, if the value of the A register is 0, the zero flag (first zero flag) becomes 1 and the carry flag becomes 0 by the command "RT Z, A". In this way, if the value stored in the address indicated by the HL register is 0, the zero flag = 1 and the carry flag = 0 can be set without performing decrementing.

The command "CP A, 2" on the fourth line of FIG. 123 (b) compares the value of the A register with 2, and if the A register is 2 or more, the carry flag is not set and becomes 0, and if it is 1. , The carry flag is set to 1. The command "CP A, 2" is a command in which a carry flag is set when the A register is less than 2, but at the execution stage of the command "CP A, 2", the value of the A register is 1 or 2 or more. Since it is one of the above (because it is not 0), by setting the carry flag with less than 2, the carry flag is set when the result is 1. In this way, if the value of the A register is 1, the carry flag can be set to 1. The command "DEC (HL)" on the fifth line decrements the 1-byte value stored in the address indicated by the HL register by 1, and updates the value stored in the address indicated by the HL register. Here, if the value stored in the address indicated by the HL register is 2 or more, the decremented value is 1 or more, so the zero flag is not set and becomes 0. If it is 1, the decremented value becomes 0. The zero flag is set and becomes 1. The carry flag does not change depending on the command "DEC (HL)". In this way, if the value stored in the address indicated by the HL register is 2 or more, the zero flag = 0 and the carry flag = 0, and if it is 1, the zero flag = 1 and the carry flag = 1. The commands on the 2nd to 5th lines correspond to step S3 in FIG. 121 (b). Then, the command "RET" on the 6th line returns to the routine one step higher. The command on the sixth line corresponds to step S4 in FIG. 121 (b). In this way, it is possible to decrement the value stored in the address indicated by the HL register by 1 and set the zero flag and the carry flag.

Then, according to the command "JR NC, TZ_STP_10" on the third line of FIG. 123 (a), if the carry flag is 0 (NC), the process is moved to TZ_STP_10. The command on the third line corresponds to steps S5 and 6 in FIG. 121 (a). In this way, processing based on the result of the BYTEDEC module becomes possible.

The BYTEDEC module is called as a subroutine from a plurality of modules. For example, the TMR_NEW module that executes the timer update process shown in step S400-15 of FIG. 26, the STC_PRC module that executes the state management process (error management process) shown in step S400-21 of FIG. 26, and step S630 of FIG. 43. The TZ_STP module that executes the special symbol stop symbol display process shown in FIG. 40, the CHGSTS module that executes the number-cutting management process shown in step S613 of FIG. The TDOVCHK module that executes the large winning opening excess winning monitoring process that is executed after the large winning opening entry ball command is set (S540-3) in the processing), and the state management processing (error management processing) shown in step S400-21 of FIG. ) Is called from the BER_CHK module or the like that executes the base error monitoring process.

As described above, the total command size of the BYTEDEC module commands shown in FIG. 123 (b) is 1 byte of the command "LD A, (HL)" on the 2nd line + 1 byte of the command "RT Z, A" on the 3rd line. + 4th line command "CP A, 2" 2 bytes + 5th line command "DEC (HL)" 1 byte + 6th line command "RET" 1 byte = 6 bytes, total execution cycle is 2nd line 2 Cycle + 3rd row 4 cycles (or 2 cycles) + 4th row 2 cycles + 5th row 4 cycles + 6th row 3 cycles = 15 cycles (or 13 cycles). The number of cycles in parentheses indicates the execution cycle when the command "RT Z, A" does not move to the next higher routine. By providing such a BYTEDEC module, it is possible to cover with the command "CALLF BYTEDEC" having a command size of 2 bytes without performing the byte counter subtraction process in each of the above-mentioned modules. Therefore, the command can be shortened and the game control process can be performed. It is possible to secure the capacity of the control area for performing the above.

FIG. 124 is an explanatory diagram for explaining another example of the command for realizing the BYTEDEC module. Here, the command group of the BYTEDEC module of FIG. 123 (b) is replaced with the command group of the BYTEDEC module of FIG. 124 (b), and another command group of arbitrary processing for calling the BYTEDEC module of FIG. 123 (a). Is used as it is as shown in FIG. 124 (a). Here, the description of the process substantially the same as that of FIG. 123 (a) as shown in FIG. 124 (a) will be omitted, and only the different processes of FIG. 124 (b) will be described.

The index “BYTEDEC:” in the first line of FIG. 124 (b) indicates the start address of the BYTEDEC module. By the command "DECM (HL)" on the second line, if the value stored in the address indicated by the HL register is 1 or more, only 1 is decremented, and if it is 0, 0 is maintained.

Here, the command "DECM (HL)" decrements the 1-byte value stored in the address indicated by the HL register, and if the carry flag is set (if it becomes -1, the address indicated by the HL register). This command forcibly stores 0 in the 1-byte value stored in. Then, if the value stored in the address indicated by the HL register is 1 or more, only 1 is decremented, and if it is 0, 0 is maintained. By executing such a command "DECM (HL)", if the value after decrementing is zero (if the value before decrementing is 1 or 0), the zero flag (first zero flag and second zero flag) is set. If the value before decrement is zero, the carry flag is set and the value is set to 1. The command size of such a command is "2" and the execution cycle is "5".

The command "RET NZ" on the third line of FIG. 124 (b) returns to the routine one step higher if the zero flag is not 1 (if the value after decrement is not zero). Here, since the decrement has already been performed by the command "DECM (HL)", the fact that the zero flag is not 1 indicates that the value before decrement is 2 or more. In that case, the zero flag is not set and becomes 0, and the carry flag is not set and becomes 0. Therefore, it is possible to return to the routine one step higher. In addition, although "NZ" is mentioned here and the first zero flag is referred to, normally, when the first zero flag is changed, the second zero flag also changes, so that "NZ" is used in all processing. Alternatively, "NTZ" can be used.

In the command "DECM (HL)", if the value stored in the address indicated by the HL register before decrementing is 1, it becomes 0 after decrementing, zero flag = 1, carry flag = 0, and 0. If there is, the decrement is not performed and 0 is maintained, and the zero flag = 1 and the carry flag = 1. That is, the carry flag is the opposite of the specifications shown in FIG. 122. Therefore, the carry flag is inverted (1 → 0, 0 → 1) by the command “CCF” on the fourth line of FIG. 124 (b). The zero flag does not change depending on the command "CCF". In this way, if the value stored in the address indicated by the HL register before decrement is 1, the zero flag = 0 and the carry flag = 1, and if it is 0, the zero flag = 1 and the carry flag = 0. .. The commands on the 2nd to 4th lines correspond to step S3 in FIG. 121 (b). Then, the command "RET" on the fifth line returns to the routine one step higher. The command on the fifth line corresponds to step S4 in FIG. 121 (b). In this way, it is possible to decrement the value stored in the address indicated by the HL register by 1 and set the zero flag and the carry flag.

Then, according to the command "JR NC, TZ_STP_10" on the third line of FIG. 124 (a), if the carry flag is 0 (NC), the process is moved to TZ_STP_10. The command on the third line corresponds to steps S5 and 6 in FIG. 121 (a). In this way, processing based on the result of the BYTEDEC module becomes possible.

The total command size of the BYTEDEC module command in FIG. 124 (b) is 2 bytes for the command "DECM (HL)" on the 2nd line + 1 byte for the command "RET NZ" on the 3rd line + 2 bytes for the command "CCF" on the 4th line. +5th line command "RET" 1 byte = 6 bytes, total execution cycle is 2nd line 5 cycles + 3rd line 3 cycles (1 cycle) + 4th line 2 cycles + 6th line 3 cycles = 13 cycles (11 cycles) ). The number of cycles in parentheses indicates the execution cycle when the command "RET NZ" does not move to the next higher routine. Therefore, the total execution cycle is reduced by at least two cycles as compared with the case of FIG. 123 (b). With such a BYTEDEC module, it is possible to secure the capacity of the control area for performing the game control process while reducing the processing load.

Further, here, the A register is not used as compared with the example of FIG. 123. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 123, when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, stack processing is not required. In this way, resources can be effectively used.

Further, in order to be able to understand by comparing FIG. 123 (b) and FIG. 124 (b), the command group that occupied the 4th line (2nd to 5th lines) in FIG. 123 (b) is shown in FIG. In 124 (b), it can be represented by 3 lines (2nd to 4th lines), and it is possible to reduce the number of commands themselves and the design load.

The BYTEDEC module selectively shifts not only to the pachinko machine but also to the slot machine in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91 according to the game state and the effect state. Then, in the REG_LOT module that executes the REG processing (AT state = "6") and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, selectively according to the game state and the effect state. The BIG_LOT module that migrates and executes the BIG processing (AT state = "7"), the JCGMSET module that executes the accessory operation symbol display processing shown in step S2900-3 of FIG. 96, is shown in step S3100 of FIG. 153. In the TMR_IPT module that executes timer interrupt processing and the CAL_MOD module for executing state-specific module execution processing shown in step S3100-21 of FIG. 98, 1 in 4 times according to the timer interrupt processing phase (0 to 3). In the IPT_PA module that selectively shifts times (every 5.96 msec) and executes the terminal board output control process, and in the CAL_MOD module for executing the state-specific module execution process shown in step S3100-21 of FIG. 98, the timer. The IPT_PC module that selectively shifts once every four times (every 5.96 msec) according to the interrupt processing phase (0 to 3) and executes the time monitoring process, and step S3100-21 in FIG. 98. In the CAL_MOD module for executing the module execution processing for each state, the process is selectively shifted once every four times (every 5.96 msec) according to the timer interrupt processing phase (0 to 3), and external signal output control is performed. It is used as a RAM_DEC module (general-purpose module) that executes counter subtraction processing, which is called by the command "RST" from an IPT_PD module or the like that executes processing.

FIG. 125 is an explanatory diagram for explaining the RAM_DEC module. The RAM_DEC module shown in FIG. 125 is a general-purpose module for counter subtraction processing, that is, for decrementing only one 1-byte variable of the main RAM 500c, like the BYTEDEC module described above. In the RAM_DEC module, as in the BYTEDEC module, not only the decrement but also the zero flag and the carry flag shown in FIG. 122 are set as a result of the decrement.

The index “RAM_DEC:” in the first line of FIG. 125 (a) indicates the start address of the RAM_DEC module. The command "LDA, (HL)" on the second line reads the 1-byte value stored at the address indicated by the HL register into the A register. In such a command "LDA, (HL)", the second zero flag is changed by its execution. Then, the command "RT Z, A" on the third line returns to the routine one step higher if the value of the A register is 0 (if the second zero flag is 1). At this time, if the value of the A register is 0, the zero flag (first zero flag) becomes 1 and the carry flag becomes 0 by the command "RT Z, A". In this way, if the value stored in the address indicated by the HL register is 0, the zero flag = 1 and the carry flag = 0 can be set without performing decrementing.

The command "CP A, 2" on the fourth line of FIG. 125 (a) compares the value of the A register with 2, and if the A register is 2 or more, the carry flag is not set and becomes 0, and if it is 1. , The carry flag is set to 1. The command "CP A, 2" is a command in which a carry flag is set when the A register is less than 2, but at the execution stage of the command "CP A, 2", the value of the A register is 1 or 2 or more. Since it is one of the above (because it is not 0), by setting the carry flag with less than 2, the carry flag is set when the result is 1. In this way, if the value of the A register is 1, the carry flag can be set to 1. The command "DEC A" on the fifth line decrements the 1-byte value stored at the address indicated by the A register by 1. The command "LD (HL), A" on the sixth line stores the value of the A register at the address indicated by the HL register. Here, if the value stored in the address indicated by the HL register is 2 or more, the decremented value is 1 or more, so the zero flag is not set and becomes 0. If it is 1, the decremented value becomes 0. The zero flag is set and becomes 1. The carry flag does not change depending on the command "DEC A". In this way, if the value stored in the address indicated by the HL register is 2 or more, the zero flag = 0 and the carry flag = 0, and if it is 1, the zero flag = 1 and the carry flag = 1. Then, the command "RET" on the 7th line returns to the routine one step higher. In this way, it is possible to decrement the value stored in the address indicated by the HL register by 1 and set the zero flag and the carry flag.

Here, by replacing with the command "DECM", the command group of FIG. 125 (a) can be changed as shown in FIG. 125 (b). The index “RAM_DEC:” in the first line of FIG. 125 (b) indicates the start address of the RAM_DEC module. By the command "DECM (HL)" on the second line, if the value stored in the address indicated by the HL register is 1 or more, only 1 is decremented, and if it is 0, 0 is maintained.

The command "RET NZ" on the third line of FIG. 125 (b) returns to the routine one step higher if the zero flag is not 1 (if the value after decrement is not zero). Here, since the decrement has already been performed by the command "DECM (HL)", the fact that the zero flag is not 1 indicates that the value before decrement is 2 or more. In that case, the zero flag is not set and becomes 0, and the carry flag is not set and becomes 0. Therefore, it is possible to return to the routine one step higher. Subsequently, the carry flag is inverted (1 → 0, 0 → 1) by the command “CCF” on the fourth line. The zero flag does not change depending on the command "CCF". In this way, if the value stored in the address indicated by the HL register before decrement is 1, the zero flag = 0 and the carry flag = 1, and if it is 0, the zero flag = 1 and the carry flag = 0. .. Then, the command "RET" on the fifth line returns to the routine one step higher. In this way, it is possible to decrement the value stored in the address indicated by the HL register by 1 and set the zero flag and the carry flag.

Here, the total command size of the command of the RAM_DEC module shown in FIG. 125 (a) is 1 byte of the command "LD A, (HL)" on the 2nd line + 1 byte + 4 of the command "RT Z, A" on the 3rd line. Line command "CP A, 2" 2 bytes + 5th line command "DEC A" 1 byte + 6th line command "LD (HL), A" 1 byte + 7th line command "RET" 1 byte = 7 It becomes a byte, and the total execution cycle is 2nd row 2 cycles + 3rd row 4 cycles (or 2 cycles) + 4th row 2 cycles + 5th row 1 cycle + 6th row 2 cycles + 7th row 3 cycles = 14 cycles (or 12 cycles) ). The number of cycles in parentheses indicates the execution cycle when the command "RT Z, A" does not move to the next higher routine. On the other hand, the total command size of the RAM_DEC module commands shown in FIG. 125 (b) is the command "DECM (HL)" on the second line, 2 bytes + the command "RET NZ" on the third line, and the command "RET NZ" on the fourth line. CCF "2 bytes + 5th line command" RET "1 byte = 6 bytes, and the total execution cycle is 2nd line 5 cycles + 3rd line 3 cycles (1 cycle) + 4th line 2 cycles + 6th line 3 cycles = 13 It becomes a cycle (11 cycles). The number of cycles in parentheses indicates the execution cycle when the command "RET NZ" does not move to the next higher routine. Therefore, by replacing the command group of FIG. 125 (a) with the command group of FIG. 125 (b), the total command size is reduced by 1 byte, and the total execution cycle is reduced by at least one cycle. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

The WORDDEC module is a general-purpose module for word counter subtraction processing, that is, decrementing a 2-byte variable of the main RAM 300c by one. In the WORDDEC module, not only the decrement but also the zero flag and the carry flag are set as a result of the decrement.

The main CPU 300a reads a program from the main ROM 300b, executes the read program, calls the WORDDEC module as a subroutine in an arbitrary process, and executes the WORDDEC module. The WORDDEC module decrements the 2-byte data held in the main RAM 300c.

FIG. 126 is a flowchart showing a specific process of the WORDDEC module. Here, as an arbitrary process, a part of the NHI_CHK module that executes the winning frequency abnormality error determination process, which is a subroutine of the state management process (error management process) shown in step S400-21 of FIG. 26, will be described. The numerical value of step S in such a figure will be used only in the description of this figure. Further, in the description of the WORDDEC module, the predetermined register is the HL register.

The main CPU 300a executes an arbitrary process as shown in FIG. 126 (a). First, the main CPU 300a sets the address of the variable to be decremented in the HL register (S1). Then, the WORDDEC module is called as a subroutine (S2).

As shown in FIG. 126 (b), the main CPU 300a decrements the 2-byte value stored in the address indicated by the HL register by 1 and sets the zero flag and the carry flag in the WORDDEC module (S3). Then, the WORDDEC module is terminated and the subroutine returns to the next higher subroutine (S4). The decrement mode and the setting of the flag are described in FIG. 122 as in the BYTEDEC module.

When the zero flag and the carry flag are set by the WORDDEC module, the main CPU 300a performs various processes using the value of the HL register. For example, here, it is determined that the decrement result is not 0 (S5), and as a result, if it is not 0 (YES in S5), it returns from the subroutine (S6), and if it is 0 (NO in S5). Perform the next process without moving.

FIG. 127 is an explanatory diagram for explaining an example of a command for realizing the WORDDEC module. Of these, FIG. 127 (a) shows a command group for arbitrary processing, and FIG. 127 (b) shows a command group for the WORDDEC module. The flowchart shown in FIG. 126 is realized by, for example, the program shown in FIG. 127.

The command "POP HL" on the first line of FIG. 127 (a) restores the address value of the winning frequency abnormality error monitoring timer saved in the stack area to the HL register. The command on the first line corresponds to step S1 in FIG. 126 (a). Then, the WORDDEC module is called as a subroutine by the command "CALLF WORDDEC" on the second line. The command on the second line corresponds to step S2 in FIG. 126 (a).

The index “WORDDEC:” in the first line of FIG. 127 (b) indicates the start address of the WORDDEC module. The command "JTW Z, (HL), WORDDEC_99" on the second line determines whether the 2-byte value stored in the address indicated by the HL register is 0, and if it is 0, it moves to the index "WORDDEC_99:". .. In such a command "JTW Z, (HL), WORDDEC_99", the zero flag is changed by its execution. For example, if the value stored in the address indicated by the HL register is 0, the zero flag becomes 1 and the carry flag becomes 0. If the value stored in the address indicated by the HL register is 0, the index "WORDDEC_99:" is moved to, and the command "RET" on the 7th line returns to the subroutine one step higher. In this way, if the value stored in the address indicated by the HL register is 0, the zero flag = 1 and the carry flag = 0 can be set without performing decrementing.

The command "DECW (HL)" on the third line of FIG. 127 (b) decrements the 2-byte value stored at the address indicated by the HL register by 1, and the value stored at the address indicated by the HL register. To update. Here, if the value stored in the address indicated by the HL register is 2 or more, the decremented value is 1 or more, so the zero flag is not set and becomes 0. If it is 1, the decremented value becomes 0. The zero flag (second zero flag) is set and becomes 1. Then, the command "RET NTZ" on the fourth line returns to the subroutine one step higher if the zero flag is not 1. Here, "NTZ" is used because the command "DECW (HL)" changes the second zero flag but does not change the first zero flag. Note that neither the zero flag nor the carry flag changes depending on the command "RET NTZ". At this time, the zero flag does not become 1 (returns to the subroutine one step higher) when the value stored in the address indicated by the HL register before decrement is 2 or more. Therefore, if the value before decrement is 2 or more, the zero flag = 0 and the carry flag = 0, so that there is no problem in returning to the subroutine one step higher.

If the zero flag is 1, the value stored in the address indicated by the HL register before decrementing is 1, the zero flag = 1 and the carry flag = 0. That is, the carry flag is the opposite of the specifications shown in FIG. 122. Therefore, the carry flag is forcibly set to 1 by the command "SCF" on the 5th line. In this way, if the value stored in the address indicated by the HL register before decrement is 1, the zero flag = 1 and the carry flag = 1. The zero flag does not change depending on the command "SCF". The commands on the 2nd to 6th lines correspond to step S3 in FIG. 126 (b). Then, the command "RET" on the 7th line returns to the subroutine one step higher. The command on the seventh line corresponds to step S4 in FIG. 126 (b). In this way, it is possible to decrement the value stored in the address indicated by the HL register by 1 and set the zero flag and the carry flag.

Subsequently, if the zero flag (second zero flag) is not 1 (if it is 0) by the command "RET NTZ" on the third line of FIG. 127 (a), the subroutine returns to the next higher subroutine. The command on the third line corresponds to steps S5 and 6 in FIG. 126 (a). In this way, processing based on the result of the WORDDEC module becomes possible.

The WORDDEC module is called as a subroutine from a plurality of modules. For example, the TMR_NEW module that executes the timer update process shown in step S400-15 of FIG. 26, the TZ_SPN module that executes the special symbol change processing shown in step S620 of FIG. 41, and step S400-21 of FIG. 26 are shown. It is called from the NHI_CHK module or the like that executes the winning frequency abnormality error determination process, which is a subroutine of the state management process (error management process).

As described above, the total command size of the commands of the WORDDEC module shown in FIG. 127 (b) is the command "JTW Z, (HL), WORDDEC_99" on the second line + the command "DECW (HL)" on the third line. 2 bytes + 4th line command "RET NTZ" 1 byte + 5th line command "SCF" 2 bytes + 7th line command "RET" 1 byte = 9 bytes, and the total execution cycle is 2nd line 6 cycles (or 5 cycles) + 3rd row 7 cycles + 4th row 3 cycles (or 1 cycle) + 5th row 2 cycles + 7th row 3 cycles = 21 cycles (or 18 cycles). The number of cycles in parentheses indicates the execution cycle when the command "JTW Z, (HL), WORDDEC_99" or the command "RET NTZ" does not move to the next higher routine. By providing such a WORDDEC module, it is possible to cover with the command "CALLF WORDDEC" having a command size of 2 bytes without performing the word counter subtraction process in each of the above-mentioned modules. Therefore, the command can be shortened and the game control process can be performed. It is possible to secure the capacity of the control area for performing the above.

FIG. 128 is an explanatory diagram for explaining another example of the command for realizing the WORDDEC module. Here, the command group of the WORDDEC module of FIG. 127 (b) is replaced with the command group of the WORDDEC module of FIG. 128 (b), and another command group of arbitrary processing for calling the WORDDEC module of FIG. 127 (a). Is used as it is as shown in FIG. 128 (a). Here, the description of the process substantially the same as that of FIG. 127 (a) as shown in FIG. 128 (a) will be omitted, and only the different processes of FIG. 128 (b) will be described.

The index “WORDDEC:” in the first line of FIG. 128 (b) indicates the start address of the WORDDEC module. By the command "DECWM (HL)" on the second line, if the value stored in the address indicated by the HL register is 1 or more, only 1 is decremented, and if it is 0, 0 is maintained.

Here, the command "DECWM (HL)" decrements the 2-byte value stored in the address indicated by the HL register, and if the carry flag is set (-1), the address indicated by the HL register. This command forcibly stores 0 in the 2-byte value stored in. Then, if the value stored in the address indicated by the HL register is 1 or more, only 1 is decremented, and if it is 0, 0 is maintained. By executing such a command "DECWM (HL)", if the value after decrement is zero (if the value before decrement is 1 or 0), the zero flag (first zero flag and second zero flag) is set. If the value before decrement is zero, the carry flag is set and the value is set to 1. The command size of such a command is "2" and the execution cycle is "7".

The command "RET NZ" on the third line of FIG. 128 (b) returns to the subroutine one step higher if the zero flag is not 1 (if the value after decrement is not zero). Here, since the decrement has already been performed by the command "DECWM (HL)", the fact that the zero flag is not 1 indicates that the value before decrement is 2 or more. In that case, the zero flag is not set and becomes 0, and the carry flag is not set and becomes 0. Therefore, it is possible to return to the subroutine one step higher.

In the command "DECWM (HL)", if the value stored in the address indicated by the HL register before decrementing is 1, it becomes 0 after decrementing, zero flag = 1, carry flag = 0, and 0. If there is, the decrement is not performed and 0 is maintained, and the zero flag = 1 and the carry flag = 1. That is, the carry flag is the opposite of the specifications shown in FIG. 122. Therefore, the carry flag is inverted (1 → 0, 0 → 1) by the command “CCF” on the fourth line of FIG. 128 (b). The zero flag does not change depending on the command "CCF". In this way, if the value stored in the address indicated by the HL register before decrement is 1, the zero flag = 1 and the carry flag = 1, and if it is 0, the zero flag = 1 and the carry flag = 0. .. The commands on the 2nd to 4th lines correspond to step S3 in FIG. 126 (b). Then, the command "RET" on the fifth line returns to the subroutine one step higher. The command on the fifth line corresponds to step S4 in FIG. 126 (b). In this way, it is possible to decrement the value stored in the address indicated by the HL register by 1 and set the zero flag and the carry flag.

Subsequently, if the zero flag (second zero flag) is not 1 (if it is 0) by the command "RET NTZ" on the third line of FIG. 128 (a), the subroutine returns to the next higher subroutine. The command on the third line corresponds to steps S5 and 6 in FIG. 126 (a). In this way, processing based on the result of the WORDDEC module becomes possible.

The total command size of the WORDDEC module command in FIG. 128 (b) is 2 bytes in the 2nd line + 1 byte in the 3rd line + 2 bytes in the 4th line + 1 byte in the 5th line = 6 bytes, and the total execution cycle is 7 in the second line. Cycle + 3rd row 3 cycles (1 cycle) + 4th row 2 cycles + 6th row 3 cycles = 15 cycles (13 cycles). The number of cycles in parentheses indicates the execution cycle when the command "RET NZ" does not move to the next higher routine. Therefore, the total command size is reduced by 3 bytes and the total execution cycle is reduced by at least 6 cycles as compared with the case of FIG. 127 (b). With such a WORDDEC module, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

Further, in order to be able to understand by comparing FIG. 127 (b) and FIG. 128 (b), the command group that occupied the 5th line (2nd to 6th lines) in FIG. 127 (b) is shown in FIG. In 128 (b), it can be represented by 3 lines (2nd to 4th lines), and it is possible to reduce the number of commands themselves and the design load.

<Command "RCP">
FIG. 129 is an explanatory diagram for explaining an example of the process of returning from the subroutine. The command "CP A, n" in FIG. 129 (a) is a command for comparing the value of the A register with the predetermined value n. When A = n, the zero flag is set to 1 and A <n. In that case, the carry flag is set to 1. The command size of the command "CP A, n" is "2", and the execution cycle is "2".

The command "RET cc" in FIG. 129 (a) refers to the zero flag or the carry flag, and if the target flag is 1, it is a command to return to the routine one step higher from the subroutine. The command size of such a command "RET cc" is "1" and the execution cycle is "3" (or "1"). The number of cycles in parentheses indicates the execution cycle when the command "RET cc" does not move to the next higher routine (does not return from the subroutine).

Here, as shown in FIG. 129 (a), the value of the A register is compared with the predetermined value n by the command “CP A, n” on the first line, and the command “RET cc” on the second line is used. , Whether or not to return from the subroutine is determined according to the comparison result. Here, the two commands can be combined (replaced) into one command "RCP cc, A, n" as shown in FIG. 129 (b).

The command "RCP cc, A, n" in FIG. 129 (b) is a command that compares the value of the A register with a predetermined value n and returns from the subroutine to the routine one step higher according to the comparison result. .. The command size of such a command "RCP cc, A, n" is "2", and the execution cycle is "5" (or "3"). The number of cycles in parentheses indicates the execution cycle when the command "RCP cc, A, n" does not move to the next higher routine.

Here, the total command size of the command group shown in FIG. 129 (a) is 2 bytes of the command "CP A, n" on the first line + 1 byte = 3 bytes of "RET cc" on the second line, and the total execution cycle. 1st row 2 cycles + 2nd row 3 cycles (1 cycle) = 5 cycles (3 cycles). On the other hand, the command size of the command "RCP cc, A, n" shown in FIG. 129 (b) is 2 bytes, and the execution cycle is 5 cycles (3 cycles). Therefore, by replacing the command group of FIG. 129 (a) with the command of FIG. 129 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process. Hereinafter, a plurality of modules capable of such replacement will be described.

FIG. 130 is an explanatory diagram for explaining the PY_CMDA module. The PY_CMDA module shown in FIG. 130 executes the main command analysis process shown in steps S100-63 in FIG. 23, that is, a process of analyzing the main command and detecting an abnormality of the main command.

The index “PY_CMDA:” in the first line of FIG. 130 (a) indicates the start address of the PY_CMDA module. By the command "LDQ A, (LOW R_BCR_BUF)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_BCR_BUF" that stores the buffer value of the main command is set to the lower 1 byte of the address. It is set to 1 byte, and the value (main command) stored at that address is read into the A register.

Then, when the buffer is cleared and the payout start designation command confirmation process is executed, as the received data confirmation process, the command "SUBA, @BCR_PAY_CLR" on the third line of FIG. The fixed value indicated by "BCR_PAY_CLR", here, 20H is subtracted. Then, the subtracted A register value is compared with 0CH by the command "CP A, 00CH" on the 4th line. Here, it is confirmed that the main command is included in the range of 20H to 2BH. That is, if the value of the A register is less than 20H, the value of the A register becomes a negative value by the command "SUB A, @BCR_PAY_CLR", and the value of the A register becomes larger than 0CH when viewed as a 1-byte value. Therefore, if the subtracted A register value is less than 0CH, the carry flag is set to 1 by the command "CP A, 00CH". Then, according to "RET NC" on the 5th line, if the carry flag is not 1, the routine returns to the next higher routine. If the carry flag is 1 (if it is included in the range of 20H to 2BH), the payout error specification command set process and the payout radio wave error flag setting process are executed, and the process returns to the routine one step higher.

Here, by replacing FIG. 129, the command group of FIG. 130 (a) can be changed as shown in FIG. 130 (b). The index “PY_CMDA:” in the first line of FIG. 130 (b) indicates the start address of the PY_CMDA module. By the command "LDQ A, (LOW R_BCR_BUF)" on the first line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_BCR_BUF" that stores the buffer value of the main command is set to the lower 1 byte of the address. It is set to 1 byte, and the value (main command) stored at that address is read into the A register.

Then, when the buffer is cleared and the predetermined process for the payout start designation command is executed, the command "SUBA, @BCR_PAY_CLR" on the third line of FIG. 130 (b) indicates from the value of the A register as "@BCR_PAY_CLR". The fixed value, here 20H, is subtracted. The command "RCP NC, A, 00CH" on the 4th line compares the subtracted A register value with 0CH, and if the carry flag is not 1, returns to the routine one step higher. Here, it is confirmed that the main command is included in the range of 20H to 2BH, and if it is not within that range, the routine returns to the next higher routine without further processing. If the carry flag is 1, the payout error specification command set process and the payout radio wave error flag setting process are executed, and the process returns to the routine one step higher.

Here, the total command size of the command group shown in FIG. 130 (a) is the command "LDQ A, (LOW R_BCR_BUF)" on the second line 2 bytes + the command "SUB A, @BCR_PAY_CLR" on the third line 2 bytes + 4 The command "CP A, 00CH" on the line is 2 bytes + "RET NC" on the 5th line is 1 byte = 7 bytes, and the total execution cycle is 3 cycles on the 2nd line + 2 cycles on the 3rd line + 2 cycles on the 4th line + 5th line. 3 cycles (1 cycle) = 10 cycles (8 cycles). On the other hand, the total command size of the command group shown in FIG. 130 (b) is the command "LDQ A, (LOW R_BCR_BUF)" on the second line, 2 bytes + the command "SUB A, @BCR_PAY_CLR" on the third line, 2 bytes + 4 lines. The first command "RCP NC, A, 00CH" is 2 bytes = 6 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 2 cycles + 4th line 5 cycles (3 cycles) = 10 cycles (8 cycles). Become. Therefore, by replacing the command group of FIG. 130 (a) with the command group of FIG. 130 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 131 is an explanatory diagram for explaining the GAT_PAS module. The GAT_PAS module shown in FIG. 131 adds the number of normal symbol reserved balls according to the gate switch passing process (gate passing process) shown in step S510 of FIG. 29, that is, the passing of the winning balls by the gate detection switch 124s. , Ordinary symbol processing is executed.

As the storage count check process, the index “GAT_PAS:” in the first line of FIG. 131 (a) indicates the start address of the GAT_PAS module. By the command "LDQ DE, LOW R_FZ_MEM" on the second line, the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address "R_FZ_MEM" is set to the lower 1 byte of the address, and the value is stored at that address. The 2-byte value (the address of the normal symbol reserved ball count counter) is read into the DE register. The command "LDA, (DE)" on the third line reads the value (counter value of the normal symbol hold ball count counter) stored in the address indicated by the DE register (that is, R_FZ_MEM) into the A register.

Then, the command "CP A, @FZ_MEM_MAX" on the fourth line of FIG. 131 (a) compares the value of the A register with the fixed value "@FZ_MEM_MAX", here "4". That is, if the value of the A register is less than 4, the carry flag is set to 1. Then, according to "RET NC" on the 5th line, if the carry flag is not 1, the routine returns to the next higher routine. That is, if the counter value of the normal symbol reserved ball number counter is 4 or more, the normal symbol reserved ball number counter is not counted any more, so the GAT_PAS module is terminated. If the carry flag is 1, the random number value acquisition process, the storage number addition process, the hit determination random number acquisition process, the transfer destination address calculation process, and the storage area storage process are executed, and the process returns to the routine one step higher. ..

Here, by replacing FIG. 129, the command group of FIG. 131 (a) can be changed as shown in FIG. 131 (b). The index “GAT_PAS:” in the first line of FIG. 131 (b) indicates the start address of the GAT_PAS module. By the command "LDQ DE, LOW R_FZ_MEM" on the first line, the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address "R_FZ_MEM" is set to the lower 1 byte of the address, and the value is stored at that address. The 2-byte value (the address of the normal symbol reserved ball count counter) is read into the DE register. The command "LDA, (DE)" on the third line reads the value (counter value of the normal symbol hold ball count counter) stored in the address indicated by the DE register (that is, R_FZ_MEM) into the A register.

Then, the command "RCP NC, A, @ FZ_MEM_MAX" on the fourth line of FIG. 131 (b) compares the value of the A register with @ FZ_MEM_MAX, and if the value of the A register is @ FZ_MEM_MAX or more, one step is performed. Return to the routine above. That is, if the counter value of the normal symbol reserved ball number counter is 4 or more, the normal symbol reserved ball number counter is not counted any more, so the GAT_PAS module is terminated. If the carry flag is 1, the storage number addition process, the winning random number acquisition process, the transfer destination address calculation process, and the storage area storage process are executed, and the process returns to the routine one step higher.

Here, the total command size of the command group shown in FIG. 131 (a) is the command "LDQ DE, LOW R_FZ_MEM" on the second line 2 bytes + the command "LD A, (DE)" on the third line 1 byte + 4 lines. The first command "CP A, @ FZ_MEM_MAX" 2 bytes + 5th line "RET NC" 1 byte = 6 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 2 cycles + 4th line 2 cycles + 5th line 3 cycles (1 cycle) = 9 cycles (7 cycles). On the other hand, the total command size of the command group shown in FIG. 131 (b) is 2 bytes of the command "LDQ DE, LOW R_FZ_MEM" on the 2nd line + 1 byte + 4th line of the command "LD A, (DE)" on the 3rd line. Command "RCP NC, A, @ FZ_MEM_MAX" 2 bytes = 5 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 2 cycles + 4th line 5 cycles (3 cycles) = 9 cycles (7 cycles). Become. Therefore, by replacing the command group shown in FIG. 131 (a) with the command group shown in FIG. 131 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 132 is an explanatory diagram for explaining the TDN_PAS module. The TDN_PAS module shown in FIG. 132 executes the count switch passing process (large winning opening passing process) shown in step S540 of FIG. 34, that is, the process of managing the winning of the large winning opening based on the count switch determination value. ..

The index “TDN_PAS:” in the first line of FIG. 132 (a) indicates the start address of the TDN_PAS module. Then, when the count switch determination value confirmation process, the special electric accessory continuous operation count determination process, the large winning opening winning designation command set processing, and the large winning opening excessive winning monitoring process are executed, two lines are executed as the special electric accessory operation check process. By the eye command "LDQ A, (LOW R_TDN_PHS)", the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address "R_TDN_PHS" is set to the lower 1 byte of the address, and the value is stored at that address. The value (special electric accessory game management phase) is read into the A register.

By the command "JCP Z, A, @ TD_OPN_BHT, TDN_PAS_10" on the third line of FIG. 132 (a), the value of the A register and the fixed value "@TD_OPN_BHT" are compared with 2, here, and if the results are equal, Move to the address "TDN_PAS_10". In this way, if the value of the A register is the value specified for the jackpot opening control state (special electric accessory game management phase is 02H), the subsequent processing is omitted and the movement is performed to the index "TDN_PAS_10:" on the sixth line. be able to. By the command "CP A, @ TD_OPN_SHT" on the 4th line, the value of the A register is compared with the fixed value "@TD_OPN_SHT" indicating the small hit big winning opening control state specified value, here, 6 and if they are equal. (Special electric accessory game management phase is 06H), the zero flag is set and it becomes 1. Then, according to "RET NZ" on the 5th line, if the zero flag is not 1, the routine returns to the next higher routine. That is, if the value of the A register is not the big hit big winning opening open control state specified value and the small hit big winning opening open control state specified value, the TDN_PAS module is terminated. If the zero flag is 1, the special electric accessory winning ball count process, the special electric illegal winning detection condition confirmation process, and the special electric illegal winning error error processing are executed to return to the routine one step higher.

Here, by replacing FIG. 129, the command group of FIG. 132 (a) can be changed as shown in FIG. 132 (b). The index “TDN_PAS:” in the first line of FIG. 132 (b) indicates the start address of the TDN_PAS module. Then, when the count switch determination value confirmation process, the special electric accessory continuous operation count determination process, the large winning opening winning designation command set processing, and the large winning opening excessive winning monitoring process are executed, the command "LDQ A, (LOW) on the second line is executed. According to "R_TDN_PHS)", the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address "R_TDN_PHS" is set to the lower 1 byte of the address, and the value stored in that address (special electric accessory game management phase). ) Is read into the A register.

By the command "JCP Z, A, @ TD_OPN_BHT, TDN_PAS_10" on the third line of FIG. 132 (b), the value of the A register and the fixed value "@TD_OPN_BHT" are compared with 2, here, and if the results are equal, Move to the address "TDN_PAS_10". In this way, if the value of the A register is the value specified in the jackpot opening control state, it is possible to skip the subsequent processing and move to the index "TDN_PAS_10:" on the fifth line. The command "RCP NZ, A, @ TD_OPN_SHT" on the 4th line compares the value of the A register with the fixed value "@TD_OPN_SHT" indicating the small hit big winning opening control state specified value, here 6, If they are equal, the routine returns to the next higher routine. That is, if the value of the A register is not the big hit big winning opening open control state specified value and the small hit big winning opening open control state specified value, the TDN_PAS module is terminated. If the zero flag is 0, the special electric accessory winning ball count process, the special electric illegal winning detection condition confirmation process, and the special electric illegal winning error error processing are executed to return to the routine one step higher.

Here, the total command size of the command group shown in FIG. 132 (a) is the command "LDQ A, (LOW R_TDN_PHS)" on the second line + the command "JCP Z, A, @ TD_OPN_BHT, TDN_PAS_10 on the third line. 3 bytes + 4th line command "CP A, @ TD_OPN_SHT" 2 bytes + 5th line "RET NZ" 1 byte = 8 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 4 cycles (or 3) Cycle) + 4th row 2 cycles + 5th row 3 cycles (1 cycle) = 12 cycles (9 cycles). On the other hand, the total command size of the command group shown in FIG. 132 (b) is the command "LDQ A, (LOW R_TDN_PHS)" on the second line + the command "JCP Z, A, @ TD_OPN_BHT, TDN_PAS_10" on the third line. 3 bytes + 4th line command "RCP NZ, A, @ TD_OPN_SHT" 2 bytes = 7 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 4 cycles (or 3 cycles) + 4th line 5 cycles (3) Cycle) = 12 cycles (9 cycles). Therefore, by replacing the command group of FIG. 132 (a) with the command group of FIG. 132 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 133 is an explanatory diagram for explaining the FD_OPN module. The FD_OPN module shown in FIG. 133 has the ordinary electric accessory winning opening opening control process shown in step 850 of FIG. 57, that is, the opening / closing process of the first variable starting port 120B with respect to the number of winnings and the operating time of the ordinary electric accessory. To execute.

The index “FD_OPN:” in the first line of FIG. 133 (a) indicates the start address of the FD_OPN module. Then, when the normal electric accessory winning opening opening / closing operation switching process is executed, the value of the Q register is set to the upper 1 byte of the address by the command "LDQ A, (LOW R_FDN_CNT)" on the second line as the specified winning number confirmation process. , The value of the lower 1 byte of the address "R_FDN_CNT" is set to the lower 1 byte of the address, and the value stored at that address (counter value of the normal electric accessory winning ball count counter) is read into the A register.

By the command "CP A, @ FDN_CNT" on the third line of FIG. 133 (a), the fixed value "@ FDN_CNT" indicating the value of the A register and the maximum number of winning balls in the winning opening related to the ordinary electric accessory, here. Then, it is compared with 8, and if it is less than 8, the carry flag is set and it becomes 1. Then, if the carry flag is 1 by "RET C" on the 4th line, the routine returns to the next higher routine. That is, if the value of the A register is less than the number of winning balls in the winning opening related to the ordinary electric accessory, the FD_OPN module is terminated. If the carry flag is 0, the normal electric accessory operation end setting process is executed, and the process returns to the routine one step higher.

Here, by replacing FIG. 129, the command group of FIG. 133 (a) can be changed as shown in FIG. 133 (b). The index “FD_OPN:” in the first line of FIG. 133 (b) indicates the start address of the FD_OPN module. Then, when the normal electric accessory winning opening opening / closing operation switching process is executed, the value of the Q register is set to the upper 1 byte of the address by the command "LDQ A, (LOW R_FDN_CNT)" on the second line as the specified winning number confirmation process. , The value of the lower 1 byte of the address "R_FDN_CNT" is set to the lower 1 byte of the address, and the value stored at that address (counter value of the normal electric accessory winning ball count counter) is read into the A register.

The fixed value "@FDN_CNT" indicating the value of the A register and the maximum number of winning balls in the winning opening related to the ordinary electric accessory by the command "RCP C, A, @ FDN_CNT" on the third line of FIG. 133 (b). , Here, the comparison with 8 is performed, and if it is less than 8, the routine returns to the next higher routine. That is, if the value of the A register is less than the number of winning balls in the winning opening related to the ordinary electric accessory, the FD_OPN module is terminated. If the carry flag is 0, the normal electric accessory operation end setting process is executed, and the process returns to the routine one step higher.

Here, the total command size of the command group shown in FIG. 133 (a) is the command "LDQ A, (LOW R_FDN_CNT)" on the second line 2 bytes + the command "CP A, @ FDN_CNT" on the third line 2 bytes + 4 The "RET C" in the first line is 1 byte = 5 bytes, and the total execution cycle is 3 cycles in the 2nd line + 2 cycles in the 3rd line + 3 cycles (1 cycle) in the 4th line = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 133 (b) is 2 bytes of the command "LDQ A, (LOW R_FDN_CNT)" on the 2nd line + 2 bytes of the command "RCP C, A, @ FDN_CNT" on the 3rd line. = 4 bytes, and the total execution cycle is 3 cycles in the 2nd row + 5 cycles (3 cycles) in the 3rd row = 8 cycles (6 cycles). Therefore, by replacing the command group of FIG. 133 (a) with the command group of FIG. 133 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 134 is an explanatory diagram for explaining the TZ_STA module. The TZ_STA module shown in FIG. 134 executes the special symbol change waiting process shown in step S610 of FIG. 37, that is, the special symbol change preparatory process based on the number of special symbol reserved balls.

The index “TZ_STA:” in the first line of FIG. 134 (a) indicates the start address of the TZ_STA module. Then, when the special symbol reserved ball number confirmation process is executed, the general-purpose module DATSEL module is called by the command "RST DATSEL" on the second line as the process non-target special figure state confirmation process, and the selection result of the control data is obtained. It is stored in the A register.

By the command "CP A, @TZ_BHT" on the third line of FIG. 134 (a), the value of the A register is compared with the fixed value "@TZ_BHT" indicating the special symbol jackpot information, here, 01H is compared with 01H. If they are equal, the zero flag is set and becomes 1. Then, if the zero flag is 1 by "RET Z" on the 4th line, the routine returns to the next higher routine. That is, if the jackpot is being confirmed, the TZ_STA module is terminated. The command "CP A, @ TZ_SHT" on the 5th line compares the value of the A register with the fixed value "@TZ_SHT" indicating special symbol small hit information, here 02H, and if it is equal to 02H, the zero flag is set. Stand up and become 1. Then, if the zero flag is 1 by "RET Z" on the 6th line, the routine returns to the next higher routine. That is, if the small hit is being confirmed, the TZ_STA module is terminated. If the zero flag is not 1, the special symbol change start setting process, the number of times command set process, and the special symbol change preparation process are executed to return to the routine one step higher.

Here, by replacing FIG. 129, the command group of FIG. 134 (a) can be changed as shown in FIG. 134 (b). The index “TZ_STA:” in the first line of FIG. 134 (b) indicates the start address of the TZ_STA module. Then, when the special symbol reserved ball number confirmation process is executed, the DATASEL module is called by the command "RST DATSEL" on the second line as the process non-target special figure state confirmation process, and the selection result of the control data is stored in the A register. Will be done.

The command "RCP Z, A, @ TZ_BHT" on the third line of FIG. 134 (b) compares the value of the A register with the fixed value "@TZ_BHT" indicating the special symbol jackpot information, here 01H. If it is equal to 01H, it returns to the routine one step higher. That is, if the jackpot is being confirmed, the TZ_STA module is terminated. The command "RCP Z, A, @ TZ_SHT" on the 4th line compares the value of the A register with the fixed value "@TZ_SHT" indicating special symbol small hit information, here 02H, and if it is equal to 02H, Return to the routine one step higher. That is, if the small hit is being confirmed, the TZ_STA module is terminated. If the zero flag is not 1, the special symbol change start setting process, the number of times command set process, and the special symbol change preparation process are executed to return to the routine one step higher.

Here, the total command size of the command group shown in FIG. 134 (a) is the command "RST DATSEL" on the second line + 1 byte + the command "CP A, @ TZ_BHT" on the third line 2 bytes + "RET" on the fourth line. "Z" 1 byte + 5th line command "CP A, @ TZ_SHT" 2 bytes + 6th line "RET Z" 1 byte = 7 bytes, and the total execution cycle is 2nd line 4 cycles + 3rd line 2 cycles + 4 lines 3rd cycle (1 cycle) + 5th row 2 cycles + 6th row 3 cycles (1 cycle) = 14 cycles (10 cycles). On the other hand, the total command size of the command group shown in FIG. 134 (b) is the command "RST DATSEL" on the second line + the command "RCP Z, A, @ TZ_BHT" on the third line 2 bytes + the command on the fourth line. "RCP Z, A, @ TZ_SHT" 2 bytes = 5 bytes, and the total execution cycle is 4 cycles in the 2nd line + 5 cycles in the 3rd line (3 cycles) + 5 cycles in the 4th line (3 cycles) = 14 cycles (10 cycles). ). Therefore, by replacing the command group of FIG. 134 (a) with the command group of FIG. 134 (b), the total command size is reduced by 2 bytes. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 135 is an explanatory diagram for explaining the TZ_RGET module. The TZ_RGET module shown in FIG. 135 performs the special symbol random number acquisition process shown in step S535 of FIG. 32, that is, the random number value is input to the register, and the register is disturbed in the transfer buffer only when the number of reserved balls is not the upper limit. Executes the process of storing numerical values.

The index “TZ_RGET:” in the first line of FIG. 135 (a) indicates the start address of the TZ_RGET module. The jackpot determination random number acquisition process is executed, and the value stored at the address indicated by the DE register (target special symbol hold ball) is executed by the command "LDA, (DE)" on the second line as the special symbol hold ball number update process. The counter value of the number counter) is read into the A register. It is assumed that when the TZ_RGET module is called, the address indicating the counter value of the target special symbol reserved ball number counter is stored in the DE register in advance.

Then, by the command "CP A, @TZ_MEM_MAX" on the third line of FIG. 135 (a), the value of the A register and the fixed value "@TZ_MEM_MAX" indicating the upper limit of the number of special symbol reserved balls, here, "4" Compare with. That is, if the value of the A register is less than 4, the carry flag is set to 1. Then, according to "RET NC" on the 4th line, if the carry flag is not 1, the routine returns to the next higher routine. That is, if the counter value of the target special symbol reserved ball number counter is 4 or more, the target special symbol reserved ball number counter is not counted any more, so the TZ_RGET module is terminated. If the carry flag is 1, the variation pattern random number acquisition process, the reach group determination random number acquisition process, the reach mode determination random number acquisition process, the transfer destination address calculation process, the storage area storage process, the acquisition time effect determination process, and the special feature. Figure Hold specification Command set processing is executed to return to the routine one step higher.

Here, by replacing FIG. 129, the command group of FIG. 135 (a) can be changed as shown in FIG. 135 (b). The index “TZ_RGET:” in the first line of FIG. 135 (b) indicates the start address of the TZ_RGET module. The jackpot determination random number acquisition process is executed, and the value (target) stored in the address (that is, R_FZ_MEM) indicated by the DE register by the command "LDA, (DE)" on the second line as the special symbol reserved ball number update process. The counter value of the special symbol reserved ball count counter) is read into the A register.

Then, by the command "RCP NC, A, @ TZ_MEM_MAX" on the third line of FIG. 135 (b), the value of the A register and the fixed value "@TZ_MEM_MAX" indicating the upper limit of the number of special symbol reserved balls, here, " 4 ”is compared, and if the value of the A register is 4 or more, the routine returns to the next higher routine. That is, if the counter value of the target special symbol reserved ball number counter is 4 or more, the target special symbol reserved ball number counter is not counted any more, so the TZ_RGET module is terminated. If the value of the A register is less than 4, the variation pattern random number acquisition process, reach group determination random number acquisition process, reach mode determination random number acquisition process, transfer destination address calculation process, storage area storage process, acquisition time effect determination process, Then, the special figure hold designation command set processing is executed, and the process returns to the routine one step higher.

Here, the total command size of the command group shown in FIG. 135 (a) is the command "LD A, (DE)" on the second line, 1 byte + the command "CP A, @TZ_MEM_MAX" on the third line, 2 bytes + 4 lines. The first "RET NC" is 1 byte = 4 bytes, and the total execution cycle is 2 cycles in the 2nd line + 2 cycles in the 3rd line + 3 cycles in the 4th line (1 cycle) = 7 cycles (5 cycles). On the other hand, the total command size of the command group shown in FIG. 135 (b) is 1 byte of the command "LD A, (DE)" on the 2nd line + 2 bytes of the command "RCP NC, A, @ TZ_MEM_MAX" on the 3rd line = It becomes 3 bytes, and the total execution cycle is 2 cycles in the 2nd row + 5 cycles (3 cycles) in the 3rd row = 7 cycles (5 cycles). Therefore, by replacing the command group shown in FIG. 135 (a) with the command group shown in FIG. 135 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 136 is an explanatory diagram for explaining the TRSVSEL module. The TRSVSEL module shown in FIG. 136 executes the preliminary area setting process shown in step S610-17 of FIG. 37, that is, the special symbol probability state and the special symbol state preliminary setting process after confirming the special symbol hit.

The index “TRSVSEL:” in the first line of FIG. 136 (a) indicates the start address of the TRSVSEL module. Then, when the state offset check flag setting process is executed, the DATSEL module, which is a general-purpose module, is called by the command "RST DATSEL" on the second line as a special symbol hit confirmation process, and the selection result of the control data is stored in the A register. Will be done.

By the command "CP A, @TZ_BHT" on the third line of FIG. 136 (a), the value of the A register is compared with the fixed value "@TZ_BHT" indicating the special symbol jackpot information, here, 01H is compared with 01H. If they are equal, the zero flag is set and becomes 1. Then, according to "RET NZ" on the 4th line, if the zero flag is not 1, the routine returns to the next higher routine. That is, if the jackpot is not confirmed, the TRSVSEL module is terminated. If the zero flag is 1, the special symbol probability state preliminary setting process and the special symbol state preliminary setting process are executed, and the process returns to the routine one step higher.

Here, by replacing FIG. 129, the command group of FIG. 136 (a) can be changed as shown in FIG. 136 (b). The index “TRSVSEL:” in the first line of FIG. 136 (b) indicates the start address of the TRSVSEL module. Then, when the state offset check flag setting process is executed, the DATASEL module is called by the command "RST DATSEL" on the second line as the special symbol hit confirmation process, and the selection result of the control data is stored in the A register.

By the command "RCP NZ, A, @ TZ_BHT" on the third line of FIG. 136 (b), the value of the A register is compared with the fixed value "@TZ_BHT" indicating the special symbol jackpot information, here, 01H. If it is not equal to 01H, the routine returns to the next higher routine. That is, if the jackpot is not confirmed, the TRSVSEL module is terminated. If it is equal to 01H, the special symbol probability state preliminary setting process and the special symbol state preliminary setting process are executed, and the process returns to the routine one step higher.

Here, the total command size of the command group shown in FIG. 136 (a) is the command "RST DATSEL" on the second line + 1 byte + the command "CP A, @ TZ_BHT" on the third line 2 bytes + "RET" on the fourth line. NZ ”1 byte = 4 bytes, and the total execution cycle is 2nd row 4 cycles + 3rd row 2 cycles + 4th row 3 cycles (1 cycle) = 9 cycles (7 cycles). On the other hand, the total command size of the command group shown in FIG. 136 (b) is 1 byte of the command "RST DATSEL" on the 2nd line + 2 bytes = 3 bytes of the command "RCP NZ, A, @ TZ_BHT" on the 3rd line. The total execution cycle is 4 cycles in the 2nd row + 5 cycles (3 cycles) in the 3rd row = 9 cycles (7 cycles). Therefore, by replacing the command group of FIG. 136 (a) with the command group of FIG. 136 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 137 is an explanatory diagram for explaining the TDOVCHK module. The TDOVCHK module shown in FIG. 137 is executed after setting the large winning opening entry command (S540-5) in the count switch passing processing (large winning opening passing processing) shown in step S540 of FIG. 34. The winning monitoring process, that is, the update processing of the large winning opening winning ball number counter and the large winning opening excess winning number counter is executed.

The index "TDOVCHK:" in the first line of FIG. 137 (a) indicates the start address of the TDOVCHK module. Then, as the special electric accessory game management phase confirmation process, the value of the Q register is set to the upper 1 byte of the address by the command "LDQ A, (LOW R_TDN_PHS)" on the second line, and the lower 1 byte of the address "R_TDN_PHS" is set. The value is set to the lower 1 byte of the address, and the value stored in the address (special electric accessory game management phase) is read into the A register.

By the command "JCP NC, A, @ TD_PRE_SHT, TDOVCHK_10" on the third line of FIG. If there is, move to the address "TDVCHK_10". In this way, if the value of the A register is a specified value after the specified value before opening the small hit big winning opening, the subsequent processing can be omitted and the movement can be moved to the index "TDVCHK_10" on the sixth line. The command "CP A, @ TD_OPN_BHT" on the 4th line compares the value of the A register with the fixed value "@TD_OPN_BHT" indicating the jackpot jackpot opening control state specified value, here, 2, and if they are equal, The zero flag is set and becomes 1. Then, if the zero flag is 1 by "RET Z" on the 5th line, the routine returns to the next higher routine. That is, if the value of the A register is the value specified in the jackpot opening control state, the TDOVCHK module is terminated. If the zero flag is not 1, the large winning opening winning ball number counter update processing, the large winning opening excess winning number counter update processing, and the large winning opening excessive winning error error processing are executed to move up one step. return.

Here, by replacing FIG. 129, the command group of FIG. 137 (a) can be changed as shown in FIG. 137 (b). The index "TDOVCHK:" in the first line of FIG. 137 (b) indicates the start address of the TDOVCHK module. Then, as the special electric accessory game management phase confirmation process, the value of the Q register is set to the upper 1 byte of the address by the command "LDQ A, (LOW R_TDN_PHS)" on the second line, and the lower 1 byte of the address "R_TDN_PHS" is set. The value is set to the lower 1 byte of the address, and the value stored in the address (special electric accessory game management phase) is read into the A register.

By the command "JCP NC, A, @ TD_PRE_SHT, TDOVCHK_10" on the third line of FIG. If there is, move to the address "TDVCHK_10". In this way, if the value of the A register is a specified value after the specified value before the opening of the small hit big winning opening, the subsequent processing can be omitted and the movement can be moved to the index "TDVCHK_10" on the fifth line. By the command "RCP Z, A, @ TD_OPN_BHT" on the 4th line, compare the value of the A register with the fixed value "@TD_OPN_BHT" indicating the jackpot jackpot opening control state specified value, here, and equalize. If so, it returns to the routine one step higher. That is, if the value of the A register is the value specified in the jackpot opening control state, the TDOVCHK module is terminated. If the zero flag is not 1, the large winning opening winning ball number counter update processing, the large winning opening excess winning number counter update processing, and the large winning opening excessive winning error error processing are executed to move up one step. return.

Here, the total command size of the command group shown in FIG. 137 (a) is the command "LDQ A, (LOW R_TDN_PHS)" on the second line + the command "JCP NC, A, @ TD_PRE_SHT, TDOVCHK_10 on the third line. 3 bytes + 4th line command "CP A, @ TD_OPN_BHT" 2 bytes + 5th line "RET Z" 1 byte = 8 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 4 cycles (or 3) Cycle) + 4th row 2 cycles + 5th row 3 cycles (1 cycle) = 12 cycles (9 cycles). On the other hand, the total command size of the command group shown in FIG. 137 (b) is the command "LDQ A, (LOW R_TDN_PHS)" on the second line + the command "JCP NC, A, @ TD_PRE_SHT, TDOVCHK_10" on the third line. 3 bytes + 4th line command "RCP Z, A, @ TD_OPN_BHT" 2 bytes = 7 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 4 cycles (or 3 cycles) + 4th line 5 cycles (3) Cycle) = 12 cycles (9 cycles). Therefore, by replacing the command group of FIG. 137 (a) with the command group of FIG. 137 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 138 is an explanatory diagram for explaining the BER_CHK module. The BER_CHK module shown in FIG. 138 is a base abnormality error monitoring process which is a subroutine of the state management process (error management process) shown in step S400-21 of FIG. 26, that is, a process of monitoring the counter value of the base error confirmation counter. To execute.

As the outswitch confirmation process, the index “BER_CHK:” in the first line of FIG. 138 (a) indicates the start address of the BER_CHK module. The command "LDQ HL, LOW R_BAS_CNT" on the second line reads the value of the Q register into the H register and the value of the lower 1 byte of the address "R_BAS_CNT" into the L register. The command "LDA, (HL)" on the third line reads the value (counter value of the base abnormality confirmation counter) stored in the address indicated by the HL register (that is, R_BAS_CNT) into the A register.

Then, the command "CP A, @BAS_CHK_CNT" on the fourth line of FIG. 138 (a) compares the value of the A register with the fixed value "@BAS_CHK_CNT" indicating the number of base abnormality detection balls, which is 20 here. That is, if the value of the A register is less than 20, the carry flag is set to 1. Then, if the carry flag is 1 by "RET C" on the 5th line, the routine returns to the next higher routine. That is, if the counter value of the base abnormality confirmation counter is less than 20, the BER_CHK module is terminated. If the carry flag is not 1, the security setting process is executed and the process returns to the routine one step higher.

Here, by replacing FIG. 129, the command group of FIG. 138 (a) can be changed as shown in FIG. 138 (b). The index “BER_CHK:” in the first line of FIG. 138 (b) indicates the start address of the BER_CHK module. The command "LDQ HL, LOW R_BAS_CNT" on the second line reads the value of the Q register into the H register, and reads the value of the lower 1 byte of the address "R_BAS_CNT" (the address that stores the base error confirmation counter) into the L register. The command "LDA, (HL)" on the third line reads the value (counter value of the base abnormality confirmation counter) stored in the address indicated by the HL register (that is, R_BAS_CNT) into the A register.

Then, the command "RCP C, A, @ BAS_CHK_CNT" on the fourth line of FIG. 138 (b) compares the value of the A register with the fixed value "@BAS_CHK_CNT" indicating the number of base abnormality detected balls. If the value of the A register is less than 20, the routine returns to the next higher routine. If the value of the A register is 20 or more, the security setting process is executed and the process returns to the routine one step higher.

Here, the total command size of the command group shown in FIG. 138 (a) is the command "LDQ HL, LOW R_BAS_CNT" on the second line + 2 bytes + the command "LD A, (HL)" on the third line + 4 lines. The first command "CP A, @ BAS_CHK_CNT" 2 bytes + 5th line "RET C" 1 byte = 6 bytes, and the total execution cycle is 2 cycles on the 2nd line + 2 cycles on the 3rd line + 2 cycles on the 4th line + 5 lines. 3 cycles (1 cycle) = 9 cycles (7 cycles). On the other hand, the total command size of the command group shown in FIG. 138 (b) is the command "LDQ HL, LOW R_BAS_CNT" on the second line, 2 bytes + the command "LDA, (HL)" on the third line, 1 byte + 4th line. Command "RCP C, A, @ BAS_CHK_CNT" 2 bytes = 5 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 2 cycles + 4th line 5 cycles (3 cycles) = 9 cycles (7 cycles). Become. Therefore, by replacing the command group of FIG. 138 (a) with the command group of FIG. 138 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 139 is an explanatory diagram for explaining the TEF_SEL module. The TEF_SEL module shown in FIG. 139 is a subroutine of the large winning opening closing effective time setting process shown in step S720-9 of FIG. 47, that is, the large winning opening closing effective time selection process, that is, until the large winning opening is closed. Executes the process of selecting the valid time from the table.

The index “TEF_SEL:” in the first line of FIG. 139 (a) indicates the start address of the TEF_SEL module. Then, as the large winning opening closing effective time data selection process, the value of the Q register is set to the upper 1 byte of the address by the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the second line, and the lower 1 byte of the address "R_ZUG_CHK_FIX" is set. The value is set to the lower 1 byte of the address, and the value (special symbol determination flag) stored at that address is read into the A register.

The command "CP A, @ ZUG_SML1" on the third line of FIG. 139 (a) compares the value of the A register with the fixed value "@ ZUG_SML1" indicating the small hit symbol 1 designated data, here 07H. If it is less than 07H, the carry flag is set and becomes 1. Then, according to "RET NC" on the 4th line, if the carry flag is not 1, the routine returns to the next higher routine. That is, if the value of the A register is equal to or greater than the small hit symbol 1 designated data, the TEF_SEL module is terminated. If the carry flag is 1, the word data selection process is executed and the process returns to the routine one step higher.

Here, by replacing FIG. 129, the command group of FIG. 139 (a) can be changed as shown in FIG. 139 (b). The index “TEF_SEL:” in the first line of FIG. 139 (b) indicates the start address of the TEF_SEL module. Then, as the large winning opening closing effective time data selection process, the value of the Q register is set to the upper 1 byte of the address by the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the second line, and the lower 1 byte of the address "R_ZUG_CHK_FIX" is set. The value is set to the lower 1 byte of the address, and the value (special symbol determination flag) stored at that address is read into the A register.

The command "RCP NC, A, @ ZUG_SML1" on the third line of FIG. 139 (b) compares the value of the A register with the fixed value "@ ZUG_SML1" indicating the small hit symbol 1 designated data, here 07H. If it is 07H or more, the routine returns to the next higher routine. That is, if the value of the A register is equal to or greater than the small hit symbol 1 designated data, the TEF_SEL module is terminated. If the value of the A register is less than the small hit symbol 1 designated data, the word data selection process is executed and the process returns to the routine one step higher.

Here, the total command size of the command group shown in FIG. 139 (a) is the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the second line, 2 bytes + the command "CP A, @ ZUG_SML1" on the third line, 2 bytes + 4. The "RET NC" in the first line is 1 byte = 5 bytes, and the total execution cycle is 3 cycles in the 2nd line + 2 cycles in the 3rd line + 3 cycles (1 cycle) in the 4th line = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 139 (b) is 2 bytes of the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the 2nd line + 2 bytes of the command "RCP NC, A, @ ZUG_SML1" on the 3rd line. = 4 bytes, and the total execution cycle is 3 cycles in the 2nd row + 5 cycles (3 cycles) in the 3rd row = 8 cycles (6 cycles). Therefore, by replacing the command group of FIG. 139 (a) with the command group of FIG. 139 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

The replacement shown in FIG. 129 is called as a subroutine from a plurality of modules not only in the pachinko machine but also in the slot machine. For example, the SET_RIG module that executes the reverse push data setting process in step S2500-37 of FIG. 92 and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 of FIG. 91 are selected according to the gaming state and the effect state. In the PRE_LOT module that executes the preparatory process (AT state = "5"), and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. In the REG_LOT module that selectively shifts and executes the processing during REG (AT state = "6"), and the EXE_SET module that executes the execution flag setting processing shown in step S2400-11 in FIG. In the BIG_SLT module that executes the BIG stock number lottery process in the BIT_LOT module that selectively shifts and executes the BIG processing (AT state = "7"), in the execution flag setting process shown in step S2400-11 of FIG. It is called from the NAV_SET module or the like that executes the instruction information setting process.

FIG. 140 is an explanatory diagram for explaining the SET_RIG module. The SET_RIG module shown in FIG. 140 executes a reverse push data setting process, that is, a process of setting data required for stop control.

The index "SET_RIG:" in the first line of FIG. 140 (a) indicates the start address of the SET_RIG module. By the command "LDQ A, (LOW _HIT_NUM)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_HIT_NUM" that stores the stop control number is set to the lower 1 byte of the address. Then, the value (stop control number) stored at that address is read into the A register.

Then, as the bit data update process used during the second stop operation, the fixed value "10" is subtracted from the value of the A register by the command "SUB A, 10" on the third line of FIG. 140 (a). Then, the subtracted A register value is compared with 48 (57-10 + 1) by the command "CP A, 57-10 + 1" on the fourth line. Here, it is confirmed that the stop control number is included in the range of 10 to 57. That is, if the value of the A register is less than 10, the value of the A register becomes a negative value by the command "SUB A, 10", and the value of the A register becomes larger than 48 when viewed as a 1-byte value. Therefore, if the value of the subtracted A register is less than 10, the carry flag is set to 1 by the command "CP A, 57-10 + 1". Then, according to "RET NC" on the 5th line, if the carry flag is not 1, the routine returns to the next higher routine. If the carry flag is 1 (if the stop control number is included in the range of 10 to 57), the next process is executed.

Subsequently, by the command "LDQ A, (LOW_HIT_NUM)" on the sixth line of FIG. 140 (a), the value of the Q register is set to the upper 1 byte of the address, and the lower 1 of the address "_HIT_NUM" for storing the stop control number. The value of the byte is set to the lower 1 byte of the address, and the value (stop control number) stored at that address is read into the A register. The command "CP A, 34" on the 7th line compares the value of the A register with the fixed value "34". Here, it is confirmed that the stop control number is less than 34. If the value of the A register is less than 34, the carry flag is set to 1 by the command "CP A, 34". Then, according to "RET NC" on the 8th line, if the carry flag is not 1, the routine returns to the next higher routine. If the carry flag is 1 (if the stop control number is less than 34), the remaining processing is executed and the process returns to the routine one step higher.

Here, by replacing FIG. 129, the command group of FIG. 140 (a) can be changed as shown in FIG. 140 (b). The index “SET_RIG:” in the first line of FIG. 140 (b) indicates the start address of the SET_RIG module. By the command "LDQ A, (LOW _HIT_NUM)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_HIT_NUM" that stores the stop control number is set to the lower 1 byte of the address. Then, the value (stop control number) stored at that address is read into the A register.

Then, as the bit data update process used during the second stop operation, the fixed value "10" is subtracted from the value of the A register by the command "SUB A, 10" on the third line of FIG. 140 (b). Compare the subtracted A register value with 48 (57-10 + 1) by the command "RCP NC, A, 57-10 + 1" on the 4th line, and if the carry flag is not 1, move up one step. return. Here, it is confirmed that the stop control number is included in the range of 10 to 57, and if it is not in the range, the routine returns to the next higher routine without further processing. If the carry flag is 1 (if the stop control number is included in the range of 10 to 57), the next process is executed.

Subsequently, by the command "LDQ A, (LOW_HIT_NUM)" on the fifth line of FIG. 140 (b), the value of the Q register is set to the upper 1 byte of the address, and the lower 1 of the address "_HIT_NUM" for storing the stop control number. The value of the byte is set to the lower 1 byte of the address, and the value (stop control number) stored at that address is read into the A register. The command "RCP NC, A, 34" on the 6th line compares the value of the A register with the fixed value "34", and if the carry flag is not 1, returns to the routine one step higher. Here, it is confirmed that the stop control number is less than 34, and if it is 34 or more, the process returns to the routine one step higher without performing the subsequent processing. If the carry flag is 1 (if the stop control number is less than 34), the remaining processing is executed and the process returns to the routine one step higher.

Here, the total command size of the command group shown in FIG. 140 (a) is the command "LDQ A, (LOW _HIT_NUM)" on the second line, 2 bytes + the command "SUB A, 10" on the third line, 2 bytes + 4 lines. First command "CP A, 57-10 + 1" 2 bytes + 5th line "RET NC" 1 byte + 6th line command "LDQ A, (LOW _HIT_NUM)" 2 bytes + 7th line command "CP A, 34" 2 bytes + 8th line "RET NC" 1 byte = 12 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 2 cycles + 4th line 2 cycles + 5th line 3 cycles (1 cycle) + 6th line 3 Cycle + 7th row 2 cycles + 8th row 3 cycles (1 cycle) = 18 cycles (14 cycles). On the other hand, the total command size of the command group shown in FIG. 140 (b) is the command command "LDQ A, (LOW _HIT_NUM)" on the second line, 2 bytes + the command "SUB A, 10" on the third line, 2 bytes + 4 lines. First command "RCP NC, A, 57-10 + 1" 2 bytes + 5th line command command "LDQ A, (LOW _HIT_NUM)" 2 bytes + 6th line command "RCP NC, A, 34" 2 bytes = 10 bytes Therefore, the total execution cycle is 2nd row 3 cycles + 3rd row 2 cycles + 4th row 5 cycles (3 cycles) + 5th row 3 cycles + 6th row 5 cycles (3 cycles) = 18 cycles (14 cycles). Therefore, by replacing the command group of FIG. 140 (a) with the command group of FIG. 140 (b), the total command size is reduced by 2 bytes. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 141 is an explanatory diagram for explaining the PRE_LOT module. The PRE_LOT module shown in FIG. 141 selectively shifts according to the game state and the effect state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. The lottery process is executed when the state is a predetermined value (for example, 5).

The index "PRE_LOT:" in the first line of FIG. 141 (a) indicates the start address of the PRE_LOT module. By the command "LDQ A, (LOW _TRG_KND)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_TRG_KND" is set to the lower 1 byte of the address and stored in that address. The value (trigger combination type) is read into the A register.

By the command "CP A, @ LOT_OFS_1FK" on the third line of FIG. 141 (a), the value of the A register and the fixed value "@ LOT_OFS_1FK" indicating "one fake" as the trigger combination type, here, 3 are set. By comparison, if it is less than 3, the carry flag is set and it becomes 1. Then, if the carry flag is 1 by "RET C" on the 4th line, the routine returns to the next higher routine. That is, if the value of the A register is less than the fixed value indicating "one fake", the PRE_LOT module is terminated. If the carry flag is 0, the REG start time setting process, the BIG start time BIG stock lottery process, and the BIG start time setting process are executed, and the process returns to the routine one step higher.

Here, by replacing FIG. 129, the command group of FIG. 141 (a) can be changed as shown in FIG. 141 (b). The index "PRE_LOT:" in the first line of FIG. 141 (b) indicates the start address of the PRE_LOT module. By the command "LDQ A, (LOW _TRG_KND)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_TRG_KND" is set to the lower 1 byte of the address and stored in that address. The value (trigger combination type) is read into the A register.

By the command "RCP C, A, @ LOT_OFS_1FK" on the third line of FIG. 141 (b), the value of the A register and the fixed value "@ LOT_OFS_1FK" indicating "one fake" as the trigger combination type, here, 3 If it is less than 3, the routine returns to the next higher routine. That is, if the value of the A register is less than the fixed value indicating "one fake", the PRE_LOT module is terminated.

Here, the total command size of the command group shown in FIG. 141 (a) is the command "LDQ A, (LOW _TRG_KND)" on the second line 2 bytes + the command "CP A, @ LOT_OFS_1FK" on the third line + 3 The "RET C" in the first line is 1 byte = 5 bytes, and the total execution cycle is 3 cycles in the 2nd line + 2 cycles in the 3rd line + 3 cycles (1 cycle) in the 4th line = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 141 (b) is 2 bytes of the command "LDQ A, (LOW _TRG_KND)" on the 2nd line + 2 bytes of the command "RCP C, A, @ LOT_OFS_1FK" on the 3rd line. = 4 bytes, and the total execution cycle is 3 cycles in the 2nd row + 5 cycles (3 cycles) in the 3rd row = 8 cycles (6 cycles). Therefore, by replacing the command group of FIG. 141 (a) with the command group of FIG. 141 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 142 is an explanatory diagram for explaining the REG_LOT module. The REG_LOT module shown in FIG. 142 selectively shifts according to the game state and the effect state in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. The lottery process is executed when the state is a predetermined value (for example, 6).

The index “REG_LOT:” in the first line of FIG. 142 (a) indicates the start address of the REG_LOT module. By the command "LDQ A, (LOW _TRG_KND)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_TRG_KND" is set to the lower 1 byte of the address and stored in that address. The value (trigger combination type) is read into the A register.

By the command "CP A, @ LOT_OFS_PDJ" on the third line of FIG. 142 (a), the value of the A register is compared with the fixed value "@LOT_OFS_PDJ" indicating "batting order bell" as the trigger combination type, here 5. If it is 5, the zero flag is set and it becomes 1. Then, according to "RET NZ" on the 4th line, if the zero flag is not 1, the routine returns to the next higher routine. That is, if the value of the A register is not a fixed value indicating "batting order bell", the REG_LOT module is terminated. If the zero flag is 0, the REG remaining navigation number subtraction process and the REG end time setting process are executed, and the process returns to the routine one step higher.

Here, by replacing FIG. 129, the command group of FIG. 142 (a) can be changed as shown in FIG. 142 (b). The index “REG_LOT:” in the first line of FIG. 142 (b) indicates the start address of the REG_LOT module. By the command "LDQ A, (LOW _TRG_KND)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_TRG_KND" is set to the lower 1 byte of the address and stored in that address. The value (trigger combination type) is read into the A register.

By the command "RCP NZ, A, @ LOT_OFS_PDJ" on the third line of FIG. 142 (b), the value of the A register and the fixed value "@LOT_OFS_PDJ" indicating "batting order bell" as the trigger combination type, here, 5 Is compared, and if it is not 5, the routine returns to the next higher routine. That is, if the value of the A register is not a fixed value indicating "batting order bell", the REG_LOT module is terminated.

Here, the total command size of the command group shown in FIG. 142 (a) is the command "LDQ A, (LOW _TRG_KND)" on the second line, 2 bytes + the command "CP A, @ LOT_OFS_PDJ" on the third line, 2 bytes + 4. The "RET NZ" in the first line is 1 byte = 5 bytes, and the total execution cycle is 3 cycles in the 2nd line + 2 cycles in the 3rd line + 3 cycles (1 cycle) in the 4th line = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 142 (b) is 2 bytes of the command "LDQ A, (LOW _TRG_KND)" on the 2nd line + 2 bytes of the command "RCP NZ, A, @ LOT_OFS_PDJ" on the 3rd line. = 4 bytes, and the total execution cycle is 3 cycles in the 2nd row + 5 cycles (3 cycles) in the 3rd row = 8 cycles (6 cycles). Therefore, by replacing the command group shown in FIG. 142 (a) with the command group shown in FIG. 142 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 143 is an explanatory diagram for explaining the BIG_SLT module. The BIG_SLT module shown in FIG. 143 executes the BIG stock number lottery process.

The index “BIG_SLT:” in the first line of FIG. 143 (a) indicates the start address of the BIG_SLT module. By the command "LDQ A, (LOW _TRG_KND)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_TRG_KND" is set to the lower 1 byte of the address and stored in that address. The value (trigger combination type) is read into the A register.

The command "CP A, @ LOT_OFS_LCY" on the third line of FIG. 143 (a) compares the value of the A register with the fixed value "@LOT_OFS_LCY" indicating "weak cherry" as the trigger combination type, here 6. However, if it is less than 6, the carry flag is set and it becomes 1. Then, if the carry flag is 1 by "RET C" on the 4th line, the routine returns to the next higher routine. That is, if the value of the A register is less than the fixed value indicating "weak cherry", the BIG_SLT module is terminated. If the carry flag is 0, the stock lottery process during BIG is executed, and the process returns to the routine one step higher.

Here, by replacing FIG. 129, the command group of FIG. 143 (a) can be changed as shown in FIG. 143 (b). The index “BIG_SLT:” in the first line of FIG. 143 (b) indicates the start address of the BIG_SLT module. By the command "LDQ A, (LOW _TRG_KND)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_TRG_KND" is set to the lower 1 byte of the address and stored in that address. The value (trigger combination type) is read into the A register.

By the command "RCP C, A, @ LOT_OFS_LCY" on the third line of FIG. 143 (b), the value of the A register and the fixed value "@LOT_OFS_LCY" indicating "weak cherry" as the trigger combination type, here, 6 If it is less than 6, the routine returns to the next higher routine. That is, if the value of the A register is less than the fixed value indicating "weak cherry", the BIG_SLT module is terminated.

Here, the total command size of the command group shown in FIG. 143 (a) is the command "LDQ A, (LOW _TRG_KND)" on the second line 2 bytes + the command "CP A, @ LOT_OFS_LCY" on the third line 2 bytes + 4 The "RET C" in the first line is 1 byte = 5 bytes, and the total execution cycle is 3 cycles in the 2nd line + 2 cycles in the 3rd line + 3 cycles (1 cycle) in the 4th line = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 143 (b) is 2 bytes of the command "LDQ A, (LOW _TRG_KND)" on the 2nd line + 2 bytes of the command "RCP C, A, @ LOT_OFS_LCY" on the 3rd line. = 4 bytes, and the total execution cycle is 3 cycles in the 2nd row + 5 cycles (3 cycles) in the 3rd row = 8 cycles (6 cycles). Therefore, by replacing the command group of FIG. 143 (a) with the command group of FIG. 143 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 144 is an explanatory diagram for explaining the NAV_SET module. The NAV_SET module shown in FIG. 144 executes an instruction information setting process, that is, an instruction information type setting process.

The index “NAV_SET:” in the first line of FIG. 144 (a) indicates the start address of the NAV_SET module. By the command "LDQ A, (LOW _YRI_LMP)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_YRI_LMP" is set to the lower 1 byte of the address and stored in that address. The value (valid lamp flag) is read to the A register.

The command "CP A, @AT_MOD_PRE" on the third line of FIG. 144 (a) compares the value of the A register with the fixed value "@AT_MOD_PRE" indicating that the AT state definition is "preparing", here 5. If it is less than 5, the carry flag is set and it becomes 1. Then, if the carry flag is 1 by "RET C" on the 4th line, the routine returns to the next higher routine. That is, if the value of the A register is less than the fixed value indicating "preparing", the NAV_SET module is terminated. If the carry flag is 0, the rest of the processing is executed and the process returns to the routine one step higher.

Here, by replacing FIG. 129, the command group of FIG. 144 (a) can be changed as shown in FIG. 144 (b). The index “NAV_SET:” in the first line of FIG. 144 (b) indicates the start address of the NAV_SET module. By the command "LDQ A, (LOW _YRI_LMP)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_YRI_LMP" is set to the lower 1 byte of the address and stored in that address. The value (valid lamp flag) is read to the A register.

By the command "RCP C, A, @ AT_MOD_PRE" on the third line of FIG. 144 (b), the value of the A register and the fixed value "@AT_MOD_PRE" indicating that the AT state definition is "preparing", here, 5 If it is less than 5, the routine returns to the next higher routine. That is, if the value of the A register is less than the fixed value indicating "preparing", the NAV_SET module is terminated.

Here, the total command size of the command group shown in FIG. 144 (a) is the command "LDQ A, (LOW _YRI_LMP)" on the second line 2 bytes + the command "CP A, @AT_MOD_PRE" on the third line 2 bytes + 4 The "RET C" in the first line is 1 byte = 5 bytes, and the total execution cycle is 3 cycles in the 2nd line + 2 cycles in the 3rd line + 3 cycles (1 cycle) in the 4th line = 8 cycles (6 cycles). On the other hand, the total command size of the command group shown in FIG. 144 (b) is the command "LDQ A, (LOW _YRI_LMP" 2 bytes on the second line + the command "RCP C, A, @ AT_MOD_PRE" 2 bytes on the third line = It becomes 4 bytes, and the total execution cycle is 3 cycles in the 2nd line + 5 cycles (3 cycles) in the 3rd line = 8 cycles (6 cycles). Therefore, the command group in FIG. 144 (a) is shown in FIG. 144 (b). By replacing with the command group, the total command size is reduced by 1 byte. By such replacement, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

<XORQ>
FIG. 145 is a flowchart showing a specific process of the TOK_PRC module. The TOK_PRC module executes the special game management process (see FIG. 36) of step S600. The numerical value of step S in such a figure will be used only in the description of this figure.

As shown in FIG. 145, the main CPU 300a loads the special game special symbol determination flag (S1), inverts the loaded special game special symbol determination flag (S2), and saves the inverted special game special symbol determination flag (S1). S3). Note that step S1 corresponds to step S600-5 in FIG. 36, step S2 corresponds to step S600-7 in FIG. 36, and step S3 corresponds to step S600-7 in FIG. 36.

FIG. 146 is an explanatory diagram for explaining an example of a command for realizing the TOK_PRC module. The flowchart shown in FIG. 145 is realized by, for example, the program shown in FIG. 146.

The index “TOK_PRC:” in the first line of FIG. 146 (a) indicates the start address of the TOK_PRC module. Then, as a special game management process, the value of the Q register is set to the upper 1 byte of the address by the command "LDQ A, (LOW R_STA_TZ)" on the second line of FIG. 146 (a), and the lower 1 byte of the address "R_STA_TZ" is set. The value of is set to the lower 1 byte of the address, and the value (special game special symbol determination flag) stored in the address is read into the A register. The command on the second line corresponds to step S1 in FIG. 145. The exclusive OR of the read value (special game special symbol determination flag) and the fixed value (here, 001H) is calculated by the command "XOR 001H" on the third line. As a result, the special game special symbol determination flag is inverted. The command on the second line corresponds to step S2 in FIG. 145. Then, by the command "LDQ (LOW R_STA_TZ), A" on the 4th line, the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address "R_STA_TZ" is set to the lower 1 byte of the address, and the address is set. The value of the A register is stored in. The command on the fourth line corresponds to step S3 in FIG. 145.

Here, the command group of FIG. 146 (a) can be changed as shown in FIG. 146 (b). The index “TOK_PRC:” in the first line of FIG. 146 (b) indicates the start address of the TOK_PRC module. Then, when the special game management process is executed, the value of the Q register is set to the upper 1 byte of the address and the value of the lower 1 byte of the address "R_STA_TZ" is set to the address by the command "XORQ (LOW R_STA_TZ), 001H" on the second line. The exclusive OR of the value (special game special symbol determination flag) and the fixed value (001H in this case) stored in the address is calculated, and the calculation result is stored in the same address.

Here, the total command size of the command group shown in FIG. 146 (a) is the command on the second line "LDQ A, (LOW R_STA_TZ)" 2 bytes + the command on the third line "XOR 001H" 2 bytes + the command on the fourth line. "LDQ (LOW R_STA_TZ), A" 2 bytes = 6 bytes, and the total execution cycle is 3 cycles in the 2nd line + 2 cycles in the 3rd line + 3 cycles in the 4th line = 8 cycles. On the other hand, the total command size of the command group shown in FIG. 146 (b) is "XORQ (LOW R_STA_TZ), 001H" 4 bytes = 4 bytes, and the total execution cycle is 7 cycles in the second line = 7 cycles. Therefore, by replacing the command group of FIG. 146 (a) with the command group of FIG. 146 (b), the total command size is reduced by 2 bytes, and the total execution cycle is also reduced by at least one cycle. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in order to be able to understand by comparing FIG. 146 (a) and FIG. 146 (b), the command group that occupied the third line (second to fourth lines) in FIG. 146 (a) is shown in FIG. In 146 (b), it can be represented by one line (second line), and it is possible to reduce the number of commands themselves and the design load.

Further, here, in the example of FIG. 146 (b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 146 (b), when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, the stack processing is also performed. unnecessary. In this way, resources can be effectively used.

<CPQ>
FIG. 147 is a flowchart showing a specific process of the TEF_SEL module. The TOK_PRC module is executed when the large winning opening closing effective time is set in the special electric accessory game timer (step S720-9) in the large winning opening opening control process (see FIG. 47). The numerical value of step S in such a figure will be used only in the description of this figure.

As shown in FIG. 147, the main CPU 300a sets the large winning opening closing effective time of the small hit game (S1), loads the special symbol determination flag (S2), and uses the loaded special symbol determination flag and the small hit symbol. It is compared with a predetermined value (here, 007H) indicating that there is (S3). The special symbol determination flag is set to 00H when it is a lost symbol, 01H to 06H when it is a big hit symbol, or 07H to 09H when it is a small hit symbol.

Then, if the comparison result is a small hit symbol (YES in S4), the TEF_SEL module is terminated (S6), and if the comparison result is not a small hit symbol (NO in S4), that is, if it is a big hit symbol, The big winning opening closing effective time table of the big role game is set (S5), and the TEF_SEL module is terminated (S6).

FIG. 148 is an explanatory diagram for explaining an example of a command for realizing the TEF_SEL module. The flowchart shown in FIG. 147 is realized by, for example, the program shown in FIG. 148.

The index “TEF_SEL:” in the first line of FIG. 148 (a) indicates the start address of the TEF_SEL module. Then, the value of "@TMR_TDN_EF3" is stored in the HL register by the command "LD HL, @ TMR_TDN_EF3" on the second line of FIG. 148 (a). In "@ TMR_TDN_EF3", the effective time for closing the large winning opening of the small hit game is set. The command on the first line corresponds to step S1 in FIG. 147.

By the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the third line of FIG. 148 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_ZUG_CHK_FIX" is set to the lower 1 byte of the address. Then, the value (special symbol determination flag) stored at that address is read into the A register. The command on the third line corresponds to step S2 in FIG. 147.

By the command "CP A, @ ZUG_SML1" on the fourth line of FIG. 148 (a), the value of the A register and the fixed value "@ ZUG_SML1" indicating the small hit symbol 1 designated data (small hit symbol), here, 07H If the value of the A register is less than 07H, the carry flag is set and the value becomes 1. The command on the fourth line corresponds to step S3 in FIG. 147.

Then, by the command "RET NC" on the fifth line of FIG. 148 (a), if the carry flag is not 1, the routine returns to the next higher routine. That is, if the value of the A register is equal to or greater than the small hit symbol 1 designated data, the TEF_SEL module is terminated. The command on the fifth line corresponds to YES in step S4 of FIG. 147 and step S6.

On the other hand, if the carry flag is 1, the value of the Q register is set to the upper 1 byte of the address by the command "LDQ A, (LOW R_TDN_FLG)" on the 6th line of FIG. The value of 1 byte is set to the lower 1 byte of the address, the value stored at that address (special electric accessory designation flag) is read into the A register, and the command "LD HL, D_EFF_TMR-" on the 7th line of FIG. 148 (a). 2 ”sets the start address“ D_EFF_TMR-2 ”of the 1-byte data group as the transfer source in the HL register.

The WORDSEL module is called as a subroutine by the command "RST WORDSEL" on the 8th line of FIG. 148 (a), the value of the A register is added to the HL register twice, and the lower byte of the address shown in the HL register is used. After the value is read into the A register, the command "RET" on the 9th line of FIG. 148 (a) returns to the routine one step higher. In the subsequent routine one step higher (in the subsequent processing), the winning opening closing effective time of the big role game is set in the timer. The sixth to eighth rows correspond to step S5 of FIG. 147.

Here, the command group of FIG. 148 (a) can be changed as shown in FIG. 148 (b). Here, the description of the process substantially the same as that shown in FIG. 148 (a) will be omitted, and only the different processes shown in FIG. 148 (b) will be described.

By the command "CPQ (LOW R_ZUG_CHK_FIX), @ ZUG_SML1" on the third line of FIG. 148 (b), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_ZUG_CHK_FIX" is set to the lower 1 byte of the address. A byte is used, and the value stored at that address (special symbol judgment flag) and the fixed value "@ ZUG_SML1" indicating the small hit symbol 1 designated data (small hit symbol) are compared, and here, 07H is compared, and the value is less than 07H. If so, the carry flag is set to 1. The command on the third line corresponds to step S2 and step S3 of FIG. 147. The command size of such a command is "3" and the execution cycle is "4".

Here, the total command size of the command group shown in FIG. 148 (a) is the command "LD HL, @ TMR_TDN_EF3" on the second line + 3 bytes + the command "LDQ A, (LOW R_ZUG_CHK_FIX)" on the third line 2 bytes + 4 lines. First command "CP A, @ ZUG_SML1" 2 bytes + 5th line "RET NC" 1 byte + 6th line command "LDQ A, (LOW R_TDN_FLG)" 2 bytes + 7th line command "LD HL, D_EFF_TMR-2" 3 bytes + 8th line command "RST WORDSEL" 1 byte + 9th line "RET" 1 byte = 15 bytes, and the execution cycle is 2nd line 3 cycles + 3rd line 2 cycles + 4th line 2 cycles + 5th line 3 Cycle (1 cycle) + 6th row 2 cycles + 7th row 3 cycles + 8th row 4 cycles + 9th row 3 cycles = 22 cycles (20 cycles). The number of cycles in parentheses indicates the execution cycle when the command "RET NC" does not move to the next higher routine.

On the other hand, the total command size of the command group shown in FIG. 148 (b) is the command "LD HL, @ TMR_TDN_EF3" on the second line + 3 bytes + the command "CPQ (LOW R_ZUG_CHK_FIX), @ ZUG_SML1" on the third line. 1 byte of the first "RET NC" + 1 byte of the command "LDQ A, (LOW R_TDN_FLG)" on the 5th line + 1 byte of the command "LD HL, D_EFF_TMR-2" on the 6th line + 1 byte of the command "RST WORDSEL" on the 7th line +8th line "RET" 1 byte = 14 bytes, and the execution cycle is 2nd line 3 cycles + 3rd line 4 cycles + 4th line 3 cycles (1 cycle) + 5th line 2 cycles + 6th line 3 cycles + 7th line 4 Cycle + 8th line 3 cycles = 22 cycles (20 cycles). The number of cycles in parentheses indicates the execution cycle when the command "RET NC" does not move to the next higher routine.

Therefore, by replacing the command group of FIG. 148 (a) with the command group of FIG. 148 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing the game control process.

Further, in order to be able to understand by comparing FIG. 148 (a) and FIG. 148 (b), the command group that occupied the second line (third line and fourth line) in FIG. 148 (a) is shown in FIG. In 148 (b), it can be represented by one line (third line), and it is possible to reduce the number of commands themselves and the design load.

Further, here, in the example of FIG. 148 (b), the A register is not used in the command on the third line. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 148 (b), if the A register is already used when executing the command on the third line, it is necessary to stack and save the value of the A register. Since the A register is not used, stack processing is not required. In this way, resources can be effectively used.

<JTANDQ>
FIG. 149 is a flowchart showing a specific process of the SWI_PRC module. The SWI_PRC module executes the switch management process (see FIG. 28) in step S500. The numerical value of step S in such a figure will be used only in the description of this figure.

As shown in FIG. 149, the main CPU 300a determines whether the first variable start port detection switch 120Bs is detected (S1), and if the first variable start port detection switch 120Bs is detected (YES in S1). , The first start port passing process (S2) and the ordinary electric accessory winning confirmation process (S3) are executed. On the other hand, unless the first variable start port detection switch 120Bs is detected (NO in S1), the first start port passage process (S2) and the normal electric accessory winning confirmation process (S3) are skipped. Note that step S1 corresponds to step S500-7 in FIG. 28, step S2 corresponds to step S520 in FIG. 28, and step S3) corresponds to step S500-9 in FIG. 28.

FIG. 150 is an explanatory diagram for explaining an example of a command for realizing the SWI_PRC module. The flowchart shown in FIG. 149 is realized by, for example, the program shown in FIG. 150.

The index “SWI_PRC:” in the first line of FIG. 150 (a) indicates the start address of the SWI_PRC module. Then, by the command "LDQ A, (LOW R_IN3_PON)" on the second line of FIG. 150 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_IN3_PON" is set to the lower 1 byte of the address. It is set to 1 byte, and the value stored at that address is read into the A register. Here, in the value stored at the same address, for example, the detection result of the first fixed start port detection switch 120As (input unit) is held in the least significant bit, and the second start is performed in the lower second bit. The detection result of the mouth detection switch 122s (input unit) is held, and the detection result of the first variable start port detection switch 120Bs (input unit) is held in the lower 3 bits. Each of these bits becomes "1" when the detection switch detects that the game ball has entered, and becomes "0" when the detection switch does not detect that the game ball has entered.

The command "AND A, @ IN3_ST2_BIT" on the third line calculates the logical product of the read value and the fixed value "@ IN3_ST2_BIT (here 00000100b). As a result, all but the lower 3 bits of the read value are 0. If the lower 3 bits of the read value is 0, the zero flag = 1, and if the lower 3 bits of the read value is 1, the zero flag = 0. That is, the first variable start. If the detection result of the mouth detection switch 120Bs is 1, the zero flag = 0 (if the entry of the game ball is detected), and if the detection result of the first variable start port detection switch 120Bs is 0 (of the game ball). Zero flag = 0 (if no entry is detected).

Then, the command "JR Z, SWI_PRC_20" on the 4th line moves to SWI_PRC_20 (7th line) if the zero flag is 1 (Z). The commands on the second to fourth lines correspond to step S1 in FIG. 149.

On the other hand, if the zero flag is not 1 by the command "JR Z, SWI_PRC_20" on the 4th line, the STA_PAS module is called as a subroutine by the command "CALLF STA_PAS" on the 5th line, and the STA_PAS module processes the passage through the first start port. Is executed. The command on the fifth line corresponds to step S2 in FIG. 149. Further, the command "CALLF FDN_CHK" on the 6th line calls the FDN_CHK module as a subroutine, and the FDN_CHK module executes the confirmation process at the time of winning a normal electric accessory. The command on the sixth line corresponds to step S3 in FIG. 149.

Here, the command group of FIG. 150 (a) can be changed as shown in FIG. 150 (b). Here, the description of the process substantially the same as that of FIG. 150 (a) will be omitted, and only the different processes of FIG. 150 (b) will be described.

By the command "JTANDQ Z, (LOW R_IN3_PON), @ IN3_ST2_BIT, SWI_PRC_20" on the second line of FIG. 150 (b), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_IN3_PON" is set. It is set to the lower 1 byte of the address, the logical product of the value stored in the address and the fixed value "@ IN3_ST2_BIT" is calculated, and if the zero flag is 1, it moves to SWI_PRC_20. The command on the second line corresponds to step S1 in FIG. 149. The command size of such a command is "4" and the execution cycle is "5 (6)". The number of cycles in parentheses indicates the execution cycle when the zero flag is 1 and the device moves to SWI_PRC_20.

Here, the total command size of the command group shown in FIG. 150 (a) is the command "LDQ A, (LOW R_IN3_PON)" on the second line, 2 bytes + the command on the third line, "AND A, @ IN3_ST2_BIT", 2 bytes + 4 lines. 1st command "JR Z, SWI_PRC_20" 2 bytes + 5th line command "CALLF STA_PAS" 2 bytes + 6th line command "CALLF FDN_CHK" 2 bytes = 10 bytes, total execution cycle is 2nd line 3 cycles + 3 lines 2nd cycle + 4th row 2 (3) cycle + 5th row 4 cycles + 6th row 4 cycles = 15 (16) cycles. The number of cycles in parentheses indicates the execution cycle when the zero flag is 1 and the device moves to SWI_PRC_20.

On the other hand, the total command size of the command group shown in FIG. 150 (b) is 4 bytes for the command "JTANDQ Z, (LOW R_IN3_PON), @ IN3_ST2_BIT, SWI_PRC_20" on the second line + 2 bytes for the command "CALLF STA_PAS" on the third line. The command "CALLF FDN_CHK" on the + 4th line is 2 bytes = 8 bytes, and the total execution cycle is 5 (6) cycles on the 2nd line + 4 cycles on the 3rd line + 4 cycles on the 4th line = 13 (14) cycles.

Therefore, by replacing the command group of FIG. 150 (a) with the command group of FIG. 150 (b), the total command size is reduced by 2 bytes, and the total execution cycle is also reduced by at least 2 cycles. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in order to be able to understand by comparing FIG. 150 (a) and FIG. 150 (b), the command group occupying the third line (second to fourth lines) in FIG. 150 (a) is shown in FIG. In 150 (b), it can be represented by one line (second line), and it is possible to reduce the number of commands themselves and the design load.

Further, in the example of FIG. 150 (b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 150 (b), when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, the stack processing is also performed. unnecessary. In this way, resources can be effectively used.

<OUT>
FIG. 151 is a flowchart showing a specific process of the CPUINIT module. The CPUINIT module executes the CPU initialization process (see FIG. 22). The numerical value of step S in such a figure will be used only in the description of this figure.

As shown in FIG. 151, the main CPU 300a executes an access permission process for permitting access to the RAM 300c (S1). Note that step S1 corresponds to step S100-9 in FIG. 22.

FIG. 152 is an explanatory diagram for explaining an example of a command for realizing the CPUINIT module. The flowchart shown in FIG. 151 is realized by, for example, the program shown in FIG. 152.

The index “CPUINIT:” in the first line of FIG. 152A indicates the start address of the CPUINIT module. Then, by the command "LDA, (@RAMENBL)" on the second line of FIG. 152 (a), the fixed value "@RAMENBL" (here, 1) indicating that access is permitted is read into the A register. Then, by the command "OUT (@RAP _____), A" on the third line of FIG. 152 (a), the value of the U register is set to the upper 1 byte of the address, and the RAM access protect register port (internal register I / O port) is set. The fixed value "@RAP _____" indicating the lower 1 byte of the address is set as the lower 1 byte, and the value (1) of the A register is output to the address. The upper 1 byte (for example, "FEH") of the address of the RAM access protect register port (internal register I / O port) is preset in the U register.

Here, the command group of FIG. 152 (a) can be changed as shown in FIG. 152 (b). Here, the description of the process substantially the same as that shown in FIG. 152 (a) will be omitted, and only the different processes shown in FIG. 152 (b) will be described.

By the command "OUT (@RAP _____), @RAMENBL" on the second line of FIG. 152 (b), the value of the U register is set to the upper 1 byte of the address, and the address of the RAM access protect register port (internal register I / O port). The fixed value "@RAP _____" indicating the lower 1 byte of is set as the lower 1 byte, and the fixed value "@RAMENBL", that is, 1 is output to the address. The command size of such a command is "3" and the execution cycle is "4".

Here, the total command size of the command group shown in FIG. 152 (a) is 2 bytes of the command "LD A, (@RAMENBL)" on the 2nd line + 2 bytes of the command "OUT (@RAP _____), A" on the 3rd line. = 4 bytes, and the total execution cycle is 2 cycles in the 2nd row + 3 cycles in the 3rd row = 5 cycles.

On the other hand, the total command size of the command group shown in FIG. 152 (b) is the command "OUT (@RAP _____), @RAMENBL" on the second line, 3 bytes = 3 bytes, and the total execution cycle is 4 cycles on the second line. = 4 cycles.

Therefore, by replacing the command group of FIG. 152 (a) with the command group of FIG. 152 (b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least one cycle. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in order to be able to understand by comparing FIG. 152 (a) and FIG. 152 (b), the command group occupying the second line (second to third lines) in FIG. 152 (a) is shown in FIG. In 152 (b), it can be represented by one line (second line), and it is possible to reduce the number of commands themselves and the design load.

Further, in the example of FIG. 152 (b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 152 (b), when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, the stack processing is also performed. unnecessary. In this way, resources can be effectively used.

FIG. 153 is an explanatory diagram for explaining the TMR_IPT module. The TMR_IPT module shown in FIG. 153 executes the timer interrupt processing shown in FIG. 98.

The index “TMR_IPT:” in the first line of FIG. 153 (a) indicates the start address of the TMR_IPT module. Then, the command "LDA, @TOCRVAL" on the second line of FIG. 153 (a) reads the fixed value "@TOCRVAL" (here, 1) indicating that access is permitted to the A register. Then, by the command "OUT (@PTOCR__), A" on the third line of FIG. 153 (a), the value of the U register is set to the upper 1 byte of the address, and the RAM access protect register port (internal register I / O port) is set. The fixed value "@PTOCR__" indicating the lower 1 byte of the address is set as the lower 1 byte of the address, and the value (1) of the A register is output to the address. The upper 1 byte (for example, "FEH") of the address of the RAM access protect register port (internal register I / O port) is preset in the U register.

Here, the command group of FIG. 153 (a) can be changed as shown in FIG. 153 (b). Here, the description of the process substantially the same as that of FIG. 153 (a) will be omitted, and only the different processes of FIG. 153 (b) will be described.

By the command "OUT (@PTOCR__), @TOCRVAL" on the second line of FIG. 153 (b), the value of the U register is set to the upper 1 byte of the address, and the address of the RAM access protect register port (internal register I / O port). The fixed value "@PTOCR__" indicating the lower 1 byte of is set as the lower 1 byte of the address, and the fixed value "@TOCRVAL", that is, 1 is output to the address. The command size of such a command is "3" and the execution cycle is "4".

Here, the total command size of the command group shown in FIG. 153 (a) is 2 bytes of the command "LDA, @TOCRVAL" on the 2nd line + 2 bytes of the command "OUT (@PTOCR__), A" on the 3rd line = It becomes 4 bytes, and the total execution cycle is 2 cycles in the 2nd line + 3 cycles in the 3rd line = 5 cycles.

On the other hand, the total command size of the command group shown in FIG. 153 (b) is the command "OUT (@PTOCR__), @TOCRVAL" on the second line, 3 bytes = 3 bytes, and the total execution cycle is 4 cycles on the second line. = 4 cycles.

Therefore, by replacing the command group of FIG. 153 (a) with the command group of FIG. 153 (b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least one cycle. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in order to be able to understand by comparing FIG. 153 (a) and FIG. 153 (b), the command group occupying the second line (second to third lines) in FIG. 153 (a) is shown in FIG. In 153 (b), it can be represented by one line (second line), and it is possible to reduce the number of commands themselves and the design load.

Further, in the example of FIG. 153 (b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 153 (a), when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, the stack processing is also performed. unnecessary. In this way, resources can be effectively used.

<LDQ>
FIG. 154 is a flowchart showing a specific process of the FZ_SPN module. The FZ_SPN module executes the above-mentioned normal symbol change processing (see FIG. 53). The numerical value of step S in such a figure will be used only in the description of this figure.

As shown in FIG. 154, the main CPU 300a saves the normal symbol stop symbol number (counter value) in the normal symbol display symbol counter. (S1). Note that step S1 corresponds to step S820-9 in FIG. 53.

FIG. 155 is an explanatory diagram for explaining an example of a command for realizing the FZ_SPN module. The flowchart shown in FIG. 154 is realized by, for example, the program shown in FIG. 155.

The index “FZ_SPN:” in the first line of FIG. 155 (a) indicates the start address of the FZ_SPN module. Then, by the command "LDQ A, (LOW R_FZ_STP)" on the second line of FIG. It is set to 1 byte, and the value (normal symbol stop symbol number) stored at that address is read into the A register.

Then, by the command "LDQ (LOW R_FZ_DSP), A" on the second line of FIG. 155 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_FZ_DSP" is set to the lower 1 byte of the address. It is set to 1 byte, and the value of the A register is stored in the address (the address of the normal symbol display symbol counter).

Here, the command group of FIG. 155 (a) can be changed as shown in FIG. 155 (b). Here, the description of the process substantially the same as that of FIG. 155 (a) will be omitted, and only the different processes of FIG. 155 (b) will be described.

By the command "LDQ (LOW R_FZ_DSP), (LOW R_FZ_STP)" on the second line of FIG. The lower 1 byte is set, the value stored in the address is set as the upper 1 byte of the Q register, the lower 1 byte value of the address "R_FZ_DSP" is set as the lower 1 byte of the address, and the value is stored in the address.

Here, the total command size of the command group shown in FIG. 155 (a) is 2 bytes of the command "LDQ A, (LOW R_FZ_STP)" on the second line + 2 bytes of the command "LDQ (LOW R_FZ_DSP), A" on the third line. = 4 bytes, and the total execution cycle is 3 cycles in the 2nd line + 3 cycles in the 3rd line = 6 cycles.

On the other hand, the total command size of the command group shown in FIG. 6 cycles = 6 cycles.

Therefore, in order to be able to understand by comparing FIG. 155 (a) and FIG. 155 (b), the command group that occupied the second line (second to third lines) in FIG. 155 (a) is totaled. In FIG. 155 (b), it can be represented by one line (second line) without changing the command size and the total execution cycle, and it is possible to reduce the number of commands themselves and the design load. ..

Further, in the example of FIG. 155 (b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 155 (b), when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, the stack processing is also performed. unnecessary. In this way, resources can be effectively used.

FIG. 156 is an explanatory diagram for explaining an example of a command for realizing the CPUINIT module. Here, in the special game, the game progresses in either the low-probability gaming state or the high-probability gaming state. The gaming machine 100 is provided with an indicator indicating that the gaming state is a high-probability gaming state, and when the gaming state is a high-probability gaming state, the indicator lights up. Then, when the player is not notified that the player is in a high-probability gaming state at the time of recovery from the power failure (so-called incubation period), the display can be hidden. At this time, if it is determined whether or not the display is lit based on the actual game state, the display will be turned on if the game state at the time of recovery from the power failure is a high-probability gaming state. Therefore, a flag indicating that the player is in hiding is prepared from the time when the power is restored until the first major game is started, and the presence or absence of lighting of the display is determined based on the flag.

The index “CPUINIT:” in the first line of FIG. 156 (a) indicates the start address of the CPUINIT module. Then, by the command "LDQ A, (LOW R_KAK_FLG)" on the second line of FIG. 156 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_KAK_FLG" is set to the lower 1 byte of the address. One byte is set, and the value stored at that address (the address of the flag indicating whether or not the game is in the high-probability game state) (1 in the high-probability game state, 0 in the non-high-probability game state) is set in the A register. read out.

Then, by the command "LDQ (LOW R_KAK_HOT), A" on the second line of FIG. 156 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_KAK_HOT" is set to the lower 1 byte of the address. It is set to 1 byte, and the value of the A register is stored in the address (the address of the flag indicating that it is hidden).

Here, the command group of FIG. 156 (a) can be changed as shown in FIG. 156 (b). Here, the description of the process substantially the same as that shown in FIG. 156 (a) will be omitted, and only the different processes shown in FIG. 156 (b) will be described.

By the command "LDQ (LOW R_KAK_HOT), (LOW R_KAK_FLG)" on the second line of FIG. 156 (b), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_KAK_FLG" is set to the address. The lower 1 byte is set, the value stored in the address is set as the upper 1 byte of the address, the value of the Q register is set as the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_KAK_HOT" is set as the lower 1 byte of the address and stored in the address.

Here, the total command size of the command group shown in FIG. 156 (a) is 2 bytes of the command "LDQ A, (LOW R_KAK_FLLG)" on the second line + 2 bytes of the command "LDQ (LOW R_KAK_HOT), A" on the third line. = 4 bytes, and the total execution cycle is 3 cycles in the 2nd line + 3 cycles in the 3rd line = 6 cycles.

On the other hand, the total command size of the command group shown in FIG. 156 (b) is the command "LDQ (LOW R_KAK_HOT), (LOW R_KAK_FLG)" on the second line, 4 bytes = 4 bytes, and the total execution cycle is the second line. 6 cycles = 6 cycles.

Therefore, in order to be able to understand by comparing FIG. 156 (a) and FIG. 156 (b), the command group that occupied the second line (second to third lines) in FIG. 156 (a) is shown in FIG. In 156 (b), it can be represented by one line (second line), and it is possible to reduce the number of commands themselves and the design load.

Further, in the example of FIG. 156 (b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 156 (b), when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, the stack processing is also performed. unnecessary. In this way, resources can be effectively used.

FIG. 157 is an explanatory diagram for explaining an example of a command for realizing the EXE_SET module. The EXE_SET module shown in FIG. 157 executes the execution flag setting process shown in step S2400-11 in FIG. 91.

The index “EXE_SET:” in the first line of FIG. 157 (a) indicates the start address of the EXE_SET module. Then, by the command "LDQ A, (LOW AT_NXT)" on the second line of FIG. 157 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "AT_NXT" is set to the lower 1 byte of the address. It is set to 1 byte, and the value (value indicating the effect state of the next game) stored in the address (the address of the value indicating the effect state of the next game) is read into the A register.

Then, by the command "LDQ (LOW AT_MOD), A" on the third line of FIG. 157 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "AT_MOD" is set to the lower 1 byte of the address. It is set to 1 byte, and the value of the A register is stored in the address (the address of the value indicating the effect state of the game).

Here, the command group of FIG. 157 (a) can be changed as shown in FIG. 157 (b). Here, the description of the process substantially the same as that of FIG. 157 (a) will be omitted, and only the different processes of FIG. 157 (b) will be described.

By the command "LDQ (LOW AT_MOD), (LOW AT_NXT)" on the second line of FIG. 157 (b), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "AT_NXT" is set to the address. The lower 1 byte is set, the value stored in the address is set as the upper 1 byte of the Q register, the lower 1 byte value of the address "AT_MOD" is set as the lower 1 byte of the address, and the value is stored in the address.

Here, the total command size of the command group shown in FIG. 157 (a) is 2 bytes of the command "LDQ A, (LOW AT_NXT)" on the second line + 2 bytes of the command "LDQ (LOW AT_MOD), A" on the third line. = 4 bytes, and the total execution cycle is 3 cycles in the 2nd line + 3 cycles in the 3rd line = 6 cycles.

On the other hand, the total command size of the command group shown in FIG. 157 (b) is 4 bytes = 4 bytes of the command "LDQ (LOW AT_MOD), (LOW AT_NXT)" on the second line, and the total execution cycle is the second line. 6 cycles = 6 cycles.

Therefore, in order to be able to understand by comparing FIG. 157 (a) and FIG. 157 (b), the command group that occupied the second line (second to third lines) in FIG. 157 (a) is shown in FIG. In 157 (b), it can be represented by one line (second line), and it is possible to reduce the number of commands themselves and the design load.

Further, in the example of FIG. 157 (b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 157 (a), when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, the stack processing is also performed. unnecessary. In this way, resources can be effectively used.

<LDIN>
FIG. 158 is a flowchart showing a specific process of the HPT_GRP module. The HPT_GRP module executes the reach group determination process of step S612-7 in the special symbol variation number determination process (see FIG. 39). The numerical value of step S in such a figure will be used only in the description of this figure. Further, in the description of the HPT_GRP module, the first register is the HL register, and the other registers are the BC register or the A register.

In the reach group determination process, the address of the reach group determination random number determination table determined in advance according to the hold type, the number of holds, the game state, and the like is stored in advance in the HL register.

As shown in FIG. 158, the main CPU 300a loads the comparison value stored in the address (table address) shown in the HL register into the BC register, and adds 2 to the value of the HL register (S1). As will be described in detail later, in the reach group determination random number determination table, a 2-byte length comparison value and a 1-byte length group number are stored as one set, and these one set are continuously stored in a plurality of orders. .. Therefore, here, by adding 2 to the value of the HL register after loading the comparison value, the HL register becomes the address value in which the group number stored next to the loaded comparison value is stored.

After that, the main CPU 300a compares the comparison value loaded in the BC register with the reach group determination random number (random number value) preloaded in the DE register (S2), and the reach stored in the address indicated in the HL register. Load the group number (S3).

After that, the main CPU 300a adds 1 to the value (table address) of the HL register (S4). Here, by adding 1 to the value of the HL register after loading the group number, the HL register becomes the address value in which the comparison value stored next to the loaded group number is stored.

Then, if the comparison value is equal to or less than the reach group determination random number (random number value) as the comparison result in step S2 (YES in S5), the main CPU 300a returns the process to step S1 and the comparison value is the reach group determination random number. If it is not the following (NO in S5), the HPT_GRP module is terminated (S6).

FIGS. 159 (a) and 159 (b) are explanatory diagrams for explaining an example of a command for realizing the HPT_GRP module. FIG. 159 (c) is an explanatory diagram for explaining an example of the reach group determination random number determination table. The flowchart shown in FIG. 158 is realized by, for example, the program shown in FIGS. 159 (a) and 159 (b). First, the reach group determination random number determination table of FIG. 159 (c) will be described, and then the commands for realizing the HPT_GRP module shown in FIGS. 159 (a) and 159 (b) will be described.

The table starting from the index “D_GRP_SEL_00:” in FIG. 159 (c) indicates the start address of any of the reach group determination random number determination tables. The fixed value "8999" in the second line, the fixed value "9099" in the fourth line, and the fixed value "9299" in the sixth line are comparison values having a length of 2 bytes, respectively, and the fixed value "9999" in the third line. The fixed value "@ D_MOD_SEL_00" on the 5th line, the fixed value "@D_MOD_SEL_01" on the 5th line, and the fixed value "@D_MOD_SEL_02" on the 7th line are group numbers having a length of 1 byte, respectively. Then, in the reach group determination random number determination table, a comparison value having a length of 2 bytes and a group number having a length of 1 byte corresponding to the comparison value are stored in sequence as one set.

The index “HPT_GRP:” in the first line of FIG. 159 (a) indicates the start address of the HPT_GRP module. Then, by the command "LDIN BC, (HL)" on the second line of FIG. 159 (a), the 2-byte length value (comparison value) stored at the address indicated by the HL register is read (loaded) into the BC register. ), Add 2 to the value of the HL register. The command on the second line corresponds to step S1 in FIG. 158. The address of the reach group determination random number determination table determined in advance is loaded in the HL register.

Then, the value stored in the BC register (comparison value) is compared with the value stored in the DE register (reach group determination random number) by the command "CP BC, DE" on the third line of FIG. 159 (a). do. Here, if the value stored in the BC register is equal to or less than the value stored in the DE register, 1 is set in the zero flag (if equal) or the carry flag (if less than). The reach group determination random number is stored in the DE register in advance. The command on the third line corresponds to step S2 in FIG. 158.

After that, the 1-byte length value (group number) stored in the address indicated by the HL register is read into the A register by the command "LDA, (HL)" on the fourth line of FIG. 159 (a). The command on the fourth line corresponds to step S3 in FIG. 158. Then, the value of the HL register is added by 1 by the command "INC HL" on the fifth line of FIG. 159 (a). The command on the fifth line corresponds to step S4 in FIG. 158.

Subsequently, when 1 is set in the zero flag or the carry flag by the command "JLS HPT_GRP" on the 6th line in FIG. 159 (a) and the command "CP BC, DE" on the 3rd line, the address indicated by "HPT_GRP". If 1 is not set in the zero flag and the carry flag, the HPT_GRP module is terminated by the command “RET” on the 7th line in FIG. 159 (a). The commands on the 6th and 7th lines correspond to steps S5 and S6 in FIG. 158. Then, when the HPT_GRP module is completed, the group number corresponding to the range shown in FIG. 9 is stored in the A register.

Here, the command group of FIG. 159 (a) can be changed as shown in FIG. 159 (b). Here, the description of the process substantially the same as that of FIG. 159 (a) will be omitted, and only the different processes of FIG. 159 (b) will be described.

By the command "LDIN A, (HL)" on the fourth line of FIG. 159 (b), the 1-byte length value (group number) stored at the address indicated by the HL register is read into the A register, and the value of the HL register is read. Is added by 1. The command on the fourth line corresponds to steps S3 and S4 of FIG. 158. The command size of such a command is "1" and the execution cycle is "2".

Here, the total command size of the command group shown in FIG. 159 (a) is the second line command "LDIN BC, (HL)" 2 bytes + the third line command "CP BC, DE" 2 bytes + the fourth line. Command "LD A, (HL)" 1 byte + 5th line command "INC HL" 1 byte + 6th line command "JLS HPT_GRP" 3 bytes + 7th line command "RET" 1 byte = 10 bytes, total execution The cycle is 4 cycles in the 2nd row + 2 cycles in the 3rd row + 2 cycles in the 4th row + 1 cycle in the 5th row + 4 (3) cycles in the 6th row + 3 cycles in the 7th row = 16 (15) cycles. The number of cycles in parentheses indicates the execution cycle when the command "JLS HPT_GRP" does not move.

On the other hand, the total command size of the command group shown in FIG. 159 (b) is the command "LDIN BC, (HL)" on the second line, 2 bytes + the command on the third line, "CP BC, DE", 2 bytes + the command on the 4th line. "LDIN A, (HL)" 1 byte + 5th line command "JLS HPT_GRP" 3 bytes + 6th line command "RET" 1 byte = 9 bytes, and the total execution cycle is 2nd line 4 cycles + 3rd line 2 Cycle + 4th row 2 cycles + 5th row 4 (3) cycles + 6th row 3 cycles = 15 (14) cycles. The number of cycles in parentheses indicates the execution cycle when the command "JLS HPT_GRP" does not move.

Therefore, by replacing the command group of FIG. 159 (a) with the command group of FIG. 159 (b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least one cycle. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in order to be able to understand by comparing FIG. 159 (a) and FIG. 159 (b), the command group occupying the second line (4th to 5th lines) in FIG. 159 (a) is shown in FIG. In 159 (b), it can be represented by one line (fourth line), and it is possible to reduce the number of commands themselves and the design load.

Further, in the example of FIG. 159 (b), when acquiring a desired 2-byte length value or 1-byte length value in a table in which a plurality of values having different byte lengths are alternately juxtaposed, the value of the HL register is used. 2 addition and 1 addition can be executed by the same command "LDIN", and the design load can be reduced.

FIG. 160 is an explanatory diagram for explaining the E_ILGER module. The E_ILGER module shown in FIG. 160 executes the fraud monitoring process shown in step S3100-19 in FIG. 98.

The index “E_ILGER:” in the first line of FIG. 160 (a) indicates the start address of the E_ILGER module. The command "LD HL, _EX_ILTM" on the second line reads the address "EX_ILTM" that stores the illegal input monitoring timer to the HL register.

After that, the command "LDA, (HL)" on the third line of FIG. 160A reads the 1-byte length value (illegal input monitoring timer) stored at the address indicated by the HL register into the A register. Then, the value of the HL register is added by 1 by the command "INC HL" on the fourth line of FIG. 160 (a). Subsequently, when the value of the A register is 0 (when the illegal input monitoring timer is 0) by the command "JTZ, A, E_ILGER01" on the fifth line of FIG. 160 (a), the subsequent processing is omitted. Then, it moves to the index "E_ILGER01:" on the 6th line, and if the value of the A register is not 0, the process is moved to the next command of the command.

Here, the command group of FIG. 160 (a) can be changed as shown in FIG. 160 (b). Here, the description of the process substantially the same as that shown in FIG. 160 (a) will be omitted, and only the different processes shown in FIG. 160 (b) will be described.

By the command "LDIN A, (HL)" on the third line of FIG. 160 (b), the 1-byte length value (illegal input monitoring timer) stored at the address indicated by the HL register is read into the A register, and the HL register is read. Add 1 to the value of. The command size of such a command is "1" and the execution cycle is "2".

Here, the total command size of the command group shown in FIG. 160 (a) is the command "LD HL, _EX_ILTM" on the second line, 3 bytes + the command "LD A, (HL)" on the third line, 1 byte + 4th line. Command "INC HL" 1 byte + 5th line command "JTZ, A, E_ILGER01" 2 bytes = 7 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 2 cycles + 4th line 1 cycle + 5 lines Eye 3 (2) cycle = 9 (8) cycle. The number of cycles in parentheses indicates the execution cycle when the command "JTZ, A, E_ILGER01" does not move.

On the other hand, the total command size of the command group shown in FIG. 160 (b) is the command "LD HL, _EX_ILTM" on the second line, 3 bytes + the command "LDIN A, (HL)" on the third line, 1 byte + the fourth line. The command "JT Z, A, E_ILGER01" has 2 bytes = 6 bytes, and the total execution cycle is 3 cycles in the 2nd line + 2 cycles in the 3rd line + 3 (2) cycles in the 4th line = 8 (7) cycles. The number of cycles in parentheses indicates the execution cycle when the command "JTZ, A, E_ILGER01" does not move.

Therefore, by replacing the command group of FIG. 160 (a) with the command group of FIG. 160 (b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least one cycle. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in order to be able to understand by comparing FIG. 160 (a) and FIG. 160 (b), the command group occupying the second line (third to fourth lines) in FIG. 160 (a) is shown in FIG. In 160 (b), it can be represented by one line (third line), and it is possible to reduce the number of commands themselves and the design load.

FIG. 161 is an explanatory diagram for explaining the E_LEVOT module. The E_LEVOT module shown in FIG. 161 is a subroutine called in the execution flag setting process shown in step S2400-11 in FIG. 91, and executes the test signal transmission process when the lever is pressed.

The index “E_LEVOT:” in the first line of FIG. 161 (a) indicates the start address of the E_LEVOT module. The command "LD HL, T_EXM_STP" on the second line reads the address "T_EXM_STP" for storing the test stop information transmission table into the HL register. In this test stop information transmission table, the values of six test signals having a length of 1 byte are continuously stored as one set, and a plurality of sets are continuously stored.

After that, the command "ADDWB HL, A" on the third line of FIG. 161 (a) adds the value of the A register to the value of the HL register, and updates the value of the HL register. The A register stores a value obtained by multiplying the instruction information type by 6. Therefore, here, the value of the HL register indicates one set of start addresses corresponding to the instruction information type in the test stop information transmission table.

Then, the fixed value "6" is read out to the B register by the command "LD B, 6" on the fourth line. The index “E_LEVOT01:” on the fifth line of FIG. 161 (a) indicates the address of the index “E_LEVOT01”.

By the command "LDA, (HL)" on the sixth line of FIG. 161 (a), the 1-byte length value (test signal value) stored at the address indicated by the HL register is read into the A register. Then, by the command command "OUT (@ S2DT__), A" on the 7th line of FIG. 161 (a), the value of the U register is set to the upper 1 byte of the address, and the RAM access protect register port (internal register I / O port). The fixed value "@ S2DT__" indicating the lower 1 byte of the address is set as the lower 1 byte, and the value of the A register is output to that address.

The value of the HL register is added by 1 by the command "INC HL" on the 8th line of FIG. 161 (a). Subsequently, the command "DJNZ E_LEVOT01" on the 9th line of FIG. 161 (a) decrements the value of the B register (subtracts "1"), and if the decremented result is not 0, the process moves to the address "E_LEVOT01". If the result of decrementing is 0, the process is moved to the command next to the command.

Here, the command group of FIG. 161 (a) can be changed as shown in FIG. 161 (b). Here, the description of the process substantially the same as that of FIG. 161 (a) will be omitted, and only the different processes of FIG. 161 (b) will be described.

The command "LDIN A, (HL)" on the sixth line of FIG. 161 (b) reads the 1-byte length value (test signal value) stored at the address indicated by the HL register into the A register and reads it into the HL register. Add 1 to the value of. The command size of such a command is "1" and the execution cycle is "2".

Here, the total command size of the command group shown in FIG. 161 (a) is the command "LD HL, T_EXM_STP" on the second line, 3 bytes + the command on the third line, "ADDWB HL, A", 1 byte + the command on the fourth line. "LD B, 6" 2 bytes + 6th line command "LD A, (HL)" 1 byte + 7th line command "OUT (@ S2DT__), A" 2 bytes + 8th line command "INC HL" 1 byte +9th line command "DJNZ E_LEVOT01" 2 bytes = 12 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 1 cycle + 4th line 2 cycles + 6th line 2 cycles + 7th line 3 cycles + 8th line 1 Cycle + 9th line 3 (2) cycle = 15 (14) cycle. The number of cycles in parentheses indicates the execution cycle when the command "DJNZ E_LEVOT01" does not move.

On the other hand, the total command size of the command group shown in FIG. 161 (b) is the command "LD HL, T_EXM_STP" on the second line, 3 bytes + the command "ADDWB HL, A" on the third line, and the command "ADDWB HL, A" on the fourth line. LD B, 6 "2 bytes + 6th line command" LDIN A, (HL) "1 byte + 7th line command" OUT (@ S2DT__), A "2 bytes + 5th line command" DJNZ E_LEVOT01 "2 bytes = The total execution cycle is 11 bytes, and the total execution cycle is 2nd row 3 cycles + 3rd row 1 cycle + 4th row 2 cycles + 6th row 2 cycles + 7th row 3 cycles + 9th row 3 (2) cycles = 14 (13) cycles. .. The number of cycles in parentheses indicates the execution cycle when the command "DJNZ E_LEVOT01" does not move.

Therefore, by replacing the command group of FIG. 161 (a) with the command group of FIG. 161 (b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least one cycle. In particular, in the example of FIG. 161 (a), if the value of the B register in the command "DJNZ E_LEVOT01" is 2 or more, the difference in the total execution cycle increases by multiplying that value by one cycle. The amount of reduction in the total execution cycle of b) also increases. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in order to be able to understand by comparing FIG. 161 (a) and FIG. 161 (b), the command group occupying the second line (6th line and 8th line) in FIG. 161 (a) is shown in FIG. In 161 (b), it can be represented by one line (sixth line), and it is possible to reduce the number of commands themselves and the design load.

<LDQP>
FIG. 162 is a flowchart showing a specific process of the SBC_OUT module. The SBC_OUT module executes the subcommand transmission process (see FIG. 23) of step S100-65. The numerical value of step S in such a figure will be used only in the description of this figure.

Here, the subcommand is set in the transmission buffer in a plurality of processes in the interrupt process and is transmitted in the subcommand transmission process. Here, the transmission buffer is, for example, a 96-byte ring buffer, and subcommands are set in order in a plurality of processes, and in the subcommand transmission process, the subcommands set first are transmitted to the subcommand board 330 in order. It is a FIFO.

As shown in FIG. 162, the main CPU 300a reads the value of the subcommand write pointer into the A register (S1), and compares the value of the subcommand write pointer with the value of the subcommand read pointer (S2). Here, if the value of the subcommand write pointer and the value of the subcommand read pointer are the same, that is, if there is no untransmitted subcommand, the zero flag is set to 1, and if they are different, that is, the untransmitted subcommand. If there is, the zero flag does not set to 1.

If the zero flag is 1 (YES in S3), the main CPU 300a terminates the SBC_OUT module, and if the zero flag is not 1 (NO in S3), the subcommand pointer upper limit value and the subcommand read pointer address. The low-order bytes are read into the DE register (S4), and the value of the subcommand read pointer is incremented by 1 if it is less than the upper limit of the subcommand pointer, and cleared to zero if it is greater than or equal to the upper limit of the subcommand pointer by the count-up process that is a general-purpose module (S4). S5).

After that, the main CPU 300a reads the address of the subcommand buffer (transmission buffer) into the HL register (S6), executes the above word data selection process (S7), and then precedes the SCU1 data register for transmitting the subcommand. The command is output (S8), the succeeding command is read into the A register (S9), the succeeding command is output to the SCU1 data register (S10), and the SBC_OUT module is terminated (S11).

FIG. 163 is an explanatory diagram for explaining an example of a command for realizing the SBC_OUT module.

The index “SBC_OUT:” in the first line of FIG. 163 (a) indicates the start address of the SBC_OUT module. Then, by the command "LDQ A, (LOW R_SBC_WPT)" on the second line of FIG. 163 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_SBC_WPT" is set to the lower 1 byte of the address. It is set to 1 byte, and the value stored at that address (the value of the subcommand write pointer) is read into the A register. The command on the second line corresponds to step S1 in FIG.

By the command "CPQ A, (LOW R_SBC_RPT)" on the third line of FIG. 163 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_SBC_RPT" is set to the lower 1 byte of the address. Then, the value stored at that address (the value of the subcommand read pointer) is compared with the value of the A register (the value of the subcommand write pointer). Here, if the value stored at the same address and the value of the A register match, 1 is set in the zero flag. The command on the third line corresponds to step S2 in FIG.

If 1 is set in the zero flag by the command "RET Z" on the fourth line of FIG. 163 (a), the SBC_OUT module is terminated. The command on the fourth line corresponds to step S3 in FIG.

By the command "LD DE, @ LMT_CMD_BFP * 256 + LOW R_SBC_RPT" on the fifth line of FIG. 163 (a), the fixed value "@LMT_CMD_BFP" indicating the upper limit of the subcommand pointer is read into the D register, and the address of the subcommand read pointer. "R_SBC_RPT" indicating the lower byte of is read into the E register. The command on the fifth line corresponds to step S4 in FIG.

The command "RST COUNTUP" on the sixth line of FIG. 163 (a) reads and executes the COUNTUP module, which is a general-purpose module. As a result, the value of the subcommand read pointer is incremented by 1 if it is less than the subcommand pointer upper limit value, and cleared to zero if it is greater than or equal to the subcommand pointer upper limit value. The command on the sixth line corresponds to step S5 in FIG.

The command "LD HL, R_SBC_SBF" on the 7th line of FIG. 163 (a) reads "R_SBC_SBF" indicating the address of the subcommand buffer (transmission buffer) into the HL register. The command on the seventh line corresponds to step S6 in FIG. Here, "R_SBC_SBF" is data having a length of 2 bytes. If the upper 1 byte of the address of the subcommand buffer is "F0H", it can be read by the command "LDQ", but since the upper 1 byte of the subcommand buffer may be "F1H", it may be read. Here, the data having a length of 2 bytes is read without using the command "LDQ".

The command "RST WORDSEL" on the 8th line of FIG. 163 (a) reads the WORDSEL module, which is a general-purpose module, adds the value of the A register to the HL register twice, and among the addresses shown in the HL register, among the addresses shown in the HL register. The value of the low-order byte (the value of the L register, that is, the preceding command) is read into the A register. The command on the eighth line corresponds to step S7 in FIG.

The command "OUT (@ S1DT__), A" on the 9th line of FIG. 163 (a) outputs the value (preceding command) of the A register to the address indicated by the fixed value "@ S1DT__". The command on the ninth line corresponds to step S8 in FIG.

The value of the H register (subsequent command) is read into the A register by the command "LD A, H" on the 10th line of FIG. 163 (a). The command on the 10th line corresponds to S9 in FIG.

The command "OUT (@ S1DT__), A" on the 11th line of FIG. 163 (a) outputs the value of the A register (subsequent command) to the address indicated by the fixed value "@ S1DT__", and the SBC_OUT module is output. finish. The command on the 11th line corresponds to step S10 in FIG. 162, and the command on the 12th line corresponds to step S11 in FIG.

Here, the command group of FIG. 163 (a) can be changed as shown in FIG. 163 (b). Here, the case where the upper 1 byte of the subcommand buffer (transmission buffer) is "F1H" will be described, and the description of the processing substantially equal to that of FIG. 163 (a) will be omitted, and the description thereof will be omitted. Only the different processes will be described.

By the command "LDQP HL, LOW R_SBC_SBF" on the 7th line of FIG. 163 (b), the value obtained by adding 1 to the value of the Q register (that is, "F1H") is at the top, and "R_SBC_SBF" is at the bottom ( The address of the subcommand buffer) is read into the HL register. The command on the seventh line corresponds to step S6 in FIG. 158. The command size of such a command is "3" and the execution cycle is "7 (5)".

Here, the total command size of the command group shown in FIG. 163 (a) is the command "LDQ A, (LOW R_SBC_WPT)" on the second line, 2 bytes + the command "CPQ A, (LOW R_SBC_RPT)" on the third line, 3 bytes. + 4th line command "RET Z" 1 byte + 5th line command "LD DE, @ LMT_CMD_BFP * 256 + LOW R_SBC_RPT" 2 bytes + 6th line command "RST COUNTUP" 1 byte + 7th line command "LD HL, R_SBC_SBF" 3 bytes + 8th line command "RST WORDSEL" 1 byte + 9th line command "OUT (@ S1DT__), A" 2 bytes + 10th line command "LD A, H" 1 byte + 11th line command "OUT ( @ S1DT__), A "2 bytes + 12th line command" RET "1 byte = 19 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 4 cycles + 4th line 3 (1) cycle + 5th line 2 Cycle + 6th row 4 cycles + 7th row 3 cycles + 8th row 4 cycles + 9th row 3 cycles + 10th row 1 cycle + 11th row 3 cycles + 12th row 3 cycles = 32 (30) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RET Z" does not move to the next higher routine.

On the other hand, the total command size of the command group shown in FIG. 163 (b) is the command "LDQ A, (LOW R_SBC_WPT)" on the second line, 2 bytes + the command "CPQ A, (LOW R_SBC_RPT)" on the third line, 3 bytes + 4. Line command "RET Z" 1 byte + 5th line command "LD DE, @ LMT_CMD_BFP * 256 + LOW R_SBC_RPT" 2 bytes + 6th line command "RST COUNTUP" 1 byte + 7th line command "LDQP HL, LOW R_SBC_SBF" 3 bytes + 8th line command "RST WORDSEL" 1 byte + 9th line command "OUT (@ S1DT__), A" 2 bytes + 10th line command "LD A, H" 1 byte + 11th line command "OUT ( @ S1DT__), A "2 bytes + 12th line command" RET "1 byte = 19 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 4 cycles + 4th line 3 (1) cycle + 5th line 2 Cycle + 6th row 4 cycles + 7th row 5 cycles + 8th row 4 cycles + 9th row 3 cycles + 10th row 1 cycle + 11th row 3 cycles + 12th row 3 cycles = 34 (32) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RET Z" does not move to the next higher routine.

Therefore, when the command group of FIG. 163 (a) is replaced with the command group of FIG. 163 (b) to access the address after F100H with "F0" set in the Q register (upper 1). When the bite is "F1H"), the design load can be reduced. When reading the special game special symbol discrimination flag in the special symbol storage area shift process shown in step S610-9 of FIG. 37, the upper 1 byte of the address in which the special game special symbol discrimination flag is stored is set to "F1H". , The command "LDQP" may be used. Further, in the external information management process shown in step S400-29 of FIG. 26, when the composite bit data is saved in the output port 2 buffer, the upper 1 byte of the output port 2 buffer is set to "F1H" and the command "LDQP" is used. May be used. Further, in the backup process when the power is turned off in FIG. 25, when the backup valid judgment value is saved in the backup valid judgment flag, the upper 1 byte of the address in which the backup valid judgment flag is stored is set to "F1H", and the command "LDQP" is set. May be used.

<RCPQ>
FIG. 164 is an explanatory diagram for explaining an example of another command for realizing the SBC_OUT module. Since FIG. 164 (a) is the same as FIG. 163 (a), the description thereof will be omitted. Further, with respect to FIG. 164 (b), the description of the process substantially the same as that of FIG. 164 (a) will be omitted, and only the different processes of FIG. 164 (b) will be described.

By the command "RCPQ Z, A, (LOW R_SBC_RPT)" on the third line of FIG. 164 (b), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_SBC_RPT" is set to the lower 1 byte of the address. It is set to 1 byte, and the value stored at that address (subcommand read pointer value) is compared with the A register value (subcommand write pointer value). If 1 is set in the zero flag, the command "RET" is set. The SBC_OUT module is terminated so as to execute. The command on the third line corresponds to steps S2 to S4 in FIG. The command size of such a command is "3" and the execution cycle is "7 (5)". The number of cycles in parentheses indicates the execution cycle when the command does not move to the next higher routine.

Here, the total command size of the command group shown in FIG. 164 (b) is the command "LDQ A, (LOW R_SBC_WPT)" on the second line + the command "RCPQ Z, A, (LOW R_SBC_RPT)" on the third line. 3 bytes + 4th line command "LD DE, @ LMT_CMD_BFP * 256 + LOW R_SBC_RPT" 2 bytes + 5th line command "RST COUNTUP" 1 byte + 6th line command "LD HL, R_SBC_SBF" 3 bytes + 7th line command "RST" WORDSEL "1 byte + 8th line command" OUT (@ S1DT__), A "2 bytes + 9th line command" LD A, H "1 byte + 10th line command" OUT (@ S1DT__), A "2 bytes +11 The command "RET" on the first line is 1 byte = 18 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 7 (5) cycle + 4th line 2 cycles + 5th line 4 cycles + 6th line 3 cycles + 7th line 4 cycles + 8th row 3 cycles + 9th row 1 cycle + 10th row 3 cycles + 11th row 3 cycles = 32 (30) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RCPQ Z, A, (LOW R_SBC_RPT)" does not move to the next higher routine.

Therefore, by replacing the command group of FIG. 164 (a) with the command group of FIG. 164 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing the game control process.

Further, in order to be able to understand by comparing FIG. 164 (a) and FIG. 164 (b), the command group occupying the second line (third to fourth lines) in FIG. 164 (a) is shown in FIG. In 164 (b), it can be represented by one line (third line), and it is possible to reduce the number of commands themselves and the design load.

FIG. 165 is an explanatory diagram for explaining an example of a command for realizing the FZ_OPN module. The FZ_OPN module shown in FIG. 165 executes a normal electric accessory winning opening opening control process (see FIG. 57).

In the ordinary electric accessory winning opening opening control process, in step S850-5, the counter value of the ordinary electric accessory winning ball number counter has not reached the specified number, that is, 1 at the first variable starting port 120B. It is determined whether or not the same number of game balls as the maximum number of winning games that can be won during the opening / closing control of the times are entered. As a result, if it is determined that the specified number has not been reached, the normal electric accessory winning opening opening control process is terminated, and if it is determined that the specified number has been reached, the process is moved to step S850-7.

As the ordinary electric accessory winning opening opening control process, the index "FZ_OPN:" in the first line of FIG. 165 (a) indicates the start address of the FZ_OPN module. Then, in step S850-5, by the command "LDQ A, (LOW R_FDN_CNT)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_FDN_CNT" is set to the lower 1 byte of the address. The value is set to 1 byte, and the value stored at that address (the counter value of the normal electric accessory winning ball count counter) is read into the A register. The command "CP A, @FDN_CNT" on the third line compares the value of the A register with the fixed value "@FDN_CNT" indicating the specified number, here 8. That is, if the value of the A register is less than 8, the carry flag is set to 1. Then, if the carry flag is 1 according to "RET C" on the 4th line, the FZ_OPN module is terminated. That is, if the counter value of the normal electric accessory winning ball number counter is less than 8, the FZ_OPN module is terminated. If the carry flag is not 1, the subsequent processing is executed.

Here, the command group of FIG. 165 (a) can be changed as shown in FIG. 165 (b). Here, the description of the process substantially the same as that of FIG. 165 (a) will be omitted, and only the different processes of FIG. 165 (b) will be described.

By the command "RCPQ C, (LOW R_FDN_CNT), @ FDN_CNT" on the second line of FIG. 165 (b), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_FDN_CNT" is set to the address. The lower 1 byte is set, and the value stored at that address (counter value of the normal electric accessory winning ball count counter) is compared with the fixed value "@FDN_CNT" indicating the specified number, here, 8 is compared, and the carry flag is set. If it is 1, the FZ_OPN module is terminated so as to execute the command "RET". The command size of such a command is "4" and the execution cycle is "8 (6)". The number of cycles in parentheses indicates the execution cycle when the command does not move to the next higher routine.

Here, the total command size of the command group shown in FIG. 165 (a) is the command "LDQ A, (LOW R_FDN_CNT)" on the second line, 2 bytes + the command "CP A, @ FDN_CNT" on the third line, 3 bytes + 4 lines. The first command "RET C" is 1 byte = 6 bytes, and the total execution cycle is 2 cycles in the 2nd line + 4 cycles in the 3rd line + 3 (1) cycle in the 4th line = 9 (7) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RET C" does not move to the next higher routine.

On the other hand, the total command size of the command group shown in FIG. 165 (b) is the command "RCPQC, (LOW R_FDN_CNT), @ FDN_CNT" on the second line, which is 4 bytes = 4 bytes, and the total execution cycle is the second line. 8 (6) cycles = 8 (6) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RCPQC, (LOW R_FDN_CNT), @FDN_CNT" does not move to the next higher routine.

Therefore, by replacing the command group of FIG. 165 (a) with the command group of FIG. 165 (b), the total command size is reduced by 2 bytes, and the total execution cycle is also reduced by at least one cycle. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in order to be able to understand by comparing FIG. 165 (a) and FIG. 165 (b), the command group that occupied the third line (second to fourth lines) in FIG. 165 (a) is shown in FIG. In 165 (b), it can be represented by one line (second line), and it is possible to reduce the number of commands themselves and the design load.

Further, in the example of FIG. 165 (b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 165 (b), when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, the stack processing is also performed. unnecessary. In this way, resources can be effectively used.

FIG. 166 is an explanatory diagram for explaining an example of a command for realizing the TD_OPN module. The TD_OPN module shown in FIG. 166 executes a large winning opening opening control process (see FIG. 47).

In the large winning opening opening control process, in step S720-5, the counter value of the large winning opening winning ball counter has not reached the specified number, that is, the maximum winning number in one round is possible for the large winning opening. It is determined whether or not the same number of game balls have entered. As a result, if it is determined that the specified number has not been reached, the large winning opening opening control process is terminated, and if it is determined that the specified number has been reached, the process is moved to step S720-7.

As the large winning opening opening control process, the index "TD_OPN:" in the first line of FIG. 166 (a) indicates the start address of the TD_OPN module. Then, in step S720-5, by the command "LDQ A, (LOW R_TDN_FLG)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_TDN_FLG" is set to the lower 1 byte of the address. It is set to 1 byte, and the value (special electric accessory designation flag) stored at that address is read into the A register. The special electric accessory designation flag indicates which large winning opening is the target of the large winning opening opening control process.

The value obtained by subtracting 1 from the address of the large winning opening specified number of winnings data table (the table showing the specified number of the special electric accessory operating ram set table in FIG. 14) by the command "LD HL, D_TDC_MAX-1" on the third line. To the HL register.

The BYTESEL module, which is a general-purpose module, is read by the command "RST BYTESEL" on the fourth line of FIG. 166 (a), the value of the A register is added to the HL register, and the value stored at the address indicated by the HL register. (Specified number) is read into the A register.

By the command "CPQ A, (LOW R_TDN_CNT)" on the fifth line of FIG. 166 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_TDN_CNT" is set to the lower 1 byte of the address. Then, the value stored in the address (counter value of the winning ball number counter of the large winning opening) is compared with the value of the A register, here, 10. That is, if the value stored at the same address is less than 10, the carry flag is not set and the value becomes 0. Then, if the carry flag is 0 according to "RET NC" on the 6th line, the TD_OPN module is terminated. That is, if the counter value of the large winning opening winning ball number counter is less than 10, the TD_OPN module is terminated. If the carry flag is 1, the subsequent processing is executed.

Here, the command group of FIG. 166 (a) can be changed as shown in FIG. 165 (b). Here, the description of the process substantially the same as that shown in FIG. 166 (a) will be omitted, and only the different processes shown in FIG. 165 (b) will be described.

By the command "RCPQ NC, A, (LOW R_TDN_CNT)" on the fifth line of FIG. It is set to 1 byte, and the value stored at that address (counter value of the winning ball number counter of the big winning opening) and the value of the A register (default value), here, 10 are compared, and if the carry flag is 0, , Terminate the TD_OPN module to execute the command "RET". The command size of such a command is "3" and the execution cycle is "7 (5)". The number of cycles in parentheses indicates the execution cycle when the command does not move to the next higher routine.

Here, the total command size of the command group shown in FIG. 166 (a) is the command "LDQ A, (LOW R_TDN_FLG)" on the second line, 2 bytes + the command on the third line, "LD HL, D_TDC_MAX-1", 3 bytes + 4 Line command "RST BYTESEL" 1 byte + 5th line command "CPQ A, (LOW R_TDN_CNT)" 3 bytes + 4th line command "RET NC" 1 byte = 10 bytes, total execution cycle is 2nd line 2 Cycle + 3rd row 3 cycles + 4th row 3 cycles + 5th row 4 cycles + 4th row 3 (1) cycle = 15 (13) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RET NC" does not move to the next higher routine.

On the other hand, the total command size of the command group shown in FIG. 166 (b) is the command "LDQ A, (LOW R_TDN_FLG)" on the second line, 2 bytes + the command on the third line, "LD HL, D_TDC_MAX-1", 3 bytes + 4 lines. The first command "RST BYTESEL" 1 byte + 5th line command "RCPQ NC, A, (LOW R_TDN_CNT)" 3 bytes = 9 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 3 cycles + 4th line 3 Cycle + 5th line 7 (5) cycle = 15 (13) cycle. The number of cycles in parentheses indicates the execution cycle when the command "RCPQ NC, A, (LOW R_TDN_CNT)" does not move to the next higher routine.

Therefore, by replacing the command group of FIG. 166 (a) with the command group of FIG. 166 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing the game control process.

Further, in order to be able to understand by comparing FIG. 166 (a) and FIG. 165 (b), the command group occupying the second line (5th to 6th lines) in FIG. 166 (a) is shown in FIG. In 166 (b), it can be represented by one line (fifth line), and it is possible to reduce the number of commands themselves and the design load.

<JCPQ>
FIG. 167 is an explanatory diagram for explaining an example of a command for realizing the HSY_PRC module. The HSY_PRC module shown in FIG. 167 executes a launch position designation management process (see steps S400-27 in FIG. 26).

As the launch position designation management process, the index “HSY_PRC:” in the first line of FIG. 167 (a) indicates the start address of the HSY_PRC module. The command "XOR A, A" on the second line calculates the exclusive OR of the value of the A register and the value of the A register, and initializes the A register.

Then, the command "LDQ HL, LOW R_TDN_FLG" on the third line reads the value of the Q register into the H register and reads the value of the lower 1 byte of the address "R_TDN_FLG" into the L register.

By the command "JCP NZ, (HL), @ TDK_AT2, HSY_PRC_10" on the 4th line, the value shown in the HL register (special electric accessory designation flag) and the fixed value "@ TDK_AT2" indicating the second big winning opening If 1 is not set in the zero flag, the process is moved to the address indicated by the index "HSY_PRC_10" on the 7th line (processing is branched).

On the other hand, if 1 is set in the zero flag, the value of the Q register is read into the H register by the command "LDQ HL, LOW R_ZUG_CHK_FIX" on the fifth line, and the value of the lower 1 byte of the address "R_ZUG_CHK_FIX" is read into the L register. ..

The value (special symbol judgment flag) indicated in the HL register by the command "JCP NZ, (HL), @ ZUG_SML1, HSY_PRC_20" on the 6th line and the fixed value "@ ZUG_SML1" indicating the small hit symbol 1 designated data, here. Then, it is compared with 07H, and if 1 is not set in the zero flag, it moves to the address shown by the index "HSY_PRC_20" on the 8th line (the process is branched).

Here, the command group of FIG. 167 (a) can be changed as shown in FIG. 167 (b). Here, the description of the process substantially the same as that shown in FIG. 167 (a) will be omitted, and only the different processes shown in FIG. 167 (b) will be described.

The value of the Q register is set to the upper 1 byte of the address and the value of the lower 1 byte of the address "R_TDN_FLG" is set by the command "JCPQ NZ, (LOW R_TDN_FLG), @ TDK_AT2, HSY_PRC_10" on the third line of FIG. 167 (b). The lower 1 byte of the address is used, and the value indicated at that address (special electric accessory designation flag) is compared with the fixed value "@TDK_AT2" indicating the second major winning opening, and if 1 is not set in the zero flag, Move to the address shown in the index "HSY_PRC_10" on the 5th line (branch the process).

The value of the Q register is set to the upper 1 byte of the address by the command "JCPQ NZ, (LOW R_ZUF_CHK_FIX, @ ZUG_SML1, HSY_PRC_20" on the 4th line of FIG. The value (special symbol judgment flag) indicated by the address is compared with the fixed value "@ TDK_AT2" indicating the second big winning opening, and the fixed value "@" indicating the small hit symbol 1 designated data is compared. Compare with "ZUG_SML1", here 07H, and if 1 is not set in the zero flag, move to the address shown in the index "HSY_PRC_20" on the 6th line (branch the process).

Here, the total command size of the command group shown in FIG. 167 (a) is the command "XOR A, A" on the second line, 1 byte + the command "LDQ HL, LOW R_TDN_FLG" on the third line, 2 bytes + the 4th line. Command "JCP NZ, (HL), @ TDK_AT2, HSY_PRC_10" 4 bytes + 5th line command "LDQ HL, LOW R_ZUG_CHK_FIX" 2 bytes + 6th line command "JCP NZ, (HL), @ ZUG_SML1, HSY_PRC_20" 4 bytes = 13 bytes, and the total execution cycle is 1 cycle in the 2nd line + 2 cycles in the 3rd line + 6 (5) cycles in the 4th line + 2 cycles in the 5th line + 2 cycles in the 6th line 6 (5) = 17 (15) cycles. .. The number of cycles in parentheses indicates the execution cycle when the command "JCP NZ, ..." does not move.

On the other hand, the total command size of the command group shown in FIG. 167 (b) is the command "XOR A, A" on the second line + the command "JCPQ NZ, (LOW R_TDN_FLG), @ TDK_AT2, HSY_PRC_10" on the third line. 4 bytes + 4th line command "JCPQ NZ, (LOW R_ZUG_CHK_FIX, @ ZUG_SML1, HSY_PRC_20" 4 bytes = 9 bytes, total execution cycle is 2nd line 1 cycle + 3rd line 6 (5) cycle + 4th line 6 ( 5) = 13 (11) cycles. The number of cycles in parentheses indicates the execution cycle when the command "JCP NZ, ..." does not move.

Therefore, by replacing the command group of FIG. 167 (a) with the command group of FIG. 167 (b), the total command size is reduced by 4 bytes, and the total execution cycle is also reduced by at least 4 cycles. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in order to be able to understand by comparing FIG. 167 (a) and FIG. 167 (b), the command group that occupied the 4th line (3rd to 6th lines) in FIG. 167 (a) is shown in FIG. In 167 (b), it can be represented by two lines (third to fourth lines), and it is possible to reduce the number of commands themselves and the design load.

Further, in the example of FIG. 167 (b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 167 (b), when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, the stack processing is also performed. unnecessary. In this way, resources can be effectively used.

FIG. 168 is an explanatory diagram for explaining an example of a command for realizing the FDN_CHK module. The FDN_CHK module shown in FIG. 168 executes a normal electric accessory winning confirmation process (see step S500-9 in FIG. 28).

As the confirmation process at the time of winning the ordinary electric accessory, the index "FDN_CHK:" in the first line of FIG. 168 (a) indicates the start address of the FDN_CHK module.

Then, by the command "LDQ HL, (LOW R_FDN_EFF)" on the second line, the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address "R_FDN_EFF" is set to the lower 1 byte of the address, and the address is set. (Normally, the value of the electric accessory closing effective timer) is read into the HL register.

If the zero flag is not 1 by the command "RET NTZ" on the third line, the FDN_CHK module is terminated. Here, "NTZ" is used because the second zero flag is changed by the command "LDQ HL, (LOW R_FDN_EFF)", but the first zero flag is not changed.

By the command "LDQ A, (LOW R_FUT_PHS)" on the 4th line, the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address "R_FUT_PHS" is set to the lower 1 byte of the address, and the value of that address. (Normal game management phase) is read into the A register.

By the command "JCP NZ, A, @ FD_OPN, FDN_CHK_10" on the 5th line, the value shown in the A register (normal game management phase) and the fixed value "@FD_OPN" indicating the normal electric accessory winning opening opening control process, Here, it is compared with 04H, and if 1 is not set in the zero flag, the process is moved to the address indicated by the index "FDN_CHK_10" on the 8th line (processing is branched).

On the other hand, if 1 is set in the zero flag, the value of the Q register is set to the upper 1 byte of the address by the command "INCQ (LOW R_FDN_CNT)" on the 6th line, and the value of the lower 1 byte of the address "R_FDN_CNT" is set to the address. Set to the lower 1 byte, add 1 to the value stored at that address (counter value of the normal electric accessory winning ball count counter), store the added value at the same address, and use the command "RET" on the 7th line. , Terminate the FDN_CHK module.

Here, the command group of FIG. 168 (a) can be changed as shown in FIG. 168 (b). Here, the description of the process substantially the same as that shown in FIG. 168 (a) will be omitted, and only the different processes shown in FIG. 168 (b) will be described.

The value of the Q register is set to the upper 1 byte of the address and the value of the lower 1 byte of the address "R_FUT_PHS" is set by the command "JCPQ NZ, (LOW R_FUT_PHS), @ FD_OPN, FDN_CHK_10" on the 4th line of FIG. 168 (b). The lower 1 byte of the address is used, and the value of that address (normal game management phase) is compared with the fixed value "@FD_OPN" indicating the normal electric accessory winning opening opening control process, here 04H, and 1 is set in the zero flag. If not, the process is moved to the address indicated by the index "FDN_CHK_10" on the 7th line (processing is branched).

Here, the total command size of the command group shown in FIG. 168 (a) is the command "LDQ HL, (LOW R_FDN_EFF)" on the second line, 2 bytes + the command "RET NTZ" on the third line, 1 byte + 4th line. Command "LDQ A, (LOW R_FUT_PHS)" 2 bytes + 5th line command "JCP NZ, A, @ FD_OPN, FDN_CHK_10" 3 bytes + 6th line command "INCQ (LOW R_FDN_CNT)" 2 bytes + 7th line command " RET ”1 byte = 11 bytes, and the total execution cycle is 2nd line 4 cycles + 3rd line 3 (1) cycle + 4th line 2 cycles + 5th line 4 (3) cycle + 6th line 5 cycles + 7th line 3 cycles = 21 (18) cycles. The number of cycles in parentheses indicates the execution cycle when the commands "RET NTZ", "JCP NZ, ..." Do not move.

On the other hand, the total command size of the command group shown in FIG. 168 (b) is the command "LDQ HL, (LOW R_FDN_EFF)" on the second line, the command "RET NTZ" on the third line, and the command on the fourth line. "JCPQ NZ, (LOW R_FUT_PHS), @ FD_OPN, FDN_CHK_10" 4 bytes + 5th line command "INCQ (LOW R_FDN_CNT)" 2 bytes + 6th line command "RET" 1 byte = 10 bytes, and the total execution cycle is 2nd row 4 cycles + 3rd row 3 (1) cycles + 4th row 6 (5) cycles + 5th row 5 cycles + 6th row 3 cycles = 19 (16) cycles. The number of cycles in parentheses indicates the execution cycle when the commands "RET NZ" and "JCPQ NTZ, ..." Do not move.

Therefore, by replacing the command group of FIG. 168 (a) with the command group of FIG. 168 (b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least 2 cycles. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in order to be able to understand by comparing FIG. 168 (a) and FIG. 168 (b), the command group occupying the second line (4th to 5th lines) in FIG. 168 (a) is shown in FIG. In 168 (b), it can be represented by one line (fourth line), and it is possible to reduce the number of commands themselves and the design load.

Further, in the example of FIG. 168 (b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 168 (b), when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, the stack processing is also performed. unnecessary. In this way, resources can be effectively used.

FIG. 169 is an explanatory diagram for explaining an example of a command for realizing the FZ_STP module. The FZ_STP module shown in FIG. 169 executes a normal symbol stop symbol display process (see FIG. 54).

As the normal symbol stop symbol display process, the index "FZ_STP:" in the first line of FIG. 169 (a) indicates the start address of the FZ_STP module.

Then, if 1 is not set in the second zero flag by the command "RET NTZ" on the second line, the FZ_STP module is terminated.

By the command "LDQ A, (LOW R_FZ_ATA)" on the third line, the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address "R_FZ_ATA" is set to the lower 1 byte of the address, and the value of that address. (Normal symbol per mark flag) is read into the A register. In addition, the normal symbol hit flag becomes 01H when the hit is decided by the ordinary figure lottery, and becomes 00H when the loss is decided.

By the command "JCP Z, A, @ FZ_ATA, FZ_STP_10" on the 4th line, the value shown in the A register (normal symbol hit flag) is compared with the fixed value "@FZ_ATA" indicating hit, here 01H. If 1 is set in the zero flag, the process moves to the address indicated by the index "FZ_STP_10" on the 8th line (processes are branched).

On the other hand, if 1 is not set in the zero flag, the value of the Q register is set to the upper 1 byte of the address by the command "CLRQ (LOW R_FUT_PHS)" on the 5th line, and the value of the lower 1 byte of the address "R_FUT_PHS" is set to the address. The lower 1 byte is set, and 0 is assigned (cleared) to the value (normal game management phase) stored at that address.

By the command "CLRQ (LOW R_FZ_STP)" on the 6th line, the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address "R_FZ_STP" is set to the lower 1 byte of the address, and the value is stored at that address. Substitute (clear) 0 for the value (normal symbol stop symbol number), and terminate the FZ_STP module by the command "RET" on the 7th line.

Here, the command group of FIG. 169 (a) can be changed as shown in FIG. 169 (b). Here, the description of the process substantially the same as that of FIG. 169 (a) will be omitted, and only the different processes of FIG. 169 (b) will be described.

By the command "JCPQ Z, (LOW R_FZ_ATA), @ FZ_ATA, FZ_STP_10" on the third line of FIG. 169 (b), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "R_FZ_ATA" is set. The lower 1 byte of the address is used, and the value of the address (normal symbol hit flag) is compared with the fixed value "@FZ_ATA" indicating the hit, here 01H. If 1 is set in the zero flag, the 7th line Move to the address indicated by the index "FZ_STP_10" (branch the process).

Here, the total command size of the command group shown in FIG. 169 (a) is the command "RET NTZ" on the second line, 1 byte + the command "LDQ A, (LOW R_FZ_ATA)" on the third line, 2 bytes + the fourth line. Command "JCP Z, A, @ FZ_ATA, FZ_STP_10" 3 bytes + 5th line command "CLRQ (LOW R_FUT_PHS)" 2 bytes + 6th line command "CLRQ (LOW R_FZ_STP)" 2 bytes + 7th line command "RET" 1 byte = 11 bytes, and the total execution cycle is 2nd line 3 (1) cycle + 3rd line 2 cycle + 4th line 4 (3) cycle + 5th line 2 cycle + 6th line 2 cycle + 7th line 3 cycle = 16 (13) It becomes a cycle. The number of cycles in parentheses indicates the execution cycle when the command "RET NTZ", "JCP Z, ..." Does not move to the next higher routine.

On the other hand, the total command size of the command group shown in FIG. 169 (b) is 1 byte of the command "RET NTZ" on the 2nd line + 4 bytes of the command "JCPQ Z, (LOW R_FZ_ATA), @ FZ_ATA, FZ_STP_10" on the 3rd line. + 4th line command "CLRQ (LOW R_FUT_PHS)" 2 bytes + 5th line command "CLRQ (LOW R_FZ_STP)" 2 bytes + 6th line command "RET" 1 byte = 10 bytes, total execution cycle is 2 lines 3 (1) cycle + 3rd row 6 (5) cycle + 4th row 2 cycles + 5th row 2 cycles + 6th row 3 cycles = 16 (13) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RET NTZ", "JCPQ Z, ..." Does not move.

Therefore, by replacing the command group of FIG. 169 (a) with the command group of FIG. 169 (b), the total command size is reduced by 1 byte. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing the game control process.

Further, in order to be able to understand by comparing FIG. 169 (a) and FIG. 169 (b), the command group occupying the second line (third line to the fourth line) in FIG. 169 (a) is shown in FIG. In 169 (b), it can be represented by one line (third line), and it is possible to reduce the number of commands themselves and the design load.

Further, in the example of FIG. 169 (b), the A register is not used. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 169 (b), when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, the stack processing is also performed. unnecessary. In this way, resources can be effectively used.

<Random number generator>
FIG. 170 is a block diagram for explaining the configuration of the random number generators 740 to 746. As described above, the main CPUs 300a and 500a are provided with a plurality of random number generators.

In the main CPUs 300a and 500a, for example, as shown in FIG. 170, a maximum value setting random number generator 740, which is a random number generator capable of setting a 16-bit maximum value, is fixed to 4 channels and a 16-bit maximum value is fixed to 65536. The maximum value fixed random number generator 742, which is a random number generator, has 4 channels, and the maximum value setting random number generator 744, which is a random number generator that can set the maximum value of 8 bits, has 8 channels, and the maximum value of 8 bits is 255. Eight channels of a maximum value fixed random number generator 746, which is a random number generator fixed to the above, are provided. These random number generators 740 to 746 are hardware random number generators (hardware random number generators).

The maximum value setting random number generator 740 can set the random number update cycle to any of 32 to 47 clocks, and sets the start value to 0001h, a value based on the ID number, or a value that is changed every time the system is reset. Can be set. The maximum value fixed random number generator 742 has a random number update cycle of one clock, and the start value is a value that is changed every time the system is reset. The system reset is to reset the state in hardware, and is executed when a predetermined abnormality occurs when the power is turned on.

The maximum value setting random number generator 744 can set the random number update cycle to any of 16 to 31 clocks, and sets the start value to 01h, a value based on the ID number, or a value that is changed every time the system is reset. Can be set. The maximum value fixed random number generator 746 has a random number update cycle of one clock, and the start value is a value that is changed every time the system is reset. In the initial setting process of step S100-1, the start value is set and saved, and the random number update cycle of the maximum value setting random number generators 740 and 744 is set and saved.

Further, the start values of these random number generators 740 to 746 are updated every time the system is reset. Then, the maximum value setting random number generator 740 updates the random number (random number counter) once at any of the 32 clocks to 47 clocks of the internal system clock by the hardware. The maximum value setting random number generator 744 updates the random number (random number counter) once at any of 16 clocks to 31 clocks of the internal system clock by hardware. The maximum value fixed random number generators 742 and 746 update the random number (random number counter) once with one clock of the internal system clock by hardware. Further, these random number generators 740 to 746 update the random numbers according to a certain rule, and the random number sequence is automatically updated every time the random number sequence is cycled. Then, when it is determined by the software that the game ball has passed the predetermined area, a random number (hardware random number count value) is acquired from the random number value register.

Further, in the main CPUs 300a and 500a, it is also possible to generate a software random number by multiplying the random number value acquired from the random number generators 740 to 746 by a predetermined numerical value in the program and dividing the random number value (software random number generator). Is. The software random number generator updates the random number while the interrupt processing generated every 4 ms is not executed. Specifically, the software random number generator compares the previous random number with the maximum value, sets the random number to 0 when the previous random number has reached the maximum value, and the previous random number has not reached the maximum value. In that case, a random number is added by 1. Then, when it is determined that the game ball has passed the predetermined area, a random number (software random number count value) is acquired.

Here, in the game machine 100, as random numbers, a big hit determination random number, a hit symbol random number, a reach group determination random number, a reach mode determination random number, a fluctuation pattern random number, and a hit determination random number are provided.

The jackpot determination random number is in the range of 0 to 65535, the hit symbol random number is in the range of 0 to 99, the reach group determination random number is in the range of 0 to 10066, and the reach mode determination random number is in the range of 0 to 250. The variation pattern random number is in the range of 0 to 238, and the winning determination random number is in the range of 0 to 99.

Further, when a plurality of hit symbols of ordinary symbols are provided, it is necessary to provide a random number of ordinary symbols, for example, in the range of 0 to 99. Further, when a plurality of fluctuation patterns (fluctuation times) of ordinary symbols are provided, it is necessary to provide a random number of fluctuation patterns of ordinary symbols, for example, in the range of 0 to 99.

FIG. 171 is a diagram illustrating a combination of random number generation units. For example, since it is necessary to generate a random number from 0 to 65535 for the jackpot determination random number, a 16-bit random number generated by the maximum value setting random number generator 740 whose maximum value is set to 65535 is used. Since it is necessary to generate a random number from 0 to 99 as the winning symbol random number, an 8-bit random number generated by the software random number generator whose maximum value is set to 99 is used.

Since it is necessary to generate a random number from 0 to 10006 as the reach group determination random number, a 16-bit random number generated by the maximum value setting random number generator 740 whose maximum value is set to 10006 is used. Since it is necessary to generate a random number from 0 to 250 as the reach mode determination random number, an 8-bit random number generated by the software random number generator whose maximum value is set to 250 is used. Since it is necessary to generate a random number from 0 to 238 as the fluctuation pattern random number, an 8-bit random number generated by the software random number generator whose maximum value is set to 238 is used.

Since it is necessary to generate a random number from 0 to 99 as the hit determination random number, an 8-bit random number generated by the maximum value setting random number generator 744 whose maximum value is set to 99 is used. Since it is necessary to generate a random number from 0 to 99 as the normal symbol random number, an 8-bit random number generated by the software random number generator whose maximum value is set to 99 is used. Since it is necessary to generate a random number from 0 to 99 as the normal figure fluctuation pattern random number, an 8-bit random number generated by a software random number generator whose maximum value is set to 99 is used.

Here, when the random number generated by the software random number generator is used, the initial value of the random number is determined in step S100-61 of FIG. 23, step S400-17 of FIG. 26, and step S100-69 of FIG. 23. It is necessary to execute the process of updating the random number. Then, the capacity of the control area for performing the game control process may be compressed.

Therefore, as shown in FIGS. 171 (b) and 171 (c), for example, the jackpot determination random number is in the range of 0 to 65535, the hit symbol random number is in the range of 0 to 99, and the reach group determination random number is in the range of 0 to 10066. The reach mode determination random number is in the range of 0 to 1000, the fluctuation pattern random number is in the range of 0 to 255, the hit determination random number is in the range of 0 to 65535, and the normal symbol random number is in the range of 0 to 99. The fluctuation pattern random number is in the range of 0 to 255. The range of these random numbers is an example, and the maximum value is 65535, which is the maximum value of the maximum value fixed random number generator 742, and the maximum value is 255, which is the maximum value of the maximum value fixed random number generator 746. The random number may be set to any random number.

Then, as shown in FIG. 171 (b), the jackpot determination random number uses a 16-bit random number generated by the maximum value setting random number generator 740 whose maximum value is set to 65535. As the winning symbol determination random number, an 8-bit random number generated by the maximum value setting random number generator 740 whose maximum value is set to 99 is used. As the reach group determination random number, a 16-bit random number generated by the maximum value setting random number generator 740 whose maximum value is set to 10006 is used. As the reach mode determination random number, a 16-bit random number generated by a maximum value setting random number generator whose maximum value is set to 1000 is used. As the variation pattern random number, an 8-bit random number generated by the maximum value fixed random number generator 746 whose maximum value is fixed at 255 is used.

As the hit determination random number, a 16-bit random number generated by the maximum value setting random number generator 740 whose maximum value is set to 65535 is used. As the normal symbol random number, an 8-bit random number generated by the maximum value setting random number generator 744 whose maximum value is set to 99 is used. As the normal figure fluctuation pattern random number, an 8-bit random number generated by the maximum value fixed random number generator 746 whose maximum value is fixed at 255 is used.

Further, as shown in FIG. 171 (c), a 16-bit random number generated by a maximum value fixed random number generator 742 whose maximum value is fixed at 65535 may be used as the jackpot determination random number and the hit determination random number. The maximum value setting random number generator 740 can appropriately set the start value, the random number update cycle, the maximum value of the random number, and the like, but the random number update cycle is slower than the maximum value fixed random number generator 742. Therefore, for the hit / fail random numbers (big hit determination random number and hit determination random number) that are directly linked to the profit of the player, it is preferable to use the maximum value fixed random number generator 742, which has a fast random number update cycle and is difficult to read the random number.

As described above, by using the random numbers generated by the random number generator 740 to 746 (hardware random number generator) as the plurality of random numbers used for the progress of the game, steps S100-61 and FIG. 26 of FIG. 23 described above are used. In steps S400-17 and S100-69 of FIG. 23, it is not necessary to determine the initial value of the random number or execute the process of updating the random number. As a result, the capacity of the main ROM 300b of about 35 bytes can be reduced, and the capacity of the main RAM 300c of about 4 bytes can be reduced. Thus, it is possible to secure the capacity of the control area for performing the game control process.

<Command "OR">
FIG. 172 is a flowchart showing a specific process of the SMC_ROT module. Here, as an arbitrary process, a process of synthesizing a phase flag indicating the position of the reel with the index flag, which is a part of the SMC_ROT module that executes the process during steady rotation, will be described. Here, the index flag is a flag represented by a 1-byte value that is turned ON when an index signal is acquired after the reels 410a, 410b, and 410c have reached the steady rotation speed. For example, when the index signal of the left reel 410a is acquired, the bit 0 of the index flag becomes 1, the bit 1 of the index flag becomes 1 when the index signal of the middle reel 410b is acquired, and when the index signal of the right reel 410c is acquired, the index flag bit 0 becomes 1. Bit 2 becomes 1. By referring to such an index flag, it is possible to confirm which reels 410a, 410b, 410c have acquired the index signal. Further, the phase flag is a flag indicated by one byte that identifies the reels 410a, 410b, 410c being processed. For example, bit 0 of the phase flag becomes 1 (00000001B) during processing of the left reel 410a, bit 1 of the phase flag becomes 1 (00000010B) during processing of the middle reel 410b, and the phase flag becomes 1 during processing of the right reel 410c. Bit 2 becomes 1 (00000100B). The numerical value of step S in such a figure will be used only in the description of this figure. Further, in the description of the SMC_ROT module, the first register is the C register, the second register is the HL register, and the register different from the first register and the second register is the A register.

At the stage of executing the SMC_ROT module, it is assumed that the value of the phase flag is already held in a predetermined register (for example, C register). Then, the main CPU 500a executes an arbitrary process as shown in FIG. 172. First, the main CPU 500a sets the address of the index flag (variable) to be ORed in the HL register (S1). Then, in order to synthesize the phase flag with the index flag, the main CPU 500a calculates the logical sum of the already set C register value (phase flag) and the 1-byte value stored in the address indicated by the HL register. Then, in order to reflect the result of the logical sum in the index flag, the value stored in the address indicated by the HL register is overwritten (S2). Here, synthesis means that when any bit of the phase flag which is a variable is set (if it is 1,) the same bit of the index flag is also set (set to 1). Therefore, since the phase flags are set for the reels 410a, 410b, and 410c being processed, the corresponding bit of the index flag is set by synthesis regardless of whether or not the index signal is acquired. Further, when all the index signals are acquired (when all the reels 410a, 410b, 410c have a steady rotation speed), all the bits corresponding to each reel of the index flag are set regardless of the phase flag (000000111B). Become. Then, the SMC_ROT module is terminated by moving to the PRE_PLS module that executes the excitation pattern update preprocessing (S3). In this way, it is possible to synthesize the phase flag with the index flag.

FIG. 173 is an explanatory diagram for explaining an example of a command for realizing the SMC_ROT module. The flowchart shown in FIG. 172 is realized by, for example, the program shown in FIG. 173.

The index “SMC_ROT:” in the first line of FIG. 173 indicates the start address of the SMC_ROT module. The command "LDQ HL, LOW_IDX_FND" on the second line reads the value of the Q register into the H register and the value of the lower 1 byte of the address "_IDX_FND" into the L register. The command on the second line corresponds to step S1 in FIG. 172.

The command "LD A, (HL)" on the third line of FIG. 173 reads the 1-byte value (index flag value) stored at the address indicated by the HL register into the A register. The command "OR A, C" on the fourth line calculates the logical sum of the value of the A register and the value of the C register, and the A register is updated according to the calculation result. Then, the value of the A register is stored in the address indicated by the HL register by the command "LD (HL), A" on the fifth line. That is, the value of the A register is overwritten with the 1-byte value stored at the address indicated by the HL register, and the value of the index flag is updated. The commands on the 3rd to 5th lines correspond to step S2 in FIG. 172.

The command "JP PRE_PLS" on the sixth line of FIG. 173 moves to the index "PRE_PLS:" indicating the start address of the PRE_PLS module. The command on the sixth line corresponds to step S3 in FIG. 172.

As described above, the total command size of the SMC_ROT module command shown in FIG. 173 is the command "LDQ HL, LOW_IDX_FND" on the second line + 2 bytes + the command "LD A, (HL)" on the third line + 4 lines. First command "OR A, C" 1 byte + 5th line command "LD (HL), A" 1 byte + 6th line command "JP PRE_PLS" 3 bytes = 8 bytes, total execution cycle is 2nd line 2 cycles + 3rd row 2 cycles + 4th row 1 cycle + 5th row 2 cycles + 6th row 3 cycles = 10 cycles. By providing the processing of the 3rd to 5th lines in the SMC_ROT module, it is possible to easily combine (logically) the index flag and the phase flag stored as variables.

FIG. 174 is an explanatory diagram for explaining another example of the command for realizing the SMC_ROT module. Here, the command group of the SMC_ROT module of FIG. 173 is replaced with the command group of the SMC_ROT module of FIG. 174.

The index “SMC_ROT:” in the first line of FIG. 174 indicates the start address of the SMC_ROT module. The command "LDQ HL, LOW_IDX_FND" on the second line reads the value of the Q register into the H register and the value of the lower 1 byte of the address "_IDX_FND" into the L register.

The command "OR (HL), C" on the third line of FIG. 174 calculates the logical sum of the 1-byte value stored in the address indicated by the HL register and the value of the C register, and the calculation result is calculated as HL. Store at the address indicated by the register. That is, the calculation result is overwritten with the 1-byte value stored in the address indicated by the HL register, and the value of the index flag is updated. The command on the third line corresponds to step S2 in FIG. 172.

The command "JP PRE_PLS" on the fourth line of FIG. 174 moves to the index "PRE_PLS:" indicating the start address of the PRE_PLS module. The command on the fourth line corresponds to step S3 in FIG. 172.

The total command size of the SMC_ROT module command shown in FIG. 174 is the command "LDQ HL, LOW_IDX_FND" on the second line + the command "OR (HL), C" on the third line + the command "OR (HL), C" on the fourth line. "JP PRE_PLS" 3 bytes = 7 bytes, and the total execution cycle is 2 cycles in the 2nd line + 5 cycles in the 3rd line + 3 cycles in the 4th line = 10 cycles. Therefore, the total command size is reduced by 1 byte as compared with the case of FIG. 173. With such an SMC_ROT module, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

Further, as can be understood by comparing FIG. 173 and FIG. 174, the command group that occupied the third line (third to fifth lines) in FIG. 173 is changed to the first line (third line) in FIG. 174. ), It is possible to reduce the number of commands themselves and the design load.

In addition, although the command "OR (HL), C" for executing the logical sum has been described here, the command "AND (HL), C" for executing the logical product and the exclusive logic are not limited to this case. Even the sum "XOR (HL), C" can be replaced in the same way as the logical sum, and the total command size can be reduced by 1 byte. The register for storing the address of the variable is not limited to the HL register but may be the DE register. Further, the register to be ORed is not limited to the C register, and A register, B register, D register, E register, H register, and L register can be adopted.

Further, here, the A register is not used as compared with the example of FIG. 173. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 173, when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, stack processing is not required. In this way, resources can be effectively used.

<Command "LDF">
FIG. 175 is a flowchart showing a specific process of the INITIAL module. Here, as an arbitrary process, a built-in register area setting process that is a part of the INITIAL module that executes the CPU initialization process shown in step S2000 of FIG. 82 will be described. The numerical value of step S in such a figure will be used only in the description of this figure. Further, in the description of the INITIAL module, the first register is an HL register.

The main CPU 500a executes an arbitrary process as shown in FIG. 175. First, the main CPU 500a sets the start address of the CPU built-in register setting data table (data table) in the HL register (S1). Then, the main CPU 500a sets the number of set data (S2).

Subsequently, the main CPU 500a sets the address and the setting data of the built-in register accessible through the input / output unit in the C register and the A register, respectively (S3). Next, the value (setting data) of the A register is output to the built-in register indicated by the C register (S4). Subsequently, the main CPU 500a decrements (subtracts “1”) the value (number of set data) of the B register, and determines whether or not the decrement result is 0 (S5). Here, if the decremented result is not 0 (NO in S5), the process from step S3 is repeated, and if the decremented result is 0 (YES in S5), the process proceeds to the next process.

FIG. 176 is an explanatory diagram for explaining an example of a command for realizing the INITIAL module. Of these, FIG. 176 (a) shows the command group of the INITIAL module, and FIG. 176 (b) shows the arrangement of the 1-byte data group in the program data of the main ROM 500b. The flowchart shown in FIG. 175 is realized by, for example, the program shown in FIG. 176.

The index "INITIAL:" in the first line of FIG. 176 (a) indicates the start address of the INITIAL module. The command "LD HL, T_CPU_REG" on the second line reads the start address "T_CPU_REG" of the CPU built-in register setting data table into the HL register. The command on the second line corresponds to step S1 in FIG. 175. The command "LD B, @ NUM_CPU_REG" on the third line reads the number of set data stored in the address "@NUM_CPU_REG" into the B register. The command on the third line corresponds to step S2 in FIG. 175.

The command "EQUA ($ -T_CPU_REG) / 2" is described in the address "@NUM_CPU_REG" so that it can be understood by referring to the 22nd line of FIG. 176 (b). Here, "$" is the address next to the final address of the 1-byte data group that is the transfer source, that is, the address "@NUM_CPU_REG" itself, and "T_CPU_REG" is the start address of the 1-byte data group that is the transfer source. Therefore, the value of the value of $ -T_CPU_REG (1 byte value indicating the number of data) becomes the total number of bytes of the 1-byte value, and when that value is divided by 2, which is the number of combinations of addresses and values, the number of set data Is derived. For example, in the example of FIG. 176 (b), the number of set data is 20/2 = 10.

The index "INITIAL01:" on the fourth line of FIG. 176 (a) indicates the start address of the iterative process. By the command "LDIN AC, (HL)" on the 5th line, the value stored in the address indicated by the HL register is stored in the C register, and is stored in the address indicated by the value obtained by adding "1" to the HL register. The value is stored in the A register. The command on the fifth line corresponds to step S3 in FIG. 175. The command "OUT (C), A" on the sixth line outputs the value (setting data) of the A register to the value (built-in register) indicated by the C register. The command on the sixth line corresponds to step S4 in FIG. 175.

For example, when the HL register is the value of the address "T_CPU_REG", the 1-byte value "@ PT0PR__" in the second line of FIG. 176 (b) is stored in the C register, and in the third line of FIG. 176 (b). The value of "120" is stored in the A register. Then, the value of the A register, that is, the value of "120" is output to the value of the C register, that is, the address indicated by "@ PT0PR__".

Subsequently, the command "DJNZ INITIAL01" on the 7th line of FIG. 176 (a) decrements the value of the B register (subtracts "1"), and if the decremented result is not 0, the process is moved to the address "INITIAL01". If the result of decrementing is 0, the process is moved to the command next to the command. Here, since the number of data is "10", the value of the B register becomes 0 when the process from "INITIAL01" is repeated 10 times. The command on the seventh line corresponds to step S5 in FIG. 175.

As described above, the total command size of the commands of the INITIAL module shown in FIG. 176 (a) is the command "LD HL, T_CPU_REG" on the second line 3 bytes + the command "LD B, @ NUM_CPU_REG" on the third line + 5 Line command "LDIN AC, (HL)" 2 bytes + 6th line command "OUT (C), A" 2 bytes + 7th line command "DJNZ INITIAL01" 2 bytes = 11 bytes, and the total execution cycle is 2nd row 3 cycles + 3rd row 2 cycles + 5th row 4 cycles + 6th row 3 cycles + 7th row 3 cycles (2 cycles) = 15 cycles (14 cycles). The number of cycles in parentheses indicates the execution cycle when the command "DJNZ INITIAL01" does not move. Here, since the number of set data = 10, the command on the 5th to 7th lines is repeated 10 times. Therefore, the actual total execution cycle is 2nd row 3 cycles + 3rd row 2 cycles + (5th row 4 cycles + 6th row 3 cycles + 7th row 3 cycles) x 9 loops + (5th row 4 cycles + 6th row) 3 cycles + 7th line 2 cycles) = 104 cycles. With such an INITIAL module, setting data can be set in an internal register.

FIG. 177 is an explanatory diagram for explaining another example of the command for realizing the INITIAL module. Here, the command group of the INITIAL module of FIG. 176 (a) is replaced with the command group of the INITIAL module of FIG. 177 (a), and other 1-byte data in the program data of the main ROM 500b of FIG. 176 (b). The group is used as it is as shown in FIG. 177 (b).

The index "INITIAL:" in the first line of FIG. 177 (a) indicates the start address of the INITIAL module. The command "LDF HL, T_CPU_REG" on the second line reads the start address "T_CPU_REG" of the CPU built-in register setting data table into the HL register. The command on the second line corresponds to step S1 in FIG. 175.

Here, the command "LDF HL, mn" is a command for storing the value of "mn" in the HL register. The command size of such a command is "2" and the execution cycle is "2". On the other hand, the commonly used load command "LD HL, mn" is also a command that stores the value of "mn" in the HL register, but the command size of the command is "3" and the execution cycle is "3". Is. Therefore, the command size is reduced by 1 byte and executed by changing "LD" to "LDF" on condition that mn is in the range of 1200H to 1DFFH on the memory map and is loaded in the HL register. The cycle is also reduced by one cycle.

As described above, the value of mn in the command "LDF HL, mn" must be one of 1200H to 1DFFH in the memory map. Therefore, in the present embodiment, the program data is arranged in the range of 1200H to 1DFFH in the used area of the main ROM 500b, and the command "LDF HL, mn" is used only when reading the data in such a range. The assemble code of "LDF HL, 1200H" is represented as 6A00H, which is the target address "1200H" plus 5800H. Therefore, the assemble codes of "LDF HL, 1200H" to "LDF HL, 1DFFH" are 6A00H to 75FFH.

The command "LD B, @ NUM_CPU_REG" on the third line of FIG. 177 (a) reads the number of set data stored in the address "@NUM_CPU_REG" into the B register. The command on the third line corresponds to step S2 in FIG. 175.

The index "INITIAL01:" on the fourth line of FIG. 177 (a) indicates the start address of the iterative process. By the command "LDIN AC, (HL)" on the 5th line, the value stored in the address indicated by the HL register is stored in the C register, and is stored in the address indicated by the value obtained by adding "1" to the HL register. The value is stored in the A register. The command on the fifth line corresponds to step S3 in FIG. 175. The command "OUT (C), A" on the sixth line outputs the value (setting data) of the A register to the value (built-in register) indicated by the C register. The command on the sixth line corresponds to step S4 in FIG. 175.

Subsequently, the command "DJNZ INITIAL01" on the 7th line of FIG. 177 (a) decrements the value of the B register (subtracts "1"), and if the decremented result is not 0, the process is moved to the address "INITIAL01". If the result of decrementing is 0, the process is moved to the command next to the command. Here, since the number of data is "10", the value of the B register becomes 0 when the process from "INITIAL01" is repeated 10 times. The command on the seventh line corresponds to step S5 in FIG. 175.

As described above, the total command size of the commands of the INITIAL module shown in FIG. 177 (a) is the command "LDF HL, T_CPU_REG" on the second line 2 bytes + the command "LD B, @ NUM_CPU_REG" on the third line + 5 Line command "LDIN AC, (HL)" 2 bytes + 6th line command "OUT (C), A" 2 bytes + 7th line command "DJNZ INITIAL01" 2 bytes = 10 bytes, and the total execution cycle is 2nd row 2 cycles + 3rd row 2 cycles + 5th row 4 cycles + 6th row 3 cycles + 7th row 3 cycles (2 cycles) = 14 cycles (13 cycles). The number of cycles in parentheses indicates the execution cycle when the command "DJNZ INITIAL01" does not move. Here, since the number of set data = 10, the command on the 5th to 7th lines is repeated 10 times. Therefore, the actual total execution cycle is 2nd line 2 cycles + 3rd line 2 cycles + (5th line 4 cycles + 6th line 3 cycles + 7th line 3 cycles) x 9 loops + (5th line 4 cycles + 6th line) 3 cycles + 7th line 2 cycles) = 103 cycles. Therefore, it can be understood that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle as compared with the case of FIG. 176 (a). With such an INITIAL module, it is possible to further shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

In the above-described embodiment, in the process of setting the setting data in the internal register by citing the INITIAL module, the command "LD HL, T_CPU_REG" is replaced with the command "LDF HL, T_CPU_REG" to further shorten the command and further shorten the command. , An example of reducing the processing load was explained. However, such a command can be applied not only to the INITIAL module but also to various modules.

For example, the command "LD HL, T_SEG_PTN" also exists in the DGEXTRN module that executes the display data conversion process, and the start address "T_SEG_PTN" of the main display display pattern data table is read into the HL register as in the INITIAL module. There is. Further, the start address "T_SEG_PTN" is included in the range of 1200H to 1DFFH. Therefore, even in the DGEXTRN module, by changing the command "LD HL, T_SEG_PTN" to the command "LDF HL, T_SEG_PTN", the command can be further shortened and the processing load can be reduced.

Further, the command "LD HL, T_FIG_LIN" also exists in the GET_ARY module that executes the symbol array data acquisition process, and the start address "T_FIG_LIN" of the symbol array offset table for each effective line is read into the HL register as in the INITIAL module. ing. Further, the start address "T_FIG_LIN" is included in the range of 1200H to 1DFFH. Therefore, also in the GET_ARY module, by changing the command "LD HL, T_FIG_LIN" to the command "LDF HL, T_FIG_LIN", the command can be further shortened and the processing load can be reduced.

By keeping the transfer source address in the range of 1200H to 1DFFH in this way, most of the commands "LD HL, mn" can be replaced with the command "LDF HL, mn". By applying such replacement to all the processes in the present embodiment, for example, the total command size can be shortened by 80 to 90 bytes.

Such a command "LDF" can be adopted not only in the above-mentioned INITIAL module but also in various modules such as a RANKSET module. Further, it can be adopted not only in slot machines but also in pachinko machines, for example, PWRFAIL modules and DYM_OUT modules.

FIG. 178 is an explanatory diagram for explaining the RANKSET module. The RANKSET module shown in FIG. 85 performs a set value switching process, that is, switches a set value and updates the set value data. Here, the data table set processing at the time of switching the set value in step S2020-5 in the RANKSET module will be described.

The index “RANKSET:” in the first line of FIG. 178 (a) indicates the start address of the RANKSET module. The command "LD HL, T_RNK_SET" on the second line reads the start address "T_RNK_SET" of the data table at the time of switching the set value into the HL register. The command "RST TABLEST" on the third line calls the TABLEST module described with reference to FIG. 119 as a subroutine. Since such a TABLEST module has already been described, detailed description thereof will be omitted here. Here, two variables (_WIN_DAT and _EXT_RQ) in the set value switching data table are set to predetermined values.

Here, if the command "LDF" is replaced, the command group of FIG. 178 (a) can be changed as shown in FIG. 178 (b). The index “RANKSET:” in the first line of FIG. 178 (b) indicates the start address of the RANKSET module. The command "LDF HL, T_RNK_SET" on the second line reads the start address "T_RNK_SET" of the data table at the time of switching the set value into the HL register. The start address "T_RNK_SET" of the data table at the time of switching the set value is arranged in the range of 1200H to 1DFFH in the used area of the main ROM 500b. The command "RST TABLEST" on the third line calls the TABLEST module described with reference to FIG. 119 as a subroutine. In this way, as in FIG. 178 (a), two variables (_WIN_DAT and _EXT_RQ) in the set value switching data table are set to predetermined values.

Here, the total command size of the command of the RANKSET module shown in FIG. 178 (a) is 3 bytes of the command "LD HL, T_RNK_SET" on the second line + 1 byte = 4 bytes of the command "RST TABLEST" on the third line. The total execution cycle is 3 cycles in the 2nd row + 4 cycles in the 3rd row = 7 cycles. On the other hand, the total command size of the command of the RANKSET module shown in FIG. 178 (b) is 2 bytes of the command "LDF HL, T_RNK_SET" on the 2nd line + 1 byte = 3 bytes of the command "RST TABLEST" on the 3rd line. The execution cycle is 2 cycles in the 2nd line + 4 cycles in the 3rd line = 6 cycles. Therefore, it can be understood that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle as compared with the case of FIG. 178 (a). With such a RANKSET module, it is possible to further shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

FIG. 179 is an explanatory diagram for explaining the PWRFAIL module. The PWRFAIL module shown in FIG. 25 performs a power-off save process, that is, switches a set value and updates the set value data. Here, the output port clearing process of step S300-11 in the PWRFAIL module will be described.

Here, it is assumed that 00H is set in the A register in advance as the initial value of the output port. The index “PWRFAIL:” in the first line of FIG. 179 (a) indicates the start address of the PWRFAIL module. The command "LD HL, D_OUT_PRT" on the second line reads the start address "D_OUT_PRT" of the output port address table into the HL register. The command "LD B, @PRT_CLR_LOP" on the third line reads the output port initialization loop counter value (13 in this case) stored in the address "@PRT_CLR_LOP" into the B register as the number of loops.

The index “PWRFAIL_20:” on the fourth line of FIG. 179 (a) indicates the start address of the iterative process. The command "LD C, (HL)" on the fifth line reads the value (output port address) stored in the address indicated by the HL register into the C register. By the command "OUT (C), A" on the sixth line, the value of the A register (00H in this case) is output to the value (built-in register) indicated by the C register, and the output port is cleared.

Subsequently, the value of the HL register is incremented by 1 by the command "INC HL" on the 7th line of FIG. 179 (a). The command "DJNZ PWRFAIL_20" on the 8th line decrements the value of the B register (subtracts "1"), and if the decremented result is not 0, it moves to the address "PWRFAIL_20" and if the decremented result is 0. , Moves the process to the next command of the command. Here, since the number of data is "13", the value of the B register becomes 0 when the process from "PWRFAIL_20" is repeated 13 times. In this way, the output port is cleared.

Here, if the command "LDF" is replaced, the command group of FIG. 179 (a) can be changed as shown in FIG. 179 (b). Here, too, it is assumed that 00H is set in the A register in advance as the initial value of the output port. The index “PWRFAIL:” in the first line of FIG. 179 (b) indicates the start address of the PWRFAIL module. The command "LDF HL, D_OUT_PRT" on the second line reads the start address "D_OUT_PRT" of the output port address table into the HL register. The start address "D_OUT_PRT" of the output port address table is arranged in the range of 1200H to 1DFFH in the used area of the main ROM 500b. The command "LD B, @PRT_CLR_LOP" on the third line reads the output port initialization loop counter value (13 in this case) stored in the address "@PRT_CLR_LOP" into the B register as the number of loops.

The index “PWRFAIL_20:” on the fourth line of FIG. 179 (b) indicates the start address of the iterative process. The command "LD C, (HL)" on the fifth line reads the value (output port address) stored in the address indicated by the HL register into the C register. By the command "OUT (C), A" on the sixth line, the value of the A register (00H in this case) is output to the value (built-in register) indicated by the C register, and the output port is cleared.

Subsequently, the value of the HL register is incremented by 1 by the command "INC HL" on the 7th line of FIG. 179 (b). The command "DJNZ PWRFAIL_20" on the 8th line decrements the value of the B register (subtracts "1"), and if the decremented result is not 0, it moves to the address "PWRFAIL_20" and if the decremented result is 0. , Moves the process to the next command of the command. Here, since the number of data is "13", the value of the B register becomes 0 when the process from "PWRFAIL_20" is repeated 13 times. In this way, the output port is cleared.

Here, the total command size of the commands of the PWRFAIL module shown in FIG. 179 (a) is the command "LD HL, D_OUT_PRT" on the second line 3 bytes + the command "LD B, @ PRT_CLR_LOP" on the third line 2 bytes + 5 lines. 1st line command "LD C, (HL)" 1 byte + 6th line command "OUT (C), A" 2 bytes + 7th line command "INC HL" 1 byte + 8th line command "DJNZ PWRFAIL_20" 2 bytes = 11 bytes, and the total execution cycle is 2nd row 3 cycles + 3rd row 2 cycles + 5th row 2 cycles + 6th row 3 cycles + 7th row 1 cycle + 8th row 3 cycles (2 cycles) = 14 cycles (13 cycles) ). Here, since the output port initialization loop counter value = 13, the commands on the 5th to 8th lines are repeated 13 times. Therefore, the actual total execution cycle is 2nd row 3 cycles + 3rd row 2 cycles + (5th row 2 cycles + 6th row 3 cycles + 7th row 1 cycle + 8th row 3 cycles) x 12 loops + (5th row) 2 cycles + 6th row 3 cycles + 7th row 1 cycle + 8th row 2 cycles) = 121 cycles.

On the other hand, the total command size of the commands of the PWRFAIL module shown in FIG. 179 (b) is 2 bytes of the command "LDF HL, D_OUT_PRT" on the 2nd line + 2 bytes of the command "LD B, @ PRT_CLR_LOP" on the 3rd line + 5th line. Command "LD C, (HL)" 1 byte + 6th line command "OUT (C), A" 2 bytes + 7th line command "INC HL" 1 byte + 8th line command "DJNZ PWRFAIL_20" 2 bytes = It becomes 10 bytes, and the total execution cycle is 2nd row 2 cycles + 3rd row 2 cycles + 5th row 2 cycles + 6th row 3 cycles + 7th row 1 cycle + 8th row 3 cycles (2 cycles) = 13 cycles (12 cycles) It becomes. Here, since the output port initialization loop counter value = 13, the commands on the 5th to 8th lines are repeated 13 times. Therefore, the actual total execution cycle is 2nd row 2 cycles + 3rd row 2 cycles + (5th row 2 cycles + 6th row 3 cycles + 7th row 1 cycle + 8th row 3 cycles) x 12 loops + (5th row) 2 cycles + 6th row 3 cycles + 7th row 1 cycle + 8th row 2 cycles) = 120 cycles. Therefore, it can be understood that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle as compared with the case of FIG. 179 (a). With such a PWRFAIL module, it is possible to further shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

FIG. 180 is an explanatory diagram for explaining the DYM_OUT module. The DYM_OUT module shown in step S400-5 of FIG. 26 has a first special symbol display 160, a second special symbol display 162, a first special symbol hold indicator 164, a second special symbol hold indicator 166, and a normal symbol. A dynamic port output process for lighting control of the display 168, the normal symbol hold display 170, the right-handed notification display 172, and the performance display monitor 184 is executed.

The index “DYM_OUT:” in the first line of FIG. 180 (a) indicates the start address of the DYM_OUT module. The command "LD HL, D_DYM_SEL" on the second line reads the start address "D_DYM_SEL" of the dynamic display selection table into the HL register. The command "RST WORDSEL" on the third line calls the WORDSEL module described with reference to FIGS. 108 to 111 as a subroutine. Since such a WORDSEL module has already been described, detailed description thereof will be omitted here. In this way, four 2-byte data in the dynamic display selection table are selected.

Here, if the command "LDF" is replaced, the command group in FIG. 180 (a) can be changed as shown in FIG. 180 (b). The index “DYM_OUT:” in the first line of FIG. 180 (b) indicates the start address of the DYM_OUT module. The command "LDF HL, D_DYM_SEL" on the second line reads the start address "D_DYM_SEL" of the dynamic display selection table into the HL register. The start address "D_DYM_SEL" of the dynamic display selection table is arranged in the range of 1200H to 1DFFH in the used area of the main ROM 500b. The command "RST WORDSEL" on the third line calls the WORDSEL module described with reference to FIGS. 108 to 111 as a subroutine. In this way, four 2-byte data in the dynamic display selection table are selected.

Here, the total command size of the commands of the DYM_OUT module shown in FIG. 180A is 3 bytes for the command "LD HL, D_DYM_SEL" on the second line + 1 byte = 4 bytes for the command "RST WORDSEL" on the third line. The total execution cycle is 3 cycles in the 2nd row + 4 cycles in the 3rd row = 7 cycles. On the other hand, the total command size of the commands of the DYM_OUT module shown in FIG. 180 (b) is 2 bytes for the command "LDF HL, D_DYM_SEL" on the second line + 1 byte = 3 bytes for the command "RST WORDSEL" on the third line. The execution cycle is 2 cycles in the 2nd line + 4 cycles in the 3rd line = 6 cycles. Therefore, it can be understood that the total command size is reduced by 1 byte and the total execution cycle is reduced by 1 cycle as compared with the case of FIG. 180 (a). With such a DYM_OUT module, it is possible to further shorten the command, reduce the processing load, and secure the capacity of the control area for performing the game control processing.

<Command "SET">
FIG. 181 is a flowchart showing a specific process of the IPT_PD module. Here, as an arbitrary process, in the CAL_MOD module for executing the state-specific module execution process shown in step S3100-21 of FIG. 98, once every four times according to the timer interrupt processing phase (0 to 3). The process of selectively shifting (every 5.96 msec) and setting the external signal 4 which is a part of the IPT_PD module that executes the external signal output control process will be described. The numerical value of step S in such a figure will be used only in the description of this figure. Further, in the description of the IPT_PD module, the predetermined register is the HL register.

The main CPU 500a executes an arbitrary process as shown in FIG. 181. First, the main CPU 500a performs a counter subtraction process related to the external signal output holding timer (S1). Then, the main CPU 500a sets the address of the output port 3 image in the HL register (S2). Subsequently, the main CPU 500a determines whether or not the security signal ON condition is satisfied by the subtraction process in step S1, and if the ON condition is satisfied, the external signal 4, that is, the predetermined value of the address indicated by the HL register is determined. Make the bit stand (set to 1) (S3). Then, the IPT_PD module is terminated and the routine returns to the next higher routine (S4). In this way, the external signal 4 can be set.

FIG. 182 is an explanatory diagram for explaining an example of a command for realizing the IPT_PD module. The flowchart shown in FIG. 181 is realized by, for example, the program shown in FIG. 182.

The index “IPT_PD:” in the first line of FIG. 182 indicates the start address of the IPT_PD module. The command "RST RAM_DEC" on the second line is a command that calls a general-purpose module that decrements a variable by one, and this command subtracts the counter related to the external signal output holding timer. Here, at least the zero flag is updated by the command "RST RAM_DEC". The command on the second line corresponds to step S1 in FIG. 181. The command "LDQ HL, LOW_OUT_PT3" on the third line reads the value of the Q register into the H register and the value of the lower 1 byte of the address "_OUT_PT3" into the L register. The zero flag does not change depending on the command "LDQ HL, LOW_OUT_PT3". The command on the third line corresponds to step S2 in FIG.

The command "JR Z, IPT_PD03" on the fourth line of FIG. 182 determines whether or not the subtraction result of the command "RST RAM_DEC" on the second line is zero, and if it is zero (if the zero flag is set). That is, if the security signal ON condition is not satisfied, the movement is performed to the index "IPT_PD03:" on the sixth line, and if it is not zero (if the zero flag is not set), the next processing is performed. The command "SET @ EXT_SG4_POS, (HL)" on the fifth line is the value defined by @ EXT_SG4_POS (here, 2) in the output port 3 image, that is, the value stored in the address indicated by the HL register. Make a bit stand. The index "IPT_PD03:" on the 6th line indicates the destination of the command "JR Z, IPT_PD03" on the 4th line. The commands on the 4th to 6th lines correspond to step S3 in FIG. 181. Then, the command "RET" on the 7th line of FIG. 182 returns to the routine one step higher. The command on the seventh line corresponds to step S4 in FIG.

As described above, the total command size of the commands of the IPT_PD module shown in FIG. 182 is the command "RST RAM_DEC" on the second line + the command "LDQ HL, LOW_OUT_PT3" on the third line, and the command "LDQ HL, LOW_OUT_PT3" on the fourth line. JR Z, IPT_PD03 "2 bytes + 5th line command" SET @ EXT_SG4_POS, (HL) "2 bytes + 7th line command" RET "1 byte = 8 bytes, and the total execution cycle is the command" JR Z, IPT_PD03 " If not moved by, 2nd line 4 cycles + 3rd line 2 cycles + 4th line 2 cycles + 5th line 5 cycles + 7th line 3 cycles = 16 cycles, and if moved by the command "JR Z, IPT_PD03", 2 4th row 4 cycles + 3rd row 2 cycles + 4th row 3 cycles + 7th row 3 cycles = 12 cycles. By providing the processing of the 4th to 6th lines in the IPT_PD module, the bit operation of the output port 3 image can be performed according to the subtraction result.

FIG. 183 is an explanatory diagram for explaining another example of the command for realizing the IPT_PD module. Here, the command group of the IPT_PD module of FIG. 182 is replaced with the command group of the IPT_PD module of FIG. 183.

The index “IPT_PD:” in the first line of FIG. 183 indicates the start address of the IPT_PD module. The command "RST RAM_DEC" on the second line is a command that calls a general-purpose module that decrements a variable by one, and this command subtracts the counter related to the external signal output holding timer. Here, at least the zero flag is updated by the command "RST RAM_DEC". The command on the second line corresponds to step S1 in FIG. 181. The command "LDQ HL, LOW_OUT_PT3" on the third line reads the value of the Q register into the H register and the value of the lower 1 byte of the address "_OUT_PT3" into the L register. The zero flag does not change depending on the command "LDQ HL, LOW_OUT_PT3". The command on the third line corresponds to step S2 in FIG.

If the subtraction result of the command "RST RAM_DEC" on the second line is not zero (if the zero flag is not set) by the command "SET NZ, @ EXT_SG4_POS, (HL)" on the fourth line of FIG. 183, that is, security. If the signal ON condition is satisfied, the bit of the value (here, 2) defined by @ EXT_SG4_POS in the output port 3 image, that is, the value of the address indicated by the HL register is set. The command on the fourth line corresponds to step S3 in FIG. 181. Then, the command "RET" on the fifth line of FIG. 183 returns to the routine one step higher. The command on the fifth line corresponds to step S4 in FIG.

Here, the command "SET cc, b, (HL)" sets the b-bit of the address value (variable) indicated by the HL register if the flag corresponding to cc (zero flag or carry flag) is true. It is a command. The command size of such a command is "2" and the execution cycle is "5" ("2"). The number of cycles in parentheses indicates the execution cycle when the flag is not true in the command "SET cc, b, (HL)".

As described above, the total command size of the commands of the IPT_PD module shown in FIG. 183 is the command "RST RAM_DEC" on the second line + the command "LDQ HL, LOW_OUT_PT3" on the third line, and the command "LDQ HL, LOW_OUT_PT3" on the fourth line. SET NZ, @ EXT_SG4_POS, (HL) "2 bytes + 5th line command" RET "1 byte = 6 bytes, and the total execution cycle is 2nd line 4 cycles + 3rd line 2 cycles + 4th line 5 cycles (2 cycles) ) + 5th line 3 cycles = 14 cycles (11 cycles). Therefore, as compared with the case of FIG. 182, the total command size is reduced by 2 bytes, and the total execution cycle is reduced by at least one cycle. With such an IPT_PD module, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, as can be understood by comparing FIG. 182 and FIG. 183, the command group that occupied the third line (fourth to sixth lines) in FIG. 182 is changed to the first line (fourth line) in FIG. 183. ), It is possible to reduce the number of commands themselves and the design load.

In addition, although the command "SET cc, b, (HL)" for setting a bit has been described here, the command "SET cc, b, r" for setting a bit may be used not only in such a case. can. Here, the command "SET cc, b, r" is r (A register, B register, D register, E register, H register, L register) if the flag corresponding to cc (zero flag or carry flag) is true. ) Is a command to set the b-bit of the value. The command size of such a command is "2" and the execution cycle is "2".

Such a command "SET" can be adopted not only in the above-mentioned IPT_PD module but also in various modules such as a DYNMOUT module. Further, it can be adopted not only in slot machines but also in pachinko machines, for example, EXT_PRC modules.

FIG. 184 is an explanatory diagram for explaining the DYNMOUT module. In the DYNMOUT module shown in step S3100-7 of FIG. 98, the main CPU 500a outputs the set output image to the output port, and the main credit display unit 430, the main payout display unit 432, the input number display, and the start display are displayed. , Dynamic port output processing (dynamic lighting control processing) for lighting control of the display, replay display, and section display 160 of the stop switches 420a, 420b, and 420c is executed.

The index “DYNMOUT:” in the first line of FIG. 184 (a) indicates the start address of the DYNMOUT module. By the command "RESQ @ CHN_DSP_BIT, (LOW _WIN_DAT + 1)" on the second line, the value of the Q register is set to the upper 1 byte of the address, and the value obtained by adding 1 to the lower 1 byte of the address "_WIN_DAT" is set to the lower 1 byte of the address. , Set (reset) 0 to the bit (bit 7 in this case) indicated by @CHN_DSP_BIT in the value stored at that address (main display data buffer 2). By the command "LDQ A, (LOW _OUT_PT2)" on the third line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_OUT_PT2" is set to the lower 1 byte of the address and stored in that address. The value (output port 2 image) is read to the A register. The command "JAND Z, A, 000000111B, DYNMOUT02" on the 4th line moves to the address "DYNMOUT02" if the logical product of the value of the A register and 00000111B is zero, and if it is not zero, the command on the 5th line To process. By the command "SETQ @ CHN_DSP_BIT, (LOW _WIN_DAT + 1)" on the 5th line, the value of the Q register is set to the upper 1 byte of the address, and the value obtained by adding 1 to the lower 1 byte of the address "_WIN_DAT" is set to the lower 1 byte of the address. , Set (set) 1 to the bit (bit 7 in this case) indicated by @CHN_DSP_BIT of the value (main display data buffer 2) stored at that address. The index "DYNMOUT02:" on the 6th line indicates the destination of the command "JAND Z, A, 000000111B, DYNMOUT02" on the 4th line. In this way, bit 7 of the main display data buffer 2 can be set according to the value of the lower 2 bits of the output port 2 image.

Here, by replacing with the command "SET", the command group of FIG. 184 (a) can be changed as shown in FIG. 184 (b). The index “DYNMOUT:” in the first line of FIG. 184 (b) indicates the start address of the DYNMOUT module. The command "LDQ HL, LOW _WIN_DAT + 1" on the second line reads the value of the Q register into the H register, and reads the value obtained by adding 1 to the value of the lower 1 byte of the address "_WIN_DAT" into the L register. The command "RES @ CHN_DSP_BIT, (HL)" on the third line sets (reset) 0 to the bit (bit 7 in this case) indicated by @CHN_DSP_BIT in the value stored at the address indicated by the HL register. By the command "LDQ A, (LOW _OUT_PT2)" on the 4th line, the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_OUT_PT2" is set to the lower 1 byte of the address and stored in that address. The value (output port 2 image) is read to the A register. The command "AND A, 000000111B" on the fifth line calculates the logical product of the value of the A register and 000000111B, and masks the A register. If the operation result of the command "AND A, 000000111B" on the 5th line is not zero (if the zero flag is not set) by the command "SET NZ, @ CHN_DSP_BIT, (HL)" on the 6th line, the HL register indicates. 1 is set in the bit (here, bit 7) indicated by @CHN_DSP_BIT in the address value (main display data buffer 2). In this way, as in FIG. 184 (a), bit 7 of the main display data buffer 2 can be set according to the value of the lower 2 bits of the output port 2 image.

Here, the total command size of the commands of the DYNMOUT module shown in FIG. 184 (a) is the command "RESQ @ CHN_DSP_BIT, (LOW _WIN_DAT + 1)" on the second line + the command "LDQ A, (LOW _OUT_PT2) on the third line. ) ”2 bytes + 4th line command“ JAND Z, A, 000000111B, DYNMOUT02 ”3 bytes + 5th line command“ SETQ @ CHN_DSP_BIT, (LOW _WIN_DAT + 1) ”3 bytes = 11 bytes, and the total execution cycle is the output port. If the lower 2 bits of the 2 images are not 0, then 6 cycles in the 2nd line + 3 cycles in the 3rd line + 3 cycles in the 4th line + 6 cycles in the 5th line = 18 cycles, and the lower 2 bits of the output port 2 image are both 0. In that case, 6 cycles in the 2nd row + 3 cycles in the 3rd row + 4 cycles in the 4th row = 13 cycles.

On the other hand, the total command size of the commands of the DYNMOUT module shown in FIG. + 4th line command "LDQ A, (LOW _OUT_PT2)" 2 bytes + 5th line command "AND A, 000000111B" 2 bytes + 6th line command "SET NZ, @ CHN_DSP_BIT, (HL)" 2 bytes = 10 bytes If the lower 2 bits of the output port 2 image are not 0, the total execution cycle is 2nd line 2 cycles + 3rd line 5 cycles + 4th line 3 cycles + 5th line 2 cycles + 6th line 5 cycles = 17 cycles. If the lower 2 bits of the output port 2 image are all 0, then 2nd line 2 cycles + 3rd line 5 cycles + 4th line 3 cycles + 5th line 2 cycles + 6th line 2 cycles = 14 cycles. Therefore, it can be understood that the total command size is reduced by 1 byte as compared with the case of FIG. 184 (a). With such a DYNMOUT module, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

FIG. 185 is an explanatory diagram for explaining the EXT_PRC module. In the EXT_PRC module shown in steps S400-29 of FIG. 26, the main CPU 500a sets output data for external information to be output from the game information output terminal board 312 to the outside.

The index “EXT_PRC:” in the first line of FIG. 185 (a) indicates the start address of the EXT_PRC module. By the command "LD BC, @ D_SEC_LOP * 256 + 0" on the second line, @D_SEC_LOP (8 in this case), which is the number of rams to be checked (number of loops), is set in the B register, and the C register is set as the initial value of the composite bit data. 0 is set. The command "JR Z, EXT_PRC_15" on the third line determines whether or not the logical product of the target ram addresses calculated before executing the command is zero, and if it is zero (if the zero flag is set). ), Moves to the index "EXT_PRC_15:" on the 5th line, and if it is not zero (if the zero flag is not set), the processing on the 4th line is performed. The command "SET @ EXT_SEC_POS, C" on the 4th line causes a bit of the value (bit 6 in this case) defined by @ EXT_SEC_POS of the C register value (synthetic bit data) to be set. The index "EXT_PRC_15:" on the fifth line indicates the destination of the command "JR Z, EXT_PRC_15" on the third line. In this way, it is possible to set bit 6 of the composite bit data according to the operation result of the logical product of the target ram address.

Here, by replacing with the command "SET", the command group of FIG. 185 (a) can be changed as shown in FIG. 185 (b). The index “EXT_PRC:” in the first line of FIG. 185 (b) indicates the start address of the EXT_PRC module. By the command "LD BC, @ D_SEC_LOP * 256 + 0" on the second line, @D_SEC_LOP (8 in this case), which is the number of rams to be checked (number of loops), is set in the B register, and the C register is set as the initial value of the composite bit data. 0 is set. The command "SET NZ, @ EXT_SEC_POS, C" on the third line determines whether the logical product of the target ram addresses calculated before the command is executed is zero, and if it is not zero (zero flag is set). (If not set), the bit of the value (bit 6 in this case) defined by @EXT_SEC_POS of the C register value (composite bit data) is set. In this way, as in FIG. 185 (a), it is possible to set bit 6 of the composite bit data according to the calculation result of the logical product of the target ram address.

Here, the total command size of the commands of the EXT_PRC module shown in FIG. 185 (a) is 2 bytes of the command "LD BC, @ D_SEC_LOP * 256 + 0" on the second line + 2 bytes of the command "JR Z, EXT_PRC_15" on the third line. +4th line command "SET @ EXT_SEC_POS, C" 2 bytes = 6 bytes, and the total execution cycle is 2nd line 2 cycles + 3rd line 2 cycles + 4th line 2 cycles = 6 cycles if the logical product is not 0. If the logical product is 0, 2 cycles in the 2nd row + 3 cycles in the 3rd row = 5 cycles.

On the other hand, the total command size of the commands of the EXT_PRC module shown in FIG. 185 (b) is the command "LD BC, @ D_SEC_LOP * 256 + 0" on the second line + the command "SET NZ, @ EXT_SEC_POS, C" on the third line. 2 bytes = 4 bytes, and the total execution cycle is 2nd row 2 cycles + 3rd row 5 cycles = 7 cycles when the logical product is not 0, and 2nd row 2 cycles + 3 rows when the logical product is 0. 2 cycles = 4 cycles. Therefore, it can be understood that the total command size is reduced by 2 bytes as compared with the case of FIG. 185 (a). With such an EXT_PRC module, it is possible to further shorten the command and secure the capacity of the control area for performing the game control process.

<Command "JANDQ">
FIG. 186 is a flowchart showing a specific process of the STOPDCT module. Here, as an arbitrary process, a process S2500-23 for confirming a stop indicator which is a part of the STOPDCT module that executes the process during rotation of the rotating cylinder shown in step S2500 of FIG. 92 will be described. The numerical value of step S in such a figure will be used only in the description of this figure. Further, in the description of the STOPDCT module, the predetermined register is the HL register.

The main CPU 500a executes an arbitrary process as shown in FIG. 186. The main CPU 500a first performs an operation target bit extraction process (S1). By such processing, the operation target bit is set in the A register. Then, the main CPU 500a synthesizes the operation target bit of the A register and the rotating rotation flag set in the D register in advance (S2). Subsequently, the main CPU 500a confirms the stop indicator by taking a logical product with the value of the address indicating the stop indicator (S3), and if the stop indicator is lit in red (YES in S4), the STOPDCT is concerned. The process is repeated from the beginning of the module, and if the stop indicator is not lit in red (NO in S4), the next process is executed. Then, by moving to the STP_REL module that executes the rotation stop processing, the STOPDCT module is terminated (S5). In this way, the pressing process according to the state of the stop indicator becomes possible.

FIG. 187 is an explanatory diagram for explaining an example of a command for realizing the STOPDCT module. The flowchart shown in FIG. 186 is realized by, for example, the program shown in FIG. 187.

The index "STOPDCT:" in the first line of FIG. 187 indicates the start address of the STOPDCT module. The command "CALLF SMPLBIT" on the second line is a command that calls the SMPLBIT module that executes the operation target bit extraction process, and the bit corresponding to the stop switch that is the operation target (actually operated) by this command is A. Set in the register. The command on the second line corresponds to step S1 in FIG. 186. The command "AND A, D" on the third line calculates the logical product of the A register in which the operation target bit is set and the D register in which the rotating rotation flag is set in advance, and the result is the A register. Hold on. The command on the third line corresponds to step S2 in FIG. 186.

By the command "ANDQ A, (LOW _OUT_PT4)" on the fourth line of FIG. 187, the value of the Q register is set to the upper 1 byte, and the value of the address "_OUT_PT4" (first predetermined value) is set to the lower 1 byte (stop). The logical product of the value of the display) and the value of the A register is calculated, and the result is held in the A register. The command on the fourth line corresponds to step S3 in FIG. 186. The command "JR Z, STOPDCT" on the 5th line determines whether or not the calculation result of the command "ANDQ A, (LOW _OUT_PT4)" on the 4th line is zero. (B) Moves to the index "STOPDCT:" (second predetermined value) on the first line, and if it is not zero (if the zero flag is not set), the next process is performed. The command on the fifth line corresponds to step S4 in FIG. 186.

As described above, the total command size of the commands of the STOPDCT module shown in FIG. 187 is 2 bytes of the command "CALLF SMPLBIT" on the 2nd line + 1 byte of the command "AND A, D" on the 3rd line + the command "ANDQ" on the 4th line. A, (LOW _OUT_PT4) "3 bytes + 5th line command" JR Z, STOPDCT "2 bytes = 8 bytes, and the total execution cycle is 2nd line 4 cycles + 3rd line 1 cycle + 4th line 4 cycles + 5th line 3 cycles (2 cycles) = 12 cycles (11 cycles). The number of cycles in parentheses indicates the execution cycle when the command "JR Z, STOPDCT" does not move. By providing the processes of the 4th and 5th lines in the STOPDCT module, the pressing process according to the state of the stop indicator can be performed.

FIG. 188 is an explanatory diagram for explaining another example of the command for realizing the STOPDCT module. Here, the command group of the STOPDCT module of FIG. 187 is replaced with the command group of the STOPDCT module of FIG. 1872.

The index "STOPDCT:" in the first line of FIG. 188 indicates the start address of the STOPDCT module. The command "CALLF SMPLBIT" on the second line is a command that calls the SMPLBIT module that executes the operation target bit extraction process, and the bit corresponding to the operation target stop switch is set in the A register by this command. The command on the second line corresponds to step S1 in FIG. 186. The command "AND A, D" on the third line calculates the logical product of the A register in which the operation target bit is set and the D register in which the rotating rotation flag is set in advance, and the result is the A register. Hold on. The command on the third line corresponds to step S2 in FIG. 186.

By the command "JANDQ Z, A, (LOW_OUT_PT4), STOPDCT" on the fourth line of FIG. 188, the value of the Q register is set to the upper 1 byte, and the value of the address "_OUT_PT4" (the first predetermined value) is set to the lower 1 byte. The logical product of the calculated value (value of the stop indicator) and the value of the A register is calculated, and it is determined whether or not the calculation result is zero. If it is zero (if the zero flag is set), the first line Moves to the index "STOPDCT:" (second predetermined value) of, and if it is not zero (if the zero flag is not set), the next processing is performed. The command on the fourth line corresponds to steps S3 and S4 of FIG. 186.

Here, the command "JANDQ cc, A, (k), e" has a value (first predetermined value) in which the value of the Q register is the upper 1 byte and the value of the address indicated by k is the lower 1 byte. The logical product of the values of the A register is calculated, and if the flag corresponding to cc (zero flag or carry flag) is true for the calculation result, the address indicated by e (second predetermined value) is moved to cc. If the corresponding flag is not true, the command moves to the next process. The command size of such a command is "4" and the execution cycle is "6" ("5"). The number of cycles in parentheses indicates the execution cycle when the flag is not true in the command "JANDQ cc, A, (k), e".

The total command size of the commands of the STOPDCT module shown in FIG. 188 is 2 bytes of the command "CALLF SMPLBIT" on the 2nd line + 1 byte of the command "AND A, D" on the 3rd line + the command "JANDQ Z, A," on the 4th line. (LOW_OUT_PT4), STOPDCT ”4 bytes = 7 bytes, and the total execution cycle is 4 cycles in the 2nd line + 1 cycle in the 3rd line + 6 cycles (5 cycles) in the 4th line = 11 cycles (10 cycles). The number of cycles in parentheses indicates the execution cycle when the command "JANDQ Z, A, (LOW _OUT_PT4), STOPDCT" does not move. Therefore, as compared with the case of FIG. 187, the total command size is reduced by 1 byte, and the total execution cycle is reduced by at least one cycle. With such a STOPDCT module, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, as can be understood by comparing FIG. 187 and FIG. 188, the command group that occupied the second line (fourth line and fifth line) in FIG. 187 is changed to the first line (fourth line) in FIG. 188. ), It is possible to reduce the number of commands themselves and the design load.

<Command "CALLEX">
The E_SETTM module sets the input error non-monitoring timer setting process, that is, the input error non-monitoring timer in the ERRWAY module that executes the error wait processing shown in step S2200-11 of FIG. 89 and step S2800-39 of FIG. 95. Module for. The E_SETTM module is arranged in another area (2000H to 3FBFH) of the main ROM 500b.

The main CPU 500a reads a program in the used area from the main ROM 500b, executes the read program, calls an E_SETTM module in another area as a subroutine in an arbitrary process, and executes the E_SETTM module. In the E_SETTM module, a timer for non-monitoring of input abnormality is set.

FIG. 189 is a flowchart showing a specific process of the E_SETTM module. Here, as an arbitrary process, a part of the BLKSHUT module that executes the blocker blockage process in the ERRWAY module that executes the error wait process shown in step S2200-11 of FIG. 89 and step S2800-39 of FIG. 95 is mentioned. explain. The numerical value of step S in such a figure will be used only in the description of this figure.

The main CPU 500a executes an arbitrary process as shown in FIG. 189 (a). The main CPU 500a confirms the blocker state, and calls the E_SETTM module in another area when bit 3 (blocker solenoid output bit number) of the output port 4 image is not 0. Therefore, the main CPU 500a first prohibits interrupts (S1) and calls an E_SETTM module in another area as a subroutine (S2).

As shown in FIG. 189 (b), the main CPU 500a saves general-purpose registers (A register, B register, C register, D register, E register, H register, L register, F register) in the E_SETTM module (S3). .. Then, the main CPU 500a sets the input abnormality non-monitoring timer value as the initial value in the A register (S4), stores the value of the A register in the value indicated by the predetermined address (input abnormality non-monitoring timer), and stores the value in the A register. The input error non-monitoring timer is set (S5). When such processing is completed, the main CPU 500a restores the general-purpose register (S6), permits interrupts (S7), terminates the E_SETTM module, and returns to the routine one step higher (S8).

Here, the E_SETTM module is designed to satisfy all the above-mentioned conditions (1) to (6) in order to appropriately divide the roles between the used area and another area while ensuring the fairness of the gaming machine. ing.

FIG. 190 is an explanatory diagram for explaining an example of a command for realizing the E_SETTM module. Of these, FIG. 190 (a) shows a command group of arbitrary processing for calling the E_SETTM module, and FIG. 190 (b) shows a command group of the E_SETTM module. The flowchart shown in FIG. 189 is realized by, for example, the program shown in FIG. 190.

Interruption is prohibited by the command "DI" on the first line of FIG. 190 (a). The command on the first line corresponds to step S1 in FIG. 189 (a). The command "CALL E_SETTM" on the second line calls the E_SETTM module as a subroutine. The command on the second line corresponds to step S2 in FIG. 189 (a).

The index “E_SETTM:” in the first line of FIG. 190 (b) indicates the start address of the E_SETTM module. By the command "EX AF, AF'" on the second line, the value of the pair register AF and the value of the pair register AF'which is the back register are exchanged, and the value of the pair register AF is saved. By the command "EXX" on the third line, the values of the pair registers BC, DE, and HL are exchanged with the values of the pair registers BC', DE', and HL', which are the back registers, and the values of the pair registers BC, DE, and HL are changed. It is evacuated. The commands on the second and third lines correspond to step S3 in FIG. 189 (b).

The command "LDA, @MDL_WAT_TMR" on the fourth line of FIG. 190 (b) corresponds to the fixed value "@MDL_WAT_TMR", that is, 250.32 msec as the input abnormality non-monitoring timer value (initial value) (252 /). 6 + 1) is read into the A register. The command on the fourth line corresponds to step S4 in FIG. 189 (b). By the command "LD (_EX_SLTM), A" on the 5th line, the value of the A register is stored in the variable "_EX_SLTM" as the input abnormality non-monitoring timer. The command on the fifth line corresponds to step S5 in FIG. 189 (b). In this way, it is possible to set the input abnormality non-monitoring timer value in the input abnormality non-monitoring timer.

The command "EXX" on the sixth line of FIG. 190 (b) replaces the values of the pair registers BC, DE, and HL with the values of the pair registers BC', DE', and HL', which are back registers. The values of DE and HL are restored. By the command "EX AF, AF'" on the 7th line, the value of the pair register AF and the value of the pair register AF'which is the back register are exchanged, and the value of the pair register AF is restored. The commands on the 6th and 7th lines correspond to step S6 in FIG. 189 (b). The interrupt is permitted by the command "EI" on the eighth line of FIG. 190 (b). Here, even if the command "EI" is executed before returning from the subroutine, interrupts are appropriately permitted. Therefore, by describing the command "EI" in the subroutine, it is possible to secure the capacity of the used area. The command on the eighth line corresponds to step S7 in FIG. 189 (b). Then, the command "RET" on the 9th line returns to the routine one step higher. The command on the ninth line corresponds to step S8 in FIG. 189 (b). In this way, it is possible to set the input abnormality non-monitoring timer in another area.

As described above, the total command size of the BLKSHUT module shown in FIG. 190 (a) and the E_SETTM module shown in FIG. 190 (b) is the command "DI" 1 byte + 2nd line of the first line of FIG. 190 (a). Command "CALL E_SETTM" 3 bytes + 2nd line command "EX AF, AF'" in Fig. 190 (b) 1 byte + 3rd line command "EXX" 1 byte + 4th line command "LD A, @ MDL_WAT_TMR" 2 bytes + 5th line command "LD (_EX_SLTM), A" 4 bytes + 6th line command "EXX" 1 byte + 7th line command "EX AF, AF'" 1 byte + 8th line command "EI" 1 byte + 9th line command "RET" 1 byte = 16 bytes, and the total execution cycle is 1st line 1 cycle in FIG. 190 (a) + 2nd line 5 cycles + 2nd line 1 in FIG. 190 (b). Cycle + 3rd row 1 cycle + 4th row 2 cycles + 5th row 4 cycles + 6th row 1 cycle + 7th row 1 cycle + 8th row 1 cycle + 9th row 3 cycles = 20 cycles. By providing such an E_SETTM module, it is possible to cover with the command "CALL E_SETTM" having a command size of 3 bytes without setting the input abnormality non-monitoring timer in each module described above. It is possible to secure the capacity of the control area for performing the control process.

FIG. 191 is an explanatory diagram for explaining another example of the command for realizing the E_SETTM module. Here, the command group of arbitrary processing that calls the E_SETTM module of FIG. 190 (a) is replaced with the command group of arbitrary processing that calls the E_SETTM module of FIG. 191 (a), and the command of the E_SETTM module of FIG. 190 (b) is replaced. The group is replaced with the command group of the E_SETTM module shown in FIG. 191 (b).

The command "CALLEX E_SETTM" on the first line of FIG. 191 (a) calls the E_SETTM module as a subroutine. The command on the first line corresponds to step S2 in FIG. 189 (a).

Here, the command "CALLEX mn" is a command that calls a subroutine having a start address indicated by a fixed value mn, like the command "CALL mn". However, the command "CALLEX mn", like the command "CALL mn", has a plurality of functions in addition to simply calling a subroutine. For example, by executing the command, non-maskable interrupt (NMI) and non-maskable interrupt (INT) are automatically prohibited, and the register bank is switched from the first register bank 726 to the second register bank 728. Call a subroutine that has a start address indicated by a fixed value mn. Therefore, the command "DI" related to interrupts and the commands "EX AF, AF'" and "EXX" (or the command "PUSH") related to evacuation are not required. Therefore, the command "CALLEX E_SETTM" on the first line of FIG. 191 (a) is applied not only to step S2 of FIG. 189 (a) but also to step S1 of FIG. 189 (a) and step S3 of FIG. 189 (b). handle. The command size of such a command is "2" and the execution cycle is "4".

However, the command "CALLEX mn" has a predetermined limitation. For example, if the called address is in the range of 2000H to 20FFH on the address map, the command size of the command is "2" and the execution cycle is "4", but in other ranges, the command size of the command is Is "4" and the execution cycle is "6". Therefore, in order to shorten the command, in the present embodiment, the call destination address, for example, "E_SETTM" is arranged so as to be included in 2000H to 20FFH.

The index “E_SETTM:” in the first line of FIG. 191 (b) indicates the start address of the E_SETTM module. By the command "LDA, @MDL_WAT_TMR" on the second line, the fixed value "@MDL_WAT_TMR", that is, (252/6 + 1) corresponding to 205.32 msec as the input abnormality non-monitoring timer value (initial value) is set in the A register. Read out. The command on the second line corresponds to step S4 in FIG. 189 (b). By the command "LD (_EX_SLTM), A" on the third line, the value of the A register is stored in the variable "_EX_SLTM" as the input error non-monitoring timer. The command on the third line corresponds to step S5 in FIG. 189 (b). In this way, it is possible to set the input abnormality non-monitoring timer value in the input abnormality non-monitoring timer.

The command "RETEX" on the fourth line of FIG. 191 (b) returns to the routine one step higher. The command on the fourth line corresponds to step S8 in FIG. 189 (b). In this way, it is possible to set the input abnormality non-monitoring timer in another area.

Here, the command "RETEX" is a command to return to the routine one step higher, like the command "RET". However, the command "RETEX" is often used in pairs with the command "CALLEX mn", and like the command "RET", it has a plurality of functions in addition to simply returning from the subroutine. For example, by executing the command, the register bank is automatically switched from the second register bank 728 to the first register bank 726, interrupting is permitted, and then the routine returns one step higher. Therefore, the command "EX" and "EX AF, AF'" (or the command "POP") related to the return and the command "EI" related to the interrupt are not required. Therefore, the command "RETEX" on the fourth line of FIG. 191 (b) corresponds not only to step S8 of FIG. 189 (b) but also to steps S6 and S7 of FIG. 189 (b). The command size of such a command is "2" and the execution cycle is "5".

The total command size of the BLKSHUT module shown in FIG. 191 (a) and the E_SETTM module shown in FIG. 191 (b) is 2 bytes of the command "CALLEX E_SETTM" in the first line of FIG. 191 (a) + FIG. 191 (b). 2nd line command "LD A, @MDL_WAT_TMR" 2 bytes + 3rd line command "LD (_EX_SLTM), A" 4 bytes + 4th line command "RETEX" 2 bytes = 10 bytes, and the total execution cycle is , 1st row 4 cycles of FIG. 191 (a) + 2nd row 2 cycles of FIG. 191 (b) + 3rd row 4 cycles + 4th row 5 cycles = 15 cycles. Therefore, as compared with the case of FIG. 190, the total command size is reduced by 6 bytes, and the total execution cycle is also reduced by at least 5 cycles. With such an E_SETTM module, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in FIG. 190, the 8th line (the 1st and 2nd lines of FIG. 190 (a) and the 2nd, 3rd, 6th to 9th lines of FIG. 190 (b)) can be understood by comparing FIG. ) Can be represented by two lines (the first line of FIG. 191 (a) and the fourth line of FIG. 191 (b)) in FIG. 191 to reduce the number of commands themselves. , It is possible to reduce the design load.

Such a command "CALLEX" can be adopted not only in the above-mentioned BLKSHUT module but also in various modules. Further, it can be adopted not only in slot machines but also in pachinko machines, for example, the DYM_OUT module.

192 and 193 are explanatory views for explaining the DYM_OUT module. The DYM_OUT module shown in step S400-5 of FIG. 26 has a first special symbol display 160, a second special symbol display 162, a first special symbol hold indicator 164, a second special symbol hold indicator 166, and a normal symbol. A dynamic port output process for lighting control of the display 168, the normal symbol hold display 170, the right-handed notification display 172, and the performance display monitor 184 is executed.

Interruption is prohibited by the command "DI" on the first line of FIG. 192 (a). The command "CALL E_DMOUT" on the second line calls the E_DMOUT module as a subroutine.

The index “E_DMOUT:” in the first line of FIG. 192 (b) indicates the start address of the E_DMOUT module. By the command "EX AF, AF'" on the second line, the value of the pair register AF and the value of the pair register AF'which is the back register are exchanged, and the value of the pair register AF is saved. By the command "EXX" on the third line, the values of the pair registers BC, DE, and HL are exchanged with the values of the pair registers BC', DE', and HL', which are the back registers, and the values of the pair registers BC, DE, and HL are changed. It is evacuated. The address "R_ERW_IOB" of the identification segment output request buffer is set in the HL register by the command "LD HL, R_ERW_IOB" on the fourth line. The command "LDA, (R_COM_CNT)" on the fifth line reads the 1-byte value (common counter) stored at the address indicated by "R_COM_CNT" into the A register. Here, the common counter is used to determine the common number of the LED dynamic lighting control, and a value indicating the common number is stored. By the command "LDA, (HL + A)" on the 6th line, the 1-byte value (display data) stored in the address obtained by adding (offset) the value of the A register to the address indicated by the HL register is stored in the A register. Read out. By the command "OUT (@OTC_PRT), A" on the 7th line, the value of the U register is set to the upper 1 byte of the address, and the fixed value "" indicating the lower 1 byte of the address of the output port 12 (internal register I / O port). "@OTC_PRT" is set to the lower 1 byte, and the value of the A register is output to that address. By the command "EXX" on the 8th line, the values of the pair registers BC, DE, and HL are exchanged with the values of the pair registers BC', DE', and HL', which are the back registers, and the values of the pair registers BC, DE, and HL are changed. Return. By the command "EX AF, AF'" on the 9th line, the value of the pair register AF and the value of the pair register AF'which is the back register are exchanged, and the value of the pair register AF is restored. The command "EI" on the 10th line allows interrupts. Here, even if the command "EI" is executed before returning from the subroutine, interrupts are appropriately permitted. Therefore, by describing the command "EI" in the subroutine, it is possible to secure the capacity of the used area. Then, the command "RET" on the 11th line returns to the routine one step higher. In this way, the dynamic port output process can be executed in another area.

Here, by replacing with the command "CALLEX", the command group of FIG. 192 can be changed as shown in FIG. 193. The command "CALLEX E_DMOUT" on the first line of FIG. 193 (a) calls the E_DMOUT module as a subroutine. Here, the callee address, for example, "E_DMOUT" is arranged so as to be included in 2000H to 20FFH.

The index “E_DMOUT:” in the first line of FIG. 193 (b) indicates the start address of the E_DMOUT module. The address "R_ERW_IOB" of the identification segment output request buffer is set in the HL register by the command "LD HL, R_ERW_IOB" on the second line. The command "LDA, (R_COM_CNT)" on the third line reads the 1-byte value (common counter) stored at the address indicated by "R_COM_CNT" into the A register. By the command "LDA, (HL + A)" on the 4th line, the 1-byte value (display data) stored in the address obtained by adding (offset) the value of the A register to the address indicated by the HL register is stored in the A register. Read out. By the command "OUT (@OTC_PRT), A" on the 5th line, the value of the U register is set to the upper 1 byte of the address, and the fixed value "" indicating the lower 1 byte of the address of the output port 12 (internal register I / O port). "@OTC_PRT" is set to the lower 1 byte, and the value of the A register is output to that address. The command "RETEX" on the 6th line returns to the routine one step higher. In this way, as in FIG. 192, the dynamic port output process can be executed in another area.

As described above, the total command size of the DYM_OUT module shown in FIG. 192 (a) and the E_DMOUT module shown in FIG. 192 (b) is the command "DI" 1 byte + 2nd line of the first line of FIG. 192 (a). Command "CALL E_DMOUT" 3 bytes + 2nd line command "EX AF, AF'" in Fig. 192 (b) 1 byte + 3rd line command "EXX" 1 byte + 4th line command "LD HL, R_ERW_IOB" 3 bytes + 5th line command "LD A, (R_COM_CNT)" 3 bytes + 6th line command "LD A, (HL + A)" 3 bytes + 7th line command "OUT (@OTC_PRT), A" 2 bytes + 8 lines First line command "EX" 1 byte + 9th line command "EX AF, AF'" 1 byte + 10th line command "EI" 1 byte + 11th line command "RET" 1 byte = 21 bytes, total execution The cycle is 1st row 1 cycle in FIG. 192 (a) + 2nd row 5 cycles + 2nd row 1 cycle in FIG. 192 (b) + 3rd row 1 cycle + 4th row 3 cycles + 5th row 4 cycles + 6th row 4 Cycle + 7th row 3 cycles + 8th row 1 cycle + 9th row 1 cycle + 10th row 1 cycle + 11th row 3 cycles = 28 cycles.

On the other hand, the total command size of the DYM_OUT module shown in FIG. 193 (a) and the E_DMOUT module shown in FIG. 193 (b) is the command "CALLEX E_DMOUT" in the first line of FIG. b) 2nd line command "LD HL, R_ERW_IOB" 3 bytes + 3rd line command "LD A, (R_COM_CNT)" 3 bytes + 4th line command "LD A, (HL + A)" 3 bytes + 5th line The command "OUT (@OTC_PRT), A" is 2 bytes + the command "RETEX" on the 6th line is 2 bytes = 15 bytes, and the total execution cycle is the 1st line 4 cycles of FIG. 193 (a) + FIG. 193 (b). 2nd row 3 cycles + 3rd row 4 cycles + 4th row 4 cycles + 5th row 3 cycles + 6th row 5 cycles = 23 cycles. Therefore, as compared with the case of FIG. 192, the total command size is reduced by 6 bytes, and the total execution cycle is also reduced by 5 cycles. With such an E_DMOUT module, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

By the way, as described with reference to FIGS. 189 to 191 the command "CALLEX mn" has a command size of "2" if the called address is in the range of 2000H to 20FFH on the address map. The execution cycle is "4", but in the other range, the command size of the command is "4" and the execution cycle is "6". Therefore, it is desirable to arrange all the called destination addresses in the range of 2000H to 20FFH. However, in 2000H to 20FFH, the number of bytes that can be described is only 256 bytes, so if the subroutine is described as it is in such a range, the number of subroutines is limited. For example, even in the E_SETTM module having a relatively small command size, the command "LDA, @MDL_WAT_TMR" on the second line of FIG. 191 (b) is 2 bytes + the command "LD (_EX_SLTM), A" on the third line is 4 bytes. Since the command "RETEX" on the + 4th line occupies 2 bytes = 8 bytes, it is not possible to arrange a large number of subroutines.

Therefore, in the present embodiment, substantially only the command "JP mn" related to movement is arranged in the range of 2000H to 20FFH on the address map, and the main body of the subroutine is arranged at the movement destination. Since the command size of the command "JP mn" is "3", 256/3 = 86 modules can be called as a subroutine by juxtaposing the command "JP mn" in the range of 2000H to 20FFH on the address map. It will be possible.

It is also possible to use the command "CALL mn" of command size "3" instead of the command "JP mn", but in that case, after the command "CALL mn", the command "RETEX" of command size "2" , So the number of subroutines is limited by the command "JP mn". Therefore, it is desirable to adopt the command "JP mn". Hereinafter, specific processing of the E_SETTM module reflecting such contents will be described.

FIG. 194 is a flowchart showing a specific process of the E_SETTM module. Here, as an arbitrary process, a part of the BLKSHUT module that executes the blocker blockage process will be described as in FIG. 189. The numerical value of step S in such a figure will be used only in the description of this figure.

The main CPU 500a executes an arbitrary process as shown in FIG. 194 (a). The main CPU 500a calls the RRE01 module as a subroutine in another area (S1).

Subsequently, as shown in FIG. 194 (b), the main CPU 500a moves to the E_SETTM module without performing significant processing in the RRE01 module (S2). As described above, the RRE01 module is a module for moving to the E_SETTM module, and is arranged in the range of 2000H to 20FFH on the address map. In this way, a large number of subroutines can be arranged.

As shown in FIG. 194 (c), the main CPU 500a sets the input abnormality non-monitoring timer value in the A register (S3) in the E_SETTM module, and sets the value of the A register to a predetermined address (input abnormality non-monitoring timer). It is stored in the indicated value and the input error non-monitoring timer is set (S4). When such processing is completed, the main CPU 500a ends the E_SETTM module and returns to the routine one step higher (S5). Since the E_SETTM module is the destination of the RRE01 module, it is not restricted by the address map. Therefore, since it can be arbitrarily arranged in the range of 2100H to 3FBFH in another region, it is permissible even if the total command size is large to some extent.

FIG. 195 is an explanatory diagram for explaining still another example of the command for realizing the E_SETTM module. Here, as shown in FIG. 195 (b), an RRE01 module for moving to the E_SETTM module is newly provided.

The command "CALLEX PRE01" on the first line of FIG. 195 (a) calls the RRE01 module as a subroutine instead of the E_SETTM module. The command on the first line corresponds to step S1 in FIG. 194 (a). The command "CALLEX PRE01" also prohibits interrupts and saves general-purpose registers.

The index "PRE01:" in the first line of FIG. 195 (b) indicates the start address of the PRE01 module. The command "JP E_SETTM" on the second line moves to the E_SETTM module main body. Such a command corresponds to step S2 in FIG. 194 (b).

When a plurality of subroutines are called through the command "CALLEX mn", an index (for example, "PRE01:") indicating the calling address of the plurality of subroutines and the command "JP mn" are continuously set in the range of 2000H to 20FFH. By doing so, the range of 2000H to 20FFH can be effectively used and a large number of subroutines can be arranged.

The index “E_SETTM:” in the first line of FIG. 195 (c) indicates the start address of the E_SETTM module. By the command "LDA, @MDL_WAT_TMR" on the second line, the fixed value "@MDL_WAT_TMR", that is, (252/6 + 1) corresponding to 205.32 msec as the input abnormality non-monitoring timer value (initial value) is set in the A register. Read out. The command on the second line corresponds to step S3 in FIG. 194 (c). By the command "LD (_EX_SLTM), A" on the third line, the value of the A register is stored in the variable "_EX_SLTM" as the input error non-monitoring timer. The command on the third line corresponds to step S4 in FIG. 194 (c). In this way, it is possible to set the input abnormality non-monitoring timer value in the input abnormality non-monitoring timer.

The command "RETEX" on the fourth line of FIG. 195 (c) returns to the routine one step higher. The command on the fourth line corresponds to step S5 in FIG. 194 (c). In this way, it is possible to set the input abnormality non-monitoring timer in another area. The command "RETEX" also executes the return of the general-purpose register and the permission of interrupt.

In the example of FIG. 195, the total command size and the total execution cycle are increased by the amount of the command “JP E_SETTM” as compared with the case of FIG. 191. However, by moving to the subroutine body via the command "JP E_SETTM", many subroutines can be arranged in the range of 2000H to 20FFH, the limit on the number of subroutines can be expanded, and the command of the subroutine itself can be expanded. Since the size limitation is relaxed, as a result, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control process.

In this way, even if only the command "JP mn" is placed in the range of 2000H to 20FFH, if the number of subroutines that can be placed is insufficient, that is, if there are 86 or more subroutines, the module with a small total command size. Is placed in the range of 2100H to 217FH (range of 128 bytes), and instead of the command "JP mn" of command size "3", the command "JR mn" of command size "2" suitable for short-distance movement is used. It may be used. By doing so, it becomes possible to arrange more commands "JR mn" in the range of 2000H to 20FFH.

<Commands "ICPLMQA", "ICPLMQ">
The RAM_INC module is a module for RAM addition processing, that is, for incrementing a 1-byte variable of the main RAM 500c by 1 up to a predetermined number. The RAM_INC module sets not only the increment but also the carry flag as a result of the increment. The RAM_INC module can also be used as a general-purpose module.

Such a RAM_INC module is called as a subroutine from a plurality of modules. For example, in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, the module selectively shifts according to the game state and the effect state, and the present precursor processing (AT state = “3”) is executed. The HID_LOT module to be executed, and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. The FIN_LOT module that executes the above, and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. ), And the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91 selectively shifts according to the game state and the effect state, and the BIG processing (AT state = "7" ") Is called from the BIT_LOT module or the like that executes.

The main CPU 500a reads a program from the main ROM 500b, executes the read program, and increments the 1-byte value held in the main RAM 500c in an arbitrary process.

FIG. 196 is a flowchart showing a specific process of the RAM_INC module. The numerical value of step S in such a figure will be used only in the description of this figure. Further, in the description of the RAM_INC module, the predetermined register is the A register, the predetermined number is the upper limit value, and the specific address is the address to be incremented.

As shown in FIG. 196 (a), the main CPU 500a sets the address to be incremented in the HL register in an arbitrary process (S1). Then, the main CPU 500a increments the 1-byte value stored in the address indicated by the HL register (S2), stores the incremented value in the address indicated by the HL address, and updates the value (S3). However, here, an upper limit value (predetermined number) is set, and the result of incrementing does not exceed the upper limit value.

197 and 198 are explanatory diagrams for explaining an example of a command for realizing the RAM_INC module. The flowchart shown in FIG. 196 is realized, for example, by the program shown in FIG. 197.

The index “RAM_INC:” in the first line of FIG. 197 indicates the start address of the RAM_INC module. The command "LDQ HL, LOW_AT_SET" on the second line reads the value of the Q register into the H register and the value of the lower 1 byte of the address "_AT_SET" into the L register. The command on the second line corresponds to step S1 in FIG. 196. As shown in FIG. 198, the command "LDA, (HL)" on the third line reads the 1-byte value (for example, 02H) stored at the address indicated by the HL register into the A register. The command "INC A" on the fourth line of FIG. 197 increments the value of the A register by, for example, from 02H to 03H as shown in FIG. 198. In order to have versatility, instead of the command "LD A, (HL)" on the third line and the command "INC A" on the fourth line, the command "LD A, 1" and the command "ADDA, ( HL) ”can also be used. In this case, the value to be incremented can be changed to a value other than 1 by changing the value of "1" stored in the A register.

The command "JCP C, A, 5, RAM_INC01" on the 5th line of FIG. 197 compares the value of the A register with the upper limit value "5", and as a result, if it is less than 5, (if the carry flag is set). ), Move to the address "RAM_INC01". In this way, if the value of the A register is less than the upper limit value of 5, it is possible to skip the next process and move to the index "RAM_INC01" on the 7th line. The upper limit value "5" is stored in the A register by the command "LDA, 5" on the sixth line. This is because when the value of the A register exceeds 5 by the command "INC A" on the 4th line, the value of the A register is forcibly overwritten with 5, so that the increment result is 5 or less. be. Here, when the value of the A register before incrementing is 4, that is, when the value of the A register is incremented from 4 to 5, the value of the A register is already 5, so it is necessary to update it to 5. However, if a process for determining that is added, the processing load increases. Therefore, priority is given to versatility, and the value of the A register is forcibly updated to 5 as in the case of exceeding 5. The commands on the 3rd to 6th lines correspond to step S2 in FIG. 196.

The index "RAM_INC01" on the 7th line of FIG. 197 indicates the destination address of the command "JCP C, A, 5, RAM_INC01" on the 5th line. The command "LD (HL), A" on the eighth line stores the value of the A register (for example, 03H) at the address indicated by the HL register, as shown in FIG. 198. The command on the eighth line corresponds to step S3 in FIG. 196. In this way, it is possible to increment the 1-byte variable of the main RAM 500c by 1 up to a predetermined number and hold the incremented value in the A register (the value of the A register can be used in the subsequent processing). Become.

As described above, the total command size of the RAM_INC module command shown in FIG. 197 is the command "LDQ HL, LOW_AT_SET" on the second line 2 bytes + the command "LD A, (HL)" on the third line 1 byte + 4 lines. First command "INC A" 1 byte + 5th line command "JCP C, A, 5, RAM_INC01" 3 bytes + 6th line command "LD A, 5" 2 bytes + 8th line command "LD (HL), A ”1 byte = 10 bytes, and the total execution cycle is 2nd row 2 cycles + 3rd row 2 cycles + 4th row 1 cycle + 5th row 4 cycles + 6th row 2 cycles + 8th row 2 cycles = 13 cycles. By providing such a RAM_INC module, the 1-byte variable can be uniformly and easily incremented, so that the command can be shortened and the capacity of the control area for performing the game control process can be secured.

FIG. 199 is an explanatory diagram for explaining another example of the command for realizing the RAM_INC module. Here, the command group of the RAM_INC module of FIG. 197 is replaced with the command group of the RAM_INC module of FIG. 199.

The index “RAM_INC:” in the first line of FIG. 199 indicates the start address of the RAM_INC module. By the command "ICPLMQA (LOW_AT_SET) 5" on the second line, the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address "_AT_SET" is set to the lower 1 byte of the address, and the address (increment). The 1-byte value stored in the target address) is compared with the upper limit value "5", and if the result is less than 5 (if the carry flag is set), 1 stored in the address to be incremented. The byte value is incremented by 1 and stored in the A register, and the 1-byte value stored in the address to be incremented is updated. If the value after increment is 5 or more (if the carry flag is not set), the upper limit value "5" is stored in the A register, and the 1-byte value stored in the address to be incremented is the upper limit value. Update to "5". The command on the second line corresponds to steps S1 to S3 in FIG. 196. In this way, it is possible to increment the 1-byte variable of the main RAM 500c by 1 up to a predetermined number and hold the incremented value in the A register (the value of the A register can be used in the subsequent processing). Become.

Here, in the command "ICPLMQA (k), n", the value of the Q register is set to the upper 1 byte of the address, the value k is set to the lower 1 byte of the address, and the 1-byte value stored in the target address and the upper limit value are set. Compared with n, if it is less than n, the 1-byte value stored in the target address is incremented by 1 and stored in the A register, and the 1-byte value stored in the target address is updated. , N or more, this command stores the upper limit value n in the A register and updates the 1-byte value stored in the target address to the upper limit value n. The command size is "4" and the execution cycle is "7".

The total command size of the command of the RAM_INC module in FIG. 199 is the command "ICPLMQA (LOW_AT_SET) 5" on the second line, 4 bytes = 4 bytes, and the total execution cycle is 7 cycles on the second line = 7 cycles. Therefore, as compared with the case of FIG. 197, the total command size is reduced by 6 bytes, and the total execution cycle is reduced by 6 cycles. With such a RAM_INC module, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, as can be understood by comparing FIG. 197 and FIG. 199, the command group that occupied the 7th line (2nd to 8th lines) in FIG. 197 is changed to the 1st line (2nd line) in FIG. 199. It can be expressed, and it is possible to reduce the number of commands themselves and the design load.

FIG. 200 is an explanatory diagram for explaining still another example of the command for realizing the RAM_INC module. In the RAM_INC module described with reference to FIG. 199, an example is given in which a 1-byte variable of the main RAM 500c is incremented by 1 up to a predetermined number and the incremented value is held in the A register. However, depending on the process, it may be sufficient to increment the 1-byte variable of the main RAM 500c by 1 up to a predetermined number without leaving the result in the A register. Here, an example of incrementing a 1-byte variable by 1 without updating the A register will be given.

The index “RAM_INC:” in the first line of FIG. 200 indicates the start address of the RAM_INC module. By the command "ICPLMQ (LOW_AT_SET) 5" on the second line, the value of the Q register is set to the upper 1 byte of the address, the value of the lower 1 byte of the address "_AT_SET" is set to the lower 1 byte of the address, and the address (increment). The 1-byte value stored in the target address) is compared with the upper limit value "5", and if the result is less than 5 (if the carry flag is set), the 1 stored in the address to be incremented is 1. The byte value is incremented by 1 and updated. If the incremented value is 5 or more (if the carry flag is not set), the 1-byte value stored in the address to be incremented is updated to the upper limit value "5". The command on the second line corresponds to steps S1 to S3 in FIG. 196. In this way, the 1-byte variable of the main RAM 500c can be incremented by 1 up to a predetermined number.

Here, in the command "ICPLMQ (k), n", the value of the Q register is set to the upper 1 byte of the address, the value k is set to the lower 1 byte of the address, and the 1-byte value stored in the target address and the upper limit value are set. As a result of comparison with n, if it is less than n, the 1-byte value stored in the target address is incremented and updated by 1, and if it is n or more, the 1-byte value stored in the target address is the upper limit. This command updates to the value n. The command size is "4" and the execution cycle is "7".

The total command size of the command of the RAM_INC module in FIG. 200 is the command "ICPLMQ (LOW_AT_SET) 5" on the second line, 4 bytes = 4 bytes, and the total execution cycle is 7 cycles on the second line = 7 cycles. Therefore, as compared with the case of FIG. 197, the total command size is reduced by 6 bytes, and the total execution cycle is reduced by 6 cycles. With such a RAM_INC module, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, here, the A register is not used as compared with the examples of FIGS. 197 and 21. Therefore, the value of the A register is not unintentionally updated. Further, in the examples of FIGS. 197 and 21, when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, stack processing is also required. No. In this way, resources can be effectively used.

Further, as can be understood by comparing FIG. 197 and FIG. 200, the command group that occupied the 7th line (2nd to 8th lines) in FIG. 197 is changed to the 1st line (2nd line) in FIG. 200. It can be expressed, and it is possible to reduce the number of commands themselves and the design load.

<Command "LDINTQR">
The TABLEST module is a general-purpose module for table set processing, that is, for setting a predetermined value (initial value) in a variable of the main RAM 500c. Here, an example of arranging the TABLEST module at 0030H on the memory map will be described.

The main CPU 500a reads a program from the main ROM 500b, executes the read program, calls a TABLEST module as a subroutine in an arbitrary process, and executes the TABLEST module. In the TABLEST module, a plurality of 1-byte values described in the program data of the main ROM 500b are transferred to an area holding a plurality of data treated as variables in the work area of the main RAM 500c. In this way, the values of a plurality of variables are set. Here, the number of data to be transferred is simply referred to as the number of data.

FIG. 201 is a flowchart showing a specific process of the TABLEST module. Here, as an arbitrary process, a part of the ERRWAY module that executes the error wait process shown in step S2200-11 of FIG. 89 and step S2800-39 of FIG. 95, that is, error display, warning sound request, and error recovery wait. Will be explained. The numerical value of step S in such a figure will be used only in the description of this figure. Further, in the description of the TABLEST module, the first register is the B register, the second register is the HL register, the register different from the first register and the second register is the A register, and the predetermined value is "1". be. Needless to say, a predetermined value can be set arbitrarily.

As shown in FIG. 201A, the main CPU 500a sets the start address of the 1-byte data group as the transfer source in the HL register in an arbitrary process (S1). Then, the TABLEST module is called as a subroutine (S2).

As shown in FIG. 201 (b), the main CPU 500a saves the BC register in the TABLEST module (S3) and prohibits interrupts (S4). Then, the main CPU 500a reads the 1-byte value stored in the address indicated by the HL register into the B register (S5). Such a 1-byte value indicates the number of data. Subsequently, the main CPU 500a is stored in the address specified by the value stored in the address indicated by the value obtained by adding "1" to the HL register, and at the address indicated by the value obtained by adding "2" to the HL register. Transfer the value, add "2" to the value of the HL register, and set the address to be transferred next (S6). Subsequently, the main CPU 500a decrements (subtracts “1”) the value of the B register, and determines whether or not the decrement result is 0 (S7). Here, if the decremented result is not 0 (NO in S7), the process from step S6 is repeated, and if the decremented result is 0 (YES in S7), the interruption is permitted (S8) and the BC register. (S9), exits the TABLEST module, and returns to the routine one step higher (S10).

202 and 203 are explanatory diagrams for explaining an example of a command for realizing the TABLEST module. Of these, FIG. 202 (a) shows a command group of arbitrary processing for calling the TABLEST module, FIG. 202 (b) shows a command group of the TABLEST module, and FIG. 202 (c) shows program data of the main ROM 500b. FIG. 202 (d) shows the arrangement of the 1-byte data group in the work area of the main RAM 500c. The flowchart shown in FIG. 201 is realized by, for example, the program shown in FIG. 202.

By the command "LD HL, T_ERR_RCV" on the first line of FIG. 202 (a), the start address "T_ERR_RCV" of the 1-byte data group as the transfer source is set in the HL register. The command on the first line corresponds to step S1 in FIG. 201 (a). Then, the TABLEST module is called as a subroutine by the command "RST TABLEST" on the second line. The command on the second line corresponds to step S2 in FIG. 201 (a).

The index "TABLSET:" in the first line of FIG. 202 (b) indicates the start address of the TABLEST module. The value of the BC register is saved in the stack area by the command "PUSH BC" on the second line. The command on the second line corresponds to step S3 in FIG. 201 (b). Interruption is prohibited by the command "DI" on the third line. The command on the third line corresponds to step S4 in FIG. 201 (b).

The 1-byte value stored at the address indicated by the HL register is read into the B register by the command "LD B, (HL)" on the fourth line of FIG. 202 (b). At this time, the address "T_ERR_RCV" is set in the HL register as shown in FIG. 202 (a). Therefore, the 1-byte value "(T_ERR_RCV_-T_ERR_RCV) / 2" in the second line of FIG. 202 (c) is read into the B register as the number of data (number of repeated transfers). Since "T_ERR_RCV_" is the address next to the final address of the 1-byte data group that is the transfer source and T_ERR_RCV is the start address of the 1-byte data group that is the transfer source, the value of T_ERR_RCV_-T_ERR_RCV (indicates the number of data). The value of 1-byte value) becomes the total number of bytes of the 1-byte value, and the number of data is derived by dividing the value by 2, which is the number of combinations of the address and the value. In the example of FIG. 202 (c), the number of data is 9/2 = 4. The command on the fourth line of FIG. 202 (b) corresponds to step S5 of FIG. 201 (b).

The index “TABLEST10:” on the fifth line of FIG. 202 (b) indicates the start address of the iterative process. Specified by the value stored in the address indicated by the value obtained by adding "1" to the HL register by the command "INLD AC, (HL)" on the 6th line and the command "LDQ (C), A" on the 7th line. The value stored in the address indicated by the value obtained by adding "2" to the HL register is stored in the address to be performed, "2" is added to the value of the HL register, and the address to be transferred next is set. The commands on the 6th and 7th lines correspond to step S6 in FIG. 201 (b).

For example, when the HL register is the value of the address "T_ERR_RCV", the lower 1-byte value of the 2-byte variable "_ERR_NUM" in the third line of FIG. 202 (c) is stored in the C register, and the lower 1-byte value of FIG. 202 (c) is stored in the C register. The value of "0" in the third line is stored in the A register.

Further, in the command "LDQ (C), A" on the 7th line of FIG. 202 (b), the value of the Q register is set to the upper 1 byte of the address, the value of the C register is set to the lower 1 byte of the address, and the address is set to that address. , A command to store the value of the register.

For example, the value of the C register, that is, the value of the lower 1 byte of "_ERR_NUM" is set as the lower 1 byte of the address, and the value of the A register, that is, the value of "0" is stored in the address.

Here, in FIGS. 202 (c) and 202 (d), the variable "_ERR_NUM" indicates an error number, the variable "_CRE_TMR" indicates a credit button detection timer, and the variable "_CRE_FLG" indicates a credit button detection flag. The variable "_SNS_OLD" indicates the previous state of the medal passing sensor bit. The arrangement of the variables shown in FIG. 202 (d) does not have to be continuous as shown in the figure, and may be separated.

Subsequently, the value of the B register is decremented (subtracted by "1") by the command "DJNZ TABLEST10" on the eighth line of FIG. 202 (b), and if the decremented result is not 0, the process is moved to the address "TABLEST10". If the result of decrementing is 0, the process is moved to the command next to the command. Here, since the number of data is "4", the value of the B register becomes 0 when the process from "TABLSET10" is repeated four times. The command on the eighth line corresponds to step S7 in FIG. 201 (b).

Interruption is permitted by the command "EI" on the 9th line of FIG. 202 (b). The command on the ninth line corresponds to step S8 in FIG. 201 (b). The data saved in the stack area is returned to the BC register by the command "POP BC" on the 10th line. The command on the tenth line corresponds to step S9 in FIG. 201 (b). Then, the command "RET" on the 11th line returns to the routine one step higher. The command on the 11th line corresponds to step S10 in FIG. 201 (b).

In this way, as shown in FIG. 203, a plurality of 1-byte values (55H, 77H, 66H, 22H) described in the program data of the main ROM 500b are converted into variables (“_ERR_NUM”, “_CRE_TMR”, “_CRE_TMR” in the work area of the main RAM 500c. It is possible to transfer to "_CRE_FLG", "_SNS_OLD").

The TABLEST module is called as a subroutine from a plurality of modules. For example, in the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, the module selectively shifts according to the game state and the effect state, and the present precursor processing (AT state = "3") is executed. HID_LOT module to be executed, EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. The FIN_LOT module that executes the above, and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. ), And the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91, selectively shifts according to the game state and the effect state, and performs REG processing (AT state = "6". The REG_LOT module that executes () and the EXE_SET module that executes the execution flag setting process shown in step S2400-11 in FIG. 91 selectively shift according to the game state and the effect state, and perform BIG processing (AT state = "AT state" 7 ”), the BIG_LOT module that executes the set value switching process shown in step S220 of FIG. 85, the FGSET UP module that executes the symbol code setting process shown in step S2400 of FIG. 91, and step S2900 of FIG. 96. It is called from the GAMESET module that executes the game transition process shown in FIG. 96, the JCGMSET module that executes the accessory operating process shown in step S290-3 of FIG. 96, and the like.

As described above, the total command size of the commands of the TABLEST module shown in FIG. 202 (b) is the command "PUSH BC" on the second line + the command "DI" on the third line + the command "LD" on the fourth line. B, (HL) "1 byte + 6th line command" INLD AC, (HL) "2 bytes + 7th line command" LDQ (C), A "2 bytes + 8th line command" DJNZ TABLEST10 "2 bytes + 9 Line command "EI" 1 byte + 10th line command "POP BC" 1 byte + 11th line command "RET" 1 byte = 12 bytes, total execution cycle is 2nd line 3 cycles + 3rd line 1 cycle + 4th line 2 cycles + 6th line 4 cycles + 7th line 3 cycles + 8th line 3 cycles (or 2 cycles) + 9th line 1 cycle + 10th line 3 cycles + 11th line 3 cycles = 23 cycles (or 22 cycles) .. The number of cycles in parentheses indicates the execution cycle when the command "DJNZ TABLEST 10" does not move. By providing such a TABLEST module, it is possible to cover with the command "RST TABLEST" having a command size of 1 byte without performing the table set processing in each of the above-mentioned modules. Therefore, the command can be shortened and the game control processing can be performed. It is possible to secure the capacity of the control area for performing.

FIG. 204 is an explanatory diagram for explaining another example of the command for realizing the TABLEST module. Here, the command group of the TABLEST module of FIG. 202 (b) is replaced with the command group of the TABLEST module of FIG. 204 (b), and other commands of arbitrary processing for calling the TABLEST module of FIG. 202 (a) are replaced. The group, the 1-byte data group in the program data of the main ROM 500b of FIG. 202 (c), and the 1-byte data group in the work area of the main RAM 500c of FIG. 202 (d) are shown in FIGS. 204 (a) and 204 (c). , FIG. 204 (d) is used as it is. Here, as shown in FIGS. 204 (a), 204 (c), and 204 (d), the processing substantially equivalent to that of FIGS. 202 (a), 202 (c), and 202 (d) is the same. The description will be omitted, and only the different processes shown in FIG. 204 (b) will be described.

The index "TABLSET:" in the first line of FIG. 204 (b) indicates the start address of the TABLSET module. The value of the BC register is saved in the stack area by the command "PUSH BC" on the second line. The command on the second line corresponds to step S3 in FIG. 201 (b). Interruption is prohibited by the command "DI" on the third line. The command on the third line corresponds to step S4 in FIG. 201 (b).

The 1-byte value stored at the address indicated by the HL register is read into the B register by the command "LD B, (HL)" on the fourth line of FIG. 204 (b). At this time, the address "T_ERR_RCV" is set in the HL register as shown in FIG. 204 (a). Therefore, the 1-byte value "(T_ERR_RCV_-T_ERR_RCV) / 2" in the second line of FIG. 204 (c) is read into the B register as the number of data (number of repeated transfers). In the example of FIG. 204 (c), the number of data is 4. The command on the fourth line of FIG. 204 (b) corresponds to step S5 of FIG. 201 (b).

The value of the HL register is incremented by 1 by the command "INC HL" on the fifth line of FIG. 204 (b). The value stored in the address specified by the value stored in the address indicated by the HL register by the command "LDINTQR (HL)" on the 6th line, plus "1" in the HL register. Is transferred, "2" is added to the value of the HL register, the address to be transferred next is set, the value of the B register is decremented (subtracted by "1"), and the process is performed until the decremented result becomes 0. Repeated. The commands on the 5th and 6th lines correspond to steps S6 and S7 in FIG. 201 (b).

Here, the command "LDINTQR (HL)" sets the value of the Q register as the upper 1 byte of the address, sets the value stored in the address indicated by the HL register as the lower 1 byte of the address, and sets the value in the HL register at that address. The value stored in the address indicated by the value obtained by adding "1" is transferred, the value of the HL register is updated by adding "2" to the value of the HL register, and the value of the B register is decremented (subtracted by "1"). ), And the value transfer is repeated until the decrement result becomes 0. The command size of such a command is "2" and the execution cycle is "5".

For example, when the HL register is the value of the address "T_ERR_RCV", the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of "_ERR_NUM" in the third line of FIG. 204 (c) is the value of the address. The lower 1 byte is set, the value of "0" in the third line of FIG. 204 (c) is transferred to the address, "2" is added to the value of the HL register, and the value of the B register is decremented ("1"). The transfer is repeated until the decrement result becomes 0, that is, four times.

Subsequently, the interrupt is permitted by the command "EI" on the 7th line of FIG. 204 (b). The command on the seventh line corresponds to step S8 in FIG. 201 (b). The data saved in the stack area is returned to the BC register by the command "POP BC" on the 8th line. The command on the eighth line corresponds to step S9 in FIG. 201 (b). Then, the command "RET" on the 9th line returns to the routine one step higher. The command on the ninth line corresponds to step S10 in FIG. 201 (b).

The total command size of the commands of the TABLEST module in FIG. 204 (b) is the command "PUSH BC" on the second line + the command "DI" on the third line + the command "LD B, (HL)" on the fourth line. 1 byte + 5th line command "INC HL" 1 byte + 6th line command "LDINTQR (HL)" 2 bytes + 7th line command "EI" 1 byte + 8th line command "POP BC" 1 byte + 9th line Command "RET" 1 byte = 9 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 1 cycle + 4th line 2 cycles + 5th line 1 cycle + 6th line 5 cycles + 7th line 1 cycle + 8th line 3 cycles + 9th line 3 cycles = 19 cycles. Therefore, as compared with the case of FIG. 202 (b), the total command size is reduced by 3 bytes, and the total execution cycle is also reduced by at least 4 cycles. In particular, in the example of FIG. 202 (b), if the value of the B register in the command "DJNZ TABLEST10" is 2 or more, the value is 10 cycles (6th line 4 cycles + 7th line 3 cycles + 8th line 3 cycles). Since the total execution cycle increases by the amount multiplied by, the reduction amount of the total execution cycle in FIG. 204 (b) also increases. With such a TABLEST module, it is possible to further shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, here, the A register and the C register are not used as compared with the example of FIG. 202. Therefore, the value of the A register and the value of the C register are not unintentionally updated. Further, in the example of FIG. 202, when the A register and the C register are already used, it is necessary to stack and save the values of the A register and the C register. However, here, the A register and the C register are used. Since it does not, stack processing is not required. In this way, resources can be effectively used.

Further, in order to be able to understand by comparing FIG. 202 (b) and FIG. 204 (b), the command group that occupied the 4th line (5th to 8th lines) in FIG. 202 (b) is shown in FIG. In 204 (b), it can be represented by two lines (fifth and sixth lines), and it is possible to reduce the number of commands themselves and the design load.

<DECWMQ>
FIG. 205 is a flowchart showing a specific process of the IPT_PC module. The IPT_PC module executes a time monitoring process that is read once every four times in step S3100-21 of the timer interrupt process (see FIG. 98). The numerical value of step S in such a figure will be used only in the description of this figure.

The time monitoring process is a process of subtracting one timer at a time (for example, a timer between games) set in the various steps of FIGS. 82 to 98.

As shown in FIG. 205 (a), the main CPU 500a reads the address in which the timer is stored into the HL register (S1), executes the WORDDEC module shown in FIG. 205 (b) (S2), and then stores the timer in the HL register. The value of the indicated address is subtracted by 1 (S3). Then, the command "RET" terminates the WORDDEC module and returns to the IPT_PC module (S4).

FIG. 206 is an explanatory diagram for explaining an example of a command for realizing the IPT_PC module. The flowchart shown in FIG. 205 is realized by, for example, the program shown in FIG. 206. Note that FIG. 206 describes, as an example, a process of subtracting a timer between games.

The index “IPT_PC:” in the first line of FIG. 206A indicates the start address of the IPT_PC module. Then, by the command "LDQ HL, (LOW_GAM_TMR)" on the second line of FIG. 206 (a), the value of the Q register is read into the H register, and the value of the lower 1 byte of the address "_GAM_TMR" is read into the L register. The command on the second line corresponds to step S1 in FIG. 205 (a).

Then, the command "CALLF WORDDEC" on the third line of FIG. 206 (a) calls the WORDDEC module shown in FIG. 206 (b). The command on the second line corresponds to step S2 in FIG. 205 (a).

The index “WORDDEC:” in the first line of FIG. 206B indicates the start address of the WORDDEC module. Then, it is stored in the address shown in the HL register (more strictly, the address shown in the HL register and the next address) by the command "DCPWLD (HL), 0" on the second line of FIG. 206 (b). The 2-byte length value (one-game timer) is read, and 1 is subtracted (updated) from the read value. Then, when 1 is set in the carry flag by subtraction, that is, when the read value is 0 (predetermined value), the address indicated in the HL register (more strictly, in the HL register). A fixed value "0 (specific value)" is stored in the indicated address and the next address). On the other hand, when 1 is not set in the carry flag, that is, when the read value is 1 or more, the subtracted value is indicated in the address indicated in the HL register (more strictly, in the HL register). Address and the next address). The command on the second line corresponds to step S3 in FIG. 205 (b).

Then, the command "RET" on the third line of FIG. 206 (b) terminates the WORDDEC module and returns to the IPT_PC module. The command on the third line corresponds to step S4 in FIG. 205 (b). In this way, it is possible to decrement one by one for each process until the 2-byte length value (one-game timer) stored at the address indicated by the HL register becomes 0.

Here, the command group of FIGS. 206 (a) and 206 (b) can be changed as shown in FIG. 206 (c). Here, the description of the processes substantially the same as those in FIGS. 206 (a) and 206 (b) will be omitted, and only the different processes in FIG. 206 (c) will be described.

By the command "DECWMQ (LOW_GAM_TMR)" on the second line of FIG. 206 (c), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_GAM_TMR" is set to the lower 1 byte of the address. The value stored at that address is read. Then, 1 is subtracted (decremented) from the read value, and when 1 is set in the carry flag by subtraction, that is, when the read value is 0, a fixed value " 0 "is stored. On the other hand, when 1 is not set in the carry flag, that is, when the read value is 1 or more, the subtracted value is stored in the address.

Here, the total command size of the command group shown in FIGS. 206 (a) and 206 (b) is the command "LDQ A, (LOW _GAM_TMR)" in the second line of FIG. 206 (a) + 2 bytes + FIG. 206. Command "CALLF WORDDEC" on the 3rd line of (a) 2 bytes + Command "DCWPLD (HL), 0" on the 2nd line of Fig. 206 (b) 4 bytes + Command "Command" on the 3rd line of Fig. 206 (b) RET ”1 byte = 9 bytes, and the total execution cycle is 2 cycles in the 2nd row in FIG. 206 (a) + 4 cycles in the 3rd row in FIG. 206 (a) + 9 cycles in the 2nd row in FIG. 206 (b) + 3 cycles in the 3rd row of FIG. 206 (b) = 18 cycles.

On the other hand, the total command size of the command group shown in FIG. 206 (c) is the command "DECWMQ (LOW_GAM_TMR)" on the second line, 3 bytes = 3 bytes, and the total execution cycle is 8 cycles on the second line = 8 cycles. It becomes.

Therefore, by replacing the command group of FIGS. 206 (a) and 206 (b) with the command group of FIG. 206 (c), the total command size is reduced by 6 bytes, and the total execution cycle is also reduced by 10 cycles. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in order to be able to understand by comparing FIG. 206 (a) and FIG. 206 (c), the command group occupying the second line (second to third lines) in FIG. 206 (a) is shown in FIG. In 206 (c), it can be represented by one line (second line), and it is possible to reduce the number of commands themselves and the design load.

Further, in the example of FIG. 206 (c), the WORDDEC module can also be deleted, and a valuable general-purpose module area can be freed up and other modules can be arranged in the area. In this way, resources can be effectively used.

<RIBIT>
FIG. 207 is a flowchart showing a specific process of the CMDPROC module. The CMDPROC module executes the above subcommand transmission process (see step S3100-11 in FIG. 98). The numerical value of step S in such a figure will be used only in the description of this figure.

As shown in FIG. 207, the main CPU 500a acquires the value of the interrupt waiting monitor register (S1). Here, the interrupt waiting monitor register is composed of 1 byte, and a power cutoff warning signal is input to the 6th bit. When the power supply voltage of the slot machine 400 becomes equal to or lower than a predetermined value, a power supply cutoff warning signal is input, the sixth bit of the interrupt waiting monitor register becomes 1, and in other cases, it becomes 0.

The main CPU 500a determines whether the power supply cutoff warning signal is input, that is, whether there is an external interrupt request by referring to the sixth bit of the acquired interrupt waiting monitor register (S2). Then, if there is an external interrupt request (YES in S2), the CMDPROC module is terminated and the routine returns one step higher. If there is no external interrupt request (NO in S2), the process moves to the next process and a subcommand is issued. It is transmitted to the sub-control board 502.

FIG. 208 is an explanatory diagram for explaining an example of a command for realizing the CMDPROC module. The flowchart shown in FIG. 207 is realized by, for example, the program shown in FIG. 208.

The index “CMDPROC:” in the first line of FIG. 208 (a) indicates the start address of the CMDPROC module. Then, by the command "INA, (@IRR _____)" on the second line of FIG. 208 (a), the value of the U register is set to the upper 1 byte of the address, and a fixed value indicating the lower 1 byte of the address of the interrupt waiting monitor register is set. “@IRR _____” is set as the lower 1 byte of the address, and the value stored at that address is read into the A register. The command on the second line corresponds to step S1 in FIG. 207.

Then, according to the command "RBIT NZ, 6, A" on the third line of FIG. 208 (a), if the sixth bit of the value stored in the A register is not 0, that is, if it is 1, the command "RET" is used. Is executed, the CMDPROC module is terminated and the routine returns to the next higher routine. On the other hand, if the 6th bit of the value stored in the A register is 0, the process is moved to the next command. The command on the third line corresponds to step S2 in FIG. 207.

Here, the command group of FIG. 208 (a) can be changed as shown in FIG. 208 (b). Here, the description of the process substantially the same as that shown in FIG. 208 (a) will be omitted, and only the different processes shown in FIG. 208 (b) will be described.

By the command "RIBIT NZ, 6, (@IRR _____)" on the second line of FIG. 208 (b), the value of the U register is set to the upper 1 byte of the address, and a fixed value indicating the lower 1 byte of the address of the interrupt waiting monitor register. If "@IRR _____" is the lower 1 byte of the address and the 6th bit of the value stored at that address is not 0, the CMDPROC module is terminated and one step higher so that the command "RET" is executed. Return to routine. On the other hand, if the 6th bit of the value stored at that address is 0, the process moves to the next command.

Here, the total command size of the command group shown in FIG. 208 (a) is 2 bytes of the command "INA, (@IRR _____)" on the second line + 2 bytes of the command "RBIT NZ, 6, A" on the third line. = 4 bytes, and the total execution cycle is 3 cycles in the 2nd row + 5 (3) cycles in the 3rd row = 8 (6) cycles. The number of cycles in parentheses indicates the execution cycle when the command "RBIT NZ, 6, A" does not move.

On the other hand, the total command size of the command group shown in FIG. 208 (b) is the command "RIBIT NZ, 6, (@IRR _____)" on the second line, 3 bytes = 3 bytes, and the total execution cycle is 7 on the second line. (5) Cycle = 7 (5) Cycle. The number of cycles in parentheses indicates the execution cycle when the command "RIBIT NZ, 6, (@IRR _____)" does not move.

Therefore, by replacing the command group of FIG. 208 (a) with the command group of FIG. 208 (b), the total command size is reduced by 1 byte, and the total execution cycle is also reduced by at least one cycle. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in the example of FIG. 208 (b), the A register used in FIG. 208 (a) is not used. Therefore, the value of the A register is not unintentionally updated. Further, in the example of FIG. 208 (a), when the A register is already used, it is necessary to stack and save the value of the A register. However, since the A register is not used here, the stack processing is also performed. unnecessary. In this way, resources can be effectively used.

Further, in order to be able to understand by comparing FIG. 208 (a) and FIG. 208 (b), the command group occupying the second line (second to third lines) in FIG. 208 (a) is shown in FIG. In 208 (b), it can be represented by one line (second line), and it is possible to reduce the number of commands themselves and the design load.

<AND + OR>
FIG. 209 is a flowchart showing a specific process of the SET_PLS module. The SET_PLS module executes the excitation pattern update process read in the stepping motor control process (see step S3100-13 in FIG. 98). The numerical value of step S in such a figure will be used only in the description of this figure.

As shown in FIG. 209, the main CPU 500a acquires the start address of the excitation pattern table in which the excitation pattern of the stepping motor 452 is stored (S1). The main CPU 500a adds, that is, offsets the offset value stored in the A register in advance to the start address of the acquired excitation pattern table (S2).

Then, the main CPU 500a acquires an output image stored in a predetermined output port (S3), and masks the upper 4 bits of the acquired output image (S4). The output image acquired here has a length of 1 byte, and the excitation pattern of the stepping motor 452 is shown in the upper 4 bits. Therefore, here, the excitation pattern is cleared by masking the upper 4 bits of the output image.

After that, the main CPU 500a synthesizes an excitation pattern by ORing the value indicated by the offset address in step S2 and the acquired output image (S5), and updates the synthesized excitation pattern as an output image. Then, the SET_PLS module is terminated and the routine returns to the next higher routine (S7).

FIG. 210 is an explanatory diagram for explaining an example of a command for realizing the SET_PLS module. The flowchart shown in FIG. 209 is realized by, for example, the program shown in FIG. 210.

The index “SET_PLS:” in the first line of FIG. 210 (a) indicates the start address of the SET_PLS module. Then, the command “LD HL, T_PLS_PTN” on the second line of FIG. 210 (a) reads the address “T_PLS_PTN” of the excitation pattern table in which the excitation pattern of the stepping motor 452 is stored into the HL register. The command on the second line corresponds to step S1 in FIG. 209.

Then, the command "ADDWB HL, A" on the third line of FIG. 210 (a) adds the value of the A register (offset value) to the value of the HL register, and updates the value of the HL register. The command on the third line corresponds to step S2 in FIG. 209.

After that, the value (output image) stored in the output port address "IY + @ OFS_OUT_PRT" is read into the A register by the command "LDA, (IY + @ OFS_OUT_PRT)" on the fourth line of FIG. 210 (a). The command on the fourth line corresponds to step S3 in FIG. 209.

Subsequently, the command "AND A, 000001111B" on the fifth line of FIG. 210 (a) calculates the logical product of the A register value (output image) and the fixed value "000011111B" (first value). (The upper 4 bits are masked), and the operation result is stored in the A register. The command on the fifth line corresponds to step S4 in FIG. 209.

Then, by the command "OR A, (HL)" on the sixth line of FIG. 210 (a), the value of the A register (masked output image) and the value stored at the address shown in the HL register (excitation pattern). , The second value) is calculated, and the calculation result is stored in the A register. The command on the sixth line corresponds to step S5 in FIG. 209.

After that, the value of the A register is stored in the output port address "IY + @ OFS_OUT_PRT" by the command "LD (IY + @ OFS_OUT_PRT), A" on the seventh line of FIG. 210 (a). The command on the seventh line corresponds to step S6 in FIG. 209. Then, the command "RET" on the eighth line of FIG. 210 (a) terminates the SET_PLS module and returns to the routine one step higher. The command on the eighth line corresponds to step S7 in FIG. 209.

Here, the command group of FIG. 210 (a) can be changed as shown in FIG. 210 (b). Here, the description of the process substantially the same as that shown in FIG. 210 (a) will be omitted, and only the different processes shown in FIG. 210 (b) will be described.

The command "RST CALADRS" on the third line of FIG. 210 (b) calls the CALADRS module shown in FIG. 210 (c). The index "CALADRS:" in the first line of FIG. 210 (c) indicates the start address of the CALADRS module. Then, the command "ADDWB HL, A" on the second line of FIG. 210 (c) adds the value of the A register (offset value) to the value of the HL register, and updates the value of the HL register. Then, the command "LDA, (HL)" on the third line reads the 1-byte value stored in the address indicated by the HL register into the A register. Then, the command "RET" on the fourth line of FIG. 210 (c) terminates the CALADRS module and returns to the SET_PLS module.

After that, by the command "AND (IY + @ OFS_OUT_PRT), 000001111B" on the fourth line of FIG. 210 (b), the logic of the value (output image) stored in the address "IY + @ OFS_OUT_PRT" and the fixed value "000011111B". The product is calculated (the upper 4 bits are masked), and the calculation result is stored in the address "IY + @ OFS_OUT_PRT".

Then, by the command "OR (IY + @ OFS_OUT_PRT), A" on the fifth line of FIG. 210 (b), the value (masked output image) stored in the address "IY + @ OFS_OUT_PRT" and the value of the A register ( The logical sum with the excitation pattern) is calculated, and the calculation result is stored in the address "IY + @ OFS_OUT_PRT".

Here, the total command size of the command group shown in FIG. 210 (a) is the command "LD HL, T_PLS_PTN" on the second line, 3 bytes + the command on the third line, "ADDWB HL, A", 1 byte + the command on the fourth line. "LD A, (IY + @ OFS_OUT_PRT)" 3 bytes + 5th line command "AND A, 00000111B" 2 bytes + 6th line command "OR A, (HL)" 1 byte + 7th line command "LD (IY + @)" OFS_OUT_PRT), A "3 bytes + 8th line command" RET "1 byte = 14 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 1 cycle + 4th line 4 cycles + 5th line 2 cycles + 6th line 2 cycles + 7th row 4 cycles + 8th row 3 cycles = 19 cycles.

On the other hand, the total command size of the command group shown in FIG. 210 (b) is the command "LD HL, T_PLS_PTN" on the second line, 3 bytes + the command "RST CALADRS" on the third line, and the command "AND (" on the fourth line. IY + @ OFS_OUT_PRT), 00000111B "4 bytes + 5th line command" OR (IY + @ OFS_OUT_PRT), A "3 bytes + 6th line command" RET "1 byte = 12 bytes, and the total execution cycle is 2nd line 3 Cycle + 3rd row 4 cycles + 4th row 7 cycles + 5th row 6 cycles + 6th row 3 cycles = 23 cycles.

Therefore, by replacing the command group of FIG. 210 (a) with the command group of FIG. 210 (b), the total command size is reduced by 2 bytes. By such replacement, it is possible to shorten the command and secure the capacity of the control area for performing the game control process. The CALADRS module, which is a general-purpose module, is read and executed by another module, and is not newly added.

Further, as can be understood by comparing FIG. 210 (a) and FIG. 210 (b), the command group of FIG. 210 (c) can be reduced by two lines from the command group of FIG. 210 (a). It is possible to reduce the number of commands themselves and the design load.

<CPLBQ>
FIG. 211 is a flowchart showing a specific process of the OTM_ATK module. The numerical value of step S in such a figure will be used only in the description of this figure.

Here, as another example of the slot machine 400, a so-called chance zone effect state is provided. The chance zone effect state is a state in which it is easier to win the AT lottery than the normal effect state, and is shifted over a predetermined game. For example, the chance zone production state is shifted over eight games, and an AT lottery is performed for each game. Then, in another example of the slot machine 400, the results of the AT lottery in each game in the chance zone production state are stored in 1 bit (winning = 1, non-winning = 0), so that the results of all AT lottery are totaled. It is managed as 8-bit (1 byte length) pass / fail information.

The OTM_ATK module executes the process of managing the result of such an AT lottery. The OTM_ATK module is called and executed in the execution flag setting process shown in step S2400-11 in FIG. 91 only when the AT lottery is won in each game.

As shown in FIG. 211, the main CPU 500a acquires the number of games in the chance zone effect state (S1) and acquires the address of the number of games bit table (S2). In the game number bit table, as will be described in detail later, bit information corresponding to each of the first to eighth games in the chance zone effect state is continuously arranged, and each bit information is the game. The bit (1 bit information) corresponding to is 1 and the other bits are 0, which is 1 byte length data.

The main CPU 500a acquires bit information corresponding to the acquired number of games from the game number bit table (S3), and also acquires 1-byte length win / loss information (1-byte information) indicating the result of the AT lottery (S4). ). Then, the main CPU 500a updates (synthesizes) the hit / miss information by calculating the logical sum of the acquired bit information and the hit / miss information (S5), and saves the updated hit / miss information (S6). The OTM_ATK module is terminated and the routine returns to the next higher routine (S7).

FIG. 212 is an explanatory diagram for explaining an example of a command for realizing the OTM_ATK module. The flowchart shown in FIG. 211 is realized by, for example, the program shown in FIG. 212.

The index “OTM_ATK:” in the first line of FIG. 212 (a) indicates the start address of the OTM_ATK module. Then, by the command "LDQ A, (LOW_CZ_CNT)" on the second line of FIG. 212 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_CZ_CNT" is set to the lower 1 byte of the address. One byte is set, and the value (number of games) stored at that address is read into the A register. The command on the second line corresponds to step S1 in FIG. 211.

Then, the command "LD HL, T_XXX_XXX" on the third line of FIG. 212 (a) reads the start address "T_XXX_XXX" of the game number bit table shown in FIG. 212 (b) into the HL register. The command on the third line corresponds to step S2 in FIG. 211.

The index "T_XXX_XXX:" in the first row of FIG. 212 (b) indicates the start address of the table "T_XXX_XXX". The value "00000001B" in the second row of FIG. 212 (b) corresponds to the first game in the chance zone effect state, and only 0 bits are 1 and the other bits are 0. Similarly, the values in the 3rd to 9th lines of FIG. 212 (b) correspond to the 2nd to 8th games in the chance zone effect state, the bit corresponding to the game is 1, and the other The bit is 0.

The CALADRS module is called by the command "RST CALADRS" on the fourth line of FIG. 212 (a). In the CALADRS module, the value of the A register (number of games) is added to the value of the HL register, the value of the HL register is updated, and the value stored at the address indicated in the updated HL register (number of games). The bit information corresponding to) is read into the A register. The command on the fourth line corresponds to step S3 in FIG. 211.

By the command "LDQ B, (LOW_ATW_BIT)" on the fifth line of FIG. 212 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_ATW_BIT" is set to the lower 1 byte of the address. Then, the value (right / wrong information) stored at that address is read into the B register. The command on the fifth line corresponds to step S4 in FIG. 211.

The logical sum of the A register value (bit information corresponding to the number of games) and the B register value (win / fail information) is calculated by the command “OR A, B” on the sixth line of FIG. 212 (a). Here, when the AT lottery is won in the game, the bit corresponding to the number of games is set to 1 in the winning / failing information. The command on the sixth line corresponds to step S5 in FIG. 211.

By the command "LDQ (LOW_ATW_BIT), A" on the 7th line of FIG. 212 (a), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_ATW_BIT" is set to the lower 1 byte of the address. Then, the value of the A register (updated pass / fail information) is stored at that address. The command on the seventh line corresponds to step S6 in FIG. 211.

Then, the command "RET" on the eighth line of FIG. 212 (a) terminates the OTM_ATK module and returns to the routine one step higher. The command on the eighth line corresponds to step S7 in FIG. 211.

Here, the command group of FIG. 212 (a) can be changed as shown in FIG. 212 (c). Here, the description of the process substantially the same as that shown in FIG. 212 (a) will be omitted, and only the different processes shown in FIG. 212 (c) will be described.

By the command "CPLBQ A, (LOW_ATW_BIT)" on the third line of FIG. 212 (c), the value of the Q register is set to the upper 1 byte of the address, and the value of the lower 1 byte of the address "_ATW_BIT" is set to the lower 1 byte of the address. Then, among the values (win / fail information) stored in the address, the bits corresponding to the values (number of games) of the A register are inverted. Therefore, here, in the winning / failing information, the bit corresponding to the game (number of games) won in the AT lottery is inverted and becomes 1.

Here, the total command size of the command group shown in FIG. 212 (a) is the command "LDQ A, (LOW _CZ_CNT)" on the second line, 2 bytes + the command "LD HL, T_XXX_XXX" on the third line, 3 bytes + 4 lines. First command "RST CALADRS" 1 byte + 5th line command "LDQ B, (LOW _ATW_BIT)" 3 bytes + 6th line command "OR A, B" 1 byte + 7th line command "LDQ (LOW _ATW_BIT), A "2 bytes + 8th line command" RET "1 byte = 13 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 3 cycles + 4th line 4 cycles + 5th line 4 cycles + 6th line 2 cycles + 7 3 cycles in the 8th line + 3 cycles in the 8th line = 22 cycles.

On the other hand, the total command size of the command group shown in FIG. 212 (c) is 2 bytes of the command "LDQ A, (LOW _CZ_CNT)" on the 2nd line + 3 bytes of the command "CPLBQ A, (LOW _ATW_BIT)" on the 3rd line. The command "RET" on the + 4th line is 1 byte = 6 bytes, and the total execution cycle is 3 cycles on the 2nd line + 6 cycles on the 3rd line + 3 cycles on the 4th line = 12 cycles.

Therefore, by replacing the command group of FIG. 212 (a) with the command group of FIG. 212 (c), the total command size is reduced by 7 bytes, and the total execution cycle is also reduced by at least 10 cycles. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

Further, in order to be able to understand by comparing FIG. 212 (a) with FIG. 212 (c), the command group occupying the 5th line (3rd to 7th lines) in FIG. 212 (a) is shown in FIG. In 212 (c), it can be represented by one line (third line), and it is possible to reduce the number of commands themselves and the design load.

Further, by replacing with the command group shown in FIG. 212 (c), the game number bit table becomes unnecessary, so that the data capacity for the game number bit table can be reduced.

<LDSB>
FIG. 213 is an explanatory diagram for explaining an example of a command for realizing the KRS_JDG module.

Here, as another example of the gaming machine 100, in a predetermined round game in a major role game, when the game ball enters the probability variation area (specific area) provided in the large winning opening, the gaming state after the major role game is displayed. Set to high probability gaming state. Then, in the large role game in which the predetermined special symbol is determined, when the predetermined number of games passes through the large winning opening in the predetermined round game, the probability variation area is opened and the game ball can enter the probability variation area. .. In the following, the probability variation area is opened when three game balls enter the large winning opening in the first round game and when five game balls enter the large winning opening in the fifth round game. This will be described with an example.

The KRS_JDG module executes the process of managing the opening of the probability variation region. The KRS_JDG module is called and executed in the large winning opening opening control process shown in FIG. 47.

The index “KRS_JDG:” in the first line of FIG. 213 (a) indicates the start address of the KRS_JDG module. Then, by the command "LDQ A, (LOW R_ROU_CNT)" on the second line of FIG. It is set to 1 byte, and the value stored in the address (the number of continuous operations of the special electric accessory, that is, the number of round games) is read into the A register.

Then, by the command "LD B, (HL)" on the third line of FIG. 213 (a), the value of the address indicated by the value stored in the HL register is read into the B register. The address "D_KRS_JDG_2" of the probability variation region determination table shown in FIG. 213 (b) is read in advance in the HL register.

The index “D_KRS_JDG_2:” in the first row of FIG. 213 (b) indicates the start address of the table “D_KRS_JDG_2”. The value "(@ D_KRS_JDG_2-D_KRS_JDG2-1) / 2" in the second line of FIG. It is a value obtained by subtracting 1 and dividing by 2, and indicates the number of determinations (the number of round games in which the probability variation region is opened).

The value “@KRS_TGT_ROU_01” in the third row of FIG. 213 (b) is a value (target round value, here 1) indicating the first round game that opens the probability variation region, and is 4 in FIG. 213 (b). The value in the line "@ KRS_JDG_01" is a value indicating how many game balls enter the large winning opening in the first round game to open the probability change area (opening identification value, open identification value, Here, it is 3). Similarly, the value "@KRS_TGT_ROU_03" in the fifth row of FIG. 213 (b) is a value (target round value, here, 5) indicating the second round game in which the probability variation region is opened, and is in FIG. 213 (b). ), The value "@ KRS_JDG_03" indicates how many game balls enter the big winning opening in the second round game to open the probability change area (open). The identification value, here, 5).

Therefore, the number of determinations is read into the B register by the command "LD B, (HL)" on the third line of FIG. 213 (a).

The index “KRS_JDG_10:” on the fourth line of FIG. 213 (a) indicates the address of the index “KRS_JDG_10”. The value of the HL register is incremented by 1 by the command "INC HL" on the fifth line of FIG. 213 (b). After that, the command "CP A, (HL)" on the sixth line of FIG. 213 (b) compares the value of the A register with the value stored at the address indicated by the value of the HL register (target round value). If the value of the A register is the same as the value of the HL register, the zero flag is set to 1, and if the value is different from the value of the HL register, the zero flag is not set and the value is 0.

Subsequently, the value of the HL register is incremented by 1 again by the command "INC HL" on the 7th line of FIG. 213 (a). After that, the value (open identification value) of the address indicated by the HL register is read into the C register by the command “LD C, (HL)” on the eighth line of FIG. 213 (a).

Then, when the zero flag is set by the command "RET Z" on the 9th line of FIG. 213 (a), the KRS_JDG module is terminated and the module returns to the next higher module.

If the zero flag is not set, the value of the B register is decremented (subtracted by "1") by the command "DJNZ KRS_JDG_10" on the 10th line of FIG. 213 (a), and if the decremented result is not 0, the address. If the result of moving to "KRS_JDG_10" and the decrement result is 0, the command "RET" on the 11th line of FIG. 213 (a) terminates the KRS_JDG module and returns to the next higher module.

Here, in the gaming machine 100, the maximum number of round games is 10. Further, the number of balls entered into the large winning opening for opening the probability variation region is set between 2 and 5 because the specified number of each round game is 10. That is, the target round value is a value of 10 or less and can be expressed by 4 bits. Therefore, the value "@KRS_TGT_ROU_01" and the value "@KRS_TGT_ROU_03" indicating the target round value are composed of 1 byte length, but may actually be 4 bits.

Further, the open identification value is a value of 5 or less and can be expressed by 3 bits. Therefore, the value "@KRS_JDG_01" and the value "@KRS_JDG_03" indicating the open identification value are composed of 1 byte length, but may actually be 3 bits.

Therefore, an example of treating two values, a target round value that can be expressed by 4 bits and an open identification value that can be expressed by 3 bits, as one value (data) having a byte length will be described below.

FIG. 214 is an explanatory diagram for explaining another example of the command for realizing the KRS_JDG module. The description of the process substantially the same as that of FIG. 213 will be omitted, and only the different process of FIG. 214 will be described.

The value of the address shown in the HL register is read into the B register by the command "LD B, (HL)" on the third line of FIG. 214 (a). The address "D_KRS_JDG_2" of the probability variation region determination table shown in FIG. 214B is read in advance in the HL register.

The value "@KRS_TGT_ROU_01 * 8 + @ KRS_JDG_01" in the third line of FIG. 214 (b) is a value (target round value) in which the upper 5 bits indicate the first round game in which the probability variation region is opened, and the lower 3 bits. However, it is a value (opening identification value) indicating how many game balls enter the large winning opening in the first round game to open the probabilistic variation area to open the probabilistic variation area. Similarly, the value “@ KRS_TGT_ROU_03 * 8 + @ KRS_JDG_03” in the fourth line of FIG. 214 (b) is a value (target round value) indicating the second round game in which the upper 5 bits open the probability variation region. The lower 3 bits are values (opening identification values) indicating how many game balls enter the large winning opening in the second round game to open the probability variation region to open the probability variation region.

By the command "LDSB 2, DE, (HL)" on the sixth line of FIG. 214 (a), the lower three bits of the value of the HL register are read into the E register (the other bits are set to 0), and the HL is set to 0. The upper 5 bits of the register value are shifted to the right by 3 bits and read into the D register (the other bits are set to 0). That is, the target round value and the open identification value are separated, the target round value is read into the D register, and the open identification value is read into the E register. Note that "2" in the command "LDSB 2, DE, (HL)" is a value indicating that the 3 bits from the 0th bit to the 2nd bit are read into the E register, and is a higher-order bit (1). It is a value indicating that (5 bits) is shifted and read to the D register.

The command "CP A, D" on the 7th line of FIG. 214 (a) compares the value of the A register with the value of the D register (target round value), and the value of the A register is the same as the value of the D register. If, the zero flag is set and becomes 1, and if it is different from the target round value, the zero flag is not set and becomes 0.

Here, the total command size of the command group shown in FIG. 213 (a) is 2 bytes of the command "LDQ A, (LOW R_ROU_CNT)" on the 2nd line + 1 byte of the command "LD B, (HL)" on the 3rd line. +5th line command "INC HL" 1 byte + 6th line command "CP A, (HL)" 1 byte + 7th line command "INC HL" 1 byte + 8th line command "LD C, (HL)" 1 byte + 9th line command "RET Z" 1 byte + 10th line command "DJNZ KRS_JDG_10" 2 bytes + 11th line command "RET" 1 byte = 11 bytes, total execution cycle is 2nd line 3 cycles + 3 Line 2 cycle + 5th line 1 cycle + 6th line 2 cycle + 7th line 1 cycle + 8th line 1 cycle + 9th line 3 (1) cycle + 10th line 3 (2) cycle + 11th line 3 (1) cycle = 19 (14) It becomes a cycle. Further, the probability variation region determination table shown in FIG. 213 (b) is 5 bytes. The number of cycles in parentheses indicates the execution cycle when the command does not move.

On the other hand, the total command size of the command group shown in FIG. 214 (a) is 2 bytes of the command "LDQ A, (LOW R_ROU_CNT)" on the 2nd line + 1 byte + 5 of the command "LD B, (HL)" on the 3rd line. Line command "INC HL" 1 byte + 6th line command "LDSB 2, DE, (HL)" 2 bytes + 7th line command "CP A, D" 1 byte + 8th line command "RET Z" 1 Bytes + 9th line command "DJNZ KRS_JDG_10" 2 bytes + 10th line command "RET" 1 byte = 11 bytes, and the total execution cycle is 2nd line 3 cycles + 3rd line 2 cycles + 5th line 1 cycle + 6th line 3 cycles + 7th row 1 cycle + 8th row 3 (1) cycle + 9th row 3 (2) cycle + 10th row 3 (1) cycle = 19 (14) cycle. Further, the probability variation region determination table shown in FIG. 214B is 3 bytes. The number of cycles in parentheses indicates the execution cycle when the command does not move.

Therefore, by replacing the command group of FIG. 213 (a) and the probability variation area determination table of FIG. 213 (b) with the command group of FIG. 214 (a) and the probability variation region determination table of FIG. 214 (b), the total size can be increased. 2 bytes are reduced. By such replacement, it is possible to shorten the command and reduce the processing load, and secure the capacity of the control area for performing the game control processing.

The command "LDSB" can be used when handling two values (information) of 8 bytes or less in total as one piece of data having a length of 1 byte, and can be applied even in cases other than the above examples. can.

Although the preferred embodiment of the present invention has been described above with reference to the accompanying drawings, it goes without saying that the present invention is not limited to such an embodiment. It is clear that a person skilled in the art can come up with various modifications or modifications within the scope of the claims, and it is understood that these also naturally belong to the technical scope of the present invention. Will be done.

<Beer hall>
For example, in the above-described embodiment, the electrical configuration and the mechanical configuration of the main control boards 300 and 500 that control the basic operation of the game are not particularly limited, but depending on the embodiment, the stability of the circuit operation may be determined. May affect.

In the gaming machine, a double-sided board in which wiring patterns are formed on the front surface and the back surface of the main control boards 300 and 500 may be used. In the double-sided substrate, via holes are provided to conduct the wiring pattern formed on the front surface and the wiring pattern formed on the back surface.

The via hole is formed so that the wiring pattern formed on the front surface and the wiring pattern formed on the back surface are made conductive by copper plating on the inner peripheral surface of the through hole penetrating the double-sided substrate.

However, since the via hole is hollow, the pattern width (cross-sectional area) is narrower than the wiring patterns formed on the front surface and the back surface. Therefore, the impedance (mainly the resistance) of the via hole becomes higher than that of the wiring pattern formed on the front surface and the back surface, and there is a possibility that the circuit operation becomes unstable. Therefore, the impedance is lowered to improve the stability of the circuit operation.

FIG. 215 is a diagram illustrating the configuration of the main control board 300. Here, the main control board 300 will be described among the main control boards 300 and 500. Note that FIG. 215 shows a front view of the main control board 300 as viewed from the surface 340a (one side). Further, in FIG. 215, for convenience of explanation, some of the electronic components arranged on the main control board 300 are shown, and in reality, electronic components (not shown) are also arranged on the main control board 300. Further, in FIG. 215, for convenience of explanation, the wiring pattern formed on the main control board 300 is omitted. The main control board 300 is mounted on the mass-produced gaming machine 100, and is the same as the one that has been tampered with in the inspection by the Public Safety Commission of the prefecture, etc., and that has been conformed in the type test. It is desirable that it is possible to determine whether it looks like it.

The main control board 300 is provided with a board main body 340. The substrate main body 340 is a double-sided substrate in which wiring patterns are formed on the front surface 340a and the back surface 340b (other surfaces, see FIG. 216). A plurality of electronic components are arranged on the surface 340a of the substrate main body 340. Examples of electronic components arranged on the board body 340 include a main CPU 300a (built-in main ROM 300b and main RAM 300c), IC 342, resistor 344, capacitor 346, LED 348, connector 350, switch 352, inductor (not shown), and the like. be.

Here, even if the electronic components are connected to each other by a wiring pattern formed only on the surface 340a, there may be a case where the patterns intersect and cannot be electrically separated. Therefore, these electronic components are connected to each other by wiring patterns formed on the front surface 340a and the back surface 340b of the substrate main body 340.

Further, the substrate main body 340 is formed with a plurality of via holes 354 for conducting the wiring pattern formed on the front surface 340a and the wiring pattern formed on the back surface 340b. The details of the beer hall 354 will be described in detail later.

Since the main control board 300 does not conform to the type test unless the electric components that can be arranged are DIP (Dual Inline Package) type electric components mounted on one side according to the rules, the occupied area of the electric components tends to increase. be. Here, if the occupied area is simply increased, the substrate main body 340 may become larger or the substrate main body 340 may become larger, which may make the layout design difficult. Therefore, by devising the arrangement of the electric parts in the substrate main body 340, the increase in the occupied area is suppressed.

The main CPU 300a and IC 342 are integrated circuits in which electrical components such as transistors, diodes, resistors, and capacitors are integrated. Further, the main CPU 300a and the IC 342 are composed of a main body formed in a flat plate shape and three or more leads 356 (see FIG. 216) protruding outward from the side surface of the long side of the main body. The leads 356 are arranged in the same number and evenly spaced on the two long side sides of the main body, and terminal numbers are sequentially assigned in the horizontal direction from the lower left to the lower right in the front view, and further, in the horizontal direction from the upper right to the upper left. Terminal numbers are assigned in sequence.

As described above, since the main CPU 300a and the IC 342 are formed vertically symmetrically in the front view, various measures are taken to prevent erroneous recognition of the vertical direction. For example, in an arrangement in which the first terminal is at the lower left in the front view (normal arrangement), a character string (not shown) is printed in the longitudinal direction at the center of the main body so as to be in the positive direction in the front view. Various notations such as alphabets, numbers, kana, kanji, and symbols can be applied to such character strings.

Further, in the main CPU 300a, the terminal 1 is arranged at the lower left in the front view, and an identifier is formed on the left side surface of the short side by cutting out a part of the left side in a semicircular shape. Further, in the IC 342, the terminal 1 is arranged at the lower left in the front view, and a circular identifier indicating the position of the terminal 1 is formed in the vicinity of the terminal 1.

The resistor 344, the capacitor 346, and the inductor are composed of a columnar or prismatic main body and leads 356 protruding outward from both ends thereof. The resistor 344, the capacitor 346, and the inductor are arranged parallel to the surface 340a of the substrate main body 340 (along the surface 340a). Further, on the resistor 344, the capacitor 346, and the inductor, endless bands having a color extending in a direction intersecting the direction in which the terminals protrude (protruding direction) are lined up in the protruding direction on the side surface portion of the columnar main body. Multiple prints are made. Then, the resistance value and accuracy of the resistor 344, the capacitance and accuracy of the capacitor 346, and the inductance and accuracy of the inductor can be specified by the color combination (color code) of the bands arranged in the protruding direction. Although the resistor 344 and the inductor have no polarity, some capacitors 346 have no polarity. It is desirable that the resistor 344, the capacitor 346, and the inductor can be visually determined to have the same performance without reading the color code values. Therefore, by arranging the resistors 344 having the same color code, the capacitor 346, and the inductor in the same direction, it is clear at a glance that they are the same electronic components even if the values are not read from the color code. It has become.

Here, an example is given in which all the electronic components are arranged on one surface (surface 340a) of the substrate main body 340. In addition, the mounting type of electronic components is an example of DIP type, but it is not limited to this case, and various mounting types such as SIP (Single Inline Package), SOP (Small Outline Package), and QFP (Quad Flat Package) are used. The type can be adopted. In DIP, since the distance between terminals is standardized, the electronic component alone occupies a certain area. Therefore, the effect of reducing the occupied area by devising the arrangement of the electronic components as shown below is likely to be remarkably generated for the DIP type electronic components.

Further, on the board main body 340, identification displays (CPU, IC1 to IC11, R1 to R9, C1 to C11, corresponding to the main CPU 300a, IC 342, resistor 344, capacitor 346, LED 348, connector 350, and switch 352 mounted are mounted. LEDs1 to LED5, CN1 to CN5, SW1) are printed in the vicinity thereof. Here, since the mounting location of the electrical component can be visually recognized, it is possible to prevent erroneous mounting. Further, the identification display is arranged at a position where it can be visually recognized (not hidden) from the front even after the electric component is mounted. Therefore, it is possible to improve workability even in confirmation after mounting. Further, in the identification display, a character string is printed so as to be in the positive direction in an arrangement in which the first terminal of the IC 342 is located at the lower left when viewed from the front. Therefore, it is possible to prevent erroneous recognition of the mounting direction of the IC 342.

Further, on the surface 340a, the display directions of such electrical component identification displays (CPU, IC1 to IC11, R1 to R9, C1 to C11, LEDs1 to LED5, CN1 to CN5, SW1) are unified as much as possible. By doing so, workability can be improved even in confirmation after mounting. Further, in a state where the resin case (not shown) for enclosing the main control board 300 is attached to the gaming machine 100, the identification display (CPU) of the main CPU 300a and the identification display (IC1 to IC11) of the IC 342 are all in front. It is attached to the surface of the main control board 300 so as to be in the positive direction visually. As a result, the operator can easily visually recognize the identification number even when the resin case for enclosing the main control board 300 is attached to the gaming machine 100, and the workability can be improved even in the confirmation after mounting. It will be possible.

Further, on the surface 340a, a guidance display for preventing misidentification of the mounting direction of the main CPU 300a and the IC 342 to be mounted is printed. For example, when the terminal 1 of the main CPU 300a is located at the lower left in the front view and an identifier is formed on the left side surface in the lateral direction by cutting out a part of the left side in a semicircular shape, the main CPU 300a is used as a substrate. A guidance display imitating the shape of the notch is printed on the substrate near the semicircular notch so that it can be placed correctly on the top. Further, when the IC 342 is arranged so that the 1st terminal is at the lower left and a circular identifier indicating the position of the 1st terminal is formed in the vicinity of the 1st terminal, the IC 342 can be correctly arranged on the substrate. A triangular (Δ) guidance display is printed on the substrate near the circular identifier. By doing so, it is possible to prevent erroneous recognition of the mounting direction of the IC 342, and it is possible to improve workability even in confirmation after mounting. If the capacitor has polarity, a positive (+) guide sign indicating the positive electrode may be printed on the substrate near the positive electrode of the capacitor.

Further, in order to smooth the input power of the IC 342, capacitors 346 are arranged respectively. As described above, one or a plurality of electric components may be arranged in association with each other in the IC 342. When arranging the capacitor 346 on the IC 342, it is necessary to bring the capacitor 346 as close to the IC 342 as possible in order to smooth the input power.

Therefore, in the main control board 300, when capacitors 346 are arranged in the vicinity of the IC 342 and the IC 342 and the capacitor 346 are regarded as one unit (observed integrally), one unit of long side x short side The capacitor 346 is arranged at a position and orientation where the area becomes smaller. For example, in the example of FIG. 215, the longitudinal direction of the capacitor 346 is arranged along the lateral direction of the IC 342. Here, the lengths of the long side of the capacitor 346 and the short side of the IC 342 are approximate (including the same length), and even if the longitudinal direction of the capacitor 346 is arranged along the short side of the IC 342. Since the rectangular shape can be roughly maintained and the area is also the short side of the IC 342 × (the long side of the IC 342 + the short side of the capacitor), the occupied area can be reduced.

Further, in IC 342, power supply terminals having different polarities are often arranged on two longitudinal side surfaces of the main body (for example, in IC 342, the positive electrode is the 20th terminal and the negative electrode is the 10th terminal). Therefore, by arranging the longitudinal direction of the capacitor 346 along the lateral direction of the IC 342, it is possible to minimize the connection between the power supply terminals having different polarities and both terminals of the capacitor 346, and the wiring pattern. Can also be minimized.

Here, an example in which one capacitor 346 is associated with one IC 342 has been described, but not limited to such a case, a plurality of electric components (resistor 344, capacitor 346, conductance) are attached to one IC 342. May be associated with. In this case, it is preferable to juxtapose the plurality of electric components so that the longitudinal directions are parallel to each other, and arrange all the electrical components along the lateral direction of the IC 342. Further, here, an example of associating one capacitor 346 with one IC 342 has been described, but the type and number of electrical parts are not limited.

Further, when a plurality of (for example, two) electric components are associated with one IC 342, the plurality of electric components are arranged in series so that their longitudinal directions are equal to each other, and the longitudinal directions of the plurality of electric components are set to the IC 342. It may be arranged along the longitudinal direction of. Here, the length of the long side when a plurality of electric parts are arranged in series and the length of the long side of the IC 342 are approximate (including the same length), and the longitudinal direction of the plurality of electric parts is the length of the IC 342. Even if it is arranged along the direction, the rectangular shape can be roughly maintained, and the area is also the long side of IC342 × (short side of IC342 + short side of electrical parts), so it is possible to reduce the occupied area. Become.

Further, in the substrate of FIG. 215, a resistor group in which a plurality of resistors 344 (here, nine) are provided as pull-up resistors and pull-down resistors may be arranged with respect to the IC 342. In this case as well, in order to fully utilize the functions of the pull-up resistor and the pull-down resistor, it is necessary to bring the resistor group as close to the IC 342 as possible.

Therefore, in the example of FIG. 215, when a plurality of resistors 344 are arranged in the vicinity of the IC 342 (IC7) and the IC 342 and the resistor group are regarded as one unit (observed integrally), the long side of one unit is taken. × Place the resistance group at a position and posture where the area of the short side becomes smaller. For example, in the example of FIG. 215, the plurality of resistors 344 are juxtaposed so that the longitudinal directions are parallel, and the juxtaposed directions are arranged along the longitudinal direction of the IC 342. Here, the short side of the resistor is shorter than the distance between the terminals of the IC 342, and the length of the resistance group in the juxtaposed direction and the length of the long side of the IC 342 are approximate (including the equal length), and the resistance groups are juxtaposed. Even if the direction is arranged along the length of the IC 342, the rectangular shape can be roughly maintained, and the area is also the long side of the IC 342 x (the short side of the IC 342 + the long side of the resistor), so that the occupied area should be reduced. Is possible.

Further, in the IC 342, terminals having the same functions such as input / output may be continuously arranged. Therefore, by arranging the resistance groups juxtaposed along the length of the IC 342, the connection between the continuous terminals of the IC 342 and one end of the plurality of resistors can be minimized, and the wiring pattern can be minimized. Can also be planned.

Here, an example of associating an electric component group having nine electric components (resistors 344) with one IC 342 has been described, but the number of electric components is arbitrarily determined not only in such a case. be able to. Further, here, an example of associating a resistor group in which a plurality of resistors 344 are provided with one IC 342 has been described, but the type and number may not matter as long as the shapes and functions of the electrical components are the same. Further, although a resistance group having a separate resistor 344 is applied here, for example, a resistance array (aggregate resistance) in which a plurality of resistors are integrally formed by molding or the like may be applied.

Further, by reducing the occupied area as described above, the density of electric parts per unit area can be increased. However, when the density of electrical components increases, it takes time to grasp the mounting position of the electrical component and to confirm the mounting position after mounting, which reduces workability. Here, workability is improved by improving the distinctiveness.

For example, in the region shown by the broken line on the substrate of FIG. 215, the IC 342 and the capacitor 346 are regularly arranged. Specifically, the positions of the left short sides of the IC 342 are aligned (equalized or almost equalized) in the left-right direction in the front view. In addition, the positions of the left short sides of the IC 342 are aligned in the vertical direction (equal to or substantially equal to each other) in the front view. In addition, the positions of the capacitors 346 are aligned in the left-right direction (equalized or almost equalized) in the front view. In addition, the positions of the capacitors 346 are aligned in the vertical direction (equal to or almost equal) in the front view. Then, the capacitors 346 and IC 342 are arranged in order (alternately) from the left side of the front view, and their center positions are aligned in the vertical direction (equalized or substantially equalized). Further, the IC 342 is associated with a capacitor 346 having the same subscript.

Here, by arranging the electric components regularly, it is possible to predict the position of another electric component from one electric component according to the rule. Therefore, the distinctiveness is improved, it becomes easy to grasp the mounting position of the electric component and to confirm the mounting position after mounting, and the workability can be improved.

For non-polar electric components such as a resistor 344, a capacitor 346, and an inductor, there is no problem in mounting the two terminals in either the vertical (left or right) direction. However, here, the directions are aligned (unified) among the electric components having the same function. For example, in FIG. 215, the arrangement (appearance) of the color codes of the resistor 344 and the capacitor 346 is arranged so as to be the same in the front view. With such an arrangement, it is possible to easily identify that the electric components are equal to each other or different from each other, and it is possible to improve workability.

Further, here, an example in which the color codes of the resistors 344 and the capacitors 346 are arranged in the same arrangement on all the main control boards 300 has been described, but the main control is not limited to this case. At least a part of the substrate 300 may be arranged so that the arrangement of the color codes of the plurality of electronic components is the same in the front view.

Further, at the time of inspection of the electric element attached to the main control board 300, for example, at the time of operation inspection in the manufacturing line of the gaming machine 100, the type test of the Safety Communication Association (Hotsukyo), which is a designated testing organization of the Public Safety Commission. It is possible to improve workability at the time of inspection at the time of inspection, on-site inspection by police or the like, at the time of inspection for identifying the faulty part when the gaming machine 100 breaks down, and the like.

FIG. 216 is a diagram illustrating joining of electronic components on the main control board 300. In FIG. 216 (a), the substrate main body 340 is shown in cross section. FIG. 216 (b) is a partially enlarged view of FIG. 216 (a). Here, IC 342 will be described as an example of an electronic component, but other electronic components are also joined in the same manner.

As shown in FIG. 216 (a), the IC 342 is provided with a plurality of leads 356. The number of leads 356 differs for each electronic component.

Further, a through hole 358 penetrating from the front surface 340a to the back surface 340b is formed in the substrate main body 340 in order to insert the lead 356 of the IC 342. The through hole 358 is formed to have an inner diameter through which the lead 356 can be inserted. Further, in the through hole 358, copper plating is applied over the inner peripheral surface in order to conduct at least one of the wiring pattern formed on the front surface 340a and the wiring pattern formed on the back surface 340b and the lead 356 of the IC 342. It is given.

Then, when the IC 342 is joined to the substrate main body 340, the IC 342 is arranged on the substrate main body 340 from the surface 340a side, and the lead 356 of the IC 342 is inserted into the through hole 358. The tip of the lead 356 inserted through the through hole 358 protrudes from the back surface 340b. After that, the conductive solder 360 is soldered to the lead 356 protruding from the back surface 340b by a flow method. As a result, the IC 342 is joined to the substrate main body 340, the IC 342 is fixed to the substrate main body 340, and the IC 342 is electrically connected to the wiring pattern formed on the main control board 300.

In the main control board 300, after all the electronic components are arranged on the surface 340a of the board main body 340, that is, after the leads 356 of all the electronic components are inserted into the through holes 358, the board main body 340 By immersing the back surface 340b in the melting solder, the melting solder flows between the lead 356 and the through hole 358, and the electronic component is bonded to the substrate main body 340.

By the way, as shown in FIG. 216 (b), the back surface 340b is covered with an insulating resist 364 while forming a wiring pattern 362. While the resist 364 covers the wiring pattern 362, it is not applied around the through hole 358 (annular).

Then, the periphery of the through hole 358 functions as a land 366 with the wiring pattern 362 exposed. The solder 360 joins the lead 356 to the substrate main body 340 so as to cover the land 366. As a result, the lead 356 conducts with the wiring pattern 362 via the solder 360.

FIG. 217 is a diagram illustrating a via hole 354. As shown in FIG. 217, the via hole 354 is formed by a through hole penetrating from the front surface 340a to the back surface 340b. The inner diameter of the via hole 354 is, for example, 0.2 to 0.3 mm. The via hole 354 is connected to the wiring pattern 362 provided on the front surface 340a of the substrate main body 340 and the wiring pattern 362 provided on the back surface 340b.

The via hole 354 is provided with copper plating 368 over the inner peripheral surface for conducting the wiring pattern 362 applied to the front surface 340a of the substrate main body 340 and the wiring pattern 362 applied to the back surface 340b. That is, in the via hole 354, the wiring pattern 362 applied to the front surface 340a of the substrate main body 340 and the wiring pattern 362 applied to the back surface 340b are made conductive by copper plating 368.

Here, the via hole 354 is usually hollow. However, when the via hole 354 is hollow, the pattern width of the copper-plated 368, that is, the cross-sectional area is narrower than that of the wiring pattern 362, so that the impedance is higher than that of the wiring pattern 362. More specifically, the via hole 354 has a higher resistance than the wiring pattern 362 and has a slightly higher inductance and capacitance.

Then, in the via hole 354, the influence on the high frequency signal and the voltage drop when the current flows may occur, and the circuit operation may become unstable.

Therefore, in the main control board 300 of the present embodiment, the front surface 340a and the back surface 340b of the board main body 340 are covered with the resist 364 so that the wiring pattern 362 is exposed around the via hole 354 (annular). Then, the portion where the wiring pattern 362 is exposed functions as a land 370.

Further, the inside of the via hole 354 is filled with conductive solder 372. In the main control board 300, when the electronic components arranged on the board main body 340 are soldered by the flow method, the land 370 formed on the back surface 340b is heated by the heat of the molten solder, and the copper plating 368 is formed. Is heated. Then, the molten solder adheres to the land 370 and flows into the copper plating 368 due to surface tension, and the inside of the via hole 354 is filled with the solder 372. Therefore, since the via hole 354 can be filled with the solder 372 together with the joining of the electronic components, the via hole 354 can be easily filled with the solder 372. The solder 372 may cover at least the land 370 (back surface 340b).

By filling the inside of the via hole 354 with the solder 372 in this way, the pattern width (cross-sectional area) of the via hole 354 can be made wider than the wiring pattern 362 formed on the front surface 340a and the back surface 340b of the substrate main body 340. can. As a result, the impedance of the via hole 354 can be made lower than that of the wiring pattern 362, and the stability of the circuit operation can be improved.

Ideally, all the via holes 354 provided on the main control board 300 are filled with solder 372, but even if only some of the via holes 354 are filled with solder 372, the effect of lowering the impedance is achieved. There is.

Ideally, the via holes 354 are completely filled with solder 372 from the front surface 340a to the back surface 340b, but even if only a part from the front surface 340a to the back surface 340b is filled with the solder 372, the impedance is increased. It has the effect of lowering.

In the above-described embodiment, the via hole 354 is filled with solder 372. However, if the via hole 354 is filled with a conductive member (conductive member), it may be another conductive member instead of the solder 372. Further, the via hole 354 may be filled with the conductive member by a method different from that of the electronic component (a method other than the flow method).

Further, in the above-described embodiment, the via hole 354 formed in the main control board 300 is filled with a conductive member (solder 372). However, the via holes 354 formed in the payout control board 310 and the sub-control board 330 may be filled with the conductive member (solder 372).

Further, in the above embodiment, the via hole 354 is filled with the conductive member in the main control board 300 which is a double-sided board. However, in a multilayer substrate in which wiring patterns 362 are formed in three or more layers, via holes 354 that conduct the wiring patterns 362 formed in different layers may be filled with a conductive member.

As described above, the main control board 300 has a substrate main body portion having a plurality of layers in which wiring patterns are formed, and via holes that penetrate the substrate main body portion and conduct wiring patterns formed in different layers. , And the inside of the via hole is filled with a conductive member. Further, the payout control board (game value imparting control board) 310 penetrates the board main body portion having a plurality of layers on which the wiring patterns are formed and the substrate main body portion to conduct the wiring patterns formed in different layers. A via hole is provided, and the inside of the via hole is filled with a conductive member. Further, the substrate includes a substrate main body having a plurality of layers on which wiring patterns are formed, and a via hole that penetrates the substrate main body and conducts wiring patterns formed in different layers to conduct each other. Is filled with a conductive member. Further, the substrate main body is formed with a through hole through which the lead of the electronic component is inserted, the lead of the electronic component is inserted into the through hole from one side, and wiring is performed around the via hole on the other surface of the board main body. Lands with exposed patterns may be formed. The game value-imparting control board is a board for imparting game value, and is a payout control board 310 for paying out medals in a slot machine 400, a frame control board for a so-called management game machine, and a so-called medalless game machine. A medal control board is included.

<Hold display production>
Further, in the effects appearing in the above-described embodiment, the player can easily guess whether or not an effect having a high expected value appears depending on the execution timing of various effects. When such a so-called first burr occurs, there is a problem that the effect of the effect is lowered. Therefore, in the present embodiment, it is possible to suppress a decrease in the effect of the effect due to the first burr.

For example, FIG. 67 shows that the hold display effect is performed in the hold display area during the variation effect. As described above, a plurality of display patterns of the hold display 212 are provided, and the display color is different for each display pattern. In the main control board 300, the acquisition-time effect determination process is executed when the hold is stored, and the look-ahead designation indicating the fluctuation information determined when the newly stored hold is read out to the 0th storage unit is specified. The command is transmitted to the sub-control board 330. When the sub-control board 330 receives the look-ahead designation command, the display pattern of the hold display 212 corresponding to the newly stored hold is determined based on the receive command. At this time, the selection ratio of each display pattern is set for each look-ahead designation command, that is, for each fluctuation information determined when the newly stored hold is read by the large winning combination lottery. That is, since the selection ratio of each display pattern is set according to whether or not the jackpot can be won and the execution pattern of the variable effect, the display pattern of the hold display 212 suggests the reliability of the jackpot.

Further, as another embodiment of the above-described embodiment, various advance notice effects suggesting the reliability of the jackpot are executed during the variation effect. Here, a specific effect will be described as an example of the advance notice effect.

FIG. 218 is a diagram illustrating an example of a specific effect. The specific effect is executed at various timings during the variable effect. For example, as shown in FIG. 218 (a), it is assumed that the effect symbols 210a, 210b, 210c are variablely displayed after the start of the variable effect. At this time, when the specific effect is executed, as shown in FIG. 218 (b), the cut-in image marked “strongest” is displayed on the main effect display unit 200a for a predetermined time. After that, instead of the cut-in image, as shown in FIG. 218 (c), the character image is displayed on the entire surface of the main effect display unit 200a. That is, in the specific effect of the present embodiment, the cut-in image and the character image are displayed on the main effect display unit 200a.

Here, the reliability of the jackpot is suggested by the specific effect. Specifically, the specific effect suggests that the reliability of the jackpot is high due to its appearance, and the reliability of the jackpot when the specific effect appears is set to, for example, 50%. In other words, if the result of the big role lottery is a loss, the appearance probability of the specific effect is low, and if the result of the big role lottery is a big hit, the appearance ratio is set so that the appearance probability of the specific effect is high. Has been done.

Although detailed description is omitted, the execution pattern of the specific effect may be only one or may be provided in a plurality. When a plurality of execution patterns of a specific effect are provided, for example, a plurality of cut-in images or character images are provided. In this case, the reliability of the jackpot can be different depending on the execution pattern of the specific effect.

In addition, the specific effect may be a definite effect in which the winning of the big hit is confirmed by the occurrence. Examples of the final effect include display of a predetermined image, output of sound, lighting of a lamp, operation of a movable body, and the like. Further, as the execution pattern of the specific effect, for example, a predetermined reach effect may be generated.

Further, here, as a specific effect, a cut-in image and a character image are displayed, but only one of these two images may be displayed. By displaying the image for the specific effect with a higher priority than the image for the other notice effect and the effect symbols 210a, 210b, 210c, the player can easily notice the appearance of the specific effect.

Although details will be described later, in the present embodiment, specific effects appear at various timings. This makes it difficult for the player to guess whether or not the specific effect appears, as compared with the case where the specific effect appears only at a preset timing, for example. On the other hand, during the variable effect, a notice effect different from the specific effect is also executed. Therefore, depending on the execution timing of the specific effect, the player may not notice the appearance of the specific effect due to the relationship with other effects. There is also sex. Therefore, in the present embodiment, attention is given to the specific effect in advance by executing the suggestion effect that suggests the appearance probability of the specific effect.

FIG. 219 is a diagram illustrating an example of a suggestion effect. The suggestion effect includes a point acquisition effect and a point notification effect. The point acquisition effect is an effect of acquiring any of 1 to 24 points, and is executed once or more during the suggestion effect. The point notification effect is an effect of notifying the player of the points acquired in the point acquisition effect by a meter. The higher the points acquired and notified in the suggestion effect, the higher the probability of appearance of the specific effect. That is, the suggestion effect suggests the appearance probability of the specific effect based on the acquired points.

Here, first, the point notification effect will be described in detail with reference to FIG. 219, and then the point acquisition effect will be described. In the point notification effect, as shown in FIG. 219 (a), a meter display unit 220 is provided at the lower right of the main effect display unit 200a. On the meter display unit 220, a meter indicating the points acquired in the point acquisition effect is displayed. Here, the meter is composed of four Chinese characters.

Specifically, as shown in FIG. 219 (b), the characters displayed on the meter display unit 220 are "Ikki Tousen", "Hyakka Ryoran", "Senjo Ikki", "Mansei Immortal", and "Sengoku Maiden". Five display patterns are provided. Here, "Ikki Tousen" is set to the first stage, "Hyakka Ryoran" is set to the second stage, "Senjo Ikki" is set to the third stage, and "Mansei Immortal" is set to the fourth stage. , "Sengoku Maiden" is set in the 5th stage.

In the point notification effect, first, the characters "Ikki Tousen" in the first stage are displayed on the meter display unit 220. In FIG. 219 (a), the character "1" is displayed in black, and the remaining three characters are displayed in white. This indicates that the points earned are 1 point. That is, in the point notification effect, the points acquired are given to the player by the display pattern of the characters displayed on the meter display unit 220 and the number of black-painted characters among the characters displayed on the meter display unit 220. Be notified.

Therefore, for example, when the points earned increase by one point from the state shown in FIG. 219 (a), as shown in FIG. 219 (b), the characters "Ikki Tousen" change to black one character at a time from the beginning. To go. Here, it is notified that the acquired points are any of 1 to 4 points by the display pattern of "Ikki Tousen" in the first stage.

Then, when the acquired points reach 5 points, the characters displayed on the meter display unit 220 change from the first stage "Ikki Tousen" to the second stage "Hyakka Ryouran". At this time, all four characters of "Hyakka Ryouran" are displayed in white, which informs that the current earned points are 5 points. As shown in FIG. 219 (b), the display pattern of the second stage notifies that the acquired points are 5 to 9 points depending on the display mode (the number of characters painted in black). Similarly, the display patterns of the third to fifth stages notify that the earned points are 10 to 14, 15 to 19, 20 to 24, respectively, depending on the display mode.

In the suggestion effect, when the display pattern finally displayed on the meter display unit 220 is the first stage or the second stage, the appearance probability (expected value of appearance) of the specific effect is low. Further, when the final display pattern is the third stage or the fourth stage, the expected value of the appearance of the specific effect is higher than when the final display pattern is the first stage and the second stage. .. Further, when the final display pattern is the fifth stage, the expected appearance value of the specific effect is further higher than when the final display pattern is the third stage and the fourth stage.

Then, when the acquired points are 24 points and all the characters of "Sengoku Maiden", which is the display pattern of the fifth stage, are displayed in black, the appearance of the specific effect is confirmed. That is, in this case, the specific effect is always executed thereafter.

It should be noted that the point notification effect only needs to be able to identify the current stage. Therefore, for example, the meter display unit 220 may be displayed only when the stage changes without constantly displaying the meter display unit 220.

The point notification effect can be executed in parallel with the point acquisition effect. When both effects are executed in parallel, the meter (display pattern, display mode) on the meter display unit 220 is updated after the points are acquired in the point acquisition effect. In addition, the points acquired in the point acquisition effect may be updated at once in the point notification effect executed thereafter. In the present embodiment, three suggestion effect execution patterns are provided, a first suggestion pattern, a second suggestion pattern, and a third suggestion pattern, and different point acquisition effects are executed for each execution pattern of the suggestion effect. ..

As will be described in detail later, when the hold is stored, it is determined whether or not the specific effect is executed. Further, regardless of whether or not the specific effect is executed, whether or not the suggestion effect is executed and, when the suggestion effect is executed, the execution pattern is determined. Therefore, when the specific effect is executed, the suggestion effect may be executed before the specific effect, or only the specific effect may be executed without the suggestion effect being executed. In addition, although the suggestion effect is executed, the specific effect may not be executed. In this case, the suggestion effect is a so-called ghost effect, and the meter display unit 220 displayed by the suggestion effect is erased at a predetermined timing.

As described above, whether or not the suggestion effect is executed is determined when the hold is stored. In other words, whether or not the suggestion effect is executed is determined for each hold. In the following, the hold for which the execution of the suggestion effect is determined is referred to as a target hold, and the variable effect executed based on the target hold is referred to as a target variation or a target variation effect. The specific effect is executed during the target change, but the suggestion effect (point acquisition effect) may be started during the target change, or another change effect before the target change (hereinafter referred to as the pre-target change). It may be started during (call).

FIG. 220 is a diagram illustrating an example of a suggestion effect of the first suggestion pattern. The suggestion effect of the first suggestion pattern can start with both pre-target variation and target variation. Here, a case where the suggestion effect of the first suggestion pattern starts with the pre-target variation will be described. For example, it is assumed that the suggestion effect of the first suggestion pattern is executed during the pre-target variation (hereinafter, referred to as the target two-fold pre-variation) two times before the target variation. In this case, as shown in FIG. 220A, the point acquisition effect of the first pattern is executed.

In the point acquisition effect of the first pattern, for example, a cut-in image indicating that three hearts have been acquired is displayed on the main effect display unit 200a. In this first pattern of point acquisition effect, the heart indicates points. Therefore, the example of FIG. 220 (a) shows that 3 points have been obtained. In addition, it may be made to show that the point was acquired by the advance notice effect other than the cut-in image such as a predetermined pattern or character. After that, as shown in FIG. 220 (b), the heart-shaped point display unit 222 is displayed at the lower part of the main effect display unit 200a, and the numerical value displayed in the cut-in image, that is, the acquired points is transferred.

After that, as shown in FIG. 220 (c), the effect symbols 210a, 210b, 210c are stopped and displayed, the target two-time previous variation is completed, and then, as shown in FIG. 220 (d), the target variation 1 is displayed. It is assumed that the pre-target fluctuation before the target (hereinafter referred to as the pre-target fluctuation) has started. At this time, the point display unit 222 remains displayed. That is, the point display unit 222 maintains the display state over a plurality of fluctuation effects.

Then, it is assumed that the point acquisition effect of the first pattern is executed again and a cut-in image showing that four hearts have been acquired is displayed during the change before the target once, as shown in FIG. 220 (e). .. In this case, as shown in FIG. 220 (f), the numerical value displayed in the cut-in image is added to the acquired points displayed on the point display unit 222. As a result, the player is notified that he / she has obtained 7 points at this point.

After that, as shown in FIG. 220 (g), the effect symbols 210a, 210b, 210c are stopped and displayed, the one-time previous variation of the target ends, and then, as shown in FIG. 220 (h), the target variation starts. Suppose you did. Also in this case, the point display unit 222 remains displayed. Then, immediately after the start of the target variation, the point display unit 222 blinks, and immediately after that, the meter display unit 220 is displayed as shown in FIG. 220 (i). Then, as shown in FIG. 220 (j), the meter of the meter display unit 220 is updated by the number of acquired points displayed on the point display unit 222.

In this way, the points acquired during the pre-target fluctuation are collectively reflected on the meter display 220 at the start of the target fluctuation. Further, although not shown, the point acquisition effect shown in FIGS. 220 (a) and 220 (e) may be displayed once or a plurality of times even during the target change. In this case, the points displayed in the cut-in image are directly reflected on the meter display unit 220. For example, in the state shown in FIG. 220 (j), it is assumed that the point acquisition effect of the first pattern is executed and a cut-in image showing that one heart has been acquired is displayed. In this case, the characters "繚" are updated in black on the meter display unit 220.

Further, the suggestion effect of the first suggestion pattern may be executed only during the target change. In this case, the points displayed in the cut-in image are directly reflected on the meter display unit 220 without displaying the point display unit 222.

FIG. 221 is a diagram illustrating an example of a suggestion effect of the second suggestion pattern. The suggestion effect of the second suggestion pattern can also be started with both the pre-target variation and the target variation, similarly to the suggestion effect of the first suggestion pattern. Here, a case where the suggestion effect of the second suggestion pattern starts with the pre-target variation will be described. For example, it is assumed that the suggestion effect of the second suggestion pattern is executed during the fluctuation two times before the target. In this case, as shown in FIG. 221 (a), the point acquisition effect of the second pattern is executed.

In the point acquisition effect of the second pattern, "zone entry" is first displayed on the main effect display unit 200a. After that, as shown in FIG. 221 (b), a large number of characters fall and accumulate on the screen of the main effect display unit 200a, and the point display unit 222 is displayed below the main effect display unit 200a. .. At this time, the point display unit 222 displays the acquired points according to the number of accumulated characters.

After that, as shown in FIG. 221 (c), the effect symbols 210a, 210b, 210c are stopped and displayed, the variation before the target two times is completed, and then, as shown in FIG. 221 (d), the target one time before. Suppose the fluctuation starts. At this time, the accumulated characters and the point display unit 222 are still displayed on the main effect display unit 200a.

Then, during the one-time previous variation of the target, as shown in FIG. 221 (e), the acquisition effect of the second pattern is executed again, an image in which a larger number of characters are accumulated is displayed, and the point display unit 222 is displayed. Points earned will be updated. After that, as shown in FIG. 221 (f), the effect symbols 210a, 210b, 210c are stopped and displayed, the one-time previous variation of the target ends, and then, as shown in FIG. 221 (g), the target variation starts. Suppose you did. Also in this case, the accumulated characters and the point display unit 222 are still displayed.

Immediately after the start of the target variation, as shown in FIG. 221 (h), an animation is displayed in which the characters accumulated on the screen are discharged below the main effect display unit 200a, and FIG. 221 (i). As shown in, the meter display unit 220 is displayed. Then, as shown in FIGS. 221 (i) and 221 (j), the meter of the meter display unit 220 is updated by the number of acquired points displayed on the point display unit 222.

In addition, here, the case where the points acquired during the pre-target fluctuation are collectively reflected on the meter display unit 220 at the start of the target fluctuation has been described. That is, in this example, the point acquisition effect of the second pattern is executed only during the pre-target variation, and is not executed during the target variation. However, the point acquisition effect of the second pattern may be executed during the target change. In this case, as in the case of the above-mentioned one-time previous change of the target, the character remains accumulated even after the start of the target change, the character further falls during the target change, and the acquired points of the point display unit 222 are updated. Will be done. Then, the character is discharged at a predetermined timing during the target fluctuation, and the meter display unit 220 is updated.

It should be noted that a plurality of types of zones that can be entered may be provided, and the character deposition pattern may be different for each zone. In this case, the expected value of the accumulated character, that is, the expected value of the points to be acquired differs depending on the zone.

FIG. 222 is a diagram illustrating an example of a suggestion effect of the third suggestion pattern. The suggestion effect of the third suggestion pattern can only be initiated in the pre-target variation. For example, it is assumed that the hold is stored during the change two times before the target, and the execution of the suggestion effect of the third suggestion pattern is decided with this hold as the target hold. In this case, as shown in FIG. 222 (a), the hold display 212 (here, the second hold display 212c) corresponding to the target hold is displayed in a special display pattern.

After that, it is assumed that the target two-time previous change is completed and the target one-time previous change is started. At this time, as shown in FIG. 222 (b), two characters are displayed on standby on the right side of the main effect display unit 200a. Then, it is assumed that the one-time previous fluctuation of the target is completed and the target fluctuation is started. At this time, as shown in FIG. 222 (c), the two characters are still displayed on standby in the main effect display unit 200a.

Then, during the target variation, the meter display unit 220 is displayed as shown in FIG. 222 (d). In addition, an enlarged hold display that is an enlargement of the hold display 212 of the special display pattern is displayed in the center of the main effect display unit 200a, and an animation is displayed in which the two characters that have been displayed on standby attack the enlarged hold display. NS. During this attack animation, as shown in FIG. 222 (e), the acquired points are displayed, and as shown in FIG. 222 (f), the meters of the meter display unit 220 are displayed by the number of displayed acquired points. Will be updated.

Here, as shown in FIGS. 222 (g) and 222 (h), it is assumed that the acquired points are further displayed during the attack animation, and the meter of the meter display unit 220 reaches the maximum value. At this time, as shown in FIG. 222 (i), a specific effect may be executed immediately after the meter of the meter display unit 220 reaches the maximum value, or a predetermined time after the meter reaches the maximum value. After that, a specific effect may be executed. When the meter reaches the maximum value and the start timing of the specific effect is separated in time, as shown in FIG. 222 (j), the meter display unit 220 displays "waiting". The production is executed.

In this way, when the meter reaches the maximum value, is it possible to execute the specific effect by providing a case where the specific effect is immediately executed and a case where the specific effect is executed with the standby effect in between? It becomes difficult for the player to guess whether or not it is, and so-called first burr can be prevented. The processing on the sub-control board 330 for executing the specific effect and the suggestion effect will be described below.

FIG. 223 (a) is a diagram for explaining an example of specific fluctuation information, and FIG. 223 (b) is a diagram for explaining an example of the occurrence timing of the specific effect. As described above, when the large winning combination lottery is executed, the fluctuation information including the combination of the fluctuation mode number and the fluctuation pattern number is determined on the main control board 300. In the sub-control board 330, the execution pattern of the variation effect, the execution presence / absence of each notice effect during the variation effect, and the execution pattern are determined based on the variation information determined by the main control board 300.

Further, in the main control board 300, when the hold is stored, the acquisition-time effect determination process is executed, and the fluctuation information determined based on the newly stored hold is determined in advance. The result of this determination is transmitted to the sub-control board 330 as a look-ahead designation command. That is, the look-ahead designation command indicates the fluctuation information determined when the big winning combination lottery is executed. Then, in the sub-control board 330, whether or not to execute the specific effect is determined based on the received look-ahead designation command. At this time, the variation information indicated by the look-ahead designation command includes variation information in which the execution of the specific effect can be determined and variation information in which the non-execution of the specific effect is always determined. In the following, the variation information that can determine the execution of the specific effect is referred to as the specific variation information.

In the present embodiment, when the specific variation information is determined, the execution pattern of the variation effect is always the reach variation pattern. That is, the specific effect is executed only during the variation effect of the reach variation pattern, and is not executed during the variation effect of the reachless variation pattern. Further, the specific effect can be executed in both a pseudo continuous reach variation pattern and a normal reach variation pattern in which pseudo variation does not occur (hereinafter, referred to as normal reach).

As shown in FIG. 223 (a), the specific variation information is variation information in which the execution pattern of the variation effect in the first half is normal reach (shown as reach in the figure), pseudo 1, pseudo 2, and pseudo 3. For example, when the variation mode numbers are 01H and 0AH, the variation effect in the first half becomes a normal reach, and in the variation effect in the second half, one of the reach development effects is executed. In addition, in the case where the variation mode number is 01H and the case where the variation mode number is 0AH, the content of the variation effect in the first half excluding the notice effect is the same.

When the variation mode numbers are 11H, 12H, 1AH, 1BH, and 1CH, the variation effect in the first half is pseudo 1, and in the variation effect in the second half, one of the reach development effects is executed. When the variation mode numbers are 11H, 12H, 1AH, 1BH, and 1CH, the contents of the variation effect in the first half are the same except for the notice effect. Similarly, in FIG. 223 (a), when the variation mode number is 21H to 2EH, the variation effect in the first half is pseudo 2, and when the variation mode number is 31H to 3FH, the variation effect in the first half is pseudo 3.

Then, in each specific variation information, when a specific effect is executed, the generation timing thereof is set in advance. Here, as shown in FIG. 223 (b), the occurrence timing of the specific effect is set in the first half of the variable effect, but the occurrence timing of the specific effect may be set in the latter half of the variable effect.

Here, in the present embodiment, the occurrence timing of the specific effect is roughly classified into the occurrence point and the occurrence period. The generation point indicates a preset time point, and here, six generation points P1 to P6 are provided. For example, the generation points P1, P3, and P5 are the points at which the effect symbols 210a, 210b, and 210c are temporarily stopped and displayed in the pseudo mode in the first, second, and third pseudo fluctuations, respectively. Further, the generation points P2 and P4 are the points at which the effect symbols 210a, 210b, and 210c start the fluctuation display in the second and third pseudo fluctuations, respectively. The generation point P6 is a time when a preset time has elapsed, for example, 5 seconds after the start of the reach fluctuation.

On the other hand, the occurrence period indicates a preset period, and here, four occurrence periods T1 to T4 are provided. For example, the occurrence periods T1, T2, and T3 are undergoing the first, second, and third pseudo fluctuations, respectively, and the generation period T4 is undergoing the reach fluctuation.

When the generation timing of the specific effect is determined at the generation point, the specific effect always occurs at any of the generation points. On the other hand, when the generation timing of the specific effect is determined in the generation period, the specific effect is generated at any timing during the generation period. As shown in FIG. 223 (a), the timing of occurrence of the specific effect is predetermined for each specific variation information. That is, the generation timing of the specific effect is determined based on the specific fluctuation information.

Here, in the case where the specific effect is executed after the suggestion effect is executed, the points earned may be maximized in the suggestion effect. In this case, if the occurrence timing of the specific effect is determined to be one of the occurrence points, the acquired points are maximized at the timing before the occurrence point. Therefore, in this case, after the acquired points are maximized, the standby effect is executed until the generated points are reached (FIG. 222 (j)). On the other hand, if the occurrence timing of the specific effect is determined in any of the occurrence periods, the points earned will be the maximum during the occurrence period. In this case, the specific effect is executed immediately after the acquired points are maximized.

FIG. 224 is a diagram illustrating a specific effect execution lottery table. When the sub-control board 330 receives the look-ahead designation command, it determines whether or not to execute the specific effect by referring to the specific effect execution lottery table. Although only the specific variation information is shown in FIG. 224, the specific effect execution lottery table is configured so that whether or not the specific effect is executed is determined for all the variation information. As shown in the figure, according to the specific effect execution lottery table, the execution of the specific effect can be determined only for the specific variation information whose generation point is the occurrence timing of the specific effect.

In other words, according to the specific effect execution lottery table, the non-execution of the specific effect is always determined for the specific variation information in which the occurrence timing of the specific effect is the occurrence period and the variation information other than the specific variation information. As shown, the ratio is set. As will be described in detail later, the execution of the specific effect is determined by another lottery process for the specific variation information whose generation timing is the occurrence period of the specific effect.

FIG. 225 (a) is a diagram for explaining the effect system determination table, and FIG. 225 (b) is a diagram for explaining the additional lottery table. When it is determined whether or not to execute the specific effect, the effect system is determined with reference to the effect system determination table regardless of the result. Here, as the production system, a fixed system and an immediate activation system are provided. The fixed system is an effect pattern that executes a suggestion effect toward the occurrence point of the specific effect described above, and the immediate activation system is an effect pattern that executes the suggestion effect toward the occurrence period of the specific effect described above. Is.

According to the production system determination table, the fixed system is determined for the specific fluctuation information for which the occurrence point is specified, and the ratio is set so that the immediate activation system is determined for the specific fluctuation information for which the occurrence period is specified. It has been done. That is, among the effect systems, the fixed system indicates that the occurrence timing of the specific effect is the generation point, and the prompt activation system indicates that the occurrence timing of the specific effect is the generation period.

Further, when the effect system is determined to be the immediate activation system, the additional lottery table is further referred to, and which timing during the generation period is determined as the generation timing of the specific effect. In addition, in FIG. 225 (b), after 1s, after 2s, etc., the elapsed time from the start of the occurrence period is shown. For example, when 1 s later is determined, 1 second after the start of the generation period is the generation timing of the specific effect. According to the additional lottery table, the selection ratio is set as shown in the figure for the specific fluctuation information of the prompt activation system.

According to the present embodiment, even when the non-execution of the specific effect is determined, the effect system and the generation timing of the specific effect are determined. This is because the suggestion effect is executed even when the specific effect is not executed. That is, when only the suggestion effect is executed without executing the specific effect, this suggestion effect is a false suggestion effect. Even when this Gase suggestion effect is executed, it is necessary to execute the point acquisition effect at various timings as if the specific effect is executed at any timing. In this way, in order to set the reference point when executing the suggestion effect or the Gase suggestion effect, the effect system and the generation timing of the specific effect are determined regardless of whether or not the specific effect is executed.

FIG. 226 is a diagram illustrating a suggestion effect determination table. When the look-ahead designation command is received, the sub-control board 330 determines whether or not the suggestion effect is executed and the execution pattern by referring to the suggestion effect determination table regardless of whether or not the specific effect is executed. Here, two tables, a suggestion effect determination table a and a b, are provided. Then, when the newly stored hold is set as the target variation, if the suggestion effect can be started from the pre-target variation, whether or not the suggestion effect is executed is determined using the suggestion effect determination table a. On the other hand, if the suggestion effect cannot be started from the pre-target variation, that is, if the suggestion effect can be started only from the target variation, the suggestion effect determination table b is used to determine whether or not the suggestion effect is executed. Will be done.

According to the suggestion effect determination table, the selection ratio of whether or not to execute the suggestion effect is set for each specific fluctuation information. In addition, in FIG. 226, "non-execution" indicates that the suggestion effect is not executed, and the "first suggestion pattern", the "second suggestion pattern", and the "third suggestion pattern" are any execution patterns. Indicates whether to execute the suggestion effect.

As described above, the suggestion effect of the third suggestion pattern can be started only in the pre-target variation. Therefore, in the suggestion effect determination table b, the ratio is set so that the third suggestion pattern is not determined.

FIG. 227 is a diagram illustrating an earned point lottery table. When the execution of the suggestion effect is decided, the total number of points to be acquired during the suggestion effect is determined by referring to the earned points lottery table. Here, two tables, the earned point lottery tables a and b, are provided. Then, when the non-execution of the specific effect is determined, the acquired points are determined using the acquired point lottery table a, and when the execution of the specific effect is determined, the acquired point lottery table b is used. The points earned are determined.

According to the earned point lottery table, the ratio is set so that any earned point from 1 to 24 is determined for each specific fluctuation information. As described above, the maximum value of the acquired points is "24", and when the acquired points become "24", the execution of the specific effect is confirmed. Therefore, in the earned point lottery table a, the ratio is set so that "24" is not determined as the earned points, and in the earned point lottery table b, the ratio is set so that "24" can be determined as the earned points. Has been made.

Although detailed explanation is omitted, when the earned points are determined, the earned points are distributed to the target variation and the pre-target variation using a predetermined lottery table. At this time, when the earned points are allocated to each of the pre-target variation and the target variation, the point acquisition effect is executed for each of the pre-target variation and the target variation as a so-called look-ahead effect. Further, when the acquired points are distributed only to the pre-target variation, the point acquisition effect is executed in the pre-target variation, and the point notification effect is executed during the target variation. Further, when the acquired points are distributed only to the target variation, the point acquisition effect and the point notification effect are executed in the target variation. Among the processes on the sub-control board 330, the processes related to the suggestion effect and the specific effect will be described below.

(Sub CPU initialization process of sub control board 330)
Here, as another aspect of FIGS. 69 to 72 of the above-described embodiment, FIGS. 228 to 231 will be described.

FIG. 228 is a flowchart illustrating the sub CPU initialization process (S1000) of the sub control board 330.

(Step S1000-1)
When the power is turned on, the sub CPU 330a reads the CPU initialization processing program from the sub ROM 330b, and also initializes and sets the flags stored in the sub RAM 330c.

(Step S1000-3)
Next, the sub CPU 330a performs a process of updating each effect random number, and thereafter repeats the process of step S1000-3 until the interrupt process is performed. It should be noted that a plurality of types of effect random numbers are provided, and here, each effect random number is updated asynchronously.

(Subtimer interrupt processing of subcontrol board 330)
FIG. 229 is a flowchart illustrating subtimer interrupt processing (S1100) of the subcontrol board 330. The sub-control board 330 is provided with a reset clock pulse generation circuit (not shown) that generates a clock pulse at a predetermined cycle (30 times per second). Then, due to the generation of the clock pulse by the reset clock pulse generation circuit, the sub CPU 330a reads the timer interrupt processing program and starts the sub timer interrupt processing.

(Step S1100-1)
The sub CPU 330a saves the register.

(Step S1100-3)
The sub CPU 330a performs a process for permitting an interrupt.

(Step S1100-5)
The sub CPU 330a updates various timer counters used in the sub control board 330. Here, the various timer counters are subtracted by 1 each time the sub-timer interrupt processing of the sub-control board 330 is performed, and the subtraction is stopped when it reaches 0, unless otherwise specified.

(Step S1200)
The sub CPU 330a analyzes the command received from the main control board 300 and performs command reception processing according to the received command. This command reception process will be described later.

(Step S1100-7)
The sub CPU 330a turns the flag ON / OFF and outputs commands to various effect devices in order to execute various effects determined at the start of the variable effect. By this time schedule management process, output is started for each effect device.

(Step S1100-9)
The sub CPU 330a returns the register and ends the sub timer interrupt process.

FIG. 230 is a flowchart illustrating a look-ahead designation command reception process executed when a look-ahead designation command is received among the command reception processes on the sub-control board 330. The look-ahead designation command is set in steps S535-21, S535-25, and S536-27 in FIG. 33, and then transmitted to the sub-control board 330 in steps S100-65 in FIG.

(Step S1210-1)
The sub CPU 330a analyzes the received look-ahead designation command and stores the fluctuation information.

(Step S1210-3)
The sub CPU 330a refers to the specific effect execution lottery table (FIG. 224), determines whether or not the specific effect is executed, and stores it based on the received look-ahead designation command.

(Step S1210-5)
The sub CPU 330a refers to the effect system determination table (FIG. 225 (a)), determines the effect system based on the received look-ahead designation command, and stores the effect system.

(Step S1210-7)
The sub CPU 330a determines in step S1210-5 whether the immediate activation system has been determined. As a result, when it is determined that the prompt activation system has been determined, the process is transferred to step S1210-9, and when it is determined that the immediate activation system has not been determined, the process is transferred to step S1210-11.

(Step S1210-9)
The sub CPU 330a refers to the additional lottery table (FIG. 225 (b)), determines and stores the occurrence timing of the specific effect based on the received look-ahead designation command.

(Step S1210-11)
The sub CPU 330a refers to the suggestion effect determination table (FIG. 226), determines whether or not the suggestion effect is executed, and stores the execution pattern based on the received look-ahead designation command.

(Step S1210-13)
The sub CPU 330a determines in step S1210-11 whether the execution of the suggestion effect is determined. As a result, when it is determined that the execution of the suggestion effect is determined, the process is transferred to step S1210-17, and when it is determined that the execution of the suggestion effect is not determined, the process is transferred to step S1210-15.

(Step S1210-15)
The sub CPU 330a executes a hold display process for determining the display pattern of the hold display 212 displayed in the hold display effect, and ends the look-ahead designation command reception process. Further, here, a process for displaying the hold display 212 in the determined display pattern is performed.

(Step S1210-17)
The sub CPU 330a refers to the earned point lottery table (FIG. 227), determines and stores the earned points based on the received look-ahead designation command.

(Step S1210-19)
The sub CPU 330a performs a process of allocating the acquired points determined in step S1210-17 to the pre-target variation and the target variation.

(Step S1210-21)
The sub CPU 330a determines in step S1210-11 whether the third suggestion pattern has been determined as the execution pattern of the suggestion effect. As a result, when it is determined that the third suggestion pattern has been determined, the process is transferred to step S1210-23, and when it is determined that the third suggestion pattern has not been determined, the process is transferred to step S1210-15.

(Step S1210-23)
The sub CPU 330a determines the display pattern of the hold display 212 as a special pattern, and ends the look-ahead designation command reception process.

FIG. 231 is a flowchart illustrating a variable command receiving process executed when a variable command (variable mode command and a variable pattern command) is received among the command receiving processes on the sub-control board 330. The variable command is set in steps S612-13 and S612-17 of FIG. 39, and then transmitted to the sub-control board 330 in steps S100-65 of FIG.

(Step S1220-1)
The sub CPU 330a analyzes the received variable command.

(Step S1220-3)
Based on the analysis result of step S1220-1, the sub CPU 330a performs the variation effect determination process for determining the execution pattern of the variation effect with reference to the variation effect determination table (FIG. 66).

(Step S1220-5)
The sub CPU 330a determines whether it is determined to execute the suggestion effect during the variation effect. As a result, when the suggestion effect is executed, the process is transferred to step S1220-7, and when the suggestion effect is not executed, the process is transferred to step S1220-23.

(Step S1220-7)
The sub CPU 330a determines whether or not it is a target variation of the suggestion effect. As a result, if it is the target variation of the suggestion effect, the process is transferred to step S1220-9, and if it is not the target variation of the suggestion effect, the process is transferred to step S1220-11.

(Step S1220-9)
The sub CPU 330a further allocates the acquired points allocated to the target variation in step S1210-19 to the executable timing of the point acquisition effect during the target variation. For example, the execution timing of the point acquisition effect is set at two or three places for each pseudo variation or reach variation, and here, the executable timing prior to the execution timing of the specific effect is determined.

As the occurrence timing, when the specific fluctuation information in which the occurrence point is defined is received, the executable timing before the occurrence point is selected. On the other hand, as the occurrence timing, when the specific fluctuation information for which the occurrence period is defined is received, at least one executable timing during the occurrence period is selected.

(Step S1220-11)
The sub CPU 330a determines the detailed content of the point acquisition effect.

(Step S1220-13)
The sub CPU 330a determines whether or not it is determined to execute the specific effect in the variable effect. As a result, when the specific effect is executed, the process is transferred to step S1220-15, and when the specific effect is not executed, the process is transferred to step S1220-23.

(Step S1220-15)
The sub CPU 330a determines whether the total number of points acquired in the suggestion effect is 24 (maximum). As a result, if it is determined that the acquired points are the maximum, the process is transferred to step S1220-17, and if it is determined that the acquired points are not the maximum, the process is transferred to step S1220-23.

(Step S1220-17)
The sub CPU 330a determines whether the effect system of the suggestion effect is an immediate activation system. As a result, if it is an immediate activation system, the process is transferred to step S1220-19, and if it is not an immediate activation system, the process is transferred to step S1220-21.

(Step S1220-19)
The sub CPU 330a sets the execution timing of the point acquisition effect to be executed last as the execution timing of the specific effect.

(Step S1220-21)
The sub CPU 330a sets the generation point specified in the specific fluctuation information at the execution timing of the specific effect, and executes the standby effect from the execution timing of the last point acquisition effect to the execution timing of the specific effect. Performs standby effect execution processing.

(Step S1220-23)
The sub CPU 330a performs a command setting process for setting a command in the operation buffer for all the effects executed during the variation effect determined in each of the above steps, and ends the variation command reception process. Here, the command set in the operation buffer is transmitted to the effect device according to the elapsed time from the start of the variation effect in the time schedule management process of step S1100-7. Further, here, a command related to a suggestion effect or a specific effect whose execution is determined when the hold is stored is also set in the operation buffer.

It should be noted that the above-mentioned playability, that is, the progress condition of the game and various control methods is only an example. The content of the game profit given to the player, such as the type, number, and content of the symbols, can be appropriately designed within the range in which the object of the present invention can be realized. In the above embodiment, the case where the progress of the game is controlled according to the registered set value has been described, but the registered set value is not essential. Further, in the present embodiment, a plurality of gaming states are provided, but one gaming state may be provided. Further, in the above embodiment, the big hit symbol and the small hit symbol are provided, but only one of the big hit symbol and the small hit symbol may be provided.

In the above embodiment, the case where the suggestion effect can be executed from the pre-target variation as the so-called look-ahead effect has been described, but the suggestion effect may be executed only in the target variation. Therefore, in the above embodiment, the presence / absence of execution of the specific effect and the suggestion effect is determined when the hold is stored, but the presence / absence of execution of the specific effect and the suggestion effect may be determined at the start of the variable effect.

In the above embodiment, it is decided that a plurality of execution patterns of the suggestion effect are provided, but only one execution pattern of the suggestion effect may be provided. Further, when a plurality of execution patterns of the suggestion effect are provided, the expected value at which the specific effect is executed, that is, the expected value of the acquired points may differ depending on the execution pattern.

The contents of the specific effect and the suggestion effect in the above embodiment are merely examples, and can be appropriately designed. For example, as a specific effect, a notice effect in which a predetermined image is displayed on the main effect display unit 200a may be adopted, or an accessory effect in which the effect accessory device 202 operates may be adopted. In any case, whether or not the specific effect is executed may be determined according to a predetermined condition, and the specific content of the suggestive effect is particularly limited as long as it is an effect that can be executed before the start of the specific effect. It's not a thing.

In the above embodiment, the standby effect is executed as the predetermined effect to be executed after the suggestive effect is executed and before the start of the specific effect, but the content of the predetermined effect can be appropriately designed. For example, as the standby effect, the time until the start of the specific effect may be counted down, as in the so-called timer effect. In any case, it is sufficient that the predetermined effect can be executed after the suggestion effect is executed in the predetermined execution pattern and before the start of the specific effect. Then, as the flow of the effect, the first pattern in which the specific effect is executed after the predetermined effect is executed after the suggestion effect is executed, and the first pattern in which the specific effect is executed without the predetermined effect being executed after the suggestion effect is executed. It suffices if there are two patterns.

In the above embodiment, when a predetermined period elapses after the suggestion effect is executed, or immediately after the suggestion effect is executed, the execution timing of the specific effect can be determined, and the predetermined period after the suggestion effect is executed. When is determined as the execution timing of the specific effect, it is decided to execute the predetermined effect during the predetermined period, but the execution timing of the specific effect is not limited to this. For example, the specific effect is not executed immediately after the suggestion effect is executed, and may always be executed when a predetermined period has elapsed since the suggestion effect was executed. At this time, there may be cases where the predetermined effect is executed and cases where the predetermined effect is not executed.

Further, for example, when the first period elapses after the suggestion effect is executed, or when the second period different from the first period elapses after the suggestion effect is executed, the specific effect is executed. The timing can be determined, and when the second period elapses after the suggestion effect is executed is determined as the execution timing of the specific effect, the predetermined effect may be executed during the second period. In this case, the second period may be shorter or longer than the first period.

In the above embodiment, the sub CPU 330a that executes the process of step S1210-3 in FIG. 230 corresponds to the specific effect execution determination means of the present invention.

Further, in the above embodiment, the sub CPU 330a that executes the process of step S1210-11 in FIG. 230 corresponds to the suggestion effect execution determination means of the present invention.

Further, in the above embodiment, the sub CPU 330a that executes the process of step S1100-7 of FIG. 229 corresponds to the specific effect executing means, the suggestion effect executing means, and the predetermined effect executing means of the present invention.

As described above, the gaming machine has a specific effect execution determining means for determining whether or not to execute the specific effect, a specific effect executing means for executing the specific effect when the execution of the specific effect is decided, and a specific effect. Suggestion effect execution determining means for determining whether or not to execute the suggestion effect that can be executed before the start of A first method comprising a predetermined effect executing means capable of executing a predetermined effect after the effect is executed and before the start of the specific effect, and the specific effect is executed after the predetermined effect is executed after the suggestive effect is executed. There is a pattern and a second pattern in which a specific effect is executed without executing a predetermined effect after the suggestion effect is executed. Further, the specific effect execution determining means determines when the first period elapses after the suggestion effect is executed, or when a second period different from the first period elapses after the suggestion effect is executed. , The execution timing of the specific effect can be determined, and the predetermined effect execution means determines the execution timing of the specific effect when the second period elapses from the execution of the suggestion effect, the second period. A predetermined effect may be executed during.

100 Pachinko machine 300, 500 Main control board 300a, 500a Main CPU
300b, 500b main ROM
300c, 500c main RAM
330, 502 Sub control board 330a, 502a Sub CPU
330b, 502b sub ROM
330c, 502c, sub RAM
400 slot machine

Claims (2)

A gaming machine comprising a CPU, a ROM in which a program used in the CPU is stored, and a RAM in which variables updated by the program are stored in a predetermined board used for the progress of the game.
The CPU
Read the program from the ROM,
Based on the program
The logical sum of the value of the first register and the value stored in the address indicated by the second register of the RAM is calculated.
A gaming machine that overwrites the result of the OR with a value stored at the address indicated by the second register. The CPU calculates the logical sum of the value of the first register and the value stored in the address indicated by the second register of the RAM without using a register different from the first register and the second register. The gaming machine according to claim 1, which is directly calculated.

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