JP2019057694A - Manufacturing method of multilayer substrate, manufacturing method of component mounting substrate, multilayer substrate and component mounting substrate - Google Patents

Manufacturing method of multilayer substrate, manufacturing method of component mounting substrate, multilayer substrate and component mounting substrate Download PDF

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JP2019057694A
JP2019057694A JP2017182701A JP2017182701A JP2019057694A JP 2019057694 A JP2019057694 A JP 2019057694A JP 2017182701 A JP2017182701 A JP 2017182701A JP 2017182701 A JP2017182701 A JP 2017182701A JP 2019057694 A JP2019057694 A JP 2019057694A
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substrate
interlayer connection
insulating substrate
hole
circuit pattern
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JP7048877B2 (en
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典史 笹岡
Norifumi Sasaoka
典史 笹岡
晃治 田口
Koji Taguchi
晃治 田口
勝又 雅昭
Masaaki Katsumata
雅昭 勝又
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Nichia Chemical Industries Ltd
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Nichia Chemical Industries Ltd
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Abstract

To provide a manufacturing method of a multilayer substrate which has the stable connection resistance value and high connection reliability in an interlayer connection part, and enables printing formation of a uniform insulation layer onto the interlayer connection part and component mounting, a manufacturing method of a component mounting substrate, the multilayer substrate and the component mounting substrate.SOLUTION: A manufacturing method of a multilayer substrate 100 includes: a process of forming a through hole 1 with punching processing so that a front surface circuit pattern 2 and a rear surface circuit pattern 3 are formed on the front surface and rear surface of an insulation substrate 4, and a portion of at least one circuit pattern on the front surface and rear surface of the insulation substrate 4 extends along the inner wall of the through hole 1 of the insulation substrate 4; and a process of forming an interlayer connection part 6 by filling the inside and circumference of the through hole 1 with the conductive paste by printing from both of the front surface and rear surface of the insulation substrate 4.SELECTED DRAWING: Figure 1B

Description

本開示は、多層基板の製造方法、部品実装基板の製造方法、多層基板、および、部品実装基板に関する。   The present disclosure relates to a multilayer board manufacturing method, a component mounting board manufacturing method, a multilayer board, and a component mounting board.

多層基板の層間接続部は、部品実装工程での熱処理や半田付け作業時の熱衝撃に耐える接続信頼性が必要である。例えば、特許文献1、特許文献2では、パンチング加工により貫通穴の形状を工夫し、貫通穴に導電性ペーストを充填することで、従来よりも接続信頼性の高い層間接続部を有した回路基板および回路基板の製造方法を開示している。   The interlayer connection portion of the multilayer substrate needs to have connection reliability that can withstand thermal shock during heat treatment and soldering work in the component mounting process. For example, in Patent Document 1 and Patent Document 2, a circuit board having an interlayer connection portion with higher connection reliability than conventional by devising the shape of the through hole by punching and filling the through hole with a conductive paste And a circuit board manufacturing method.

特開平7−302962号公報JP 7-302962 A 特開平10−51095号公報JP-A-10-51095

しかしながら上記特許文献の技術では、層間接続部の表面および裏面に平坦性がなく、層間接続部上に部品を実装することが難しい。また、例えば、印刷可能な絶縁樹脂をスクリーン印刷法などで形成する場合、層間接続部の表面および裏面に平坦性がないため、層間接続部の表面および裏面で絶縁層に歪みや段差などが生じる。そのため、絶縁層にボイド、ピンホールなどが生じ、均一な絶縁層の形成ができず、層間接続部近傍の電気絶縁性が低下する懸念がある。また、多層基板の層間接続部は、接続信頼性の他、安定した接続抵抗値が要求される。   However, in the technique of the above-mentioned patent document, the front and back surfaces of the interlayer connection part are not flat, and it is difficult to mount components on the interlayer connection part. In addition, for example, when a printable insulating resin is formed by a screen printing method or the like, there is no flatness on the front and back surfaces of the interlayer connection portion, so that the insulating layer is distorted or stepped on the front and back surfaces of the interlayer connection portion. . For this reason, voids, pinholes and the like are generated in the insulating layer, so that a uniform insulating layer cannot be formed, and there is a concern that the electrical insulation in the vicinity of the interlayer connection portion is lowered. Further, the interlayer connection portion of the multilayer substrate is required to have a stable connection resistance value in addition to connection reliability.

本開示に係る実施形態は、層間接続部において安定した接続抵抗値と高い接続信頼性を有し、層間接続部上への均一な絶縁層の印刷形成や部品実装が可能な多層基板の製造方法、部品実装基板の製造方法、多層基板、および、部品実装基板を提供することを課題とする。   Embodiments according to the present disclosure have a stable connection resistance value and high connection reliability in an interlayer connection, and a method for manufacturing a multilayer substrate capable of printing a uniform insulating layer on the interlayer connection and mounting components. It is an object of the present invention to provide a component mounting board manufacturing method, a multilayer board, and a component mounting board.

本開示の実施形態に係る多層基板の製造方法は、絶縁基板の表面および裏面に回路パターンが形成され、前記絶縁基板の表面および裏面のうちの少なくとも一方の前記回路パターンの一部が前記絶縁基板の貫通穴の内壁に沿って延出するようにパンチング加工により前記貫通穴を形成する工程と、前記貫通穴の内部および周囲に、前記絶縁基板の表面および裏面の両面から、印刷により導電性ペーストを充填して層間接続部を形成する工程と、を含む。   In the method for manufacturing a multilayer substrate according to an embodiment of the present disclosure, a circuit pattern is formed on a front surface and a back surface of an insulating substrate, and a part of the circuit pattern on at least one of the front surface and the back surface of the insulating substrate is the insulating substrate. Forming the through hole by punching so as to extend along the inner wall of the through hole, and conductive paste by printing from both the front and back surfaces of the insulating substrate in and around the through hole. And forming an interlayer connection part.

本開示の実施形態に係る部品実装基板の製造方法は、前記記載の多層基板の製造方法で製造された多層基板の表面および裏面にレジストを形成する工程と、前記レジストを形成した多層基板に部品を実装する工程と、を含む。   A component mounting board manufacturing method according to an embodiment of the present disclosure includes a step of forming a resist on the front and back surfaces of the multilayer board manufactured by the multilayer board manufacturing method described above, and a component on the multilayer board on which the resist is formed. Mounting.

本開示の実施形態に係る多層基板は、絶縁基板の表面および裏面に設けられた回路パターンと、前記絶縁基板および前記回路パターンを貫通する貫通穴に導電性ペーストが充填されて形成された層間接続部と、前記絶縁基板の表面および裏面のうちの少なくとも一方の前記回路パターンの一部が前記絶縁基板の前記貫通穴の内壁に沿って延出した延出部と、を備え、前記絶縁基板の表面および裏面における前記層間接続部の部位が平坦である。   A multilayer substrate according to an embodiment of the present disclosure includes a circuit pattern provided on a front surface and a back surface of an insulating substrate, and an interlayer connection formed by filling a conductive paste in a through hole penetrating the insulating substrate and the circuit pattern. A part of the circuit pattern of at least one of the front surface and the back surface of the insulating substrate extending along the inner wall of the through hole of the insulating substrate, and the insulating substrate The portions of the interlayer connection portion on the front surface and the back surface are flat.

本開示の実施形態に係る部品実装基板は、前記記載の多層基板に、実装部品が実装されたものである。   A component mounting board according to an embodiment of the present disclosure is obtained by mounting a mounting component on the multilayer board described above.

本開示に係る実施形態の多層基板の製造方法によれば、層間接続部において安定した接続抵抗値と高い接続信頼性を有し、層間接続部上への絶縁層の印刷形成や部品実装が可能な多層基板を製造することができる。
本開示に係る実施形態の部品実装基板の製造方法によれば、層間接続部において安定した接続抵抗値と高い接続信頼性を有し、また絶縁層の絶縁性が高い部品実装基板を製造することができる。
本開示に係る実施形態の多層基板によれば、層間接続部において安定した接続抵抗値と高い接続信頼性を有し、層間接続部上への絶縁層の印刷形成や部品実装が可能となる。
本開示に係る実施形態の部品実装基板によれば、層間接続部において安定した接続抵抗値と高い接続信頼性を有し、また絶縁層の絶縁性が高い。
According to the multilayer substrate manufacturing method of the embodiment according to the present disclosure, the interlayer connection portion has a stable connection resistance value and high connection reliability, and printing of an insulating layer on the interlayer connection portion and component mounting are possible. A multilayer substrate can be manufactured.
According to the method for manufacturing a component mounting board of the embodiment according to the present disclosure, a component mounting board having a stable connection resistance value and high connection reliability in an interlayer connection portion and having a high insulation property of an insulating layer is manufactured. Can do.
According to the multilayer substrate of the embodiment according to the present disclosure, the interlayer connection portion has a stable connection resistance value and high connection reliability, and an insulating layer can be printed on the interlayer connection portion and components can be mounted.
According to the component mounting board of the embodiment according to the present disclosure, the interlayer connection portion has a stable connection resistance value and high connection reliability, and the insulating layer has high insulation.

実施形態に係る多層基板の構成を模式的に示す平面図である。It is a top view showing typically the composition of the multilayer substrate concerning an embodiment. 実施形態に係る多層基板の構成を模式的に示す断面図であり、図1AのIB−IB線に相当する断面を示す。It is sectional drawing which shows typically the structure of the multilayer substrate which concerns on embodiment, and shows the cross section corresponded to the IB-IB line | wire of FIG. 1A. 実施形態に係る多層基板の製造方法における、回路パターンを形成する前の状態を示す断面図である。It is sectional drawing which shows the state before forming a circuit pattern in the manufacturing method of the multilayer substrate which concerns on embodiment. 実施形態に係る多層基板の製造方法における、回路パターンを形成する工程を示す断面図である。It is sectional drawing which shows the process of forming a circuit pattern in the manufacturing method of the multilayer substrate which concerns on embodiment. 実施形態に係る多層基板の製造方法における、貫通穴を形成する工程を示す断面図である。It is sectional drawing which shows the process of forming a through hole in the manufacturing method of the multilayer substrate which concerns on embodiment. 実施形態に係る多層基板の製造方法における、層間接続部を形成する工程を示す断面図であり、絶縁基板の裏面から導電性ペーストを充填する工程を示す断面図である。It is sectional drawing which shows the process of forming the interlayer connection part in the manufacturing method of the multilayer board | substrate which concerns on embodiment, and is sectional drawing which shows the process of filling with an electrically conductive paste from the back surface of an insulated substrate. 実施形態に係る多層基板の製造方法における、層間接続部を形成する工程を示す断面図であり、絶縁基板の表面から導電性ペーストを充填する工程を示す断面図である。It is sectional drawing which shows the process of forming the interlayer connection part in the manufacturing method of the multilayer board | substrate which concerns on embodiment, and is sectional drawing which shows the process of filling with an electrically conductive paste from the surface of an insulated substrate. 実施形態に係る多層基板の製造方法における、層間接続部の部位を研磨する工程を示す断面図である。It is sectional drawing which shows the process of grind | polishing the site | part of the interlayer connection part in the manufacturing method of the multilayer substrate which concerns on embodiment. 実施形態に係る部品実装基板の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of the component mounting board which concerns on embodiment. 実施形態に係る部品実装基板の製造方法における、レジストを形成する前の多層基板を示す断面図である。It is sectional drawing which shows the multilayer substrate before forming the resist in the manufacturing method of the component mounting board which concerns on embodiment. 実施形態に係る部品実装基板の製造方法における、レジストを形成する工程を示す断面図であり、多層基板の表面にレジストを形成する工程を示す断面図である。It is sectional drawing which shows the process of forming a resist in the manufacturing method of the component mounting board | substrate which concerns on embodiment, and is sectional drawing which shows the process of forming a resist on the surface of a multilayer substrate. 実施形態に係る部品実装基板の製造方法における、レジストを形成する工程を示す断面図であり、多層基板の裏面にレジストを形成する工程を示す断面図である。It is sectional drawing which shows the process of forming the resist in the manufacturing method of the component mounting board | substrate which concerns on embodiment, and is sectional drawing which shows the process of forming a resist in the back surface of a multilayer substrate. 実施形態に係る部品実装基板の製造方法における、部品を実装する工程を示す断面図であり、接着層を形成する工程を示す断面図である。It is sectional drawing which shows the process of mounting components in the manufacturing method of the component mounting board which concerns on embodiment, and is sectional drawing which shows the process of forming an contact bonding layer. 実施形態に係る部品実装基板の製造方法における、部品を実装する工程を示す断面図であり、部品を実装した後の状態を示す断面図である。It is sectional drawing which shows the process of mounting components in the manufacturing method of the component mounting board which concerns on embodiment, and is sectional drawing which shows the state after mounting components. 実施例で用いた、導電性ペーストを充填する前の層間接続部評価用基板を示す画像である。It is an image which shows the board | substrate for interlayer connection part evaluation before filling with the electrically conductive paste used in the Example. 図7Aの一部を拡大して示す画像である。It is an image which expands and shows a part of Drawing 7A. 実施例で用いた、導電性ペーストを充填した後の層間接続部評価用基板における層間接続部の接続状態を模式的に示す斜視図である。It is a perspective view which shows typically the connection state of the interlayer connection part in the board | substrate for interlayer connection part evaluation after filling with the electrically conductive paste used in the Example.

<実施形態>
実施形態を、以下に図面を参照しながら説明する。ただし、以下に示す形態は、本実施形態の技術思想を具現化するための多層基板の製造方法、部品実装基板の製造方法、多層基板、および、部品実装基板を例示するものであって、以下に限定するものではない。また、実施の形態に記載されている構成部品の寸法、材質、形状、その相対的配置などは、特定的な記載がない限り、本発明の範囲をそれのみに限定する趣旨ではなく、単なる例示に過ぎない。なお、各図面が示す部材の大きさや位置関係などは、説明を明確にするために誇張していることがある。
<Embodiment>
Embodiments will be described below with reference to the drawings. However, the forms shown below exemplify a multilayer board manufacturing method, a component mounting board manufacturing method, a multilayer board, and a component mounting board for embodying the technical idea of the present embodiment. It is not limited to. In addition, the dimensions, materials, shapes, relative arrangements, and the like of the components described in the embodiments are not intended to limit the scope of the present invention only to specific examples unless otherwise specified. Only. Note that the size and positional relationship of the members shown in each drawing may be exaggerated for clarity of explanation.

[多層基板]
まず、本実施形態に係る多層基板について説明する。
図1Aは、実施形態に係る多層基板の構成を模式的に示す平面図である。図1Bは、実施形態に係る多層基板の構成を模式的に示す断面図であり、図1AのIB−IB線に相当する断面を示す。
[Multilayer substrate]
First, the multilayer substrate according to the present embodiment will be described.
FIG. 1A is a plan view schematically showing the configuration of the multilayer substrate according to the embodiment. 1B is a cross-sectional view schematically showing the configuration of the multilayer substrate according to the embodiment, and shows a cross section corresponding to the line IB-IB in FIG. 1A.

多層基板100は、絶縁基板4と、絶縁基板4の表面に設けられた表面回路パターン2と、絶縁基板4の裏面に設けられた裏面回路パターン3と、貫通穴1に導電性ペーストが充填されて形成された層間接続部6と、表面回路パターン2の一部が絶縁基板4の貫通穴1の内壁に沿って延出した延出部20と、を備える。   In the multilayer substrate 100, the conductive paste is filled into the insulating substrate 4, the front surface circuit pattern 2 provided on the surface of the insulating substrate 4, the back surface circuit pattern 3 provided on the back surface of the insulating substrate 4, and the through hole 1. And an extended portion 20 in which a part of the surface circuit pattern 2 extends along the inner wall of the through hole 1 of the insulating substrate 4.

絶縁基板4としては、1枚もしくは複数枚のガラスクロスにエポキシ樹脂などの熱硬化性絶縁樹脂を含侵させ、この熱硬化性絶縁樹脂を硬化させたガラスエポキシや、フィルム状のポリイミド、液晶ポリマーなどが挙げられる。なお、絶縁基板4は、一般的に両面に銅箔が張り付いた両面銅張積層板として製造されている。
絶縁基板4がガラスエポキシである場合、厚さは50〜1000μmとすることができる。また、絶縁基板4がポリイミドである場合、厚さは12〜50μmとすることができる。絶縁基板4としては、このように、ある程度の厚みのある板から薄板まで用いることができる。
As the insulating substrate 4, one or a plurality of glass cloths are impregnated with a thermosetting insulating resin such as an epoxy resin, and the glass epoxy, film-like polyimide, or liquid crystal polymer in which the thermosetting insulating resin is cured. Etc. The insulating substrate 4 is generally manufactured as a double-sided copper-clad laminate with copper foil attached to both sides.
When the insulating substrate 4 is glass epoxy, the thickness can be 50 to 1000 μm. Moreover, when the insulating substrate 4 is a polyimide, thickness can be 12-50 micrometers. As the insulating substrate 4, it is possible to use a plate having a certain thickness to a thin plate.

表面回路パターン2は、絶縁基板4の表面上に形成されている。裏面回路パターン3は、絶縁基板4の裏面上に形成されている。表面回路パターン2および裏面回路パターン3は、所望の形状に配線して形成されている。表面回路パターン2および裏面回路パターン3は、銅などの金属性の材料からなる。   The surface circuit pattern 2 is formed on the surface of the insulating substrate 4. The back circuit pattern 3 is formed on the back surface of the insulating substrate 4. The front surface circuit pattern 2 and the back surface circuit pattern 3 are formed by wiring in a desired shape. The front surface circuit pattern 2 and the back surface circuit pattern 3 are made of a metallic material such as copper.

表面回路パターン2および裏面回路パターン3の厚みは、12〜70μmとすることが好ましい。表面回路パターン2および裏面回路パターン3の厚みが12μm以上であれば、表面回路パターン2および裏面回路パターン3を形成しやすい。一方、厚みが70μm以下であれば、多層基板100を薄くすることができる。   The thickness of the front surface circuit pattern 2 and the back surface circuit pattern 3 is preferably 12 to 70 μm. If the thickness of the front surface circuit pattern 2 and the back surface circuit pattern 3 is 12 μm or more, the front surface circuit pattern 2 and the back surface circuit pattern 3 are easily formed. On the other hand, if the thickness is 70 μm or less, the multilayer substrate 100 can be thinned.

貫通穴1は、表面回路パターン2、絶縁基板4、および、裏面回路パターン3を貫通するように形成されている。貫通穴1の直径は、例えば、0.2〜0.3mmである。   The through hole 1 is formed so as to penetrate the front surface circuit pattern 2, the insulating substrate 4, and the back surface circuit pattern 3. The diameter of the through hole 1 is, for example, 0.2 to 0.3 mm.

層間接続部6は、表面回路パターン2と裏面回路パターン3とを電気的に接続する部位である。層間接続部6は、貫通穴1に導電性ペーストを充填することで形成される。また、層間接続部6は、導電性ペーストを貫通穴1の内部および周囲に充填するとともに表面回路パターン2および裏面回路パターン3と十分接触させた状態で硬化させて形成されている。ここで貫通穴1の周囲とは貫通穴1の近傍であり、例えば貫通穴1から1mm以内、好ましくは0.3mm以内、より好ましくは0.1mm以内を指す。
層間接続部6は、貫通穴1に導電性ペーストを充填して形成されることで、部品などを実装する工程での熱衝撃に対する接続信頼性が向上する。
The interlayer connection portion 6 is a portion that electrically connects the front surface circuit pattern 2 and the back surface circuit pattern 3. The interlayer connection 6 is formed by filling the through hole 1 with a conductive paste. In addition, the interlayer connection portion 6 is formed by filling a conductive paste in and around the through-hole 1 and curing it in a state where it is sufficiently in contact with the front surface circuit pattern 2 and the back surface circuit pattern 3. Here, the periphery of the through-hole 1 is the vicinity of the through-hole 1, for example, within 1 mm, preferably within 0.3 mm, more preferably within 0.1 mm from the through-hole 1.
The interlayer connection portion 6 is formed by filling the through hole 1 with a conductive paste, thereby improving connection reliability against thermal shock in a process of mounting components and the like.

層間接続部6は、絶縁基板4の表面および裏面において、凸状に形成されている。また、層間接続部6は、表面回路パターン2および裏面回路パターン3の一部を被覆している。本実施形態では、層間接続部6は、この表面回路パターン2および裏面回路パターン3を被覆した部位も含むものとする。
すなわち、層間接続部6は、貫通穴1内に充填された穴内充填部5a、6aと、穴内充填部5a、6aの両端に形成され、貫通穴1の周辺まで広がる穴外平板部5b、6bとを有している。ここで貫通穴1は、穴内充填部5aのみ、または穴内充填部6aのみが充填されている場合を含む。
The interlayer connection portion 6 is formed in a convex shape on the front surface and the back surface of the insulating substrate 4. Further, the interlayer connection portion 6 covers a part of the front surface circuit pattern 2 and the back surface circuit pattern 3. In the present embodiment, the interlayer connection portion 6 includes a portion covering the front surface circuit pattern 2 and the back surface circuit pattern 3.
That is, the interlayer connection part 6 is formed at both ends of the in-hole filling parts 5a and 6a filled in the through hole 1 and the in-hole filling parts 5a and 6a. And have. Here, the through hole 1 includes a case where only the in-hole filling portion 5a or only the in-hole filling portion 6a is filled.

導電性ペーストとしては、例えば、フレーク状、鱗片状または樹皮状の銀粉や銅粉などのフィラーと、熱硬化性のバインダ樹脂と、を混合したものを用いることができる。
また、導電性ペーストとしては、できるだけ体積抵抗率が小さく、バインダ樹脂や溶剤成分の含有量が少ないものを用いることが好ましい。
導電性ペーストは、例えば、体積抵抗率が2×10‐5〜1.5×10‐4Ω・cm、バインダ樹脂含有量が3〜10質量%のものを用いることが好ましい。このような導電性ペーストであれば、層間接続部6の抵抗値がより小さくなり、かつ抵抗値のバラツキもより小さくなる。体積抵抗率は、より好ましくは7.5×10‐5Ω・cm程度であり、バインダ樹脂含有量は、より好ましくは6〜7質量%である。また、導電性ペーストは、例えば、溶剤含有量が0〜1質量%のものを用いることが好ましい。
As the conductive paste, for example, a mixture of a filler such as flaky, scaly, or bark-like silver powder or copper powder and a thermosetting binder resin can be used.
Further, as the conductive paste, it is preferable to use a paste having a volume resistivity as low as possible and a low content of binder resin or solvent component.
For example, it is preferable to use a conductive paste having a volume resistivity of 2 × 10 −5 to 1.5 × 10 −4 Ω · cm and a binder resin content of 3 to 10% by mass. With such a conductive paste, the resistance value of the interlayer connection portion 6 becomes smaller and the variation in resistance value becomes smaller. The volume resistivity is more preferably about 7.5 × 10 −5 Ω · cm, and the binder resin content is more preferably 6 to 7% by mass. Moreover, it is preferable to use a conductive paste having a solvent content of 0 to 1% by mass, for example.

また、導電性ペーストは、硬化時の熱収縮が小さいものが好ましい。具体的には、硬化時の質量減少率が1%以下であることが好ましい。このような導電性ペーストであれば、後述する層間接続部6の表面となる穴外平板部6bおよび裏面となる穴外平板部5bにおける平面度をより制御しやすくなる。ここでは、先に絶縁基板4の裏面側から導電性ペーストを充填するため、穴内充填部5aに充填された導電性ペーストが収縮したとしても、絶縁基板4の表面側から導電性ペーストを再度充填するため、絶縁基板4の表面における穴外平板部6bの凹みを小さくすることができ、穴外平板部6bを平坦にすることができる。   The conductive paste preferably has a small thermal shrinkage at the time of curing. Specifically, it is preferable that the mass reduction rate during curing is 1% or less. Such a conductive paste makes it easier to control the flatness in the out-of-hole flat plate portion 6b serving as the surface of the interlayer connection portion 6 described later and the out-of-hole flat plate portion 5b serving as the back surface. Here, since the conductive paste is filled from the back side of the insulating substrate 4 first, even if the conductive paste filled in the hole filling portion 5a contracts, the conductive paste is filled again from the front side of the insulating substrate 4 Therefore, the recess of the out-hole flat plate portion 6b on the surface of the insulating substrate 4 can be reduced, and the out-of-hole flat plate portion 6b can be flattened.

多層基板100は、表面回路パターン2の一部が絶縁基板4の貫通穴1の内壁に沿って延出した延出部20を有する。すなわち、多層基板100は、貫通穴1を形成する際に表面回路パターン2の一部を押し延ばすことで延出部20が形成される。この延出部20は、表面回路パターン2の貫通穴1側の端部が絶縁基板4の内層に向かって延出し、貫通穴1の内部において、絶縁基板4に密着するように形成されている。
本実施形態は、多層基板100が延出部20を有することで、導電性ペーストにより形成された穴内充填部5a、6aと表面回路パターン2との接触面積が通常の貫通穴よりも広くなる。そのため、層間接続部6の抵抗値が低くなり、かつ抵抗値が安定化する。
The multilayer substrate 100 has an extended portion 20 in which a part of the surface circuit pattern 2 extends along the inner wall of the through hole 1 of the insulating substrate 4. That is, in the multilayer substrate 100, the extending portion 20 is formed by pushing a part of the surface circuit pattern 2 when forming the through hole 1. The extended portion 20 is formed so that the end portion on the through hole 1 side of the surface circuit pattern 2 extends toward the inner layer of the insulating substrate 4 and is in close contact with the insulating substrate 4 inside the through hole 1. .
In the present embodiment, since the multilayer substrate 100 has the extended portion 20, the contact area between the in-hole filling portions 5a and 6a formed of the conductive paste and the surface circuit pattern 2 becomes wider than a normal through hole. For this reason, the resistance value of the interlayer connection 6 is lowered and the resistance value is stabilized.

延出部20の長さ、すなわち、貫通穴1の内壁に位置する表面回路パターン2の一部の延出した長さ(縦方向の長さ)は、5〜35μmが好ましい。延出部20の長さが5μm以上であれば、穴内充填部5a、6aと表面回路パターン2との接触面積がより広くなる。そのため、多層基板100は、層間接続部6の抵抗値がより低くしやすく、かつ抵抗値がより安定化しやすくなる。一方、延出部20の長さが35μm以下であれば、延出部20をより形成しやすくなる。   The length of the extended portion 20, that is, the length of the part of the surface circuit pattern 2 located on the inner wall of the through hole 1 (length in the vertical direction) is preferably 5 to 35 μm. If the length of the extension part 20 is 5 μm or more, the contact area between the hole filling parts 5a, 6a and the surface circuit pattern 2 becomes wider. Therefore, in the multilayer substrate 100, the resistance value of the interlayer connection portion 6 is easily lowered and the resistance value is more easily stabilized. On the other hand, if the length of the extension part 20 is 35 μm or less, the extension part 20 is more easily formed.

絶縁基板4の表面および裏面における層間接続部6の部位は、平坦に形成されている。すなわち、層間接続部6の表面および裏面における凸状の部位(穴外平板部5b、6b)の上面が平坦に形成されている。
ここで、平坦とは、穴外平板部6bの最薄部と最厚部の厚み差が20μm以下であるものとし、好ましくは10μm以下、より好ましくは5μm以下であるものとする。
The portions of the interlayer connection 6 on the front and back surfaces of the insulating substrate 4 are formed flat. That is, the upper surfaces of the convex portions (out-hole plate portions 5b, 6b) on the front surface and the back surface of the interlayer connection portion 6 are formed flat.
Here, “flat” means that the thickness difference between the thinnest part and the thickest part of the out-hole flat plate part 6b is 20 μm or less, preferably 10 μm or less, more preferably 5 μm or less.

層間接続部6の平坦な部位の厚み、すなわち、絶縁基板4の表面となる穴外平板部6bおよび裏面となる穴外平板部5bの厚みは、10〜30μmであることが好ましい。穴外平板部5b、6bの厚みが10μm以上であれば、層間接続部6を形成しやすくなる。一方、穴外平板部5b、6bの厚みが30μm以下であれば、多層基板100の厚みを薄くすることができる。なお、絶縁基板4の表面における穴外平板部6bの厚みとは、表面回路パターン2の上面から、絶縁基板4の表面における穴外平板部6bの上面までの厚みである。また、絶縁基板4の裏面における穴外平板部5bの厚みとは、裏面回路パターン3の上面から、絶縁基板4の裏面における穴外平板部5bの上面までの厚みである。
穴外平板部5b、6bの厚みは、貫通穴1に充填する際の導電性ペーストの量により制御することができる。また、穴外平板部5b、6bを研磨することで制御することができる。
It is preferable that the thickness of the flat part of the interlayer connection part 6, that is, the thickness of the out-of-hole flat plate part 6 b serving as the surface of the insulating substrate 4 and the out-of-hole flat plate part 5 b serving as the back surface is 10 to 30 μm. When the thickness of the out-hole flat plate portions 5b and 6b is 10 μm or more, the interlayer connection portion 6 is easily formed. On the other hand, if the thickness of the out-hole flat plate portions 5b and 6b is 30 μm or less, the thickness of the multilayer substrate 100 can be reduced. The thickness of the out-hole flat plate portion 6b on the surface of the insulating substrate 4 is the thickness from the upper surface of the surface circuit pattern 2 to the upper surface of the out-of-hole flat plate portion 6b on the surface of the insulating substrate 4. Further, the thickness of the out-of-hole flat plate portion 5 b on the back surface of the insulating substrate 4 is the thickness from the upper surface of the back surface circuit pattern 3 to the upper surface of the out-of-hole flat plate portion 5 b on the back surface of the insulating substrate 4.
The thickness of the out-hole flat plate portions 5b and 6b can be controlled by the amount of the conductive paste when filling the through-hole 1. Moreover, it can control by grind | polishing the flat-plate part 5b, 6b outside a hole.

以上説明した通り、本実施形態では、多層基板100は、層間接続部6の表面となる穴外平板部6bおよび裏面となる穴外平板部5bが平坦に形成されている。
多層基板100の層間接続部6は、部品を実装する工程での熱処理や半田付け作業時の熱衝撃に耐える接続信頼性が必要である。従来の多層基板では、めっきによるスルーホール接続が多く用いられている。しかしながら、このような多層基板では、基板厚方向への基板の熱膨張率とめっきの熱膨張率との差により生じる応力で、スルーホールのコーナー部にクラックが生じ接続信頼性を低下させる。そのため、例えば、背景技術で説明した特許文献1、特許文献2に記載のように、めっきによるスルーホール接続に対して、貫通穴に導電性ペーストを充填する接続方法も提案されている。
As described above, in the present embodiment, in the multilayer substrate 100, the out-of-hole flat plate portion 6b serving as the surface of the interlayer connection portion 6 and the out-of-hole flat plate portion 5b serving as the back surface are formed flat.
The interlayer connection portion 6 of the multilayer substrate 100 needs to have a connection reliability that can withstand heat shock during a component mounting process and thermal shock during soldering. In conventional multilayer substrates, through-hole connection by plating is often used. However, in such a multilayer substrate, a crack is generated in the corner portion of the through hole due to the stress generated by the difference between the thermal expansion coefficient of the substrate in the thickness direction of the substrate and the thermal expansion coefficient of the plating, thereby reducing connection reliability. Therefore, for example, as described in Patent Document 1 and Patent Document 2 described in the background art, a connection method for filling a through-hole with a conductive paste is proposed for through-hole connection by plating.

上記特許文献1、特許文献2では、貫通穴に埋め込まれた導電性ペーストにより接続部を形成しているが、貫通穴への導電性ペーストの充填が不十分であり、また、導電性ペーストを硬化する際に、バインダ樹脂の熱収縮が生じてしまう。そのため、層間接続部の表面および裏面に平坦性がなく、層間接続部上に部品を実装することが困難である。そのため従来は、層間接続部と部品実装部を分けて配置していたのが実情である。しかしながら、これにより基板面積の増加が生じてしまう問題点がある。   In Patent Document 1 and Patent Document 2, the connection portion is formed by the conductive paste embedded in the through hole. However, the conductive paste is insufficiently filled in the through hole. When cured, the binder resin undergoes thermal shrinkage. For this reason, the front and back surfaces of the interlayer connection portion are not flat, and it is difficult to mount components on the interlayer connection portion. Therefore, conventionally, the interlayer connection part and the component mounting part are arranged separately. However, there is a problem that the substrate area increases due to this.

また上記特許文献1、特許文献2のような層間接続部では、層間接続部上に設けられる絶縁層にも制約が生じてしまう。具体的には、例えば、印刷可能な絶縁樹脂をスクリーン印刷法などで形成する場合、層間接続部の表面および裏面に平坦性がないため、層間接続部の凹部分でボイド、ピンホールなどが生じる。そのため、均一な絶縁層形成ができず、接続部近傍の電気絶縁性が低下する懸念がある。そのため、多層基板の表面および裏面の凹凸に追従できる厚みの接着剤を有するカバーレイフィルムなどを貼り付けていたのが実情である。しかしながら、接着剤を有するカバーレイフィルムなどの貼り付けでは、接着材の厚み相当分、基板の総厚みが厚くなる問題点がある。   Further, in the interlayer connection portions as in Patent Document 1 and Patent Document 2, the insulating layer provided on the interlayer connection portion is also restricted. Specifically, for example, when a printable insulating resin is formed by a screen printing method or the like, voids and pinholes are generated in the concave portions of the interlayer connection portion because the front and back surfaces of the interlayer connection portion are not flat. . For this reason, a uniform insulating layer cannot be formed, and there is a concern that the electrical insulation in the vicinity of the connecting portion is lowered. Therefore, the actual situation is that a coverlay film or the like having an adhesive having a thickness that can follow the unevenness of the front and back surfaces of the multilayer substrate is attached. However, when a coverlay film or the like having an adhesive is attached, there is a problem that the total thickness of the substrate is increased by an amount corresponding to the thickness of the adhesive.

また、特にLED実装用の基板においては、基板表面の絶縁層は、白色であることや、反射率、耐光性などを考慮する必要がある。しかしながら、一般的な接着剤層を有するポリイミド樹脂からなるカバーレイフィルムでは、LEDの連続点灯試験においてポリイミド樹脂が光劣化してしまう不具合がある。そのため、顧客の要求特性を満足することができないのが実情である。   In particular, in an LED mounting substrate, the insulating layer on the substrate surface must be white, reflectivity, light resistance, and the like. However, in a coverlay film made of a polyimide resin having a general adhesive layer, there is a problem that the polyimide resin undergoes photodegradation in an LED continuous lighting test. Therefore, the actual situation is that the required characteristics of customers cannot be satisfied.

ここで、顧客からの回路基板への要求事項は年々多くなってきており、特に多くの電子機器類が、小型、薄型化、および軽量化するために、部品を含めた基板面積の小型化と高密度化、絶縁層の薄型化といった要求が高まっている。しかしながら、従来の接続構造をもつ多層基板では、これらの要求に応えることができなくなっている。   Here, the requirements for circuit boards from customers are increasing year by year, and in particular, many electronic devices are becoming smaller, thinner, and lighter in order to reduce the board area including components. There are increasing demands for higher density and thinner insulating layers. However, a multilayer board having a conventional connection structure cannot meet these requirements.

本実施形態では、多層基板100は、層間接続部6の表面となる穴外平板部6bおよび裏面となる穴外平板部5bが平坦であることから、層間接続部6上へのレジスト形成が容易で絶縁性が高く、また、層間接続部6上への部品実装が容易である。   In the present embodiment, in the multilayer substrate 100, since the out-of-hole flat plate portion 6b serving as the front surface of the interlayer connection portion 6 and the out-of-hole flat plate portion 5b serving as the back surface are flat, it is easy to form a resist on the inter-layer connection portion 6. Therefore, the insulating property is high, and the component mounting on the interlayer connection portion 6 is easy.

[多層基板の製造方法]
次に、本実施形態に係る多層基板の製造方法の一例について説明する。
図2Aは、実施形態に係る多層基板の製造方法における、回路パターンを形成する前の状態を示す断面図である。図2Bは、実施形態に係る多層基板の製造方法における、回路パターンを形成する工程を示す断面図である。図2Cは、実施形態に係る多層基板の製造方法における、貫通穴を形成する工程を示す断面図である。図3Aは、実施形態に係る多層基板の製造方法における、層間接続部を形成する工程を示す断面図であり、絶縁基板の裏面から導電性ペーストを充填する工程を示す断面図である。図3Bは、実施形態に係る多層基板の製造方法における、層間接続部を形成する工程を示す断面図であり、絶縁基板の表面から導電性ペーストを充填する工程を示す断面図である。図3Cは、実施形態に係る多層基板の製造方法における、層間接続部の部位を研磨する工程を示す断面図である。
なお、各工程においてスキージやマスクに同一番号を付しているが、物理的同一物を用いている訳ではなく、機能や性状などが共通するだけであり、異なる大きさ、材質などを使用することができる。
[Multilayer substrate manufacturing method]
Next, an example of a method for manufacturing a multilayer substrate according to the present embodiment will be described.
FIG. 2A is a cross-sectional view illustrating a state before the circuit pattern is formed in the method for manufacturing a multilayer substrate according to the embodiment. FIG. 2B is a cross-sectional view illustrating a process of forming a circuit pattern in the method for manufacturing a multilayer substrate according to the embodiment. FIG. 2C is a cross-sectional view illustrating a process of forming a through hole in the method for manufacturing a multilayer substrate according to the embodiment. FIG. 3A is a cross-sectional view showing a step of forming an interlayer connection part in the method for manufacturing a multilayer substrate according to the embodiment, and is a cross-sectional view showing a step of filling a conductive paste from the back surface of the insulating substrate. FIG. 3B is a cross-sectional view showing a step of forming an interlayer connection part in the method for manufacturing a multilayer substrate according to the embodiment, and is a cross-sectional view showing a step of filling a conductive paste from the surface of the insulating substrate. FIG. 3C is a cross-sectional view showing a step of polishing a portion of the interlayer connection portion in the method for manufacturing a multilayer substrate according to the embodiment.
The same number is assigned to the squeegee and the mask in each process, but the physical same thing is not used, only the function and properties are common, and different sizes and materials are used. be able to.

本実施形態の多層基板の製造方法は、回路パターンを形成する工程と、貫通穴を形成する工程と、層間接続部を形成する工程と、層間接続部の部位を研磨する工程と、を含み、この順に行う。なお、各部材の材質や配置などについては、前記した多層基板100の説明で述べた通りであるので、ここでは適宜、説明を省略する。   The method of manufacturing a multilayer substrate according to the present embodiment includes a step of forming a circuit pattern, a step of forming a through hole, a step of forming an interlayer connection, and a step of polishing a portion of the interlayer connection. Perform in this order. Note that the material and arrangement of each member are the same as described in the description of the multilayer substrate 100 described above, and thus the description thereof will be omitted as appropriate.

(回路パターンを形成する工程)
回路パターンを形成する工程は、絶縁基板4の表面および裏面に表面回路パターン2および裏面回路パターン3を形成する工程である。
(Process for forming a circuit pattern)
The step of forming the circuit pattern is a step of forming the front surface circuit pattern 2 and the back surface circuit pattern 3 on the front and back surfaces of the insulating substrate 4.

この工程では、例えば、まず、シート状の1枚もしくは複数枚のガラスクロスにエポキシ樹脂を含浸させ、その表面に表面銅箔2a、裏面に裏面銅箔3aを接合してエポキシ樹脂を硬化させて形成した市販の両面銅張積層板を用意する。次に、表面銅箔2aおよび裏面銅箔3aにエッチングを施して表面回路パターン2および裏面回路パターン3を形成する。
なお、市販の両面銅張積層板を用いずに、絶縁基板4の表面に表面銅箔2aおよび裏面に裏面銅箔3aを接合してもよい。また、あらかじめ、表面回路パターン2および裏面回路パターン3が形成された両面銅張積層板を購入してもよい。
In this step, for example, first, one or more sheet-like glass cloths are impregnated with an epoxy resin, the front surface copper foil 2a is bonded to the front surface, and the back surface copper foil 3a is bonded to the back surface to cure the epoxy resin. A commercially available double-sided copper-clad laminate is prepared. Next, the front surface copper foil 2 a and the back surface copper foil 3 a are etched to form the front surface circuit pattern 2 and the back surface circuit pattern 3.
In addition, you may join the surface copper foil 2a to the surface of the insulated substrate 4, and the back surface copper foil 3a to the back surface, without using a commercially available double-sided copper clad laminated board. Moreover, you may purchase the double-sided copper clad laminated board in which the surface circuit pattern 2 and the back surface circuit pattern 3 were formed previously.

(貫通穴を形成する工程)
貫通穴を形成する工程は、絶縁基板4の表面回路パターン2の一部が絶縁基板4の貫通穴1の内壁に沿って延出するようにパンチング加工により貫通穴1を形成する工程である。
(Process for forming through holes)
The step of forming the through hole is a step of forming the through hole 1 by punching so that a part of the surface circuit pattern 2 of the insulating substrate 4 extends along the inner wall of the through hole 1 of the insulating substrate 4.

この工程では、絶縁基板4における表面回路パターン2および裏面回路パターン3が存在する部分において、絶縁基板4の表面側からパンチングピン(パンチ)14を差し込んでパンチング加工して、例えば、貫通穴径φ0.2〜0.3mmの貫通穴1を形成する。ここで、貫通穴1を形成する際には、表面回路パターン2の一部が絶縁基板4の貫通穴1の内壁に沿って延出している構造となる。すなわち、表面回路パターン2の端部が絶縁基板4の内層に向かって強制的に押し込まれることで延びて、貫通穴1の内部に延出部20が形成される。
パンチング加工においては、延出部20の長さが絶縁基板4の厚みに対して0.05〜0.5倍、好ましくは0.1〜0.4倍となるように調整することが好ましい。またパンチング加工においては、延出部20の長さが5〜35μmとなるように調整することが好ましい。
In this step, punching processing is performed by inserting a punching pin (punch) 14 from the front surface side of the insulating substrate 4 at a portion of the insulating substrate 4 where the front surface circuit pattern 2 and the rear surface circuit pattern 3 are present. The through hole 1 having a diameter of 2 to 0.3 mm is formed. Here, when the through hole 1 is formed, a part of the surface circuit pattern 2 extends along the inner wall of the through hole 1 of the insulating substrate 4. That is, the end portion of the surface circuit pattern 2 extends by being forcibly pushed toward the inner layer of the insulating substrate 4, and the extension portion 20 is formed inside the through hole 1.
In the punching process, it is preferable to adjust the length of the extended portion 20 to be 0.05 to 0.5 times, preferably 0.1 to 0.4 times the thickness of the insulating substrate 4. Moreover, in punching, it is preferable to adjust so that the length of the extension part 20 may be 5-35 micrometers.

延出部20の長さ調整は、主に、パンチングピンを構成する、パンチの径、ダイ(パンチ受け側)の径を調整することにより行う。表面回路パターン2および裏面回路パターン3の厚み、材質にもよるが、例えばパンチ径φ0.2〜0.3mmに対しては、ダイの径φ0.21〜0.32mm程度に設定することが好ましく、パンチとダイの間に0.005〜0.01mm程度のギャップを設定する。   The length of the extending portion 20 is mainly adjusted by adjusting the diameter of the punch and the diameter of the die (punch receiving side) that constitute the punching pin. Although depending on the thickness and material of the front surface circuit pattern 2 and the back surface circuit pattern 3, for example, for a punch diameter of 0.2 to 0.3 mm, it is preferable to set the die diameter to about 0.21 to 0.32 mm. A gap of about 0.005 to 0.01 mm is set between the punch and the die.

(層間接続部を形成する工程)
層間接続部を形成する工程は、貫通穴1の内部および周囲に、絶縁基板4の表面および裏面の両面から、印刷により導電性ペースト6cを充填して層間接続部6を形成する工程である。ここでは絶縁基板4の裏面、表面の順に導電性ペースト6cを充填するが、絶縁基板4の表面、裏面の順に導電性ペースト6cを充填してもよい。
(Process for forming interlayer connection)
The step of forming the interlayer connection portion is a step of forming the interlayer connection portion 6 by filling the inside and the periphery of the through hole 1 with the conductive paste 6c by printing from both the front surface and the back surface of the insulating substrate 4. Here, the conductive paste 6c is filled in the order of the back surface and the front surface of the insulating substrate 4, but the conductive paste 6c may be filled in the order of the surface and the back surface of the insulating substrate 4.

この工程では、まず、導電性ペースト6cを、マスク11を介して、絶縁基板4の裏面からスクリーン印刷法で貫通穴1に充填する。スクリーン印刷の条件は、例えば、クリアランス0〜2mmとし、20〜300μm厚、開口穴径φ0.2〜0.5mmのメタルマスク11、または、150〜400メッシュ、乳剤厚10〜20μmのスクリーンマスク11と、硬度70〜80のウレタンゴムのスキージ40とを用い、スキージ実効角度15〜30度、印圧0.2〜0.4MPa、スキージ速度10〜50mm/sec、スキージ往復印刷とすることができる。絶縁基板4の表面および裏面のうち、先に印刷する面の印刷を往復印刷とすることで、貫通穴1に導電性ペースト6cをより充填しやすくなる。なお、絶縁基板4の厚みが薄い場合や貫通穴1が大きい場合は、スキージ片道印刷でも導電性ペースト6cが貫通穴1に充填されるので、スキージ片道印刷としても構わない。   In this step, first, the conductive paste 6c is filled into the through hole 1 from the back surface of the insulating substrate 4 through the mask 11 by screen printing. The screen printing conditions are, for example, a clearance of 0 to 2 mm, a metal mask 11 having a thickness of 20 to 300 μm and an opening hole diameter of φ 0.2 to 0.5 mm, or a screen mask 11 having a thickness of 150 to 400 mesh and an emulsion thickness of 10 to 20 μm. And a urethane rubber squeegee 40 having a hardness of 70 to 80, an effective squeegee angle of 15 to 30 degrees, a printing pressure of 0.2 to 0.4 MPa, a squeegee speed of 10 to 50 mm / sec, and squeegee reciprocal printing. . Of the front and back surfaces of the insulating substrate 4, the surface to be printed first is the reciprocating printing, whereby the through-hole 1 can be more easily filled with the conductive paste 6 c. In addition, when the thickness of the insulating substrate 4 is thin or the through hole 1 is large, the conductive paste 6c is filled in the through hole 1 even in the squeegee one-way printing, and therefore the squeegee one-way printing may be used.

その後、導電性ペースト6cを、例えば80〜120℃の一定温度で15〜30分加熱させ仮硬化させる。この導電性ペースト6cの仮硬化は、導電性ペースト6cの表面が乾燥する程度の状態であることが好ましく、仮硬化後の導電性ペースト6cは絶縁体の状態であることが好ましい。   Thereafter, the conductive paste 6c is heated and temporarily cured at a constant temperature of, for example, 80 to 120 ° C. for 15 to 30 minutes. The temporary curing of the conductive paste 6c is preferably in a state where the surface of the conductive paste 6c is dried, and the conductive paste 6c after the temporary curing is preferably in an insulator state.

仮硬化後の導電性ペースト6cが絶縁体の状態であることが好ましい理由を以下に説明する。
次工程の表面からスクリーン印刷で、裏面から印刷形成した導電性ペースト6cと表面から形成した導電性ペースト6cが接続する。その際、裏面から印刷形成した導電性ペースト6cの硬化が進み過ぎ「導電体」の状態になっていると、裏面から印刷形成した導電性ペースト6cと表面から形成した導電性ペースト6cとの接続界面の導通状態が悪くなる場合がある。導通状態が悪くなると、接続抵抗値が高くなる、熱衝撃に対する接続信頼性が低下する、などの品質問題が生じる。そのため、仮硬化後の導電性ペースト6cは絶縁体の状態であることが好ましい。
The reason why the pre-cured conductive paste 6c is preferably in an insulating state will be described below.
The conductive paste 6c printed from the back surface and the conductive paste 6c formed from the front surface are connected by screen printing from the front surface of the next step. At this time, if the conductive paste 6c printed and formed from the back surface is excessively hardened, the conductive paste 6c printed from the back surface and the conductive paste 6c formed from the front surface are connected. There is a case where the conductive state of the interface is deteriorated. When the conduction state is deteriorated, quality problems such as an increase in connection resistance value and a decrease in connection reliability against thermal shock occur. Therefore, it is preferable that the electrically conductive paste 6c after temporary curing is in an insulator state.

仮硬化後の導電性ペースト6cを絶縁体の状態とするには、以下の方法を用いることができる。
まず、あらかじめ、導電性ペースト6cをライン印刷した試料を用いて、熱処理試験を行う。そして、加熱温度や加熱時間に対して、どのくらいの条件で、(1)導電性ペースト6cがどのくらい硬くなるか、(2)ラインの抵抗値がどのくらいの値になるか、を確認して仮硬化条件を導出する。これにより、絶縁体の状態となる仮硬化条件を決定する。なお、全く仮硬化せずに次工程に進むことも可能である。しかしながら、ウェット状態の導電性ペースト6cが基板表面に露出した状態で、次工程で印刷テーブルや吸着紙に吸着させることは、導電性ペースト6cが基板からはぎ取られるなどの弊害を引き起こす。そのため、裏面から印刷形成した導電性ペースト6cは仮硬化させることが好ましい。
The following method can be used to bring the conductive paste 6c after temporary curing into an insulating state.
First, a heat treatment test is performed using a sample in which the conductive paste 6c is line printed in advance. Then, under what conditions with respect to the heating temperature and heating time, (1) how hard the conductive paste 6c is, and (2) how much the resistance value of the line is, is temporarily cured Derive conditions. Thereby, the temporary hardening conditions used as the state of an insulator are determined. It is also possible to proceed to the next step without pre-curing at all. However, when the conductive paste 6c in the wet state is exposed on the substrate surface, it is adsorbed on the printing table or the suction paper in the next step, which causes problems such as the conductive paste 6c being peeled off from the substrate. Therefore, it is preferable that the conductive paste 6c printed from the back surface is temporarily cured.

このようにして、まず、穴内充填部5aと、絶縁基板4の裏面の穴外平板部5bとを有する接合体部5が形成される。なお、図3Aでは、便宜上、導電性ペースト6cを仮硬化した後の状態として接合体部5を図示している。   In this way, first, the joined body portion 5 having the in-hole filling portion 5a and the out-hole flat plate portion 5b on the back surface of the insulating substrate 4 is formed. In FIG. 3A, for convenience, the bonded body portion 5 is illustrated as a state after the conductive paste 6c is temporarily cured.

続いて、マスク11を介して、絶縁基板4の表面からスクリーン印刷法で導電性ペースト6cを印刷形成する。導電性ペースト6cは、絶縁基板4の裏面から印刷充填した導電性ペースト6cと同じものを使用することができる。スクリーン印刷の条件は、例えば、クリアランス0〜2mmとし、20〜50μm厚、開口穴径φ0.2〜0.5mmのメタルマスク11、または、150〜400メッシュ、乳剤厚10〜20μmのスクリーンマスク11と、硬度80のウレタンゴムのスキージ40とを用い、スキージ実効角度15〜70度、印圧0.1〜0.4MPa、スキージ速度10〜100mm/secとし、スキージ片道印刷とすることができる。   Subsequently, the conductive paste 6c is printed and formed from the surface of the insulating substrate 4 through the mask 11 by a screen printing method. As the conductive paste 6c, the same paste as the conductive paste 6c printed and filled from the back surface of the insulating substrate 4 can be used. The screen printing conditions are, for example, a clearance of 0 to 2 mm, a metal mask 11 having a thickness of 20 to 50 μm and an opening hole diameter of 0.2 to 0.5 mm, or a screen mask 11 having a thickness of 150 to 400 mesh and an emulsion thickness of 10 to 20 μm. And a squeegee 40 of urethane rubber having a hardness of 80, and an squeegee effective angle of 15 to 70 degrees, a printing pressure of 0.1 to 0.4 MPa, a squeegee speed of 10 to 100 mm / sec, and squeegee one-way printing.

その後、導電性ペースト6cを180〜200℃の一定温度で45〜90分加熱させ硬化させる。これにより、表面回路パターン2と裏面回路パターン3とを電気的に接続する層間接続部6が形成される。なお、図3Bでは、便宜上、導電性ペースト6cを硬化した後の状態として層間接続部6を図示している。
なお、絶縁基板4の表面、裏面の順に導電性ペースト6cを充填する場合は、前記した裏面からのスクリーン印刷法の条件と、表面からのスクリーン印刷法の条件とを入れかえればよい。
Thereafter, the conductive paste 6c is heated and cured at a constant temperature of 180 to 200 ° C. for 45 to 90 minutes. Thereby, the interlayer connection part 6 which electrically connects the front surface circuit pattern 2 and the back surface circuit pattern 3 is formed. In FIG. 3B, for convenience, the interlayer connection portion 6 is illustrated as a state after the conductive paste 6c is cured.
When the conductive paste 6c is filled in the order of the front surface and the back surface of the insulating substrate 4, the above-described screen printing method conditions from the back surface and the screen printing method conditions from the front surface may be interchanged.

本実施形態では、導電性ペースト6cを充填する工程において、貫通穴1の内部に、絶縁基板4の表面および裏面の両面から、印刷により導電性ペースト6cを充填することで、絶縁基板4の表面および裏面における層間接続部6の穴外平板部5b、6bの部位を平坦にすることができる。   In the present embodiment, in the step of filling the conductive paste 6c, the conductive paste 6c is filled into the through hole 1 from both the front and back surfaces of the insulating substrate 4 by printing, so that the surface of the insulating substrate 4 is filled. And the site | part of the hole outside flat plate parts 5b and 6b of the interlayer connection part 6 in a back surface can be made flat.

(層間接続部の部位を研磨する工程)
層間接続部の部位を研磨する工程は、絶縁基板4の表面および裏面における層間接続部6の部位を平坦に研磨する工程である。すなわち、この工程は、層間接続部6の表面および裏面における穴外平板部5b、6bの上面がより平坦になるように、穴外平板部5b、6bの上面を研磨する工程である。
(Process of polishing the part of the interlayer connection)
The step of polishing the portion of the interlayer connection portion is a step of flatly polishing the portion of the interlayer connection portion 6 on the front and back surfaces of the insulating substrate 4. That is, this step is a step of polishing the upper surfaces of the out-of-hole flat plate portions 5b and 6b so that the upper surfaces of the out-of-hole flat plate portions 5b and 6b on the front surface and the back surface of the interlayer connection portion 6 become flatter.

実装部品10の電極形状および厚みと表面レジスト7の厚みとの関係などから、必要に応じて、表面レジスト7を印刷形成する前に層間接続部6の研磨処理を実施してもよい。その場合は、セラミックバフ30での物理研磨が好ましい。層間接続部6の研磨処理を行うことで、層間接続部6の穴外平板部5b、6bの部位をさらに平坦にすることができる。なお、層間接続部の部位を研磨する工程は必須の工程として行わなくてもよい。   From the relationship between the electrode shape and thickness of the mounting component 10 and the thickness of the surface resist 7, the interlayer connection portion 6 may be subjected to a polishing process before the surface resist 7 is printed and formed as necessary. In that case, physical polishing with the ceramic buff 30 is preferable. By performing the polishing process of the interlayer connection portion 6, the portions of the out-hole plate portions 5 b and 6 b of the interlayer connection portion 6 can be further flattened. In addition, the process of grind | polishing the site | part of an interlayer connection part does not need to be performed as an essential process.

[部品実装基板]
次に、本実施形態に係る部品実装基板について説明する。
図4は、実施形態に係る部品実装基板の構成を模式的に示す断面図である。
部品実装基板101は、多層基板100と、多層基板100の表面における一部の領域に設けられた表面レジスト7と、多層基板100の裏面に設けられた裏面レジスト8と、多層基板100の表面の層間接続部6上に、半田ペーストである接着層9を介して設けられた実装部品10と、を備える。
[Component mounting board]
Next, the component mounting board according to the present embodiment will be described.
FIG. 4 is a cross-sectional view schematically showing the configuration of the component mounting board according to the embodiment.
The component mounting substrate 101 includes a multilayer substrate 100, a surface resist 7 provided in a partial region on the surface of the multilayer substrate 100, a back surface resist 8 provided on the back surface of the multilayer substrate 100, and the surface of the multilayer substrate 100. A mounting component 10 is provided on the interlayer connection portion 6 via an adhesive layer 9 that is a solder paste.

表面レジスト7は、実装部品10の周辺に形成されている。すなわち、表面レジスト7は、層間接続部6とその近傍を除く表面回路パターン2上に設けられている。裏面レジスト8は、裏面回路パターン3と、層間接続部6を覆うように形成されている。   The surface resist 7 is formed around the mounting component 10. That is, the surface resist 7 is provided on the surface circuit pattern 2 excluding the interlayer connection portion 6 and the vicinity thereof. The back resist 8 is formed so as to cover the back circuit pattern 3 and the interlayer connection 6.

表面レジスト7および裏面レジスト8としては、例えば、エポキシなどの共重合樹脂に溶剤や消泡剤などを混合した一般的なものや、酸化チタンなどのフィラーを添加した白色化したものを用いることができる。なお、表面レジスト7および裏面レジスト8は絶縁層となる。表面レジスト7および裏面レジスト8の厚みは、例えば、10〜30μmである。表面レジスト7の厚みは穴外平板部6bの厚みと同等もしくは厚い方が好ましい。穴外平板部6bの厚みを表面レジスト7の厚みよりも薄くすることで接着層9の高さを抑えることができ、実装部品10の高さを低くすることができるからである。穴外平板部6bの厚みは表面レジスト7の厚みに比べて、例えば0.5〜0.9倍程度の厚みが好ましく、0.6〜0.8倍程度の厚みがより好ましい。穴外平板部6bの厚みを0.5倍以上とすることで層間接続部6の厚みを抑えることができ、0.9倍以下とすることで電気伝導性を高いまま維持することができる。表面レジスト7と裏面レジスト8との厚みは同一でも良いが異なっていてもよい。   As the front surface resist 7 and the back surface resist 8, for example, a general one obtained by mixing a copolymer resin such as epoxy with a solvent or an antifoaming agent, or a whitened one obtained by adding a filler such as titanium oxide is used. it can. The front surface resist 7 and the back surface resist 8 become insulating layers. The thicknesses of the front surface resist 7 and the back surface resist 8 are, for example, 10 to 30 μm. The thickness of the surface resist 7 is preferably equal to or thicker than the thickness of the out-hole flat plate portion 6b. This is because the height of the adhesive layer 9 can be suppressed and the height of the mounting component 10 can be reduced by making the thickness of the out-hole flat plate portion 6 b thinner than the thickness of the surface resist 7. The thickness of the out-hole flat plate portion 6b is, for example, preferably about 0.5 to 0.9 times, and more preferably about 0.6 to 0.8 times the thickness of the surface resist 7. By setting the thickness of the out-hole flat plate portion 6b to 0.5 times or more, the thickness of the interlayer connection portion 6 can be suppressed, and by setting it to 0.9 times or less, the electrical conductivity can be kept high. The thicknesses of the front surface resist 7 and the back surface resist 8 may be the same or different.

接着層9の材料としては、例えば、Sn−Ag−Cu、Au、Ag、Cu、Sn、Biなどやこれらの合金を用いることができる。実装部品10としては、例えば、LED、チップ抵抗器、コンデンサなどが挙げられる。   As a material of the adhesive layer 9, for example, Sn—Ag—Cu, Au, Ag, Cu, Sn, Bi, or an alloy thereof can be used. Examples of the mounting component 10 include an LED, a chip resistor, and a capacitor.

[部品実装基板の製造方法]
次に、本実施形態に係る部品実装基板の製造方法について説明する。
図5Aは、実施形態に係る部品実装基板の製造方法における、レジストを形成する前の多層基板を示す断面図である。図5Bは、実施形態に係る部品実装基板の製造方法における、レジストを形成する工程を示す断面図であり、多層基板の表面にレジストを形成する工程を示す断面図である。図5Cは、実施形態に係る部品実装基板の製造方法における、レジストを形成する工程を示す断面図であり、多層基板の裏面にレジストを形成する工程を示す断面図である。図6Aは、実施形態に係る部品実装基板の製造方法における、部品を実装する工程を示す断面図であり、接着層を形成する工程を示す断面図である。図6Bは、実施形態に係る部品実装基板の製造方法における、部品を実装する工程を示す断面図であり、部品を実装した後の状態を示す断面図である。硬化前の表面レジストは7c、硬化前の裏面レジストは8cとする。
[Manufacturing method of component mounting board]
Next, a method for manufacturing the component mounting board according to the present embodiment will be described.
FIG. 5A is a cross-sectional view illustrating the multilayer substrate before the resist is formed in the method for manufacturing the component mounting substrate according to the embodiment. FIG. 5B is a cross-sectional view showing a step of forming a resist in the method for manufacturing a component mounting board according to the embodiment, and is a cross-sectional view showing a step of forming a resist on the surface of the multilayer board. FIG. 5C is a cross-sectional view showing a step of forming a resist in the method for manufacturing a component mounting board according to the embodiment, and is a cross-sectional view showing a step of forming a resist on the back surface of the multilayer board. FIG. 6A is a cross-sectional view illustrating a process of mounting a component in the method for manufacturing a component mounting board according to the embodiment, and is a cross-sectional view illustrating a process of forming an adhesive layer. FIG. 6B is a cross-sectional view illustrating a process for mounting a component in the method for manufacturing a component mounting board according to the embodiment, and is a cross-sectional view illustrating a state after the component is mounted. The front resist before curing is 7c, and the back resist before curing is 8c.

本実施形態の部品実装基板の製造方法は、一例として、前記した多層基板にレジストを形成する工程と、部品を実装する工程と、を含み、この順に行う。なお、各部材の材質や配置などについては、前記した部品実装基板の説明で述べた通りであるので、ここでは適宜、説明を省略する。   The method for manufacturing a component mounting board according to the present embodiment includes, as an example, a step of forming a resist on the multilayer substrate described above and a step of mounting components, which are performed in this order. Note that the material and arrangement of each member are as described in the description of the component mounting board, and therefore the description thereof will be omitted as appropriate.

(レジストを形成する工程)
レジストを形成する工程は、多層基板100の表面および裏面に表面レジスト7および裏面レジスト8を形成する工程である。ここでは多層基板100の表面、裏面の順に表面レジスト7、裏面レジスト8を形成するが、多層基板100の裏面、表面の順に裏面レジスト8、表面レジスト7を形成してもよい。
(Process for forming resist)
The step of forming the resist is a step of forming the front surface resist 7 and the back surface resist 8 on the front surface and the back surface of the multilayer substrate 100. Here, the front surface resist 7 and the back surface resist 8 are formed in the order of the front surface and the back surface of the multilayer substrate 100, but the back surface resist 8 and the front surface resist 7 may be formed in the order of the back surface and the front surface of the multilayer substrate 100.

この工程では、まず、多層基板100の表面回路パターン2上に、所望の塗布パターンを形成したスクリーンマスク12、表面レジスト7cを用いて、スクリーン印刷法で表面レジスト7を形成する。   In this step, first, the surface resist 7 is formed on the surface circuit pattern 2 of the multilayer substrate 100 by a screen printing method using the screen mask 12 and the surface resist 7c on which a desired coating pattern is formed.

スクリーン印刷の条件は、例えば、クリアランス0.5〜5.0mmとし、100〜400メッシュ、乳剤厚10〜20μmのスクリーンマスク12と、硬度60〜80のウレタンゴムのスキージ40とを用い、スキージ実効角度60〜80度、印圧0.2〜0.4MPa、スキージ速度20〜100mm/sec、スキージ片道印刷とすることができる。その後、表面レジスト7を50〜250℃で、5〜60分加熱させ硬化させる。   Screen printing conditions are, for example, a clearance of 0.5 to 5.0 mm, a screen mask 12 of 100 to 400 mesh, an emulsion thickness of 10 to 20 μm, and a urethane rubber squeegee 40 of hardness 60 to 80, and a squeegee effective. An angle of 60 to 80 degrees, a printing pressure of 0.2 to 0.4 MPa, a squeegee speed of 20 to 100 mm / sec, and squeegee one-way printing can be used. Thereafter, the surface resist 7 is heated and cured at 50 to 250 ° C. for 5 to 60 minutes.

続いて、裏面回路パターン3上に、スクリーンマスク12、裏面レジスト8cを用いて、スクリーン印刷法で裏面レジスト8を形成する。裏面レジスト8は、絶縁基板4の表面から印刷形成したレジストと同じものを使用することができ、スクリーン印刷の条件は、表面レジスト7の印刷形成時と同じ条件とすることができる。その後、裏面レジスト8を50〜250℃で、5〜60分加熱させ硬化させる。これにより、表面回路パターン2と裏面回路パターン3の所望の範囲に絶縁層が形成される。   Subsequently, the back resist 8 is formed on the back circuit pattern 3 by a screen printing method using the screen mask 12 and the back resist 8c. The back resist 8 can be the same as the resist printed and formed from the surface of the insulating substrate 4, and the screen printing conditions can be the same as those during the printing of the front resist 7. Thereafter, the back resist 8 is heated and cured at 50 to 250 ° C. for 5 to 60 minutes. Thereby, an insulating layer is formed in a desired range of the front surface circuit pattern 2 and the back surface circuit pattern 3.

(部品を実装する工程)
部品を実装する工程は、表面レジスト7および裏面レジスト8を形成した多層基板100に部品を実装する工程である。
(Process for mounting components)
The step of mounting the component is a step of mounting the component on the multilayer substrate 100 on which the front surface resist 7 and the back surface resist 8 are formed.

この工程では、まず、部品の実装部分に開口部を設けたメタルマスク13、スキージ40を用いて半田ペースト9cを印刷し、接着層9を形成する。次に、接着層9上に実装部品10を載せ、接着層9を硬化させて実装部品10を多層基板100と接続し固定させる。   In this step, first, the solder paste 9c is printed using the metal mask 13 and the squeegee 40 each having an opening in a component mounting portion, and the adhesive layer 9 is formed. Next, the mounting component 10 is placed on the adhesive layer 9, the adhesive layer 9 is cured, and the mounting component 10 is connected and fixed to the multilayer substrate 100.

この例では、半田ペースト9cを層間接続部6上に直接塗布したが、部品の接合強度の観点から、あらかじめ部品の実装部分にめっき処理や有機防錆処理をしておいてもよい。   In this example, the solder paste 9c is directly applied on the interlayer connection portion 6, but from the viewpoint of the bonding strength of the component, the mounting portion of the component may be subjected to a plating process or an organic rust prevention process in advance.

以上説明した通り、本実施形態によれば、層間接続部6が貫通穴1に導電性ペースト6cを充填することで形成されている。ここで、層間接続部6に用いられる材料と基板絶縁樹脂との熱膨張率差に着目すると、バインダ樹脂を含んでいる導電性ペースト6cと絶縁基板4の絶縁樹脂材料との熱膨張率差は、一般的に用いられているめっきによるスルーホール接続におけるめっき金属と基板の絶縁樹脂材料との熱膨張率差に比べ小さい。そのため、熱衝撃時の応力が抑えられることにより、多層基板100は、部品などを実装する工程での接続信頼性が向上する。   As described above, according to the present embodiment, the interlayer connection portion 6 is formed by filling the through hole 1 with the conductive paste 6c. Here, paying attention to the difference in thermal expansion coefficient between the material used for the interlayer connection portion 6 and the substrate insulating resin, the difference in thermal expansion coefficient between the conductive paste 6c containing the binder resin and the insulating resin material of the insulating substrate 4 is The difference in thermal expansion coefficient between the plating metal and the insulating resin material of the substrate in the through-hole connection by plating that is generally used is small. Therefore, since the stress during thermal shock is suppressed, the connection reliability of the multilayer substrate 100 in the process of mounting components and the like is improved.

また、パンチング加工により表面回路パターン2の一部が絶縁基板4の貫通穴1の内壁に沿って延出している延出部20が形成されている。これにより、貫通穴1の内部および周囲に充填された導電性ペースト6cで形成された穴内充填部5a、6aと表面回路パターン2との接触面積が一般の接続部構造よりも広くなる。そのため、層間接続部6の抵抗値が小さくなり、かつ抵抗値のバラツキも小さくなる。また、層間接続部6の表面および裏面が平坦であるため、層間接続部6上への表面レジスト7および裏面レジスト8の形成や部品実装が容易となる。そのため、多層基板100における、層間接続部6の絶縁性を向上させたり、部品実装密度を高めたりすることができる。また、特にLED部品の実装において重要な、実装部品10の搭載位置の精度、傾きの精度なども、層間接続部6の表面および裏面の平坦性により確保できる。また、絶縁層の薄いフレキシブル基板へも適用可能であり、電子機器、ディスプレイの小型化、薄型化、狭額縁化にも貢献できる。   Further, an extending portion 20 in which a part of the surface circuit pattern 2 extends along the inner wall of the through hole 1 of the insulating substrate 4 is formed by punching. As a result, the contact area between the hole filling portions 5a, 6a formed of the conductive paste 6c filled in and around the through hole 1 and the surface circuit pattern 2 becomes wider than that of a general connection portion structure. Therefore, the resistance value of the interlayer connection portion 6 is reduced, and the variation in resistance value is also reduced. Further, since the front and back surfaces of the interlayer connection 6 are flat, it is easy to form the surface resist 7 and the back resist 8 on the interlayer connection 6 and to mount components. Therefore, it is possible to improve the insulation of the interlayer connection portion 6 in the multilayer substrate 100 and increase the component mounting density. In addition, the accuracy of the mounting position of the mounting component 10 and the accuracy of the inclination, which are particularly important in mounting LED components, can be ensured by the flatness of the front and back surfaces of the interlayer connection portion 6. Further, it can be applied to a flexible substrate having a thin insulating layer, and can contribute to downsizing, thinning, and narrowing the frame of electronic devices and displays.

以下、実施例について説明する。
図7Aは、実施例で用いた、導電性ペーストを充填する前の層間接続部評価用基板を示す画像である。図7Bは、図7Aの一部を拡大して示す画像である。図7Cは、実施例で用いた、導電性ペーストを充填した後の層間接続部評価用基板における層間接続部の接続状態を模式的に示す斜視図である。
Examples will be described below.
FIG. 7A is an image showing an interlayer connection evaluation substrate before filling with a conductive paste used in the example. FIG. 7B is an image showing a part of FIG. 7A in an enlarged manner. FIG. 7C is a perspective view schematically showing a connection state of the interlayer connection portion in the interlayer connection portion evaluation substrate after being filled with the conductive paste used in the example.

層間接続部評価用基板を用いて層間接続部の評価を実施した。層間接続部評価用基板は、基板外形寸法は40mm×190mmで、左上端と左下端の測定用ランド間を、デイジーチェーン状に0.9mm間隔で140箇所直列接続された層間接続部が全40列つながる構造である。そして、1基板中の層間接続部の総数は5600箇所となる構造を有している。なお、層間接続部評価用基板は、貫通穴径φ0.25mmのものを3個、貫通穴径φ0.2mmのものを3個、合計6個作製した。   The interlayer connection portion was evaluated using the interlayer connection portion evaluation substrate. The board for evaluating the interlayer connection part has a board outer dimension of 40 mm × 190 mm, and 40 interlayer connection parts are connected in series at 140 locations in a daisy chain at intervals of 0.9 mm between the upper left and lower left measurement lands. It is a structure that connects columns. The total number of interlayer connection portions in one substrate is 5600. In addition, as for the board | substrate for an interlayer connection part evaluation, 6 pieces with a through-hole diameter of 0.25 mm and 3 pieces with a through-hole diameter of 0.2 mm were produced in total.

層間接続部評価用基板は、前記した多層基板の製造方法により製造した。具体的には以下の通りである。
まず、厚みが400μmの絶縁基板(ガラスエポキシ)の表面および裏面に、厚みが35μmの銅箔を接合し、層間接続部における多層基板の総厚みを470μmとした。次に、両面の銅箔にエッチングを施して表面回路パターンおよび裏面回路パターンを形成した。次に、絶縁基板の表面側からパンチングピンでパンチング加工して、貫通穴径φ0.25mmおよび貫通穴径φ0.2mmの貫通穴を形成した。
The substrate for evaluating the interlayer connection portion was manufactured by the method for manufacturing a multilayer substrate described above. Specifically, it is as follows.
First, a copper foil having a thickness of 35 μm was bonded to the front and back surfaces of an insulating substrate (glass epoxy) having a thickness of 400 μm, and the total thickness of the multilayer substrate in the interlayer connection portion was set to 470 μm. Next, the copper foil on both sides was etched to form a front surface circuit pattern and a back surface circuit pattern. Next, punching was performed from the surface side of the insulating substrate with a punching pin to form a through hole having a through hole diameter of 0.25 mm and a through hole diameter of 0.2 mm.

次に、導電性ペーストを、マスクを介して、絶縁基板の表面からスクリーン印刷法で貫通穴に充填した。スクリーン印刷の条件は、クリアランス0〜1mmとし、20〜30μm厚、開口穴径φ0.3、0.35mmのメタルマスクと、硬度80のウレタンゴムのスキージとを用い、スキージ実効角度15度、印圧0.3MPa、スキージ速度10mm/sec、スキージ往復印刷とした。その後、導電性ペーストを、120℃の一定温度で30分加熱させ仮硬化させた。導電性ペーストとしては、フレーク状の銀およびフレーク状の銀コート銅粉のフィラーと、熱硬化性のバインダ樹脂とを混合したものを用いた。また、導電性ペーストとしては、体積抵抗率が7.5×10‐5Ω・cm、バインダ樹脂含有量が6〜7質量%、溶剤含有量が0質量%、硬化時の質量減少率が1%未満のものを用いた。 Next, the conductive paste was filled into the through holes by screen printing from the surface of the insulating substrate through the mask. The conditions for screen printing are a clearance of 0 to 1 mm, a metal mask with a thickness of 20 to 30 μm, an opening hole diameter of 0.3 and 0.35 mm, and a urethane rubber squeegee with a hardness of 80. The pressure was 0.3 MPa, the squeegee speed was 10 mm / sec, and the squeegee reciprocating printing was performed. Thereafter, the conductive paste was heated at a constant temperature of 120 ° C. for 30 minutes to be temporarily cured. As the conductive paste, a mixture of flaky silver and flaky silver-coated copper powder filler and a thermosetting binder resin was used. As the conductive paste, the volume resistivity is 7.5 × 10 −5 Ω · cm, the binder resin content is 6 to 7% by mass, the solvent content is 0% by mass, and the mass reduction rate upon curing is 1 Less than% was used.

続いて、マスクを介して、絶縁基板の裏面からスクリーン印刷法で、前記表面から印刷充填したものと同様の導電性ペーストを印刷形成した。スクリーン印刷の条件は、クリアランス0〜1mmとし、20〜30μm厚、開口穴径φ0.3、0.35mmのメタルマスクと、硬度80のウレタンゴムのスキージとを用い、スキージ実効角度15度、印圧0.4MPa、スキージ速度10mm/sec、スキージ片道印刷とした。その後、導電性ペーストを200℃の一定温度で60分加熱させ硬化させた。
これにより、表面回路パターンと裏面回路パターンとを電気的に接続する層間接続部を形成した。
Subsequently, a conductive paste similar to that printed and filled from the front surface was printed by screen printing from the back surface of the insulating substrate through a mask. The conditions for screen printing are a clearance of 0 to 1 mm, a metal mask with a thickness of 20 to 30 μm, an opening hole diameter of 0.3 and 0.35 mm, and a urethane rubber squeegee with a hardness of 80. The pressure was 0.4 MPa, the squeegee speed was 10 mm / sec, and squeegee one-way printing. Thereafter, the conductive paste was cured by heating at a constant temperature of 200 ° C. for 60 minutes.
Thereby, the interlayer connection part which electrically connects a front surface circuit pattern and a back surface circuit pattern was formed.

このようにして得られた層間接続部評価用基板を解析した結果、導通不良箇所は検出されなかった。また、貫通穴径φ0.25mmの層間接続部は6.8〜7.6mΩ(n=3基板)、貫通穴径φ0.2mmの層間接続部は10.1〜12.9mΩ(n=3基板)の接続抵抗値を有していた。これは、接続部寸法から計算して妥当な抵抗値で、バラツキも小さいものであり、この解析により使用上問題がないことが確認できた。   As a result of analyzing the substrate for evaluating an interlayer connection obtained in this way, a conduction failure point was not detected. The through hole diameter φ0.25 mm interlayer connection is 6.8 to 7.6 mΩ (n = 3 substrate), and the through hole diameter φ0.2 mm interlayer connection is 10.1 to 12.9 mΩ (n = 3 substrate). ) Connection resistance value. This is an appropriate resistance value calculated from the dimensions of the connecting portion and has little variation, and this analysis confirmed that there was no problem in use.

続いて、得られた層間接続部評価用基板を用いて、260℃半田ディップ(10回繰り返し)耐熱試験、260℃リフロー処理(10回繰り返し)耐熱試験を実施した。その結果、貫通穴径φ0.2mm、0.25mmの層間接続部評価用基板ともに、抵抗値変化率は10%未満であり、使用上問題がないことが確認できた。   Subsequently, a 260 ° C. solder dip (repeated 10 times) heat resistance test and a 260 ° C. reflow treatment (repeated 10 times) heat resistance test were performed using the obtained interlayer connection evaluation board. As a result, the resistance change rate was less than 10% for both the interlayer connection portion evaluation substrates having through-hole diameters of 0.2 mm and 0.25 mm, and it was confirmed that there was no problem in use.

層間接続部における銅箔表面からの導電性ペーストの高さ(穴外平板部の厚さ)については、段差計やマイクロスコープなどを用いて測定した結果、10〜30μm程度であった。   The height of the conductive paste from the surface of the copper foil in the interlayer connection portion (thickness of the plate portion outside the hole) was about 10 to 30 μm as a result of measurement using a step gauge, a microscope, or the like.

以上、本実施形態に係る多層基板の製造方法、部品実装基板の製造方法、多層基板、および、部品実装基板について、発明を実施するための形態により具体的に説明したが、本発明の趣旨はこれらの記載に限定されるものではなく、特許請求の範囲の記載に基づいて広く解釈されなければならない。また、これらの記載に基づいて種々変更、改変などしたものも本発明の趣旨に含まれる。   The multilayer board manufacturing method, the component mounting board manufacturing method, the multilayer board, and the component mounting board according to the present embodiment have been specifically described with reference to the embodiments for carrying out the invention. It is not limited to these descriptions, and should be widely interpreted based on the description of the scope of claims. Further, various changes and modifications based on these descriptions are also included in the spirit of the present invention.

例えば、多層基板100は、表面回路パターン2の一部が絶縁基板4の貫通穴1の内壁に沿って延出した延出部20を有するものとした。しかし、裏面回路パターン3の一部が絶縁基板4の貫通穴1の内壁に沿って延出した延出部を有するものであってもよい。また、絶縁基板4の表面側および裏面側の両方に延出部を有するものであってもよい。   For example, the multilayer substrate 100 has an extended portion 20 in which a part of the surface circuit pattern 2 extends along the inner wall of the through hole 1 of the insulating substrate 4. However, a part of the back circuit pattern 3 may have an extending portion that extends along the inner wall of the through hole 1 of the insulating substrate 4. Moreover, you may have an extension part in both the surface side of the insulated substrate 4, and a back surface side.

また、例えば、多層基板の製造方法では、層間接続部を形成する工程において、絶縁基板4の表面からの印刷(後に印刷する面の印刷)は、片道印刷としたが、往復印刷としてもよい。
また、多層基板の製造方法および部品実装基板の製造方法は、前記各工程に悪影響を与えない範囲において、前記各工程の間、あるいは前後に、他の工程を含めてもよい。例えば、製造途中に混入した異物を除去する異物除去工程などを含めてもよい。
Further, for example, in the method for manufacturing a multilayer substrate, in the step of forming the interlayer connection portion, printing from the surface of the insulating substrate 4 (printing of a surface to be printed later) is one-way printing, but may be reciprocal printing.
In addition, the multilayer substrate manufacturing method and the component mounting substrate manufacturing method may include other steps between or before and after each step as long as they do not adversely affect each step. For example, a foreign matter removing step for removing foreign matter mixed in during manufacturing may be included.

本開示の実施形態に係る多層基板および部品実装基板は、電子機器、ディスプレイなどに利用することができる。   The multilayer substrate and the component mounting substrate according to the embodiment of the present disclosure can be used for electronic devices, displays, and the like.

1 貫通穴
2 表面回路パターン
2a 表面銅箔
3 裏面回路パターン
3a 裏面銅箔
4 絶縁基板
5 接合体部
5a,6a 穴内充填部
5b,6b 穴外平板部
6 層間接続部
6c 導電性ペースト
7、7c 表面レジスト
8、8c 裏面レジスト
9 接着層
9c 半田ペースト
10 実装部品
11 マスク
12 スクリーンマスク
13 メタルマスク
14 パンチングピン
20 延出部
30 セラミックバフ
40 スキージ
100 多層基板
101 部品実装基板
DESCRIPTION OF SYMBOLS 1 Through-hole 2 Front surface circuit pattern 2a Front surface copper foil 3 Back surface circuit pattern 3a Back surface copper foil 4 Insulation board | substrate 5 Junction part 5a, 6a Filling part 5b, 6b Outer flat plate part 6 Interlayer connection part 6c Conductive paste 7, 7c Front surface resist 8, 8c Back surface resist 9 Adhesive layer 9c Solder paste 10 Mounting component 11 Mask 12 Screen mask 13 Metal mask 14 Punching pin 20 Extension part 30 Ceramic buff 40 Squeegee 100 Multilayer substrate 101 Component mounting substrate

Claims (10)

絶縁基板の表面および裏面に回路パターンが形成され、前記絶縁基板の表面および裏面のうちの少なくとも一方の前記回路パターンの一部が前記絶縁基板の貫通穴の内壁に沿って延出するようにパンチング加工により前記貫通穴を形成する工程と、
前記貫通穴の内部および周囲に、前記絶縁基板の表面および裏面の両面から、印刷により導電性ペーストを充填して層間接続部を形成する工程と、を含む多層基板の製造方法。
Punching so that circuit patterns are formed on the front and back surfaces of the insulating substrate, and a part of the circuit pattern of at least one of the front and back surfaces of the insulating substrate extends along the inner wall of the through hole of the insulating substrate. Forming the through hole by processing;
And a step of filling the conductive paste by printing from both the front surface and the back surface of the insulating substrate inside and around the through-hole to form an interlayer connection portion.
前記層間接続部を形成する工程の後、前記絶縁基板の表面および裏面における前記層間接続部の部位を平坦に研磨する工程を行う請求項1に記載の多層基板の製造方法。   The method for manufacturing a multilayer substrate according to claim 1, wherein after the step of forming the interlayer connection portion, a step of flatly polishing the portion of the interlayer connection portion on the front surface and the back surface of the insulating substrate is performed. 前記導電性ペーストは、体積抵抗率が2×10‐5〜1.5×10‐4Ω・cm、バインダ樹脂含有量が3〜10質量%である請求項1に記載の多層基板の製造方法。 2. The method for producing a multilayer substrate according to claim 1, wherein the conductive paste has a volume resistivity of 2 × 10 −5 to 1.5 × 10 −4 Ω · cm and a binder resin content of 3 to 10 mass%. . 前記絶縁基板の表面および裏面のうち、先に印刷する面の印刷が往復印刷であり、後に印刷する面の印刷が片道印刷である請求項1または請求項2に記載の多層基板の製造方法。   3. The method for manufacturing a multilayer substrate according to claim 1, wherein printing of a surface to be printed first is reciprocal printing and printing of a surface to be printed later is one-way printing among the front and back surfaces of the insulating substrate. 前記絶縁基板は、厚さが50〜1000μmガラスエポキシ、または、厚さが12〜50μmのポリイミドであり、前記絶縁基板の表面および裏面に形成された前記回路パターンの厚みが12〜70μmである請求項1から請求項4のいずれか一項に記載の多層基板の製造方法。   The insulating substrate is a glass epoxy having a thickness of 50 to 1000 μm or a polyimide having a thickness of 12 to 50 μm, and the thickness of the circuit pattern formed on the front and back surfaces of the insulating substrate is 12 to 70 μm. The manufacturing method of the multilayer substrate as described in any one of Claims 1-4. 請求項1から請求項5のいずれか一項に記載の多層基板の製造方法で製造された多層基板の表面および裏面にレジストを形成する工程と、
前記レジストを形成した多層基板に部品を実装する工程と、を含む部品実装基板の製造方法。
Forming a resist on the front surface and the back surface of the multilayer substrate manufactured by the multilayer substrate manufacturing method according to any one of claims 1 to 5;
Mounting the component on the multilayer substrate on which the resist is formed.
絶縁基板の表面および裏面に設けられた回路パターンと、前記絶縁基板および前記回路パターンを貫通する貫通穴に導電性ペーストが充填されて形成された層間接続部と、前記絶縁基板の表面および裏面のうちの少なくとも一方の前記回路パターンの一部が前記絶縁基板の前記貫通穴の内壁に沿って延出した延出部と、を備え、
前記絶縁基板の表面および裏面における前記層間接続部の部位が平坦である多層基板。
Circuit patterns provided on the front and back surfaces of the insulating substrate, interlayer connection portions formed by filling the insulating substrate and through holes penetrating the circuit pattern with conductive paste, and the front and back surfaces of the insulating substrate A part of at least one of the circuit patterns extending along the inner wall of the through hole of the insulating substrate, and
A multilayer substrate in which portions of the interlayer connection portion on the front surface and the back surface of the insulating substrate are flat.
前記導電性ペーストは、体積抵抗率が2×10‐5〜1.5×10‐4Ω・cm、バインダ樹脂含有量が3〜10質量%である請求項7に記載の多層基板。 The multilayer substrate according to claim 7, wherein the conductive paste has a volume resistivity of 2 × 10 −5 to 1.5 × 10 −4 Ω · cm and a binder resin content of 3 to 10% by mass. 前記絶縁基板は、厚さが50〜1000μmガラスエポキシ、または、厚さが12〜50μmのポリイミドであり、前記絶縁基板の表面および裏面に形成された前記回路パターンの厚みが12〜70μmである請求項7または請求項8に記載の多層基板。   The insulating substrate is a glass epoxy having a thickness of 50 to 1000 μm or a polyimide having a thickness of 12 to 50 μm, and the thickness of the circuit pattern formed on the front and back surfaces of the insulating substrate is 12 to 70 μm. Item 9. The multilayer substrate according to Item 7 or Item 8. 請求項7から請求項9のいずれか一項に記載の多層基板に、実装部品が実装された部品実装基板。   The component mounting board | substrate with which the mounting component was mounted in the multilayer substrate as described in any one of Claims 7-9.
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