JP2019053617A - システムｌｓｉおよびシステムｌｓｉの故障検出方法 - Google Patents

システムｌｓｉおよびシステムｌｓｉの故障検出方法 Download PDF

Info

Publication number
JP2019053617A
JP2019053617A JP2017178232A JP2017178232A JP2019053617A JP 2019053617 A JP2019053617 A JP 2019053617A JP 2017178232 A JP2017178232 A JP 2017178232A JP 2017178232 A JP2017178232 A JP 2017178232A JP 2019053617 A JP2019053617 A JP 2019053617A
Authority
JP
Japan
Prior art keywords
bus
module
group
system lsi
cpus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017178232A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019053617A5 (https=
Inventor
直昭 大久保
Naoaki Okubo
直昭 大久保
田辺　淳
Atsushi Tanabe
田辺　　淳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Devices and Storage Corp filed Critical Toshiba Corp
Priority to JP2017178232A priority Critical patent/JP2019053617A/ja
Priority to CN201810177821.0A priority patent/CN109508315A/zh
Priority to US15/913,449 priority patent/US10846164B2/en
Publication of JP2019053617A publication Critical patent/JP2019053617A/ja
Publication of JP2019053617A5 publication Critical patent/JP2019053617A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/079—Root cause analysis, i.e. error or fault diagnosis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/082—Associative directories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0826—Limited pointers directories; State-only directories without pointers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1048—Scalability
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1056—Simplification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hardware Redundancy (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP2017178232A 2017-09-15 2017-09-15 システムｌｓｉおよびシステムｌｓｉの故障検出方法 Pending JP2019053617A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2017178232A JP2019053617A (ja) 2017-09-15 2017-09-15 システムｌｓｉおよびシステムｌｓｉの故障検出方法
CN201810177821.0A CN109508315A (zh) 2017-09-15 2018-03-05 系统lsi以及系统lsi的故障检测方法
US15/913,449 US10846164B2 (en) 2017-09-15 2018-03-06 System LSI and fault detection method for system LSI

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017178232A JP2019053617A (ja) 2017-09-15 2017-09-15 システムｌｓｉおよびシステムｌｓｉの故障検出方法

Publications (2)

Publication Number Publication Date
JP2019053617A true JP2019053617A (ja) 2019-04-04
JP2019053617A5 JP2019053617A5 (https=) 2019-10-17

Family

ID=65720250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017178232A Pending JP2019053617A (ja) 2017-09-15 2017-09-15 システムｌｓｉおよびシステムｌｓｉの故障検出方法

Country Status (3)

Country Link
US (1) US10846164B2 (https=)
JP (1) JP2019053617A (https=)
CN (1) CN109508315A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022185582A1 (ja) * 2021-03-05 2022-09-09 オムロン株式会社 データ処理装置、データ処理方法およびプログラム

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020177074A (ja) * 2019-04-16 2020-10-29 株式会社デンソー 車両用装置、車両用装置の制御方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0844629A (ja) * 1994-07-26 1996-02-16 Matsushita Electric Works Ltd メモリアクセス異常監視装置
JP2003316752A (ja) * 2002-04-25 2003-11-07 Nec Corp マルチプロセッサシステムおよびリソース割り当て方法
JP2004199579A (ja) * 2002-12-20 2004-07-15 Hitachi Ltd マルチプロセッサシステム
JP2009116398A (ja) * 2007-11-01 2009-05-28 Nec Computertechno Ltd ノードコントローラ、分散共有メモリ型情報処理装置、キャッシュコヒーレンシ制御方法
JP2009238056A (ja) * 2008-03-28 2009-10-15 Fujitsu Ltd マイクロプロセッサおよびシグネチャ生成方法ならびに多重化システムおよび多重化実行検証方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5522058A (en) * 1992-08-11 1996-05-28 Kabushiki Kaisha Toshiba Distributed shared-memory multiprocessor system with reduced traffic on shared bus
JP3467631B2 (ja) * 1994-06-07 2003-11-17 株式会社ルネサステクノロジ ロジックｌｓｉ
JP3412349B2 (ja) * 1994-12-28 2003-06-03 株式会社日立製作所 制御装置
JP3872118B2 (ja) 1995-03-20 2007-01-24 富士通株式会社 キャッシュコヒーレンス装置
JPH10260897A (ja) 1997-03-21 1998-09-29 Toshiba Corp キャッシュシステム
JP3864509B2 (ja) * 1997-08-19 2007-01-10 株式会社日立製作所 マルチプロセッサシステム
JP3983820B2 (ja) 1998-01-07 2007-09-26 富士通株式会社 コンピュータシステム及びメモリ保護の方法
US6209064B1 (en) * 1998-01-07 2001-03-27 Fujitsu Limited Cache coherence unit with integrated message passing and memory protection for a distributed, shared memory multiprocessor system
AU3966599A (en) 1998-04-27 1999-11-16 Atlantek, Inc. Apparatus for automated printing and assembly of passport booklets
JP3736305B2 (ja) * 2000-07-06 2006-01-18 日本電気株式会社 ディスクキャッシュシステムおよびディスクキャッシュ制御方法
US6792512B2 (en) * 2002-08-06 2004-09-14 International Business Machines Corporation Method and system for organizing coherence directories in shared memory systems
GB0315504D0 (en) * 2003-07-02 2003-08-06 Advanced Risc Mach Ltd Coherent multi-processing system
JP4263976B2 (ja) * 2003-09-24 2009-05-13 株式会社東芝 オンチップマルチコア型耐タンパプロセッサ
US20050138267A1 (en) * 2003-12-23 2005-06-23 Bains Kuljit S. Integral memory buffer and serial presence detect capability for fully-buffered memory modules
JP5100176B2 (ja) * 2007-03-29 2012-12-19 株式会社東芝 マルチプロセッサシステム
JP2011039713A (ja) * 2009-08-07 2011-02-24 Panasonic Corp 外部バスインタフェース、ｌｓｉおよびシステム
CN102947807B (zh) * 2010-06-14 2015-09-09 富士通株式会社 多核处理器系统、缓存一致性控制方法以及缓存一致性控制程序
JP5121896B2 (ja) * 2010-08-11 2013-01-16 株式会社東芝 マルチコアプロセッサシステムおよびマルチコアプロセッサ
CN103150264B (zh) * 2013-01-18 2014-09-17 浪潮电子信息产业股份有限公司 一种基于扩展型Cache Coherence协议的多级一致性域仿真验证和测试方法
US9292444B2 (en) * 2013-09-26 2016-03-22 International Business Machines Corporation Multi-granular cache management in multi-processor computing environments
US10740167B2 (en) * 2016-12-07 2020-08-11 Electronics And Telecommunications Research Institute Multi-core processor and cache management method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0844629A (ja) * 1994-07-26 1996-02-16 Matsushita Electric Works Ltd メモリアクセス異常監視装置
JP2003316752A (ja) * 2002-04-25 2003-11-07 Nec Corp マルチプロセッサシステムおよびリソース割り当て方法
JP2004199579A (ja) * 2002-12-20 2004-07-15 Hitachi Ltd マルチプロセッサシステム
JP2009116398A (ja) * 2007-11-01 2009-05-28 Nec Computertechno Ltd ノードコントローラ、分散共有メモリ型情報処理装置、キャッシュコヒーレンシ制御方法
JP2009238056A (ja) * 2008-03-28 2009-10-15 Fujitsu Ltd マイクロプロセッサおよびシグネチャ生成方法ならびに多重化システムおよび多重化実行検証方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022185582A1 (ja) * 2021-03-05 2022-09-09 オムロン株式会社 データ処理装置、データ処理方法およびプログラム
JP2022135468A (ja) * 2021-03-05 2022-09-15 オムロン株式会社 データ処理装置、データ処理方法およびプログラム
JP7694064B2 (ja) 2021-03-05 2025-06-18 オムロン株式会社 データ処理装置、データ処理方法およびプログラム

Also Published As

Publication number Publication date
CN109508315A (zh) 2019-03-22
US20190087254A1 (en) 2019-03-21
US10846164B2 (en) 2020-11-24

Similar Documents

Publication Publication Date Title
JP3722415B2 (ja) 効率的なバス機構及びコヒーレンス制御を有する繰り返しチップ構造を有するスケーラブル共用メモリ・マルチプロセッサ・コンピュータ・システム
TWI516933B (zh) 用於在本地代理者之記憶體鏡像及遷移之裝置及方法以及電腦可讀取媒體
EP2294581B1 (en) A system for distributing available memory resource
US20130227219A1 (en) Processor, information processing apparatus, and arithmetic method
US11392441B2 (en) Error reporting for non-volatile memory modules
JP6005392B2 (ja) ルーティングのための方法及び装置
JPWO2010097925A1 (ja) 情報処理装置
US7159079B2 (en) Multiprocessor system
KR101498452B1 (ko) 복합 멀티-코어 및 멀티-소켓 시스템의 디버깅
US10176131B1 (en) Controlling exclusive access using supplemental transaction identifiers
JP2019053617A (ja) システムｌｓｉおよびシステムｌｓｉの故障検出方法
JP2009187314A (ja) 二重化コントローラ・システム、ｃｐｕモジュール、そのプログラム
US9330024B1 (en) Processing device and method thereof
KR20230157080A (ko) 스토리지 장치, 스토리지 장치 및 메모리 장치를 포함하는 컴퓨팅 장치, 그리고 컴퓨팅 장치의 동작 방법
CN201159895Y (zh) 多处理器连接电路
US11221794B2 (en) Memory array element sparing
US20100131718A1 (en) Multiprocessor system
US9081673B2 (en) Microprocessor and memory access method
US9436613B2 (en) Central processing unit, method for controlling central processing unit, and information processing apparatus
JP7489954B2 (ja) 処理システム内の処理タスク
CN101238448B (zh) 用于监控多处理器系统中的存储单元的方法和设备
US20050165974A1 (en) Computer apparatus and computer system
CN118984312B (zh) 网口绑定方法、装置、计算机设备及存储介质
WO2011030498A1 (ja) データ処理装置及びデータ処理方法
WO2025128115A1 (en) Address space support for point-to-point cache coherency

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190909

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190909

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200722

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200825

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20210302