JP2019021886A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2019021886A JP2019021886A JP2017142155A JP2017142155A JP2019021886A JP 2019021886 A JP2019021886 A JP 2019021886A JP 2017142155 A JP2017142155 A JP 2017142155A JP 2017142155 A JP2017142155 A JP 2017142155A JP 2019021886 A JP2019021886 A JP 2019021886A
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- JP
- Japan
- Prior art keywords
- bonding pad
- groove
- bonding
- wire
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05016—Shape in side view
- H01L2224/05017—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】 半導体装置は、半導体基板と、前記半導体基板の上面に設けられており、ワイヤがボンディングされるボンディングパッド、を備えている。前記ボンディングパッドには、前記ボンディングパッドの上面を直線状に延びる第1の溝と、前記ボンディングパッドの前記上面を前記第1の溝とは異なる方向に直線状に延びる第2の溝と、が形成されている。前記第1の溝と前記第2の溝は、前記ボンディングパッドを平面視したときに前記ボンディングパッドの中心で交わっている。
【選択図】図2
Description
12:半導体基板
14:主電極
16:ボンディングパッド
18:リード線
20:ワイヤ
20a:線状部
20b:先端部
22:第1の溝
24:第2の溝
50:キャピラリ
Claims (1)
- 半導体装置であって、
半導体基板と、
前記半導体基板の上面に設けられており、ワイヤがボンディングされるボンディングパッド、
を備えており、
前記ボンディングパッドには、前記ボンディングパッドの上面を直線状に延びる第1の溝と、前記ボンディングパッドの前記上面を前記第1の溝とは異なる方向に直線状に延びる第2の溝と、が形成されており、
前記第1の溝と前記第2の溝は、前記ボンディングパッドを平面視したときに前記ボンディングパッドの中心で交わっている、
半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017142155A JP2019021886A (ja) | 2017-07-21 | 2017-07-21 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017142155A JP2019021886A (ja) | 2017-07-21 | 2017-07-21 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2019021886A true JP2019021886A (ja) | 2019-02-07 |
Family
ID=65353222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017142155A Pending JP2019021886A (ja) | 2017-07-21 | 2017-07-21 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2019021886A (ja) |
-
2017
- 2017-07-21 JP JP2017142155A patent/JP2019021886A/ja active Pending
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