JP2018527690A - 擬似デュアルポートメモリ - Google Patents

擬似デュアルポートメモリ Download PDF

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Publication number
JP2018527690A
JP2018527690A JP2018513483A JP2018513483A JP2018527690A JP 2018527690 A JP2018527690 A JP 2018527690A JP 2018513483 A JP2018513483 A JP 2018513483A JP 2018513483 A JP2018513483 A JP 2018513483A JP 2018527690 A JP2018527690 A JP 2018527690A
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JP
Japan
Prior art keywords
write
clock
memory
read
mode
Prior art date
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Pending
Application number
JP2018513483A
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English (en)
Japanese (ja)
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JP2018527690A5 (cg-RX-API-DMAC7.html
Inventor
クウォク、トニー・チュン・イウ
デサイ、ニシト・ニティン
ジュン、チャンホ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2018527690A publication Critical patent/JP2018527690A/ja
Publication of JP2018527690A5 publication Critical patent/JP2018527690A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
JP2018513483A 2015-09-15 2016-08-16 擬似デュアルポートメモリ Pending JP2018527690A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/855,319 US10061542B2 (en) 2015-09-15 2015-09-15 Pseudo dual port memory
US14/855,319 2015-09-15
PCT/US2016/047219 WO2017048440A1 (en) 2015-09-15 2016-08-16 Pseudo dual port memory

Publications (2)

Publication Number Publication Date
JP2018527690A true JP2018527690A (ja) 2018-09-20
JP2018527690A5 JP2018527690A5 (cg-RX-API-DMAC7.html) 2018-11-15

Family

ID=56787738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018513483A Pending JP2018527690A (ja) 2015-09-15 2016-08-16 擬似デュアルポートメモリ

Country Status (6)

Country Link
US (1) US10061542B2 (cg-RX-API-DMAC7.html)
EP (1) EP3350716B1 (cg-RX-API-DMAC7.html)
JP (1) JP2018527690A (cg-RX-API-DMAC7.html)
KR (1) KR20180053720A (cg-RX-API-DMAC7.html)
CN (1) CN108027787B (cg-RX-API-DMAC7.html)
WO (1) WO2017048440A1 (cg-RX-API-DMAC7.html)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10768856B1 (en) * 2018-03-12 2020-09-08 Amazon Technologies, Inc. Memory access for multiple circuit components
US11024347B2 (en) 2019-10-17 2021-06-01 Marvell Asia Pte, Ltd. Multiple sense amplifier and data path-based pseudo dual port SRAM
US11417370B2 (en) * 2020-08-12 2022-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device
US11640838B2 (en) * 2021-09-24 2023-05-02 Qualcomm Incorporated Pseudo-dual-port SRAM with burst-mode address comparator
US12340871B2 (en) 2023-04-21 2025-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuits with dynamically adjustable pulse widths and methods for operating the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040190364A1 (en) * 2003-03-25 2004-09-30 Jung Chang Ho Clock generator for pseudo dual port memory
US20070109884A1 (en) * 2005-11-17 2007-05-17 Jung Chang H Pseudo-dual port memory having a clock for each port
US20070109909A1 (en) * 2005-11-17 2007-05-17 Jung Chang H Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent
US20090158077A1 (en) * 2007-12-12 2009-06-18 Broadcom Coroporation Circuit and method for generation of duty cycle independent core clock
US20090231937A1 (en) * 2008-03-13 2009-09-17 Qualcomm Incorporated Address Multiplexing in Pseudo-Dual Port Memory
US20140153349A1 (en) * 2012-11-30 2014-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Simultaneous Two/Dual Port Access on 6T SRAM

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8102721B2 (en) * 2007-06-27 2012-01-24 Infineon Technologies Ag Pseudo dual-port memory
US8370557B2 (en) 2008-12-19 2013-02-05 Intel Corporation Pseudo dual-port SRAM and a shared memory switch using multiple memory banks and a sideband memory
CN102110464B (zh) 2009-12-26 2015-06-10 上海芯豪微电子有限公司 宽带读写存储器装置
CN102567248A (zh) * 2010-12-31 2012-07-11 中国航空工业集团公司第六三一研究所 一种避免双端口存储器访问冲突的控制电路与方法
US8958254B2 (en) 2012-02-22 2015-02-17 Texas Instruments Incorporated High performance two-port SRAM architecture using 8T high performance single port bit cell
US9892768B2 (en) * 2012-02-24 2018-02-13 Avago Technologies General Ip (Singapore) Pte. Ltd. Latching pseudo-dual-port memory multiplexer
US8902672B2 (en) 2013-01-01 2014-12-02 Memoir Systems, Inc. Methods and apparatus for designing and constructing multi-port memory circuits

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040190364A1 (en) * 2003-03-25 2004-09-30 Jung Chang Ho Clock generator for pseudo dual port memory
US20070109884A1 (en) * 2005-11-17 2007-05-17 Jung Chang H Pseudo-dual port memory having a clock for each port
US20070109909A1 (en) * 2005-11-17 2007-05-17 Jung Chang H Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent
US20090158077A1 (en) * 2007-12-12 2009-06-18 Broadcom Coroporation Circuit and method for generation of duty cycle independent core clock
US20090231937A1 (en) * 2008-03-13 2009-09-17 Qualcomm Incorporated Address Multiplexing in Pseudo-Dual Port Memory
JP2011515002A (ja) * 2008-03-13 2011-05-12 クゥアルコム・インコーポレイテッド 疑似デュアル・ポート・メモリにおけるアドレス多重化
US20140153349A1 (en) * 2012-11-30 2014-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Simultaneous Two/Dual Port Access on 6T SRAM

Also Published As

Publication number Publication date
KR20180053720A (ko) 2018-05-23
CN108027787B (zh) 2021-01-22
US20170075379A1 (en) 2017-03-16
EP3350716A1 (en) 2018-07-25
EP3350716B1 (en) 2020-08-12
US10061542B2 (en) 2018-08-28
CN108027787A (zh) 2018-05-11
WO2017048440A1 (en) 2017-03-23

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