JP2018527690A5 - - Google Patents
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- Publication number
- JP2018527690A5 JP2018527690A5 JP2018513483A JP2018513483A JP2018527690A5 JP 2018527690 A5 JP2018527690 A5 JP 2018527690A5 JP 2018513483 A JP2018513483 A JP 2018513483A JP 2018513483 A JP2018513483 A JP 2018513483A JP 2018527690 A5 JP2018527690 A5 JP 2018527690A5
- Authority
- JP
- Japan
- Prior art keywords
- clock
- write
- mode
- read
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004044 response Effects 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 13
- 230000006870 function Effects 0.000 claims description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/855,319 US10061542B2 (en) | 2015-09-15 | 2015-09-15 | Pseudo dual port memory |
| US14/855,319 | 2015-09-15 | ||
| PCT/US2016/047219 WO2017048440A1 (en) | 2015-09-15 | 2016-08-16 | Pseudo dual port memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2018527690A JP2018527690A (ja) | 2018-09-20 |
| JP2018527690A5 true JP2018527690A5 (cg-RX-API-DMAC7.html) | 2018-11-15 |
Family
ID=56787738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018513483A Pending JP2018527690A (ja) | 2015-09-15 | 2016-08-16 | 擬似デュアルポートメモリ |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US10061542B2 (cg-RX-API-DMAC7.html) |
| EP (1) | EP3350716B1 (cg-RX-API-DMAC7.html) |
| JP (1) | JP2018527690A (cg-RX-API-DMAC7.html) |
| KR (1) | KR20180053720A (cg-RX-API-DMAC7.html) |
| CN (1) | CN108027787B (cg-RX-API-DMAC7.html) |
| WO (1) | WO2017048440A1 (cg-RX-API-DMAC7.html) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10768856B1 (en) * | 2018-03-12 | 2020-09-08 | Amazon Technologies, Inc. | Memory access for multiple circuit components |
| US11024347B2 (en) | 2019-10-17 | 2021-06-01 | Marvell Asia Pte, Ltd. | Multiple sense amplifier and data path-based pseudo dual port SRAM |
| US11417370B2 (en) * | 2020-08-12 | 2022-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device |
| US11640838B2 (en) * | 2021-09-24 | 2023-05-02 | Qualcomm Incorporated | Pseudo-dual-port SRAM with burst-mode address comparator |
| US12340871B2 (en) | 2023-04-21 | 2025-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuits with dynamically adjustable pulse widths and methods for operating the same |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6809983B2 (en) * | 2003-03-25 | 2004-10-26 | Lsi Logic Corporation | Clock generator for pseudo dual port memory |
| US7251193B2 (en) * | 2005-11-17 | 2007-07-31 | Qualcomm Incorporated | Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent |
| US7319632B2 (en) * | 2005-11-17 | 2008-01-15 | Qualcomm Incorporated | Pseudo-dual port memory having a clock for each port |
| US8102721B2 (en) * | 2007-06-27 | 2012-01-24 | Infineon Technologies Ag | Pseudo dual-port memory |
| US7890789B2 (en) * | 2007-12-12 | 2011-02-15 | Broadcom Corporation | Circuit and method for generation of duty cycle independent core clock |
| US7760562B2 (en) * | 2008-03-13 | 2010-07-20 | Qualcomm Incorporated | Address multiplexing in pseudo-dual port memory |
| US8370557B2 (en) | 2008-12-19 | 2013-02-05 | Intel Corporation | Pseudo dual-port SRAM and a shared memory switch using multiple memory banks and a sideband memory |
| CN102110464B (zh) | 2009-12-26 | 2015-06-10 | 上海芯豪微电子有限公司 | 宽带读写存储器装置 |
| CN102567248A (zh) * | 2010-12-31 | 2012-07-11 | 中国航空工业集团公司第六三一研究所 | 一种避免双端口存储器访问冲突的控制电路与方法 |
| US8958254B2 (en) | 2012-02-22 | 2015-02-17 | Texas Instruments Incorporated | High performance two-port SRAM architecture using 8T high performance single port bit cell |
| US9892768B2 (en) * | 2012-02-24 | 2018-02-13 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Latching pseudo-dual-port memory multiplexer |
| US9230622B2 (en) | 2012-11-30 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Simultaneous two/dual port access on 6T SRAM |
| US8902672B2 (en) | 2013-01-01 | 2014-12-02 | Memoir Systems, Inc. | Methods and apparatus for designing and constructing multi-port memory circuits |
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2015
- 2015-09-15 US US14/855,319 patent/US10061542B2/en active Active
-
2016
- 2016-08-16 EP EP16754650.6A patent/EP3350716B1/en active Active
- 2016-08-16 KR KR1020187010409A patent/KR20180053720A/ko not_active Abandoned
- 2016-08-16 JP JP2018513483A patent/JP2018527690A/ja active Pending
- 2016-08-16 WO PCT/US2016/047219 patent/WO2017048440A1/en not_active Ceased
- 2016-08-16 CN CN201680053088.0A patent/CN108027787B/zh active Active