JP2018506849A - 電界効果トランジスタの半導体材料の積層の上面の多層パッシベーション - Google Patents
電界効果トランジスタの半導体材料の積層の上面の多層パッシベーション Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
Description
○2価、3価または4価の窒化化合物を含む軸zに沿った半導体材料の積層(Emp)と、
○ドレイン(D)、ソース(S)およびゲート(G)と、
○前記積層(Emp)の上面(14)の上に配置され2つの副層(16a;16b)を含むパッシベーション層(16)と、を含む電界効果トランジスタであって、前記ドレイン(D)、前記ソース(S)および前記ゲート(G)は、
○電圧差(それぞれVDS、VGS)がドレイン(D)とソース(S)間またはゲート(G)とソース(S)間に印加されたときのゲート(G)とドレイン(D)間またはゲート(G)とソース(S)間のゲート(G)の基部における高電界強度の第1の区域(Z1)と、
○低電界強度の第2の区域(Z2)と、を定義するということと、
○前記第1の副層(16a)は第2の区域(Z2)全体にわたって延伸し、電気的降伏電界Ecl1を有する第1の材料(Mat1)を含み、前記第1副層(16a)の電荷は積層(Emp)の前記上面(14)の電荷より厳密に少なく、
○前記第2の副層(16b)は第1の区域(Z1)全体にわたって延伸し、第1の副層(16a)を覆い、Ecl1より厳密に大きな電気的降伏電界Ecl2を有する第2の材料(Mat2)を含むことと、を特徴とする、電界効果トランジスタが提供される。
−第1の材料を含む第1の副層を第2の区域上に合成する第1の工程と、
−第2の材料を含む第2の副層を第1の副層および第1の区域上に合成する第2の工程と、を含む方法が提供される。
Claims (13)
- ○2価、3価または4価の窒化化合物を含む軸zに沿った半導体材料の積層(Emp)と、
○ドレイン(D)、ソース(S)およびゲート(G)と、
○前記積層(Emp)の上面(14)の上に配置され2つの副層(16a;16b)を含むパッシベーション層(16)と、を含む電界効果トランジスタであって、前記ドレイン(D)、前記ソース(S)および前記ゲート(G)は、
○電圧差(それぞれVDS、VGS)が前記ドレイン(D)と前記ソース(S)間または前記ゲート(G)と前記ソース(S)間に印加されたときの前記ゲート(G)と前記ドレイン(D)間または前記ゲート(G)と前記ソース(S)間の前記ゲート(G)の基部における高電界強度の第1の区域(Z1)と、
○低電界強度の第2の区域(Z2)と、を画定するということと、
○前記第1の副層(16a)は、前記第2の区域(Z2)全体にわたって延伸し、電気的降伏電界Ecl1を有する第1の材料(Mat1)を含み、前記第1副層(16a)の電荷は前記積層(Emp)の前記上面(14)の電荷より厳密に少なく、
○前記第2の副層(16b)は前記第1の区域(Z1)全体にわたって延伸し、前記第1の副層(16a)を覆い、Ecl1より厳密に大きな電気的降伏電界Ecl2を有する第2の材料(Mat2)を含むことと、を特徴とする電界効果トランジスタ。 - 前記第1副層(16a)の電荷は前記上面(14)の電荷の1%以下である、請求項1に記載のトランジスタ。
- 前記軸zの方向の前記第1の副層(16a)の厚さは20nm以上である、請求項1または2に記載のトランジスタ。
- 前記第1の材料(Mat1)は窒化珪素またはアルミナ(Al2O3)を含む、請求項1乃至3のいずれか一項に記載のトランジスタ。
- 前記第1の材料(Mat1)は誘導結合プラズマ化学気相堆積(ICP−CVD)または原子層堆積(ALD)により生成される、請求項4に記載のトランジスタ。
- 前記第2の材料(Mat2)は窒化珪素(SiN)または酸化珪素(SiO2)または窒化アルミニウム(AlN)を含む、請求項1乃至5のいずれか一項に記載のトランジスタ。
- 前記第2の材料は、熱処理を伴う、プラズマ強化化学気相堆積(PECVD)により、または陰極スパッタにより、または原子層堆積(ALD)により得られる、請求項6に記載のトランジスタ。
- 前記軸zの方向の前記第2の副層(16b)の厚さは50nm以上である、請求項1乃至7のいずれか一項に記載のトランジスタ。
- 請求項1乃至8のいずれか一項に記載のトランジスタの積層(Emp)上にパッシベーション層(16)を製作する方法であって、
−前記第1の材料(Mat1)を含む前記第1の副層(16a)を前記第2の区域(Z2)上に合成する第1の工程と、
−前記第2の材料(Mat2)を含む前記第2の副層(16b)を前記副層(16a)および前記第1の区域(Z1)上に合成する第2の工程と、を含む方法。 - 前記第1の材料(Mat1)は前記積層(Emp)の前記上面(14)の前記第1および第2の原子層だけを改質する方法により合成される、請求項9に記載の方法。
- 前記第1の材料(Mat1)は誘導結合プラズマ化学気相堆積(ICP−CVD)または原子層堆積(ALD)により合成される、請求項10に記載の方法。
- 前記第2の材料(Mat2)の合成温度(Tsynth)は前記トランジスタが作動しているときに前記第1の区域(Z1)全体にわたって観測される最高温度より高い、請求項9乃至11のいずれか一項に記載の方法。
- 前記第2の材料(Mat2)は、熱処理を伴う、プラズマ強化化学気相堆積(PECVD)方法により、または陰極スパッタにより、または原子層堆積(ALD)により合成される、請求項12に記載の方法。
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FR1403025A FR3031239B1 (fr) | 2014-12-30 | 2014-12-30 | Passivation multicouche de la face superieure de l'empilement de materiaux semi-conducteurs d'un transistor a effet de champ. |
FR1403025 | 2014-12-30 | ||
PCT/EP2015/081346 WO2016107870A1 (fr) | 2014-12-30 | 2015-12-29 | Passivation multicouche de la face supérieure de l'empilement de matériaux semi-conducteurs d'un transistor à effet de champ |
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US (1) | US20180019334A1 (ja) |
EP (1) | EP3241238A1 (ja) |
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US10714536B2 (en) | 2018-10-23 | 2020-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to form memory cells separated by a void-free dielectric structure |
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- 2015-12-29 WO PCT/EP2015/081346 patent/WO2016107870A1/fr active Application Filing
- 2015-12-29 US US15/540,993 patent/US20180019334A1/en not_active Abandoned
- 2015-12-29 CN CN201580076556.1A patent/CN107408573A/zh active Pending
- 2015-12-29 JP JP2017535340A patent/JP2018506849A/ja active Pending
- 2015-12-29 EP EP15832737.9A patent/EP3241238A1/fr not_active Withdrawn
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JP2001223341A (ja) * | 2000-02-08 | 2001-08-17 | Furukawa Electric Co Ltd:The | 電源装置 |
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WO2007040160A1 (ja) * | 2005-09-30 | 2007-04-12 | Nec Corporation | 電界効果トランジスタ |
WO2008035403A1 (en) * | 2006-09-20 | 2008-03-27 | Fujitsu Limited | Field-effect transistor |
JP2012089677A (ja) * | 2010-10-19 | 2012-05-10 | Fujitsu Ltd | 半導体装置及び半導体装置の製造方法 |
JP2014078537A (ja) * | 2011-02-15 | 2014-05-01 | Sharp Corp | 横型半導体装置 |
JP2013077620A (ja) * | 2011-09-29 | 2013-04-25 | Fujitsu Ltd | 化合物半導体装置及びその製造方法 |
JP2013219273A (ja) * | 2012-04-11 | 2013-10-24 | Sharp Corp | 窒化物半導体装置 |
US20130277680A1 (en) * | 2012-04-23 | 2013-10-24 | Bruce M. Green | High Speed Gallium Nitride Transistor Devices |
JP2014165501A (ja) * | 2013-02-26 | 2014-09-08 | Freescale Semiconductor Inc | Mishfetおよびショットキーデバイスの統合 |
JP2014183125A (ja) * | 2013-03-18 | 2014-09-29 | Fujitsu Ltd | 半導体装置 |
Also Published As
Publication number | Publication date |
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EP3241238A1 (fr) | 2017-11-08 |
US20180019334A1 (en) | 2018-01-18 |
FR3031239A1 (fr) | 2016-07-01 |
FR3031239B1 (fr) | 2023-04-28 |
WO2016107870A1 (fr) | 2016-07-07 |
CN107408573A (zh) | 2017-11-28 |
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