JP2018195623A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 123
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 238000010438 heat treatment Methods 0.000 claims abstract description 88
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 26
- 239000012298 atmosphere Substances 0.000 claims abstract description 25
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000001301 oxygen Substances 0.000 claims abstract description 22
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 22
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 35
- 238000003949 trap density measurement Methods 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 230000005527 interface trap Effects 0.000 description 14
- 230000005684 electric field Effects 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000000758 substrate Substances 0.000 description 10
- 239000012299 nitrogen atmosphere Substances 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 238000011156 evaluation Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000003763 carbonization Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
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- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
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- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Abstract
Description
なお、図面は模式的または概念的なものであり、各部分の厚さと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
なお、本願明細書と各図において、既出の図に関して前述したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
図2は、実施形態に係る半導体装置を例示する模式的断面図である。
図1に示すように、実施形態に係る半導体装置の製造方法は、第1膜の準備(ステップS110)、第1熱処理(ステップS120)、及び、第2熱処理(ステップS130)を含む。
図3は、実施形態に係る半導体装置の製造方法を例示する模式図である。
図3の横軸は、時間tmである。縦軸は、温度Tである。
図4は、上記の方法により作製された試料110a(トランジスタ)における電圧−電流特性の測定結果を示す。図4の横軸は、ドレイン電圧VD(V)である。縦軸は、ドレイン電流ID(mA)である。図4には、ゲート電圧VGが、5V、15V、20V及び25Vの時の特性が例示されている。図4に示すように、良好な特性が得られている。
図5は、試料110aにおける移動度μの評価結果を示す。図5の横軸は、ゲートにおける電界強度EF(MV/cm)である。縦軸は、移動度μ(cm2/(V・s))である。図5には、第1参考例の試料119の特性も示されている。試料119においては、上記の第1熱処理が行われず、第2熱処理だけが行われる。
図6は、試料110aのしきい値の変化の評価結果を例示している。この評価においては、試料110aにおいて、半導体部材50と第1導電膜E1(ゲート電極)と、の間に、直流電界が印加される。直流電界の印加時間Tsの経過に対する、しきい値電圧の変化ΔVthが評価される。図6の横軸は、印加時間Ts(103sec(秒))である。縦軸は、しきい値電圧の変化ΔVth(V)である。この例では、直流電界が、+4MV/cm、または、−2MV/cmであるときの特性が示されている。直流電界の印加における温度が、175℃である。
図7は、上記の試料110aの二次イオン質量分析(SIMS:Secondary Ion Mass Spectrometry)による分析結果を示している。図7の横軸は、Z軸方向における位置pZ(深さ)である。縦軸は、窒素の濃度CN(×1021cm−3)である。図7から分かるように、試料110aにおいては、半導体部材50と第1膜10との間の界面近傍(界面15を含む領域)において、高い濃度CNの窒素が観測される。この例では、界面近傍における窒素の濃度CN(ピーク濃度)は、約2.4×1021cm−3である。このように、実施形態に係る製造方法により作製された試料110aにおいては、高い濃度CN(例えば、1×1020cm−3以上1×1022cm−3以下)の窒素が観測できる。
図8に示すように、第1膜10は、界面近傍領域10a及びバルク領域10bを含む。界面近傍領域10aは、バルク領域10bと半導体部材50との間に位置する。一方、半導体部材50は、界面近傍領域50a及びバルク領域50bを含む。界面近傍領域50aは、バルク領域50bと第1膜10との間に位置する。
図9(a)及び図9(b)の横軸は、キャパシタ素子に印加される電界EG(MV/cm)である。図9(a)の縦軸は、電流密度JG(A/cm2)である。複数の素子に関して、図9(a)に示す特性が評価され、その評価結果から、複数の素子のそれぞれにおける破壊電界が導出される。その結果が統計的に処理され、図9(b)の特性が得られる。図9(b)は、複数の素子についての、破壊電界の分布を示す。図9(b)の縦軸は、標準偏差NDである。
図10に示すように、半導体装置111は、第1導電形の第1半導体領域51、第2導電形の第2半導体領域52、第1導電形の第3半導体領域53、第2導電形の第4半導体領域54、第1膜10、第1導電膜E1、第2導電膜E2、第3導電膜E3、及び、絶縁膜I1を含む。半導体装置111は、トランジスタである。上記の半導体領域は、例えば、窒化珪素を含む。第2半導体領域52が、上記の半導体部材50に対応する。第1膜10は、例えば、ゲート絶縁膜に対応する。第1導電膜E1は、ゲート電極に対応する。第2導電膜E2は、例えば、ソース電極に対応する。第3導電膜E3は、例えば、ドレイン電極に対応する。この例では、基板55(SiC基板)が設けられている。
図10に示すように、半導体装置111は、第1導電形の第1半導体領域51、第2導電形の第2半導体領域52、第1導電形の第3半導体領域53、第2導電形の第4半導体領域54、第1膜10、第1導電膜E1、第2導電膜E2、第3導電膜E3、及び、絶縁膜I1を含む。半導体装置111は、トランジスタである。上記の半導体領域は、例えば、炭化珪素を含む。第2半導体領域52が、上記の半導体部材50に対応する。第1膜10は、例えば、ゲート絶縁膜に対応する。第1導電膜E1は、ゲート電極に対応する。第2導電膜E2は、例えば、ソース電極に対応する。第3導電膜E3は、例えば、ドレイン電極に対応する。この例では、基板55(SiC基板)が設けられている。
Claims (9)
- 炭化珪素を含む半導体部材の上に堆積され珪素及び酸素を含む第1膜を、酸素を含む第1雰囲気中で500℃以上900℃以下の第1温度の第1熱処理を実施することと、
前記第1熱処理の後に前記第1膜を窒素を含む第2雰囲気で1200℃以上1400℃未満の第2温度の第2熱処理を実施することと、
を備えた、半導体装置の製造方法。 - 前記第2熱処理の後において、前記第1膜に含まれる窒素の濃度は、1×1020cm−3以上1×1022cm−3以下である、請求項1記載の半導体装置の製造方法。
- 前記第1膜は、化学気相成長により形成された、請求項1または2に記載の半導体装置の製造方法。
- 前記第1膜を前記半導体部材の上に堆積することをさらに備えた、請求項1〜3のいずれか1つに記載の半導体装置の製造方法。
- 前記第2雰囲気は、酸素を含まない、または、
前記第2雰囲気に含まれる酸素の濃度は、3vol%以下である、請求項1〜4のいずれか1つに記載の半導体装置の製造方法。 - 前記第1雰囲気における酸素の濃度は、5vol%以上である、請求項1〜5のいずれか1つに記載の半導体装置の製造方法。
- 前記第1熱処理と前記第2熱処理との間において、前記第1膜の温度を前記第1温度よりも低い第3温度にすることをさらに備えた、請求項1〜6のいずれか1つに記載の半導体装置の製造方法。
- 前記第1熱処理の前における前記第1膜の厚さは、20nm以上60nm以下である、請求項1〜7のいずれか1つに記載の半導体装置の製造方法。
- 前記第2熱処理の後に、前記第1膜の上に導電膜を形成することをさらに備えた、請求項1〜8のいずれか1つに記載の半導体装置の製造方法。
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