JP2018182888A - Power supply system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply system capable of suppressing a drop in a supply voltage to a load even when a short circuit occurs.SOLUTION: A sub FETQs shuts down connection between a main battery Bm and a sub battery Bs connected in parallel to supply a power supply to a stabilized load Ls and executes power supply to the stabilized load Ls from only the sub battery Bs. A first comparator CP1 compares a voltage V1 of the main battery Bm to a reference voltage Vref and turns off the sub FETQs upon detection of a voltage drop in the main battery Bm.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power supply system.

  Conventionally, as a power supply system mentioned above, what mounts a main battery and a sub battery in vehicles, and supplies power to each of a main side load and a sub side load is proposed (patent documents 1). In the power supply system of Patent Document 1, a switch is provided between the main battery and the sub-battery, and the switch is normally turned off so that only the main battery is charged from the alternator. On the other hand, during regeneration, the switch is turned on to charge both the main battery and the sub-battery from the alternator.

JP, 2014-36458, A

  However, in the power supply system described above, when a short circuit to ground occurs near the main battery wiring, a voltage drop of the main battery occurs for about several hundred ms until the fuse is blown. At this time, when the switch is turned on, the voltage drop of the main battery is accompanied by the voltage drop of the sub-battery, and the voltage supplied to the sub-side load is also lowered.

  The present invention has been made in view of the above background, and an object of the present invention is to provide a power supply system capable of suppressing a drop in a supply voltage to a load even if a short circuit occurs.

  A power supply system according to a first aspect of the present invention disconnects between a first battery and a second battery connected in parallel for supplying power to a load, and allows the load to be supplied with power from only the second battery. A switch is compared with a voltage of the first battery and a reference voltage, and when a voltage drop of the first battery is detected, the switch is turned off to disconnect between the first battery and the second battery. And a first comparator.

A power supply system according to a second aspect includes a pair of semiconductor switches connected in series between the first battery and the second battery such that a forward direction of a parasitic diode is reverse.
The switch turned off by the first comparator is characterized in that only the semiconductor switch in which the forward direction of the parasitic diode in the pair of semiconductor switches is directed from the second battery to the first battery.

  In the power supply system according to the third aspect, in the time period from when the first comparator is turned off to when the switch is turned off, the voltage of the second battery is detected after the first comparator detects a voltage drop. Is shorter than the time it takes to drop to the lower limit voltage of the load.

  A power supply system according to a fourth aspect of the present invention compares a voltage of the first battery with a voltage of the second battery, and a value obtained by subtracting the voltage of the second battery from the voltage of the first battery is a predetermined value or less And a second comparator for turning off the switch when it becomes.

  As described above, according to the first aspect, the first comparator compares the voltage of the first battery with the reference voltage, and turns off the switch when the voltage drop of the first battery is detected. As a result, even if the first battery shorts and a voltage drop occurs, it can be detected quickly and the switch can be turned off, and even if a short occurs, a drop in the supply voltage to the load can be suppressed.

  According to the second aspect, the switch turned off by the first comparator is constituted only by the semiconductor switch in which the forward direction of the parasitic diode in the pair of semiconductor switches is directed from the second battery to the first battery. Accordingly, only one of the pair of semiconductor switches may be turned off by the first comparator, and the other may not be turned off by the first comparator.

  According to the third aspect, the switch is turned off before the second battery drops below the operation lower limit voltage of the load after the first comparator is turned off. It is possible to suppress a drop in the supply voltage to the motor.

  According to the fourth aspect, a drop in the supply voltage to the load can be suppressed.

It is a circuit diagram showing a power supply system of the present invention in a 1st embodiment. It is a time chart of output of a comparator, voltage V1 of a main battery, and voltage V2 supplied to a stabilization load. It is a graph which shows the relationship between the minimum value of the voltage supplied to a stabilization load, and interruption | blocking time. It is a time chart with the voltage of the main battery, the voltage supplied to the stabilization load, and the gate voltage of the sub FET. It is a circuit diagram showing the power supply system of the present invention in a 2nd embodiment.

First Embodiment
Hereinafter, a first embodiment of the present invention will be described based on FIG. The power supply system 1 of the present embodiment is provided in a vehicle equipped with two batteries of a main battery Bm as a first battery and a sub-battery Bs as a second battery connected in parallel to each other. A vehicle travels with an engine (internal combustion engine) as a drive source. At the time of start of the engine, the vehicle is given initial rotation to the engine by driving of the starter motor ST.

  The main battery Bm is configured of, for example, a lead battery. The main battery Bm is connected to the starter motor ST and the general load Lm, and supplies power to the starter motor ST and the general load Lm. The general load Lm is, for example, a load that is not controlled during automatic operation, such as a headlight or an air conditioner. Further, the main battery Bm is connected to the alternator ALT and charged by the alternator ALT.

  In addition, a protector FL such as a fusible link is provided at the plus terminal of the main battery Bm, and when the overcurrent continues to flow through the main battery Bm, the protector FL is cut off and the overcurrent can be shut off. The sub-battery Bs is configured of a lead battery or a lithium ion battery. The sub-battery Bs is connected to a regulated load Ls as a load, and the regulated load Ls is supplied with power. The stabilization load Ls is, for example, a load controlled at the time of automatic operation such as a power steering or an electric brake. The stabilized load Ls is a load for which stable power supply is required, and a stabilized operation lower limit voltage is defined.

  The power supply system 1 includes a main FET Qm and a sub FET Qs as a pair of semiconductor switches, a gate drive circuit 11, a first comparator CP1, and an NPN transistor Tr.

  The main FET Qm and the sub FET Qs are provided between the main battery Bm and the sub battery Bs, and turn on and off the connection between the main battery Bm and the sub battery Bs. The starter motor ST, the alternator ALT and the general load Lm described above are connected to the main battery Bm side further than the main FET Qm and the sub FET Qs. Further, the stabilized load Ls is connected to the sub-battery Bs side of the main FET Qm and the sub FET Qs.

  Thereby, when the main FET Qm and the sub FET Qs are turned off, the connection between the starter motor ST, the alternator ALT and the general load Lm and the sub battery Bs is turned off, and the connection between the stabilized load Ls and the main battery Bm is turned off. Be done.

  The main FET Qm and the sub FET Qs are N-channel type. The drain of the main FET Qm is connected to the main battery Bm side, the source is connected to the sub battery Bs side, and the forward direction of the parasitic diode Dm is directed from the sub battery Bs to the main battery Bm. The main FET Qm cuts off the current flowing from the main battery Bm to the sub battery Bs.

  The sub FET Qs has a drain connected to the sub battery Bs side and a source connected to the main battery Bm side, and a forward direction of the parasitic diode Ds is a direction from the main battery Bm to the sub battery Bs. The sub FET Qs cuts off the current flowing from the sub battery Bs to the main battery Bm.

  The gate drive circuit 11 supplies gate voltage to each of the main FET Qm and the sub FET Qs via the resistors Rm and Rs according to an instruction from an external control unit (not shown), for example, to turn on and off the main FET Qm and the sub FET Qs. Control circuit. Specifically, the control unit, for example, normally turns off the main FET Qm and the sub FET Qs, turns on the main FET Qm and the sub FET Qs during the regenerative operation, and instructs the alternator ALT to charge the sub battery Bs.

  When turning on the main FET Qm and the sub FET Qs, the gate drive circuit 11 applies a gate voltage of about 10 V as a source voltage (voltage of the main battery Bm) to the gates of the main FET Qm and the sub FET Qs. In addition, when turning off the main FET Qm and the sub FET Qs, the gate drive circuit 11 reduces the voltage to a voltage equal to or lower than the source voltage (the voltage of the main battery Bm) + the threshold voltage.

  The first comparator CP1 has an inverting input connected to the positive side of the main battery Bm (between the main battery Bm and the main FET Qm), and a non-inverting input connected to the reference voltage source 12. Thereby, the voltage V1 of the main battery Bm is input to the inverting input of the first comparator CP1, and the reference voltage Vref from the reference voltage source 12 is input to the non-inverting input. The reference voltage Vref is set to be equal to or higher than the stabilization operation lower limit voltage of the stabilization load Ls. The output of the first comparator CP1 is L level while the voltage V1 of the main battery Bm is higher than the reference voltage Vref, and the output is H level when the voltage V1 of the main battery Bm is lower than the reference voltage Vref.

  The output of the first comparator CP1 is connected to the base of the NPN transistor Tr. The emitter of the NPN transistor Tr is grounded, and the collector is connected between the gate of the sub FET Qs and the resistor Rs. Thus, while the output of the first comparator CP1 is at L level, the NPN transistor Tr is turned off, and the sub FET Qs is turned on / off by the gate drive circuit 11. On the other hand, when the output of the first comparator CP1 becomes H level, the NPN transistor Tr is turned on and the gate of the sub FET Qs is grounded, so the sub FET Qs is forcibly turned off regardless of the output of the gate drive circuit 11. .

  Next, the operation of the power supply system 1 configured as described above will be described with reference to the time chart of FIG. The gate drive circuit 11 turns on or off the main FET Qm and the sub FET Qs in accordance with a command from an external control unit.

  At normal times, the voltage V1 of the main battery Bm is almost never lower than the reference voltage Vref, and as shown in FIG. 2, the output of the first comparator CP1 becomes L level. As a result, the NPN transistor Tr is turned off, and the main FET Qm and the sub FET Qs are turned on and off according to the control of the gate drive circuit 11.

  Now, as shown in FIG. 1, it is assumed that a short circuit occurs in the wiring of the main battery Bm. At this time, as shown in FIG. 2, the voltage V1 of the main battery Bm drops sharply at the timing when the short circuit occurs, and becomes lower than the reference voltage Vref. The output of the first comparator CP1 switches from L to H at the timing when the voltage V1 of the main battery Bm becomes lower than or equal to the reference voltage Vref. As a result, the NPN transistor Tr is turned on, the gate of the sub FET Qs is grounded, and the sub FET Qs is forcibly turned off.

  That is, even if the sub FET Qs is on-controlled by the gate drive circuit 11, it is forcibly turned off. At this time, the main FET Qm is turned on and off according to the control of the gate drive circuit 11. Since the voltage of the sub battery Bs is higher than the voltage V1 of the main battery Bm while the wiring short occurs, no current flows from the sub battery Bs to the main battery Bm through the parasitic diode Ds of the sub FET Qs. . Therefore, even if the main FET Qm is on, if the sub FET Qs is off, it is possible to disconnect between the main battery Bm and the sub battery Bs. And since the voltage supplied to the stabilization load Ls is switched to the voltage of the sub battery Bs, there is no possibility that the operation of the stabilization load Ls will be stopped.

  Note that, as shown in FIG. 2, the sub FET Qs does not turn off immediately after the first comparator CP1 switches from L to H, and turns off after the cutoff time T has elapsed. This is because it takes time to pull out the charge accumulated in the gate capacitance. After the cutoff time T has elapsed and the sub FET Qs is turned off, the voltage supplied to the stabilized load Ls is stabilized.

In order to turn off the sub FET Qs instantaneously, the charge extraction speed may be increased, but for this purpose, the circuit becomes larger and the cost is increased, so it is desirable to set the minimum necessary cutoff time T. Here, there is an inductance component L in the wiring of the stabilized load Ls, and the voltage V2 supplied to the stabilized load Ls falls due to the inductance component L later than the voltage V1 of the main battery Bm. The voltage V2 supplied to the stabilized load Ls is expressed by the following equation (1).
V2 = V1-i x R + L x (di / dt) (1)

  Here, i is the current flowing to the stabilized load Ls, and R is the resistance of the load wiring. By considering the inductance component L, a delay of the cutoff time T is created. L × (di / dt) decreases transiently as time t elapses. That is, as shown in FIG. 2, when the voltage V1 of the main battery Bm drops, the voltage V2 supplied to the stabilized load Ls does not immediately drop to (V1-i × R) but falls slowly ( Approaches V1-i × R). Therefore, it is only necessary to turn off the sub FET Qs until the voltage V1 of the main battery Bm falls below the reference voltage Vref (= the stabilization operation lower limit voltage).

  Next, FIG. 3 shows the result of examining the cutoff time T required to keep the voltage V2 supplied to the stabilization load Ls of a certain vehicle at or above the reference voltage Vref (= the stabilization operation lower limit voltage). As shown in the figure, it is sufficient to keep a voltage of 10 V or more as the stabilization operation lower limit voltage, but it can be understood that the cutoff time T may be 10 μs.

  Next, FIG. 4 shows a time chart of the voltage V1 of the main battery Bm, the voltage V2 supplied to the stabilized load Ls, and the gate voltage of the sub FET Qs when the cutoff time T is 6 μs. As shown in the figure, the minimum value of the voltage V2 supplied to the stabilized load Ls could be suppressed to 11V. If the short circuit continues after the sub FET Qs is turned off, the protector FL is cut off and the overcurrent is cut off.

  According to the first embodiment described above, the first comparator CP1 compares the voltage V1 of the main battery Bm with the reference voltage Vref, and turns off the sub FET Qs when a voltage drop of the main battery Bm is detected. As a result, even if the main battery Bm shorts and a voltage drop occurs, it can be detected quickly to turn off the sub FET Qs, and even if a short occurs, the voltage V2 supplied to the stabilized load Ls decreases. It can be suppressed.

  Further, according to the first embodiment described above, the switch turned off by the first comparator CP1 is the sub FET Qs in which the forward direction of the parasitic diode Ds of the pair of main FET Qm and sub FET Qs is directed from the main battery Bm to the sub battery Bs. It consists only of Thus, only the sub FET Qs may be turned off by the first comparator CP1.

  Further, according to the first embodiment described above, the sub FET Qs detects the voltage drop of the first comparator CP1 after the first comparator CP1 detects a voltage drop during the cutoff time T from when the first comparator CP1 is turned off to when the main battery is turned off. What is shorter than the time until the voltage V1 of Bm falls to the stabilization operation lower limit voltage is used. As a result, after the first comparator CP1 is turned off, the sub FET Qs can be turned off before the sub battery Bs falls below the stabilization operation lower limit voltage, so that the stabilized load Ls can be further shortened even if a short circuit occurs. Can be suppressed from becoming lower than or equal to the stabilization operation lower limit voltage, and the stabilization load Ls is unlikely to be momentarily disconnected.

Second Embodiment
Next, a second embodiment of the present invention will be described based on FIG. In the power supply system 1 of the first embodiment shown in FIG. 1 described above, the pair of the main FET Qm and the sub FET Qs is provided between the main battery Bm and the sub battery Bs. Thereby, when the alternator ALT is in the power generation state (when the voltage V1 is higher than the electromotive force of the sub battery Bs), the main FET Qm is turned off to switch the voltage V1 supplied to the stabilized load Ls to the sub battery Bs. it can.

  However, for example, in an application where only the current from the alternator ALT is supplied to the stabilized load Ls, as shown in FIG. 5, the main FET Qm may be omitted and only the sub FET Qs may be provided. In the example of FIG. 5, the sub FET Qs is always on, and the sub FET Qs is turned off only when the voltage V1 of the main battery Bm is lower than the voltage V3 of the sub battery Bs.

  The voltage V1 drops below the voltage V3 when, for example, the consumption of the general load Lm temporarily increases and exceeds the power generation capacity of the alternator ALT. In this case, the sub FET Qs is turned off to switch the power supply to the stabilized load Ls to the sub battery Bs. As a result, it is possible to suppress a decrease in the voltage V2 supplied to the stabilized load Ls.

  In the example shown in FIG. 5, the control of the sub FET Qs described above is performed by the second comparator CP2. The second comparator CP2 has an inverting input connected to the positive side of the sub battery Bs (between the sub battery Bs and the stabilized load Ls), and a non-inverting input is the positive side of the main battery Bm (the main battery Bm and the sub FET Qs Connected). As a result, the voltage V3 of the sub battery Bs is input to the inverting input of the second comparator CP2, and the voltage V1 of the main battery Bm is supplied to the noninverting input. The output of the second comparator CP2 is H level while the voltage V1 of the main battery Bm is higher than the voltage V3 of the sub battery Bs, and the output is L level when the voltage V1 of the main battery Bm is lower than the voltage V2 of the sub battery Bs. Become.

  While the output of the second comparator CP2 is at the H level (V1> V3), the sub FET Qs is turned on. On the other hand, the sub FET Qs is turned off while the output of the second comparator CP2 is at L level (V1 <V3). That is, the second comparator CP2 turns off the sub FET Qs when the value obtained by subtracting the voltage V3 from the voltage V1 becomes 0 (= predetermined value) or less.

  A delay circuit 13 may be provided between the voltage V1 of the main battery Bm and the voltage V3 of the sub battery Bs and the input of the second comparator CP2. By delaying the input by the delay circuit 13, a filter is applied to the input, so it is possible to suppress the on / off control of the sub FET Qs frequently due to noise on the wiring.

  In the second embodiment described above, the sub FET Qs is turned off when V1 <V3. However, the present invention is not limited to this. For example, a negative offset voltage V1 is input to the non-inverting input of the second comparator CP2. Thus, the sub FET Qs is turned off when V1−offset voltage <V3. That is, the second comparator CP2 can turn off the sub FET Qs when the value obtained by subtracting the voltage V3 from the voltage V1 is equal to or less than the offset voltage (positive predetermined value). As a result, the sub FET Qs can be turned off in a state where the voltage V1 is higher than the voltage V3 but the flowing current approaches zero.

  Further, the voltage V1 plus offset is input to the non-inverting input of the second comparator CP2. Thus, the sub FET Qs is turned off when V1 + offset voltage <V3. That is, the second comparator CP2 can turn off the sub FET Qs when the value obtained by subtracting the voltage V3 from the voltage V1 is equal to or less than the negative offset voltage (negative predetermined value). As a result, the sub FET Qs can be turned off in a state where the voltage V1 is sufficiently lower than the voltage V3 and a certain amount of current flows reversely.

  According to the above-described second embodiment, the voltage V1 of the main battery Bm and the voltage V3 of the sub battery Bs are compared, and the sub FET Qs is turned off when the voltage of the main battery Bm falls below the voltage of the sub battery Bs. A second comparator CP2 is provided. As a result, it is possible to further suppress the decrease in the supply voltage to the stabilized load Ls.

  Further, in the first and second embodiments described above, no switch is provided between the sub-battery Bs and the stabilization load Ls, but a switch may be provided as in the prior art.

  The present invention is not limited to the above embodiment. That is, various modifications can be made without departing from the scope of the present invention.

Bm Main battery (first battery)
Bs sub battery (second battery)
CP1 1st comparator Ls stabilized load (load)
Qm Main FET (semiconductor switch)
Qs sub FET (switch, semiconductor switch)
Vref reference voltage

Claims (4)

A switch for disconnecting between a first battery and a second battery connected in parallel for supplying power to a load and for supplying power to the load from only the second battery;
A first comparator that compares the voltage of the first battery with a reference voltage and turns off the switch when a voltage drop of the first battery is detected, thereby disconnecting the first battery and the second battery And a power supply system characterized by comprising. A pair of semiconductor switches connected in series such that a forward direction of a parasitic diode is reversed between the first battery and the second battery;
The switch which is turned off by the first comparator is constituted by only the semiconductor switch in which the forward direction of the parasitic diode among the pair of semiconductor switches is directed from the second battery to the first battery. The power supply system according to Item 1.   In the switch, the voltage of the second battery drops to the operation lower limit voltage of the load after the first comparator detects a voltage drop for a time from when the first comparator is turned off to when the switch is turned off. The power supply system according to claim 1 or 2, wherein one shorter than the time until is used.   The voltage of the first battery is compared with the voltage of the second battery, and the switch is turned off when a value obtained by subtracting the voltage of the second battery from the voltage of the first battery becomes lower than a predetermined value. The power supply system according to any one of claims 1 to 3, further comprising a second comparator.

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