JP2018179578A - Circuit board, method for manufacturing circuit board, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a circuit board in which damage attributable to stresses occurring in a conductor pin connecting part is suppressed.SOLUTION: A probe card 1, which is a circuit board, includes, for example, a glass layer 52, a glass layer 51 provided thereon and having a resin part 51c, a conductor via 30 penetrating the resin part 51c, and a probe pin 40 that is a conductor pin provided on the conductor via 30 and on the resin part 51c. According to the probe card 1, when a terminal of a semiconductor element and the probe pin 40 are contacted under pressure when electrically inspecting the semiconductor element, stresses occurring in the root 41 of the probe pin 40 and its periphery are relieved by the resin part 51c and damage attributable to the stress is suppressed.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a circuit board, a method of manufacturing a circuit board, and an electronic apparatus.

  Circuit board (probe card, etc.) provided with conductor pins (also referred to as probe pins, contact pins, etc.) provided corresponding to the terminals of the semiconductor elements for electrical inspection of semiconductor elements such as LSI (Large Scale Integration) The technique using (also called) is known. The conductor pins provided on the circuit board connected to the measuring device are pressed into contact with the corresponding terminals of the wafer-state or singulated semiconductor element, and the electric inspection of the semiconductor element is performed.

Japanese Patent Application Laid-Open No. 8-201427 JP 2004-85281 A

  When a glass layer is used as a layer for forming a conductor via and a wire connected to the conductor pin of a circuit board used for electrical inspection of a semiconductor element, the wire is miniaturized from the viewpoint of the flatness and the fine processability And densification, thereby reducing the number of layers.

  However, if a conductor pin is provided directly on the glass layer, when the conductor pin is pressure-welded to the terminal of the semiconductor element, the stress generated at the connection portion between the conductor pin and the glass layer damages the glass layer. There is a possibility that the measurement by the conductor pin can not be performed accurately.

  According to one aspect, a first glass layer, a first layer provided on the first glass layer and having a resin portion, a conductor via penetrating the resin portion, the conductor via, and the resin portion There is provided a circuit board including conductor pins provided on the circuit board.

  Further, according to one aspect, there is provided an electronic device comprising the method for manufacturing a circuit board as described above, and the circuit board as described above and a measuring device connected thereto.

  A circuit board is realized in which damage due to stress generated at the connection portion of the conductor pin is suppressed. Also, an electronic device provided with such a circuit board is realized.

It is explanatory drawing of an electrical inspection. It is explanatory drawing of the probe card which used the glass layer. It is a figure showing an example of the probe card concerning a 1st embodiment. It is an explanatory view of a resin part concerning a 1st embodiment. It is explanatory drawing of the electrical inspection using the probe card which concerns on 1st Embodiment. It is a figure which shows a stress analysis model. It is a figure which shows a stress analysis result. It is a figure (the 1) which shows an example of the formation method of the probe card concerning a 1st embodiment. FIG. 7 is a second diagram showing an example of a method of forming a probe card according to the first embodiment; FIG. 13 is a third diagram showing an example of a method of forming a probe card according to the first embodiment. It is a figure showing the modification of the probe card concerning a 1st embodiment. It is a figure which shows the stress analysis result about the modification of a probe card. It is a figure which shows an example of the probe card which concerns on 2nd Embodiment. It is a figure showing an example of the probe card concerning a 3rd embodiment.

First, an example of electrical inspection of a semiconductor element using a probe card will be described.
FIG. 1 is an explanatory view of the electrical inspection. In FIG. 1, the probe card and the semiconductor element schematically show the cross section of the main part thereof.

  The semiconductor element 100 to be subjected to the electrical inspection is, for example, a semiconductor chip such as an LSI, and has a plurality of terminals 110 such as electrode pads on its surface 100 a. The semiconductor element 100 to be subjected to the electrical inspection may be the semiconductor element 100 in the wafer state before singulation, or may be the semiconductor element 100 after singulation.

An inspection apparatus 200a used for an electrical inspection of the semiconductor element 100 includes a probe card 300 and a measurement apparatus 400 connected thereto.
For example, a printed circuit board is used for the probe card 300. Probe card 300 has insulating layer 310, wiring 320 and conductor via 330 provided in insulating layer 310, probe pins 340 provided on one surface 310 a of insulating layer 310, and the other surface 310 b of insulating layer 310. It includes a provided measurement terminal 350. For the insulating layer 310, a resin material such as an epoxy resin is used. A metal material such as copper (Cu) is used for the wiring 320, the conductor via 330, the probe pin 340, and the measurement terminal 350. The probe pin 340 (the tip thereof) provided on the one surface 310 a side of the probe card 300 is provided at a position corresponding to the terminal 110 of the semiconductor element 100 to be subjected to the electrical inspection. The measuring device 400 is connected by a cable 410 to a measuring terminal 350 provided on the other surface 310 b side of the probe card 300.

  During the electrical inspection, the probe pins 340 of the probe card 300 are in contact with the terminals 110 of the semiconductor element 100. Then, a predetermined electrical signal is sent from the measuring device 400 to the probe card 300, and the electrical signal is input from the probe card 300 to the corresponding terminal 110 of the semiconductor element 100 through the wiring 320, the conductor via 330 and the probe pin 340. Be done. In response to the input, an electrical signal output from the terminal 110 of the semiconductor device 100 is sent to the probe card 300 through the corresponding probe pin 340, and further sent from the probe card 300 to the measuring device 400. It is measured. For example, based on the measurement result of the measuring apparatus 400, the pass / fail determination of the semiconductor element 100 is performed.

  In the electrical inspection of the semiconductor device 100 using the probe card 300, the pressure 500 is sufficient to simultaneously contact the plurality of probe pins 340 of the probe card 300 with the corresponding plurality of terminals 110 of the semiconductor device 100 with reduced contact resistance. It is put on. The electrical inspection is performed in a state where the probe pin 340 and the terminal 110 are in pressure contact as described above. The semiconductor element 100 may be provided with a large number of terminals 110 such as hundreds to thousands. When the terminals 110 and the probe pins 340 are in pressure contact with each other, such as several kg to several tens kg High pressure 500 may be applied.

  On the other hand, when the number of terminals 110 of the semiconductor element 100 to be subjected to the electrical inspection increases, the number of probe pins 340 of the probe card 300 provided correspondingly also increases. As a result, the number of layers of the insulating layer 310 for providing the conductor vias 330 and the wires 320 connected to the probe pins 340 also increases, and for example, the number of layers of the probe card 300 may be 50 to 60. An increase in the number of layers of the probe card 300 leads to an increase in the size thereof, and high accuracy is required for the formation of the wiring 320 and the conductor via 330 on the insulating layer 310 for each of the buildup formation and lamination processes. Therefore, in the formation of the probe card 300, the cost may increase and the yield may decrease.

As one of methods for reducing the number of probe card layers, a method using a glass substrate (glass substrate) as an insulating layer for providing a conductor via and a wiring connected to a probe pin can be considered.
FIG. 2 is an explanatory view of a probe card using a glass layer. FIG. 2A schematically shows a cross section of a main part of a probe card and a semiconductor element to which it is connected. In FIG. 2 (B), the X portion of FIG. 2 (A) is enlarged and schematically illustrated.

  In the probe card 300A shown in FIGS. 2A and 2B, the glass layer 310A is used as the insulating layer on which the wiring 320 and the conductor via 330, the probe pin 340, and the measurement terminal 350 are provided. As an example, FIG. 2B illustrates four stacked glass layers 311, glass layers 312, glass layers 313, and glass layers 314. The glass layers 311 to 314 are adhered by an adhesive layer 360 interposed between them.

Glass has high flatness and is easily microfabricated, and therefore, it is possible to achieve miniaturization and densification of the wiring and the conductor via as compared with the case where a resin is used for the insulating layer of the probe card.
For example, in the probe card 300A using the glass layer 310A as the insulating layer, the wiring 320 and the conductor via 330 can be miniaturized and densified by several times as compared with the probe card 300 of the printed board. By using the glass layer 310A as the insulating layer and miniaturizing and densifying the wiring 320 and the conductor via 330, it is possible to form the probe card 300A having a smaller number of layers. Furthermore, the probe pins 340 of the probe card 300A can be formed with high density corresponding to the fine-pitched terminals 110 provided on the semiconductor element 100.

  However, when the probe pin 340 is provided by directly contacting a part of the glass layer 310A of the probe card 300A on the glass layer 311 on the probe pin 340 side, the probe pin 340 and the terminal 110 of the semiconductor element 100 When the pressure 500 is applied for pressure contact, the glass layer 311 may be damaged.

  That is, the force applied to the probe pin 340 when pressed against the terminal 110 generates a stress, for example, a lateral (planar) stress at the root 341 of the probe pin 340 and its periphery. When such a stress is generated in the glass layer 311, damage 600 such as a crack may occur at the root 341 of the probe pin 340 or in the vicinity thereof. Damage 600 generated in the glass layer 311 may also spread from the glass layer 311 to the inner layer.

  When stress 600 causes damage 600 to glass layer 311, the support of probe pin 340 near the damage 600 is weakened and the force of pressure 500 is not sufficiently applied to probe pin 340, and contact with corresponding terminal 110 An increase in resistance or no contact with the corresponding terminal 110 may occur. An increase in the contact resistance between the probe pin 340 and the terminal 110 may lower the measurement accuracy of the semiconductor element 100 and thereby lower the accuracy of the pass / fail judgment of the semiconductor element 100.

In view of the above-described points, a configuration as shown below as an embodiment is adopted here to suppress damage due to stress of the probe card and a decrease in measurement accuracy and the like due to it.
First, the first embodiment will be described.

  FIG. 3 is a view showing an example of a probe card according to the first embodiment. FIG. 3 (A) schematically shows a main part plane of the example of the probe card as viewed from the probe pin side, and FIG. 3 (B) schematically shows a cross section of the main part of the example of the probe card. It shows. FIG. 3B is a schematic cross-sectional view taken along line L3-L3 in FIG.

The probe card 1 (circuit board) shown in FIGS. 3A and 3B includes an insulating layer 10, a wire 20, a conductor via 30, and a probe pin 40 (conductor pin).
In the probe card 1, a plurality of laminated glass layers 50 are used as the insulating layer 10. As an example, FIG. 3 (B) illustrates four laminated glass layers 51, 52, 53, and 54. The number of glass layers 50 included in the probe card 1 is not limited to four. For each glass layer 50, various glass materials such as quartz glass, borosilicate glass, soda glass, and alkali free glass are used.

  The wiring 20 is, as shown in FIG. 3B, all or a part of one or more layers of the glass layer 50 group (glass layers 51 to 54 in this example) included in the insulating layer 10 Provided in For example, on the one surface 50b of the predetermined glass layer 50, the wiring 20 having a predetermined pattern shape is provided. For the wiring 20, various conductor materials, for example, metal materials such as Cu are used. In addition, for the wiring 20, a conductor material such as an alloy material containing a plurality of metals or a conductive paste containing a conductive filler in a resin may be used. The glass layer 50 on which the wiring 20 is provided is bonded to the other glass layer 50 laminated thereon or below by the interposed adhesive layer 60. For the adhesive layer 60, various adhesive materials such as resin are used.

  As shown in FIG. 3 (B), the conductor via 30 is a surface of the glass layer 51 which is the glass layer 50 of the outermost layer on the probe pin 40 side from each wire 20 of the glass layer 50 group bonded by the adhesive layer 60. It is provided to extend to 51a. Each conductor via 30 penetrates the glass layer 50 or the glass layer 50 and the adhesive layer 60 from the wiring 20 to which it is connected to the surface 51 a. For the conductor vias 30, various conductor materials, for example, metal materials such as Cu are used. Besides, for the conductor via 30, a conductor material such as an alloy material containing a plurality of metals or a conductive paste containing a conductive filler in a resin may be used.

  As shown in FIGS. 3A and 3B, the probe pins 40 protrude outward of the glass layer 51 on the surface 51a of the glass layer 51 in correspondence with the conductor vias 30 connected to the respective wires 20. To be provided. For the probe pin 40, for example, various metal materials such as Cu are used.

  As shown in FIGS. 3A and 3B, the outermost glass layer 51 on the probe pin 40 side is the other glass layer 50 side of the inner layer from the surface 51a at the portion where the probe pin 40 is provided. And a recessed portion 51b. The recess 51 b is larger in size than the probe pin 40 in plan view, and has an opening size (opening size on the surface 51 a) larger than the external size of the base 41 of the probe pin 40. The resin portion 51c is provided in the recess 51b. The conductor via 30 connected to the wiring 20 penetrates the resin portion 51 c and reaches the surface 51 a of the glass layer 51. The probe pins 40 protruding from the surface 51a are provided on the conductor via 30 penetrating the resin portion 51c in the recess 51b and on the resin portion 51c around the conductor via 30, and the conductor via 30 and the resin portion 51c around it Supported by

  The planar shape of the concave portion 51b shown in FIG. 3A is an example, and various planar shapes such as a substantially circular shape, a rectangular shape, a substantially rectangular shape, etc. may be adopted without being limited to the circular shape as illustrated. Moreover, the cross-sectional shape of the recessed part 51b shown to FIG. 3 (B) is also an example, Comprising: Not only circular shape like an illustration but various cross-sectional shapes may be employ | adopted. The shape of the recess 51b will be further described later.

FIG. 4 is an explanatory view of a resin portion according to the first embodiment. FIGS. 4A and 4B schematically show cross sections of the resin part and the peripheral part thereof.
For example, as shown in FIG. 4A, a resin material 51ca is used for the resin portion 51c provided in the recess 51b. For the resin material 51ca, various resin materials such as epoxy resin, polyimide resin, silicone resin and the like are used.

  Further, as shown in FIG. 4B, for example, as the resin portion 51c, various resin materials 51ca may be used in which an insulating or conductive filler 51cb is contained. Examples of the filler 51cb contained in the resin material 51ca include particulate fillers such as ceramic particles and metal particles, and fibrous fillers such as glass fibers, carbon fibers and ceramic fibers.

  The resin portion 51c is made of a material whose elastic modulus is lower than the elastic modulus of the glass used for the glass layer 51 and the elastic modulus of the probe pin 40 provided on the resin portion 51c. For example, for the resin portion 51c, a material whose elastic modulus is equal to or less than 1/10 of the elastic modulus of the probe pin 40 is used. The resin portion 51c can adjust the filling property into the concave portion 51b and the elastic modulus according to the type and the composition of the resin material to be used, and the type and the content thereof when the filler is contained.

The probe card 1 having the above configuration is used to conduct an electrical inspection of the semiconductor element.
FIG. 5 is an explanatory view of an electrical test using the probe card according to the first embodiment. FIG. 5A schematically shows a cross section of the main part of the probe card and the semiconductor element to which it is connected, and also schematically shows the measuring device connected to the probe card 1. In FIG. 5 (B), the Y part of FIG. 5 (A) is enlarged and schematically illustrated.

  The semiconductor element 100 to be subjected to the electrical inspection is, for example, a semiconductor chip such as an LSI, and has a plurality of terminals 110 such as electrode pads on its surface 100 a. The semiconductor element 100 to be subjected to the electrical inspection may be the semiconductor element 100 in the wafer state before singulation, or may be the semiconductor element 100 after singulation.

The inspection apparatus 200 used for the electrical inspection of the semiconductor device 100 includes the probe card 1 as described above and the measurement apparatus 400 connected thereto.
At the time of the electrical inspection, the probe card 1 is disposed with the side of the glass layer 51 provided with the probe pin 40 facing the side of the surface 100 a provided with the terminal 110 of the semiconductor element 100. Then, a predetermined pressure 500 is applied, and the probe pins 40 of the probe card 1 and the terminals 110 of the corresponding semiconductor element 100 are pressure-welded. Thus, the probe card 1 and the semiconductor element 100 are electrically connected to each other through the probe pins 40 (as well as the wires 20 and the conductor vias 30 connected to them) and the terminals 110. A predetermined electrical signal is input to the semiconductor element 100 through the probe card 1 from the measuring device 400 connected to the measurement terminal 15 of the probe card 1 by the cable 410, and the input is received and output from the semiconductor element 100 to the probe card 1 The electrical signal to be measured is measured by the measuring device 400. Thus, the electrical inspection of the semiconductor element 100 is performed.

  In the probe card 1, the end of the root 41 of the probe pin 40 connected to the conductor via 30 connected to the wire 20 in the inner layer is located on the lower elastic modulus resin portion 51 c provided on the glass layer 51. Therefore, when the probe pin 40 of the probe card 1 is brought into pressure contact with the terminal 110 of the semiconductor element 100 by the pressure 500, the stress generated at the base 41 of the probe pin 40 and its periphery is relaxed by the resin portion 51c. .

Here, the result of analyzing the stress generated at the root 41 of the probe pin 40 and the periphery thereof will be described.
FIG. 6 is a view showing a stress analysis model. 6 (A) and 6 (B) schematically show the cross section of the main part of the probe card in a perspective view.

  FIG. 6A shows, for comparison, a model corresponding to the probe card 300A as shown in FIG. 2B, in which the resin portion is not provided in the glass layer provided with the probe pins. FIG. 6 (B) shows a model corresponding to the probe card 1 as shown in FIG. 3 (A) and FIG. 3 (B) in which the resin part is provided in the glass layer provided with the probe pins.

  The model 70 shown in FIG. 6A, which corresponds to the probe card 300A, includes the glass layer 311 and the glass layer 312, the adhesive layer 360, the conductor via 330 penetrating these, and the probe pins provided on the conductor via 330. Including 340. In this model 70, the end of the root 341 of the probe pin 340 is located on the surface 311 a of the glass layer 311 and in contact with the glass layer 311.

  The model 71 shown in FIG. 6B, which corresponds to the probe card 1, includes the glass layer 51 and the glass layer 52, the adhesive layer 60, the resin portion 51c provided on the glass layer 51, and the conductor via 30 penetrating them. And probe pins 40 provided on the conductor vias 30 and the resin portion 51c. In this model 71, the end of the root 41 of the probe pin 40 is located on the resin portion 51c exposed to the surface 51a of the glass layer 51 and in contact with the resin portion 51c.

FIG. 7 is a view showing a stress analysis result.
FIG. 7A shows a stress analysis result of the glass layer 311 provided with the probe pin 340 when a constant pressure is applied to the model 70 shown in FIG. 6A. FIG. 7B shows the stress analysis result of the glass layer 51 provided with the probe pin 40 when a constant pressure is applied to the model 71 shown in FIG. 6B.

  As shown in FIG. 7A, when the end of the root 341 of the probe pin 340 is in contact with the glass layer 311 as in the model 70 (FIG. 6A), as shown in FIG. A large stress is generated at the root P1 of the base 341 and the portion P corresponding to the periphery thereof. In particular, stress is concentrated at the root 341 of the probe pin 340.

  On the other hand, as shown in FIG. 7B, when the end of the root 41 of the probe pin 40 is in contact with the resin portion 51c provided on the glass layer 51 as in the model 71 (FIG. 6B). The stress generated at the base 41 of the probe pin 40 and the portion Q corresponding to the periphery thereof is relaxed.

  Thus, the probe pin 40 is connected by providing the resin portion 51c on the glass layer 51 on which the probe pin 40 is provided and positioning the end of the base 41 of the probe pin 40 on the resin portion 51c. The stress generated in the glass layer 51 can be relaxed. This makes it possible to suppress damage such as a crack or the like generated in the glass layer 51 (damage 600 as shown in FIG. 2B).

  In the probe card 1, the resin portion 51 c relieves the stress at the time of pressure contact between the probe pin 40 and the terminal 110 (FIG. 5) in this manner, thereby suppressing damage such as cracks. And the increase in the contact resistance with the terminal 110 is suppressed. As a result, the performance of the semiconductor element 100 can be measured with high accuracy, and the pass / fail judgment of the semiconductor element 100 by electrical inspection can be performed with high accuracy.

Then, an example of the formation method of the above probe cards 1 is demonstrated.
8 to 10 illustrate an example of a method of forming a probe card according to the first embodiment. 8A to 8C, 9A to 9C, and 10A to 10C, respectively, the cross section of the main part of each process of forming a probe card. It has illustrated typically.

  In the formation of the probe card 1, for example, a multilayer glass substrate 1a as shown in FIG. 8A is first prepared. Here, as an example, a multilayer glass substrate 1a including four glass layers 50 (glass layers 51 to 54) is illustrated. The number of layers of the glass layer 50 group included in the multilayer glass substrate 1a (and the probe card 1 formed from the multilayer glass substrate 1a) is not limited to four.

  The multilayer glass substrate 1a includes a laminate 1b in which a glass layer 50 group (glass layers 52 to 54 in this example) excluding the glass layer 51 which is the outermost layer is bonded by an interposed adhesive layer 60. Wirings 20 having a predetermined pattern shape are provided in predetermined glass layers 50 in the laminate 1 b (in this example, the wirings 20 provided on the glass layers 52 and 53 are shown). In the wiring 20 positioned in the inner layer of the laminate 1 b, the glass layer 50 or the conductor via 30 provided so as to penetrate the glass layer 50 and the adhesive layer 60 (the conductor via 30 shown in FIG. Part of) is connected. The outermost glass layer 51 provided with the wiring 20 having a predetermined pattern shape is adhered by the adhesive layer 60 on the laminate 1 b provided with such a conductor via 30, as shown in FIG. 8A. The multilayer glass substrate 1a is as shown.

  In addition, various glass materials are used for the glass layer 50, for example, the thickness shall be about 100 micrometers. For the adhesive layer 60, various adhesive materials are used, and the thickness thereof is, for example, about 10 μm. Various conductor materials are used for the wires 20 and the conductor vias 30.

  After the preparation of the multilayer glass substrate 1a as described above, as shown in FIG. 8B, a resist is applied to the surface (the surface 51a of the glass layer 51 and the surface 50b of the glass layer 54) of the prepared multilayer glass substrate 1a. Two are formed. For example, a dry film resist is formed as the resist 2.

  After the formation of the resist 2, as shown in FIG. 8C, the formed resist 2 is exposed and developed, and the opening 2a is formed in the area of the glass layer 51 where the below-described recess 51b is formed. It is formed.

  After formation of the opening 2a of the resist 2, as shown in FIG. 9A, using the resist 2 in which the opening 2a is formed as a mask, the portion of the glass layer 51 exposed from the opening 2a has glass solubility It is removed by wet etching using an etching solution of As a glass-soluble etching solution, for example, an etching solution containing hydrofluoric acid is used. Thus, the recess 51 b is formed in the glass layer 51. For example, in the glass layer 51, a recess 51b having a diameter of about 150 μm is formed in the opening size on the surface 51a. Further, as an example, the glass layer 51 is formed with a recess 51 b having a depth that does not penetrate it.

After wet etching, as shown in FIG. 9B, the resist 2 used for the mask is removed by peeling or the like.
Here, although the example which forms the recessed part 51b by the wet etching which set the resist 2 as a mask was shown, the laser processing using a carbon dioxide gas laser and an ultraviolet (Ultra Violet; UV) laser, or the recessed part 51b is formed by sandblasting processing. You may

  After formation of the recess 51b by wet etching or the like, as shown in FIG. 9C, the recess 51b is filled with a predetermined resin material having a lower elastic modulus than the glass layer 51 and a probe pin 40 described later. . For example, a thermosetting, thermoplastic or ultraviolet curable resin material, or such a resin material containing a filler is filled in the recess 51 b. The resin material is, for example, filled in the recess 51b by screen printing, and after filling, the resin material is cured by a method according to the resin material. A predetermined resin material is filled in the concave portion 51b and hardened, whereby the resin portion 51c exposed to the surface 51a is formed in the glass layer 51.

  After forming the resin portion 51c, as shown in FIG. 10A, the resin portion 51c and the glass layer 51 provided with the resin portion 51c are penetrated and connected to the hole 3 (via hole) communicating with the wiring 20 or the wiring 20 in the inner layer. The holes 3 (via holes) leading to the conductor vias 30 are formed. The holes 3 are formed in the region inside the outer edge of the resin portion 51c. The holes 3 are formed by laser processing using a carbon dioxide gas laser or the like, and the opening size thereof is, for example, about 80 μm in diameter.

  After the holes 3 are formed, as shown in FIG. 10B, a predetermined conductor material is formed in the holes 3. For example, a metal material such as Cu is formed in the hole 3 by plating. Alternatively, the conductive paste is filled in the holes 3 by screen printing, and after filling, the resin material contained in the conductive paste is cured. By forming a predetermined conductor material in the holes 3, conductor vias 30 which are connected to the respective wirings 20 in the multilayer glass substrate 1 a and extend to the surface 51 a of the glass layer 51 are formed.

  After the formation of the conductor vias 30, as shown in FIG. 10C, the probe pins 40 are formed on the conductor vias 30 and the resin portion 51c. As an example, first, pad portion 40a is formed on the inner side of the outer edge of resin portion 51c so as to cover conductor via 30 penetrating resin portion 51c, and then pin portion 40b is formed on pad portion 40a Be done. For example, a metal material such as Cu is formed on the conductor via 30 and the resin portion 51c by plating to form the pad 40a, and a metal material such as Cu on the pad 40a by plating. Thus, the pin portion 40 b is formed. The pad portion 40a is formed, for example, in a size of about 100 μm in diameter, and the pin portion 40b is formed, for example, in a size of about 50 μm in diameter and about 50 μm in length. The pad portion 40a is formed on the resin portion 51c and the conductor via 30, and the pin portion 40b is formed on the pad portion 40a, whereby the probe pin 40 having the pad portion 40a and the pin portion 40b thereon is formed. Be done.

  By the steps as described above, the probe card 1 in which the probe pins 40 are provided on the conductor vias 30 and the resin portion 51 c of the glass layer 51 is formed. By positioning the end of the root 41 of the probe pin 40 on the resin portion 51 c, the stress when the probe pin 40 is in pressure contact with the semiconductor element to be subjected to the electrical inspection is relieved by the resin portion 51 c. The probe card 1 in which the damage is suppressed is realized.

  The shape of the resin portion 51c provided in the glass layer 51 of the probe card 1 (and the recess 51b provided with the same) is not limited to the above example. The resin portion 51c can also be shaped, for example, as shown in FIG.

  FIG. 11 is a view showing a modification of the probe card according to the first embodiment. FIGS. 11A to 11D schematically show the cross section of the main part of the probe card in a perspective view.

  Here, the glass layer 51 and the glass layer 52, the adhesive layer 60, the resin portion 51c provided in the glass layer 51, the conductor via 30 penetrating these, and the probe pins provided on the conductor via 30 and the resin portion 51c. The lower part of 40 is illustrated.

  As shown in FIG. 11A, the resin portion 51c can have a shape in which the external size decreases in a tapered manner from the surface 51a of the glass layer 51 to the inside. As shown in FIG. 11B, resin portion 51c is also shaped so as to be curved in a wave shape to reduce the external size from surface 51a of glass layer 51 to the inside, and is made of glass layer 51 with conductor via 30. It can be made into the shape which restrained the angle formed in a contact site. The resin portion 51c can also be shaped so as to penetrate the glass layer 51 in a cylindrical shape from the surface 51a of the glass layer 51, as shown in FIG. 11C. Also, as shown in FIG. 11D, the resin portion 51c can be shaped such that the outer size is reduced in a tapered manner from the surface 51a of the glass layer 51 to penetrate the glass layer 51.

  When forming the probe card 1 having the resin portion 51c shaped as shown in FIGS. 11A to 11D, the concave portion 51b shaped corresponding to each resin portion 51c to be formed in the glass layer 51. (Corresponding to the steps of FIG. 8C, FIG. 9A and FIG. 9B). The resin portion 51c is formed by filling and curing the resin material in the formed recess 51b (corresponding to the process of FIG. 9C), and the conductor via 30 penetrating it is formed (FIG. 10A and 10 (B)), the probe pin 40 is formed on the conductor via 30 and the resin portion 51c (corresponding to the process of FIG. 10 (C)).

FIG. 12 is a view showing a stress analysis result of a modified example of the probe card.
In FIG. 12A, the stress of the glass layer 51 provided with the probe pins 40 when a constant pressure is applied to the probe card 1 having the resin portion 51c as shown in FIG. 11A. The analysis results are shown. In FIG. 12B, the stress of the glass layer 51 provided with the probe pins 40 when a certain pressure is applied to the probe card 1 having the resin portion 51c as shown in FIG. 11B. The analysis results are shown. In FIG. 12C, the stress of the glass layer 51 provided with the probe pins 40 when a certain pressure is applied to the probe card 1 having the resin portion 51c as shown in FIG. 11C. The analysis results are shown. In FIG. 12 (D), when a constant pressure is applied to the probe card 1 having the resin portion 51 c as shown in FIG. 11 (D), the stress of the glass layer 51 provided with the probe pin 40 The analysis results are shown.

  In the case of the probe card 1 having the resin portion 51c as shown in FIG. 11 (A), as shown in FIG. 12 (A) as compared with the case where the probe pins are in contact with the glass layer (FIG. 7 (A)) The stress generated at the base 41 of the probe pin 40 and the portion Q1 corresponding to the periphery thereof is relaxed. Similarly, in the probe card 1 having the resin portion 51c as shown in FIGS. 11 (B) to 11 (D), as shown in FIGS. 12 (B) to 12 (D), respectively, The stress generated at the root 41 and the portions Q2 to Q4 corresponding to the periphery thereof is relaxed. By forming the glass layer 51 so as to suppress the formation of a corner at the contact portion with the conductor via 30, generation and concentration of stress can be suppressed more effectively.

  As described above, the glass layer 51 on which the probe pins 40 of the probe card 1 are provided can be provided with the recess 51 b and the resin portion 51 c of various shapes. Further, based on the pressure 500 applied during the electrical inspection of the semiconductor element 100 as described above, the shapes of the recess 51b and the resin portion 51c are selected to adjust the stress generated in the glass layer 51 on which the probe pin 40 is provided and the distribution thereof. You can also

Next, a second embodiment will be described.
FIG. 13 is a view showing an example of a probe card according to the second embodiment. FIG. 13 schematically illustrates the cross section of an example of the probe card.

  The probe card 1A (circuit board) shown in FIG. 13 is different from the probe card 1 described in the first embodiment in that it has a configuration in which a resin portion 51c is provided on the surface layer of the glass layer 51. A conductor via 30 connected to the wiring 20 in the inner layer is provided to penetrate the resin portion 51c provided on the surface layer of the glass layer 51, and the probe pin 40 is provided on the conductor via 30 and the resin portion 51c around it. Provided.

  As described above, as the resin portion 51c provided on the surface layer of the glass layer 51, various resin materials such as an epoxy resin, or those containing a predetermined filler in various resin materials are used. The resin portion 51 c is made of a material whose elastic modulus is lower than that of the glass layer 50 and the probe pin 40.

  In the probe card 1A as shown in FIG. 13, since the resin portion 51c is provided on the surface layer of the glass layer 51, the formation of the recess 51b by etching or the like on the glass layer 51 as described in the first embodiment. Can be omitted. Therefore, it becomes possible to realize probe card 1A simply and at low cost.

  In the probe card 1A, the end of the root 41 of the probe pin 40 connected to the conductor via 30 is located on the lower elastic modulus resin portion 51c provided on the surface layer of the glass layer 51. Therefore, when the probe pins 40 of the probe card 1A are in pressure contact with the terminals of the semiconductor element during the electrical inspection, the stress generated at the base 41 of the probe pins 40 and the periphery thereof is relaxed by the resin portion 51c. As a result, damage such as a crack generated in the glass layer 51, thereby weakening the support of the probe pin 40, and increase in contact resistance with the terminals of the semiconductor element are suppressed, and measurement accuracy of the semiconductor element and accuracy of pass / fail judgment are improved. Is taken.

Next, a third embodiment will be described.
FIG. 14 is a view showing an example of a probe card according to the third embodiment. FIG. 14 schematically illustrates the cross section of an example of the probe card.

  The probe card 1B (circuit board) shown in FIG. 14 is described in the first embodiment in that the layer provided with the probe pins 40 stacked on the glass layer 52 is the resin portion 51c. This is different from the probe card 1 described above. A conductor via 30 connected to the wiring 20 in the inner layer is provided to penetrate the resin portion 51c laminated on the glass layer 52, and a probe pin 40 is provided on the conductor via 30 and the resin portion 51c around it. Be

  Similarly to the above, as the resin portion 51c to be laminated on the glass layer 52, one in which various resin materials such as epoxy resin, or various resin materials contain a predetermined filler is used. The resin portion 51 c is made of a material whose elastic modulus is lower than that of the glass layer 50 and the probe pin 40.

  In the probe card 1B as shown in FIG. 14, since the resin portion 51c is laminated on the glass layer 52, the outermost glass layer 51 as described in the first embodiment is omitted, It is possible to omit the formation of the recess 51 b by etching or the like. Therefore, it becomes possible to realize probe card 1B simply and at low cost.

  In the probe card 1B, the end of the root 41 of the probe pin 40 connected to the conductor via 30 is located on the lower elastic modulus resin portion 51c laminated on the glass layer 52. Therefore, when the probe pin 40 of the probe card 1B is in pressure contact with the terminal of the semiconductor element during the electrical inspection, the stress generated at the base 41 of the probe pin 40 and the periphery thereof is relaxed by the resin portion 51c. As a result, damage such as a crack, weakening of the support of the probe pin 40 due to it, and increase in contact resistance with the terminals of the semiconductor element are suppressed, and measurement accuracy of the semiconductor element and accuracy of pass / fail judgment can be improved.

1, 1A, 1B, 300, 300A probe card 1a multilayer glass substrate 1b laminate 2 resist 2a opening 3 hole 10, 310 insulating layer 15, 350 measurement terminal 20, 320 wiring 30, 330 conductor via 40, 340 probe pin 40a Pad portion 40b Pin portion 41, 341 Root 50, 51, 52, 53, 54, 310A, 311, 312, 313, 314 Glass layer 50b, 51a, 100a, 310a, 310b, 311a Surface 51b Recess 51c Resin portion 51ca Resin Material 51cb Filler 60, 360 Adhesive layer 70, 71 Model 100 Semiconductor device 110 terminal 200, 200a Inspection device 400 Measuring device 410 Cable 500 Pressure 600 Damage P, Q, Q1, Q2, Q3, Q4 part

Claims (8)

A first glass layer,
A first layer provided on the first glass layer and having a resin portion;
Conductor vias penetrating through the resin portion;
A circuit board comprising: conductor pins provided on the conductor vias and the resin portion.   The circuit board according to claim 1, wherein the first layer has a second glass layer and a recess provided in the second glass layer, and the resin portion is in the recess.   The circuit board according to claim 1, wherein the resin portion is thinner than the thickness of the first layer.   The circuit board according to claim 1, wherein the resin portion penetrates the first layer.   The said resin part contains a filler, The circuit board in any one of the Claims 1 thru | or 4 characterized by the above-mentioned. Forming a first layer having a resin portion on the first glass layer;
Forming conductor vias through the resin portion;
Forming a conductor pin on the conductor via and the resin portion. In the step of forming the first layer,
Forming a second glass layer on the first glass layer;
Forming a recess in the second glass layer;
Forming the resin portion in the recess, and manufacturing the circuit board according to claim 6. Circuit board,
A measuring device connected to the circuit board, inputting a first signal to the circuit board, and measuring a second signal output from the circuit board;
The circuit board is
A first glass layer,
A first layer provided on the first glass layer and having a resin portion;
Conductor vias penetrating through the resin portion;
An electronic device comprising: conductor pins provided on the conductor via and the resin portion.

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