JP2018110530A - On-time setting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce output ripples of a switching power supply device.SOLUTION: An ON time setting method is a method of setting ON time Ton for a switching power supply device of an ON time fixed type, which generates an output voltage from an input voltage by driving a coil by turning on/off an output transistor and a synchronous rectification transistor. For example, by comparing a first voltage VX of a ramp waveform which increases for the ON time Ton with a second voltage VY which is reduced as a load is lighter in a current discontinuous mode and finishing the ON time Ton, the ON time Ton is shortened as the load is lighter in the current discontinuous mode. Also, for example, by comparing the first voltage VX with a second voltage VY which is reduced transiently when the current discontinuous mode has been switched to a current continuous mode and finishing ON time Ton, the ON time Ton is transiently shortened when the current discontinuous mode has been switched to the current continuous mode.SELECTED DRAWING: Figure 12

Description

  The present invention relates to an on-time setting circuit, and a power supply control IC and a switching power supply using the same.

  Switching power supply devices of non-linear control method (for example, fixed on time method, fixed off time method, or hysteresis window method) are switching power supply devices of linear control method (for example, voltage mode control method and current mode control method). In comparison, it has a feature that a high load response characteristic can be obtained with a simple circuit configuration.

  In addition, some switching power supply devices have a function (so-called reverse current blocking function) that detects a reverse current of a coil current and forcibly turns off a synchronous rectification transistor at a light load.

  As an example of the related art related to the above, Patent Document 1 can be cited.

U.S. Pat. No. 8,476,887

  However, in the conventional switching power supply device, when a multilayer ceramic capacitor having a small ESR [equivalent series resistance] is used as the output smoothing capacitor, the output ripple in the current discontinuous mode (= light load state in which a reverse current of the coil current occurs). There was a problem of increasing.

  In addition, in the conventional switching power supply device, since there is no hysteresis in the threshold of the load current at which switching between the continuous current mode (= heavy load state in which no reverse current of the coil current occurs) and the discontinuous current mode occurs, The switching between the two modes becomes unstable, and there is a problem in that the output ripple increases due to the switching between the two modes.

  In view of the above-mentioned problems found by the inventors of the present application, the present invention provides an on-time setting circuit capable of reducing output ripple, and a power supply control IC and a switching power supply device using the on-time setting circuit. Objective.

  An on-time setting circuit disclosed in the present specification is a switching power supply of a fixed on-time system that generates a desired output voltage from an input voltage by driving a coil by turning on / off an output transistor and a synchronous rectification transistor. In the current discontinuous mode, the on-time is shortened as the load is light (first configuration).

  The on-time setting circuit having the first configuration includes a first voltage generator that generates a first voltage having a ramp waveform that rises over the on-time, and a second voltage that generates a predetermined second voltage. And a comparator that compares the first voltage with the second voltage to end the on-time, and the second voltage generator is configured to reduce the load in the current discontinuous mode as the load is lighter. It is preferable to adopt a configuration (second configuration) for lowering two voltages.

  In the on-time setting circuit having the second configuration, the second voltage generation unit integrates a switch voltage appearing at a connection node between the output transistor and the synchronous rectification transistor or a divided voltage thereof to integrate the second voltage generation unit. An RC filter that generates two voltages, a current path breaker that cuts off a current path from the switch voltage input terminal to the ground terminal when switching is stopped, and the second voltage by capacitively dividing the output voltage when switching is resumed And a pull-up unit that instantaneously pulls up to a predetermined initial value (third configuration).

  In the on-time setting circuit having the third configuration, the pull-up unit may have a configuration (fourth configuration) designed so that the initial value decreases as the load is lighter.

  In the on-time setting circuit having the fourth configuration, the pull-up unit has an initial value that is higher than an integral value obtained by the RC filter in a load region immediately before switching from the current discontinuous mode to the current continuous mode. A configuration designed to be high (fifth configuration) is preferable.

  In the on-time setting circuit having any one of the second to fifth configurations, the second voltage generator transiently lowers the second voltage when the current discontinuous mode is switched to the current continuous mode. A configuration including a pull-down unit (sixth configuration) is preferable.

  Also, the on-time setting circuit disclosed in this specification is a fixed on-time method that generates a desired output voltage from an input voltage by driving a coil by turning on / off an output transistor and a synchronous rectification transistor. It is provided in the switching power supply device, and has a configuration (seventh configuration) in which the on-time is transiently shortened when switching from the current discontinuous mode to the current continuous mode.

  The on-time setting circuit having the seventh configuration includes a first voltage generation unit that generates a first voltage having a ramp waveform that rises over the on-time, and a second voltage that generates a predetermined second voltage. And a comparator that compares the first voltage with the second voltage to end the on-time, and the second voltage generator switches from the current discontinuous mode to the current continuous mode. It is preferable to adopt a configuration (eighth configuration) in which the second voltage is transiently reduced at the time.

  The power supply control IC disclosed in the present specification includes a ripple injection circuit that generates a feedback voltage by superimposing a ripple voltage simulating a coil current on the output voltage or a divided voltage thereof, and a predetermined reference voltage. A reference voltage generation circuit that generates a comparison signal, a main comparator that generates a comparison signal by comparing the feedback voltage and the reference voltage, and a one-shot pulse generation circuit that generates a one-shot pulse as a set signal in accordance with the comparison signal An RS flip-flop that sets the output signal to a first logic level in response to the set signal, and resets the output signal to a second logic level in response to a reset signal; and the output signal to the first logic level. When the on-time elapses after being set, the first to eighth pulses are generated for the reset signal. An on-time setting circuit comprising any one of the configurations, a gate driver circuit for generating a drive signal for the output transistor and the synchronous rectification transistor according to the output signal, and the synchronous rectification transistor by detecting a reverse flow of the coil current And a backflow detection circuit for forcibly turning off the power supply (9th configuration).

  The switching power supply disclosed in this specification generates a power supply control IC having the ninth configuration and an output voltage from an input voltage by attaching a part or all of the power supply control IC to the power supply control IC. And a switch output stage (tenth configuration).

  According to the invention disclosed in this specification, it is possible to provide an on-time setting circuit capable of reducing output ripple, and a power supply control IC and a switching power supply device using the on-time setting circuit.

Block diagram showing the overall configuration of the switching power supply Timing chart showing switching operation under heavy load Timing chart showing reverse flow cut-off operation at light load Characteristics of switch output stage 20 Schematic showing behavior of coil current IL Circuit diagram showing basic configuration of on-time setting circuit 16 Timing chart showing basic operation of on-time setting circuit 16 The circuit diagram which shows the 1st modification of the 2nd voltage generation part Y The circuit diagram which shows the 2nd modification of the 2nd voltage generation part Y Timing chart showing pull-up operation of second voltage VY The circuit diagram which shows the 3rd modification of the 2nd voltage generation part Y Timing chart showing pull-down operation of second voltage VY Ton-Iout correlation diagram Timing chart showing a transition example of output behavior with load increase / decrease Block diagram showing a configuration example of a television equipped with a switching power supply device Front view of a TV equipped with a switching power supply Side view of a TV equipped with a switching power supply Rear view of a TV with a switching power supply

<Switching power supply>
FIG. 1 is a block diagram showing the overall configuration of the switching power supply apparatus. The switching power supply device 1 of this configuration example is a step-down DC / DC converter that generates an output voltage Vout from an input voltage Vin by a non-linear control method (bottom detection on-time fixed method). The switching power supply device 1 includes a semiconductor device 10 and various discrete components externally attached to the semiconductor device 10 (N-channel MOS [metal oxide semiconductor] field effect transistors N1 and N2, a coil L1, a capacitor C1, and a resistor R1. And a switch output stage 20 formed by R2).

  The semiconductor device 10 is a main body (so-called power supply control IC) that comprehensively controls the entire operation of the switching power supply device 1. The semiconductor device 10 has external terminals T1 to T7 (upper gate terminal T1, lower gate terminal T2, switch terminal T3, feedback terminal T4, input voltage terminal T5 as means for establishing electrical connection with the outside of the device. , Output voltage terminal T6 and ground terminal T7).

  The external terminal T1 is connected to the gate of the transistor N1. The external terminal T2 is connected to the gate of the transistor N2. The external terminal T3 is connected to the application terminal of the switch voltage Vsw (a connection node between the source of the transistor N1 and the drain of the transistor N2). The external terminal T4 is connected to an application end (a connection node between the resistor R1 and the resistor R2) of the divided voltage Vdiv. The external terminal T5 is connected to the application terminal for the input voltage Vin. The external terminal T6 is connected to the application terminal for the output voltage Vout. The external terminal T7 is connected to the ground terminal.

  Next, the connection relationship of discrete components attached to the semiconductor device 10 will be described. The drain of the transistor N1 is connected to the application terminal for the input voltage Vin. The source of the transistor N2 is connected to the ground terminal. The source of the transistor N1 and the drain of the transistor N2 are both connected to the first end of the coil L1. The second end of the coil L1 and the first end of the capacitor C1 are both connected to the application terminal for the output voltage Vout. The second end of the capacitor C1 is connected to the ground end. The resistors R1 and R2 are connected in series between the application terminal of the output voltage Vout and the ground terminal.

  The transistor N1 is an output transistor that is on / off controlled according to the gate signal G1 input from the external terminal T1. The transistor N2 is a synchronous rectification transistor that is on / off controlled in accordance with the gate signal G2 input from the external terminal T2. As the rectifying element, a diode may be used instead of the transistor N2. The transistors N1 and N2 can also be built in the semiconductor device 10. The coil L1 and the capacitor C1 function as a rectifying / smoothing unit that rectifies and smoothes the rectangular-wave switch voltage Vsw appearing at the external terminal T3 to generate the output voltage Vout. The resistors R1 and R2 function as a divided voltage generation unit that divides the output voltage Vout to generate a divided voltage Vdiv. However, when the output voltage Vout is within the input dynamic range of the ripple injection circuit 11 (or the main comparator 13), the divided voltage generation unit may be omitted.

  Next, the internal configuration of the semiconductor device 10 will be described. The semiconductor device 10 includes a ripple injection circuit 11, a reference voltage generation circuit 12, a main comparator 13, a one-shot pulse generation circuit 14, an RS flip-flop 15, an on time setting circuit 16, and a gate driver circuit 17. The backflow detection circuit 18 is integrated.

  The ripple injection circuit 11 adds a ripple voltage Vrpl (a pseudo ripple component simulating a coil current IL flowing through the coil L1) to the divided voltage Vdiv to generate a feedback voltage Vfb (= Vdiv + Vrpl). If such a ripple injection technique is introduced, stable switching control can be performed even if the ripple component of the output voltage Vout (and thus the divided voltage Vdiv) is not so large. A ceramic capacitor or the like can be used. However, when the ripple component of the output voltage Vout is sufficiently large, the ripple injection circuit 11 can be omitted.

  The reference voltage generation circuit 12 generates a predetermined reference voltage Vref.

  The main comparator 13 compares the feedback voltage Vfb input to the inverting input terminal (−) and the reference voltage Vref input to the non-inverting input terminal (+) to generate the comparison signal S1. The comparison signal S1 is at a low level when the feedback voltage Vfb is higher than the reference voltage Vref, and is at a high level when the feedback voltage Vfb is lower than the reference voltage Vref.

  The one-shot pulse generation circuit 14 generates a one-shot pulse (eg, a falling pulse) in the set signal S2 using the falling edge of the comparison signal S1 as a trigger.

  The RS flip-flop 15 sets the output signal S4 to a high level at the pulse edge (eg, falling edge) of the set signal S2 input to the set end (S), and the reset signal input to the reset end (R). The output signal S4 is reset to a low level at the pulse edge (eg, falling edge) of S3.

  The on-time setting circuit 16 outputs a reset signal S3 after a predetermined on-time Ton has elapsed after the inverted output signal S4B of the RS flip-flop 15 (= the logic inverted signal of the output signal S4) has fallen to a low level. A one-shot pulse (eg, falling pulse) is generated.

  The gate driver circuit 17 generates gate signals G1 and G2 according to the output signal S4 of the RS flip-flop 15, and switches the transistors N1 and N2 in a complementary manner. Note that the term “complementary” used in this specification includes the case where the transistors N1 and N2 are turned on / off completely, as well as the transistors N1 and N2 from the viewpoint of preventing through current. This includes a case where a delay is given to the on / off transition timing (a case where a so-called simultaneous off period (dead time) is provided).

  The backflow detection circuit 18 monitors the backflow of the coil current IL (coil current IL flowing from the coil L1 to the ground terminal via the transistor N2) and generates a backflow detection signal S5. The backflow detection signal S5 is latched at a high level (a logic level when a backflow is detected) when a backflow of the coil current IL is detected, and a low level (a logic when no backflow is detected) at the rising edge of the gate signal G1 in the next cycle. Level). As a method for monitoring the backflow of the coil current IL, for example, a zero cross point at which the switch voltage Vsw switches from negative to positive during the ON period of the transistor N2 may be detected. When the backflow detection signal S5 is at a high level, the gate driver circuit 17 generates the gate signal G2 so as to forcibly turn off the transistor N2 without depending on the output signal S4.

  The ripple injection circuit 11, the reference voltage generation circuit 12, the main comparator 13, the one-shot pulse generation circuit 14, the RS flip-flop 15, the on-time setting circuit 16, the gate driver circuit 17, and the backflow detection circuit 18 described above are: A non-linear control method for generating the output voltage Vout from the input voltage Vin by performing on / off control of the transistors N1 and N2 according to the comparison result of the feedback voltage Vfb and the reference voltage Vref (in this configuration example, bottom detection on-time) Functions as a switching control circuit.

<Switching operation>
FIG. 2 is a timing chart showing the switching operation at the time of heavy load (current continuous mode), in which the feedback voltage Vfb, the set signal S2, the reset signal S3, and the output signal S4 are depicted in order from the top.

  When the feedback voltage Vfb decreases to the reference voltage Vref at time t11, the set signal S2 falls to the low level, and the output signal S4 changes to the high level. Accordingly, the transistor N1 is turned on, and the feedback voltage Vfb starts to rise.

  Thereafter, when the reset signal S3 falls to the low level at the time t12 due to the elapse of the on time Ton, the output signal S4 transitions to the low level. Therefore, the transistor N1 is turned off, and the feedback voltage Vfb starts to fall again.

  The gate driver circuit 17 generates gate signals G1 and G2 in accordance with the output signal S4, and performs on / off control of the transistors N1 and N2 using this. Specifically, when the output signal S4 is at a high level, basically, the gate signal G1 is set to a high level to turn on the transistor N1, and the gate signal G2 is set to a low level to turn off the transistor N2. Is done. Conversely, when the output signal S4 is at a low level, basically, the gate signal G1 is set to a low level to turn off the transistor N1, and the gate signal G2 is set to a high level to turn on the transistor N2.

  Due to the on / off control of the transistors N1 and N2, the switch voltage Vsw having a rectangular waveform appears at the external terminal T3. The switch voltage Vsw is rectified and smoothed by the coil L1 and the capacitor C1, and the output voltage Vout is generated. The output voltage Vout is divided by the resistors R1 and R2, and the divided voltage Vdiv (and thus the feedback voltage Vfb) is generated. With such output feedback control, the switching power supply device 1 generates the desired output voltage Vout from the input voltage Vin with a very simple configuration.

<Backflow blocking operation>
FIG. 3 is a timing chart showing the reverse flow cut-off operation at the time of light load (in the current discontinuous mode). The gate signals G1 and G2, the reverse flow detection signal S5, the coil current IL, and the switch voltage Vsw are sequentially shown from the top. It is depicted.

  At times t21 to t22, since the gate signal G1 is at a high level and the gate signal G2 is at a low level, the transistor N1 is turned on and the transistor N2 is turned off. Accordingly, at times t21 to t22, the switch voltage Vsw rises to substantially the input voltage Vin, and the coil current IL increases.

  At time t22, when the gate signal G1 falls to the low level and the gate signal G2 rises to the high level, the transistor N1 is turned off and the transistor N2 is turned on. Therefore, the switch voltage Vsw decreases to a negative voltage (= GND−IL × RN2, where RN2 is the on-resistance value of the transistor N2), and the coil current IL starts to decrease.

  Here, when the output current Iout flowing through the load is sufficiently heavy, the energy stored in the coil L1 is large, so that the coil current IL has a zero value until time t24 when the gate signal G1 is raised to the high level again. The switch voltage Vsw is maintained at a negative voltage while continuing to flow toward the load without falling below. On the other hand, at the time of light load when the output current Iout flowing through the load is small, the energy stored in the coil L1 is small. Therefore, at time t23, the coil current IL falls below the zero value, and a reverse flow of the coil current IL occurs. The polarity of the voltage Vsw switches from negative to positive. In such a state, since the electric charge stored in the capacitor C1 is returned to the input side via the coil L1, the efficiency at a light load is lowered.

  Therefore, the switching power supply device 1 uses the backflow detection circuit 18 to detect backflow of the coil current IL (polarity inversion of the switch voltage Vsw), and during the high level period (time t23 to t24) of the backflow detection signal S5, the transistor N2 Is forcibly turned off. By adopting such a configuration, the reverse flow of the coil current IL can be promptly interrupted, so that it is possible to eliminate a decrease in efficiency at a light load.

<ON time setting circuit>
Next, a basic design concept of the on-time setting circuit 16 will be described with reference to FIGS. 4 and 5.

  FIG. 4 is a characteristic diagram of the switch output stage 20. In this figure, L is the inductance of the coil L1, DCR is the equivalent series resistance of the coil L1, RonH is the on-resistance of the transistor N1, RonL is the on-resistance of the transistor N2, and IL ~ is the average value of the coil current IL. Show.

  FIG. 5 is a schematic diagram showing the behavior of the coil current IL in the switching period Tsw. As shown in this figure, the coil current IL increases from the current value I0 to the current value I1 over the on time Ton (= the time during which the transistor N1 is turned on and the transistor N2 is turned off), and then the off time Toff. The current value I1 decreases from the current value I1 to the current value I2 over the period (= time when the transistor N1 is turned off and the transistor N2 is turned on). The current values I1 and I2 can be expressed by the following equations (1a) and (1b), respectively.

  In the steady state, I0 = I2 is established. By substituting this and rearranging the formulas (1a) and (1b), the following formula (2) is obtained.

  From the above equation (2), in order to make the switching cycle Tsw (and thus the switching frequency fsw (= 1 / Tsw)) constant, the current is proportional to Vin− (RonH−RonL) × IL˜ It can be seen that the required time for charging the capacitor from 0 V to Vout + (RonL + DCR) × IL˜ may be set as the on time Ton.

  Here, Vin−RonH × IL˜ corresponds to the high level VswH (= voltage level at the on time Ton) of the switch voltage Vsw, and −RonL × IL˜ represents the low level VswL (= off time Toff of the switch voltage Vsw). Vout + DCR × IL˜ corresponds to the average potential of the switch voltage Vsw (hereinafter referred to as the average switch voltage Vsw˜).

  Therefore, assuming that Vin−RonH >> − RonL × IL˜, in order to make the switching cycle Tsw constant, first, during the off time Toff, the capacitor is connected to the low level VswL (= −RonL) of the switch voltage Vsw. XIL ~), and after that, when the transistor N1 is turned on, the capacitor starts to charge with a current proportional to the high level VswH (= Vin-RonH * IL ~) of the switch voltage Vsw. The on-time setting circuit 16 may be designed so that the time required to reach the voltage Vsw ~ is set as the on-time Ton.

  FIG. 6 is a circuit diagram showing a basic configuration of the on-time setting circuit 16 designed based on the above design concept. The on-time setting circuit 16 of this configuration example includes a first voltage generation unit X, a second voltage generation unit Y, and a comparator Z.

  The first voltage generator X receives the switch voltage Vsw and the inverted output signal S4B and generates a first voltage VX having a ramp waveform (or a triangular waveform or a slope waveform). The first voltage VX rises at a predetermined slope from the initial value during the on time Ton (= low level period of the inverted output signal S4B), and the initial value during the off time Toff (= high level period of the inverted output signal S4B). Reset to.

  The second voltage generation unit Y receives the switch voltage Vsw and generates the second voltage VY. The second voltage VY corresponds to the reference voltage of the comparator Z.

  The comparator Z includes a first voltage VX input from the first voltage generator X to the inverting input terminal (−), and a second voltage VY input from the second voltage generator Y to the non-inverting input terminal (+). To generate the reset signal S3. The reset signal S3 becomes low level when the first voltage VX is higher than the second voltage VY, and conversely becomes high level when the first voltage VX is lower than the second voltage VY. Note that the falling edge of the reset signal S3 functions as an end trigger for the on-time Ton.

  Next, the circuit configuration of the first voltage generator X will be described in detail with reference to FIG. The first voltage generator X includes resistors X1 to X5, a capacitor X6, P-channel MOS [metal-oxide-semiconductor] field effect transistors X7 and X8, N-channel MOS field effect transistors X9 to X12, and an operational amplifier. X13 and a discharge controller X14.

  A first end of the resistor X1 (resistance value Rf) is connected to an input end of the switch voltage Vsw. The second end of the resistor X1 and the first end of the resistor X3 (resistance value Rhop) are both connected to the output terminal of the first voltage VX (= the inverting input terminal (−) of the comparator Z). The second end of the resistor X3 is connected to the first end of the capacitor X6 (capacitance value Cf). The second end of the capacitor X6 is connected to the ground end.

  The non-inverting input terminal (+) of the operational amplifier X13 is connected to the output terminal of the first voltage VX. The output terminal of the operational amplifier X13 is connected to the gate of the transistor X9. The drain of the transistor X9 is connected to the inverting input terminal (−) of the operational amplifier X13 and the first terminal of the resistor X2 (resistance value Rf). A second end of the resistor X2 is connected to the ground end. The sources of the transistors X7 and X8 are both connected to the power supply terminal. The gates of the transistors X7 and X8 are both connected to the drain of the transistor X8. The drain of the transistor X7 is connected to the output terminal of the first voltage VX. The drain of the transistor X8 is connected to the drain of the transistor X9.

  The drain of the transistor X10 is connected to the first end of the capacitor X6. The source of the transistor X10 is connected to the ground terminal. The gate of the transistor X10 is connected to the first output terminal (= the output terminal of the first discharge control signal Sa) of the discharge controller X14. A first end of the resistor X4 (resistance value Rd) is connected to an input end of the switch voltage Vsw. A second end of the resistor X4 is connected to the drain of the transistor X11. The source of the transistor X11 and the drain of the transistor X12 are both connected to the first end of the capacitor X6. The source of the transistor X12 is connected to the first end of the resistor X5 (resistance value Rd). A second end of the resistor X5 is connected to the ground terminal. The gates of the transistors X11 and X12 are both connected to the second output terminal (= the output terminal of the second discharge control signal Sb) of the discharge controller X14. An inverted output signal S4B is input to the discharge controller X14.

  In the first voltage generation unit X configured as described above, the resistors X1 and X2, the transistors X7 to X9, and the operational amplifier X13 correspond to a charging circuit for the capacitor X6. A first current IX1 (= (Vsw−VX) / Rf) corresponding to the difference between the switch voltage Vsw and the first voltage VX flows through the resistor X1. Since the operational amplifier X13 controls the gate of the transistor X9 so that the non-inverting input terminal (+) and the inverting input terminal (−) are short-circuited, the first voltage VX appears at the first terminal of the resistor X2. Accordingly, the second current IX2 (= VX / Rf) corresponding to the first voltage VX flows through the resistor X2. The current mirror composed of the transistors X7 and X8 generates the third current I3 (= Vsw / Rf) corresponding to the switch voltage Vsw by mirroring the second current IX2 and adding it to the first current IX1.

  During the low level period (= on time Ton) of the inverted output signal S4B, the discharge controller X14 turns off the transistors X10 to X12, so that the discharge path of the capacitor X6 is cut off. Accordingly, since the capacitor X6 is charged by the third current I3, the first voltage VX increases.

  Note that, when the capacitor X6 is charged, the first voltage VX starts to increase from zero, so the second current IX2 also starts to increase from zero. Therefore, even if there is a slight activation delay, the on-time Ton is not greatly affected.

  The resistor X3 generates a correction voltage for correcting a signal delay time generated in the main comparator 13, the gate driver circuit 17, and the like. By providing such a resistor X3, it is possible to perform a delay time correction corresponding to Cf × Rhop. Note that when the resistance value Rhop of the resistor X3 is changed, the input voltage dependency characteristic (Vin dependency characteristic) of the switching frequency fsw is changed. Therefore, it is desirable that the resistance value Rhop of the resistor X3 is adjusted to the optimum value according to the previous evaluation result.

  In the first voltage generation unit X configured as described above, the resistors X4 and X5, the transistors X10 to X12, and the discharge control unit X14 correspond to a discharge circuit of the capacitor X6. In the high level period (= off time Toff) of the inverted output signal S4B, the discharge control unit X14 first turns on the transistor X10 and turns off the transistors X11 and X12 for a predetermined minimum off time (for example, 100 ns). As a result, the capacitor X6 is quickly discharged to the GND potential (= 0V) via the transistor X10.

  Thereafter, the discharge controller X14 turns off the transistor X10 and turns on the transistors X11 and X12. As a result, the capacitor X6 is further discharged to a negative voltage (= VswL / 2) obtained by dividing the low level VswL of the switch voltage Vsw by 1/2.

  Note that when the transistor N2 is forcibly turned off in the current discontinuous mode (when the reverse flow is interrupted), both the transistors N1 and N2 are turned off, so that the switch voltage Vsw substantially rises to the output voltage Vout. Therefore, when the transistors X11 and X12 are turned on as described above, the capacitor X6 is charged to ½ of the output voltage Vout during the off time Toff, so that the subsequent on-time setting operation (= first voltage) (Comparison operation between VX and second voltage VY) is hindered. Therefore, in the current discontinuous mode, the discharge control by the discharge control unit X14 is performed so that the first voltage VX is fixed to the GND potential (= 0V) over the high level period of the inverted output signal S4B. Specifically, the transistor X10 is turned on and the transistors X11 and X12 are turned off over the high level period of the inverted output signal S4B.

  Next, the circuit configuration of the second voltage generator Y will be described in detail with reference to FIG. The second voltage generation unit Y includes resistors Y1 to Y3 and capacitors Y4 and Y5.

  A first end of the resistor Y1 (resistance value: Rf1) is connected to an input end of the switch voltage Vsw. The second end of the resistor Y1 is connected to the first end of the resistor Y2 (resistance value: Rf1), the first end of the resistor Y3 (resistance value: Rf2), and the first end of the capacitor Y4 (capacitance value: Cf1). Has been. The second end of the resistor Y2 and the second end of the capacitor Y4 are both connected to the ground terminal. The second end of the resistor Y3 and the first end of the capacitor Y5 (capacitance value: Cf2) are both connected to the output terminal of the second voltage VY (= the non-inverting input terminal (+) of the comparator Z). The second end of the capacitor Y5 is connected to the ground end.

  In the second voltage generating unit Y configured as described above, the resistor Y1 and the resistor Y2 function as a voltage dividing circuit that generates a divided voltage (= Vsw / 2) of the switch voltage Vsw. The resistors Y1 and Y3 and the capacitors Y4 and Y5 function as a secondary RC low-pass filter (RC integration circuit) that integrates the divided voltage (= Vsw / 2) of the switch voltage Vsw to generate the second voltage VY. To do. In the second voltage generation unit Y of this configuration example, a second voltage VY (= Vsw˜ / 2) corresponding to ½ of the average switch voltage Vsw˜ is generated.

  The order of the RC low-pass filter is not limited to the second order, and may be the first order or the third order or higher.

  Further, when the second voltage VY is generated without dividing the switch voltage Vsw, the resistor Y2, the resistors X4 and X5, and the transistor X10 are unnecessary. However, since the fluctuation range of the first voltage VX becomes large, attention must be paid to the withstand voltage design of the on-time setting circuit 16 when handling a high input voltage Vin.

  FIG. 7 is a timing chart showing the basic operation of the on-time setting circuit 16, and in order from the top, the switch voltage Vsw, the first voltage VX, the second voltage VY, the reset signal S3, the inverted output signal S4B, and the first discharge control. The signal Sa and the second discharge control signal Sb are depicted.

  Times t31 to t33 correspond to a high level period (= off time Toff) of the inverted output signal S4B. During the period, first, the first discharge control signal Sa is set to a high level and the second discharge control signal Sb is set to a low level over a period of time t31 to t32. As a result, the transistor X10 is turned on and the transistors X11 and X12 are turned off, so that the first voltage VX is quickly discharged to the GND potential (= 0V).

  Next, from time t32 to t33, the first discharge control signal Sa is set to the low level, and the second discharge control signal Sb is set to the high level. As a result, since the transistor X10 is turned off and the transistors X11 and X12 are turned on, the first voltage VX is further reduced to a divided voltage (= VswL / 2) obtained by dividing the low level VswL of the switch voltage Vsw by half. Discharged.

  On the other hand, the time t33 to the time t34 correspond to the low level period (= on time Ton) of the inverted output signal S4B. During the period, both the first discharge control signal Sa and the second discharge control signal Sb are at a low level. As a result, the discharge path of the capacitor X6 is cut off, so that the charging of the capacitor X6 with the third current I3 proceeds and the first voltage VX increases. At time t34, when the first voltage VX becomes higher than the second voltage VY, the reset signal S3 falls to the low level, and the on time Ton ends. Note that the same operation as described above is repeated after time t34.

  As described above, the on-time setting circuit 16 discharges the capacitor X6 to the initial value (= VswL / 2) corresponding to the low level VswL of the switch voltage Vsw during the off-time Toff, and then the transistor N1 is turned on. At the time, the capacitor X6 starts to be charged with the third current IX3 proportional to the high level VswH of the switch voltage Vsw until the first voltage VX reaches the second voltage VY (= 1/2 of the average switch voltage Vsw ~). The required time is set as the on-time Ton.

  By adopting such a configuration, fluctuations in the switching frequency fsw can be suppressed without impairing the advantages of the nonlinear control method. Therefore, it is possible to improve output voltage accuracy and load regulation characteristics, and facilitate measures against EMI (electromagnetic interference) and noise in set design. In addition, the switching power supply device 1 can be applied without any problem as a power supply means for an application in which the fluctuation of the input voltage Vin is large or an application that requires various output voltages Vout.

<Second Voltage Generating Unit (First Modification)>
FIG. 8 is a circuit diagram showing a first modification of the second voltage generator Y. The second voltage generation unit Y of the present modification is based on the basic configuration (FIG. 6), and further includes capacitors Y6 and Y7, P-channel MOS field effect transistors Y8 to Y10, and an N-channel MOS electric field. It includes effect transistors Y11 to Y14 and an inverter Y15. Therefore, the same reference numerals as those in FIG. 6 are assigned to the same circuit elements as those in the previous basic configuration, and the redundant description is omitted. In the following, the characteristic portions of the first modification will be mainly described.

  The first end of the capacitor Y6 (capacitance value: Cf1) is connected to the input end of the output voltage Vout. The second end of the capacitor Y6 is connected to the first end of the capacitor Y4.

  The second end of the resistor Y2 and the second end of the capacitor Y4 are not connected to the ground end, but are connected to the drain of the transistor Y13. The source of the transistor Y13 is connected to the ground terminal. The gate of the transistor Y13 is connected to the input terminal of the enable signal EN. Thus, the transistor Y13 is inserted between the resistor Y2 and the capacitor Y4 and the ground terminal.

  The source of the transistor Y8 is connected to the first end of the capacitor Y4. The drain of the transistor Y8 is connected to the second end of the capacitor Y4. The gate of the transistor Y8 is connected to the input terminal of the enable signal EN.

  The source of the transistor Y9 is connected to the first end of the capacitor Y6. The drain of the transistor Y9 is connected to the second end of the capacitor Y6. The gate of the transistor Y9 is connected to the input terminal of the enable signal EN.

  The second end of the resistor Y3 is connected not to the output end of the second voltage VY but to the drain of the transistor Y14. The source of the transistor Y14 is connected to the output terminal of the second voltage VY. The gate of the transistor Y14 is connected to the input terminal of the enable signal EN. Thus, the transistor Y14 is inserted between the second end of the resistor Y3 and the output end of the second voltage VY.

  A first end of the capacitor Y7 (capacitance value: Cf2) is connected to the drain of the transistor Y10. The second end of the capacitor Y7 is connected to the first end of the capacitor Y5.

  The source of the transistor Y10 is connected to the input terminal of the output voltage Vout. The drain of the transistor Y10 is connected to the first end of the capacitor Y7. The gate of the transistor Y10 is connected to the output terminal of the inverter Y15.

  The drain of the transistor Y11 is connected to the first end of the capacitor Y5. The source of the transistor Y11 is connected to the second end of the capacitor Y5. The gate of the transistor Y11 is connected to the output terminal of the inverter Y15. The input end of the inverter Y15 is connected to the input end of the enable signal EN.

  The drain of the transistor Y12 is connected to the first end of the capacitor Y7. The source of the transistor Y12 is connected to the second end of the capacitor Y7. The gate of the transistor Y12 is connected to the output terminal of the inverter Y15.

  The enable signal EN becomes low level when switching is stopped (= when the reverse current of the coil current IL is detected and both the transistors N1 and N2 are turned off), and when switching is resumed (= the transistor N1 is turned on in the next cycle) Logic signal that goes high. As the enable signal EN, for example, the backflow detection signal S5 described above can be used.

  When the enable signal EN is at the low level, the transistors Y13 and Y14 are turned off, and the current path through the resistors Y1 and Y2 and the current path through the resistor Y3 are both cut off. That is, the transistors Y13 and Y14 function as a current path breaker that blocks a current path from the input terminal of the switch voltage Vsw to the ground terminal when switching is stopped. With such a configuration, it is possible to realize power saving when switching is stopped.

  However, while the current path is cut off, the second voltage VY drops to the GND potential (= 0V). Therefore, when switching is resumed, the second voltage VY needs to be quickly raised to the original voltage value (= Vsw ~ / 2). However, in the integration process of the switch voltage Vsw by the RC low-pass filter, it takes a long time to recover the second voltage VY, which causes an obstacle to the on-time setting operation.

  On the other hand, the average switch voltage Vsw˜ in the steady state substantially coincides with the output voltage Vout. In view of this fact, the second voltage generation unit Y of the present modified example capacitively divides the output voltage Vout when switching is resumed, whereby the second voltage VY is set to a predetermined initial value VY0 (= Vout / 2≈Vsw˜ / 2). ) Has a pull-up portion that pulls up momentarily.

  More specifically, in the second voltage generation unit Y of this modification, capacitors Y6 and Y7 are connected in series to the capacitors Y4 and Y5 that form the RC low-pass filter, respectively. That is, between the input terminal of the output voltage Vout and the ground terminal, a first capacity voltage dividing circuit composed of capacitors Y4 and Y6 and a second capacity voltage dividing circuit composed of capacitors Y5 and Y7 are formed. Two capacitive voltage dividing circuits function as a pull-up unit.

  When the enable signal EN rises from a low level to a high level and the transistor Y13 is turned on, a capacitance divided voltage (= Vout / 2) appears at a connection node between the capacitors Y4 and Y6. Similarly, when the enable signal EN rises from a low level to a high level and the transistor Y10 is turned on, a capacitance divided voltage (= Vout / 2) appears at a connection node between the capacitors Y5 and Y7.

  With such a configuration, when switching is resumed, the second voltage VY is instantaneously raised to the predetermined initial value VY0 (= Vout / 2) without waiting for the integration process of the switch voltage Vsw by the RC low-pass filter. Is possible. Note that after restarting the switching, the second voltage VY settles to the original voltage value (= integrated value Vsw˜ / 2 obtained by the RC low-pass filter) according to the time constant of the RC low-pass filter.

  While the enable signal EN is at the high level, the connection node between the resistor Y1 and the resistor Y2 is biased to Vout / 2 by the first capacitor voltage dividing circuit, and the output terminal of the second voltage VY is the second capacitor. Biased to Vout / 2 by the pressure circuit. Therefore, since the second voltage VY can easily follow the output fluctuation, the behavior of the second voltage VY can be stabilized.

  The capacitors Y4 to Y7 are connected in parallel with transistors Y8 and Y9 and transistors Y11 and Y12, respectively. The transistors Y8 and Y9 and the transistors Y11 and Y12 are both turned on when the enable signal EN is at a high level and turned off when the enable signal EN is at a low level.

  Therefore, when the enable signal EN is raised to a high level when switching is resumed, both ends of each of the capacitors Y4 to Y7 are short-circuited, and the charge accumulated in each capacitor is discharged. With such a configuration, the pull-up operation of the second voltage VY can be correctly performed every time switching is resumed.

<Second Voltage Generating Unit (Second Modification)>
FIG. 9 is a circuit diagram showing a second modification of the second voltage generator Y. The second voltage generation unit Y of the present modification is based on the first modification (FIG. 8), and further includes a resistor Y18, capacitors Y16 and Y17, and an N-channel type as additional elements of the pull-up unit. MOS field effect transistor Y19. Therefore, the same circuit elements as those of the first modification are denoted by the same reference numerals as those in FIG. 8, and redundant description is omitted. Hereinafter, the characteristic parts of the second modification will be mainly described. .

  The first end of the capacitor Y16 (capacitance value: Ch1) is connected to the first end of the capacitor Y7. The second end of the capacitor Y16 and the first end of the resistor Y18 (resistance value: Rh2) are both connected to the output end of the second voltage VY. The second end of the resistor Y18 is connected to the first end of the capacitor Y17 (capacitance value: Ch2). The second end of the capacitor Y17 is connected to the ground end.

  The drain of the transistor Y19 is connected to the first end of the resistor Y18. The source of the transistor Y19 is connected to the second end of the resistor Y18. The gate of the transistor Y19 is connected to the input terminal of the enable signal EN.

  In addition, since the pull-up unit of the second voltage generation unit Y is composed of only passive devices and switches, no bias current is required, and zero standby current can be easily realized. In principle, there is no delay at startup.

  Next, an on-time modulation operation using the above additional elements (capacitors Y16 and Y17, resistor Y18, and transistor Y19) will be described. When the capacitor Y17 is ignored, by adding the capacitor Y16, the initial value VY1 of the second voltage VY when switching is resumed is a voltage value represented by the following equation (3). That is, the larger the capacitance value Ch1 of the capacitor Y16, the higher the initial value VY1 of the second voltage VY.

  On the other hand, when the capacitor Y16 is ignored, by adding the capacitor Y17, the initial value VY2 of the second voltage VY when switching is resumed is a voltage value represented by the following equation (4). That is, the larger the capacitance value Ch2 of the capacitor Y17, the lower the initial value VY2 of the second voltage VY.

  However, the above equation (4) is established when the capacitor Y17 is completely discharged at the time of restarting the switching, that is, the low level period of the enable signal EN (= the off period of the transistor Y19) is the same as that of the capacitor Y17. This is a case where it is longer than the time constant τ (= Ch2 × Rh2) of the RC circuit comprising the resistor Y18.

  As the low level period of the enable signal EN is shorter than the time constant τ, the charge of the capacitor Y17 remains without being discharged, and thus the effect of lowering the initial value of the second voltage VY is reduced. That is, the effect of lowering the initial value by the capacitor Y17 increases as the load is light (= the low level period of the enable signal EN is long), and decreases as the load is heavy (= the low level period of the enable signal EN is short).

  The combined operation of the capacitors Y16 and Y17 is as follows.

  First, in the load region immediately before switching from the current discontinuous mode to the current continuous mode, the low level period of the enable signal EN is sufficiently shorter than the time constant τ described above, and the charge stored in the capacitor Y17 is hardly discharged. Become. Accordingly, since the capacitor Y17 can be ignored, the second voltage VY is pulled up to the initial value VY1 expressed by the above equation (3) when switching is resumed.

  On the other hand, in the current discontinuous mode, when the load becomes light enough and the capacitor Y17 is completely discharged during the low level period of the enable signal EN, the initial value VY3 of the second voltage VY when switching is resumed is The voltage value is expressed by the following equation (5). This state corresponds to a state in which capacitive division of the output voltage Vout is performed using all four capacitors (Y5, Y7, Y16, Y17).

  However, the above equation (5) is satisfied when the capacitor Y17 is completely discharged at the time of restarting the switching. As the load becomes heavier (= the lower level period of the enable signal EN becomes shorter), The initial value of the two voltages VY approaches VY3 from VY3.

  The second voltage VY gradually settles from the initial value toward the original voltage value (= Vsw ~ / 2) after switching is resumed. However, the first voltage VX crosses the second voltage VY after the switching is resumed and before the second voltage VY settles to the original voltage value. Accordingly, the higher the initial value of the second voltage VY, the longer the on-time Ton. Conversely, the lower the initial value of the second voltage VY, the shorter the on-time Ton.

  As can be seen from the above equation (5), if Ch1> Ch2, VY3> VY0, and if Ch1 <Ch2, VY3 <VY0. Therefore, desired on-time characteristics can be obtained by appropriately setting the capacitance values Ch1 and Ch2.

  FIG. 10 is a timing chart showing the pull-up operation of the second voltage VY. The behavior of the enable signal EN and the second voltage VY is depicted in order from the top. When the enable signal EN is raised to a high level at time t41, the second voltage VY is instantaneously raised to the initial value corresponding to the load by the pull-up operation described above.

  For example, as indicated by the solid line of the second voltage VY, in the load region immediately before switching from the current discontinuous mode to the current continuous mode, the initial value VY1 of the second voltage VY is higher than the original voltage value (= Vsw ~ / 2). It is good to design the pull-up part so that it becomes high. By performing such a design, once the backflow of the coil current IL is detected and the current discontinuous mode is entered, the on-time Ton of the transistor N1 is intentionally extended. Accordingly, the peak value of the coil current IL increases, and the output current Iout supplied to the load increases. Therefore, during the remaining time constant, the same output current Iout operates in the current discontinuous mode. Hysteresis is ensured when shifting from the continuous current mode to the discontinuous current mode.

  In addition, as shown by the small broken line, large broken line, one-dot chain line, or two-dot chain line of the second voltage VY, the pull-up unit is designed so that the initial value of the second voltage VY becomes lower as the load is lighter. It is good to leave. By performing such a design, the on-time Ton is shortened as the load is lighter in the current discontinuous mode, so that the output ripple at the time of light load can be reduced.

<Second Voltage Generating Unit (Third Modification)>
FIG. 11 is a circuit diagram showing a third modification of the second voltage generator Y. The second voltage generator Y of the present modification is based on the second modification (FIG. 9), and further includes a capacitor Y20, a P-channel MOS field effect transistor Y21, and an N-channel MOS field effect transistor. Y22. Therefore, the same circuit elements as those of the second modification example are denoted by the same reference numerals as those in FIG. 9, thereby omitting redundant description. In the following, the characteristic parts of the third modification example will be mainly described. .

  The source of the transistor Y21 is connected to the output terminal of the second voltage VY. The drain of the transistor Y21 is connected to the first end of the capacitor Y20 (capacitance value Ch3) and the drain of the transistor Y22. The second end of the capacitor Y20 and the source of the transistor Y22 are both connected to the ground terminal. The gates of the transistors Y21 and Y22 are both connected to the input terminal of the operation mode determination signal SKIP.

  The operation mode determination signal SKIP is at a high level when the backflow of the coil current IL is detected and both the transistors N1 and N2 are turned off (that is, in the current discontinuous mode), and the backflow of the coil current IL is detected. This is a logic signal that goes to a low level when the transistor N1 is turned on (ie, in the current continuous mode).

  The capacitor Y20 and the transistors Y21 and Y22 connected in this way function as a pull-down unit that transiently pulls down the second voltage VY when switching from the current discontinuous mode to the current continuous mode. Hereinafter, the dynamic hysteresis applying operation when the operation mode is switched by the pull-down unit will be described in detail.

  FIG. 12 is a timing chart showing the pull-down operation of the second voltage VY. In order from the top, the coil current IL, the switch voltage Vsw, the enable signal EN, the operation mode determination signal SKIP, and the first voltage VX (broken line) and A second voltage VY (solid line) is depicted.

  Prior to time t109, the current discontinuous mode in which the coil current IL falls below the zero value during the off time Toff. When switching is stopped, the second voltage generator Y enters a power saving state, and the second voltage VY decreases to 0V. On the other hand, when switching is resumed, the second voltage VY is instantaneously raised to an initial value higher than the original voltage value (= Vsw˜ / 2) (see time t101, time t104, or time t107). These operations are as described above.

  In the current discontinuous mode, the operation mode determination signal SKIP is maintained at a high level. At this time, the transistor Y21 is turned off and the transistor Y22 is turned on. Accordingly, since both ends of the capacitor Y20 are short-circuited, the pull-down portion does not affect the operation of generating the second voltage VY.

  On the other hand, at time t109, the operation mode determination signal SKIP rises to the low level as the transistor N1 is turned on before the backflow of the coil current IL is detected (= before the enable signal EN falls to the low level). It's down. At this time, the transistor Y21 is turned off and the transistor Y22 is turned on. Accordingly, since the capacitor Y20 is inserted between the output terminal of the second voltage VY and the ground terminal, the second voltage VY is transiently lowered.

  If the pull-down unit is not introduced, the second voltage VY gradually returns to the original voltage value Vsw ~ / 2 according to the time constant τ of the RC low-pass filter, as shown by the thin broken line in the figure. To go. Therefore, even after the transition from the current discontinuous mode to the current continuous mode, the on-time Ton continues to be extended for a while, so that the state in which it is easy to return to the current discontinuous mode is continued.

  On the other hand, when the pull-down unit is introduced, once the current continuous mode is entered, the second voltage VY is lowered and the on-time Ton is shortened. As a result, the peak-to-peak value of the coil current IL becomes small, and the bottom value of the coil current IL becomes difficult to fall below the zero value, so that the current continuous mode is maintained until the output current Iout is sufficiently reduced.

  11 and 12, the description has been given by taking as an example a configuration in which a pull-down unit is further introduced on the basis of the second modified example (FIG. 9), but the introduction target of the pull-down unit is limited to this. Instead of this, it is also possible to introduce a pull-down unit based on the basic configuration (FIG. 6) or the first modification (FIG. 8).

<Correlation between on-time and output current>
FIG. 13 is a correlation diagram between the on-time Ton and the output current Iout. In the current discontinuous mode in which the output current Iout is smaller than the threshold current Ith (denoted as DCM [discontinuous current mode]), the ON time Ton is shortened as the output current Iout is smaller. Such an on-time modulation operation can prevent an increase in output ripple.

  On the other hand, in the current continuous mode in which the output current Iout is larger than the threshold current Ith (denoted as CCM [continuous current mode]), the switching frequency fsw is affected by the on resistance of the transistors N1 and N2 and the equivalent series resistance of the coil L1. Is adjusted according to the output current Iout. As described above, the adjustment operation of the on-time Ton is performed by setting the capacitor to the low level VswL (= −RonL × IL˜) of the switch voltage Vsw during the off-time Toff, and then the transistor N1 is turned on. At that time, the capacitor starts to be charged with a current proportional to the high level VswH (= Vin−RonH × IL˜) of the switch voltage Vsw, and the required time until the capacitor potential reaches the average switch voltage Vsw˜ is set as the on time Ton. It is realized by doing.

  Further, in the load region where switching between the current discontinuous mode and the current continuous mode occurs, hysteresis is given to the on-time Ton. By adopting such a configuration, the current continuous mode and the current discontinuous mode are not irregularly repeated at the transition from the light load to the heavy load (or at the transition from the heavy load to the light load). It is possible to prevent an increase in the ripple component of the output voltage Vout due to irregular mode transition.

<Simulation results>
FIG. 14 is a timing chart showing a transition example of the output behavior accompanying the increase / decrease of the load. From the top, the reset signal S3, the output voltage Vout, the switch voltage Vsw, the second voltage VY, the gate signal G1, and the operation mode determination signal. SKIP and output current Iout are depicted.

  As indicated by the regions P1 and P2, when the switching frequency fsw decreases at light load, the second voltage VY is decreased and the on-time Ton is shortened. Thereby, an increase in output ripple at light load can be prevented.

  In addition, as indicated by the regions P3 and P4, the second voltage VY is transiently lowered during the transition from the current discontinuous mode to the current continuous mode. On the other hand, as indicated by the region P5, at the time of transition from the current continuous mode to the current discontinuous mode, the second voltage VY is raised to a voltage value higher than the integral value (= Vsw ~ / 2) obtained by the RC low-pass filter. It is done. Thereby, since hysteresis is given to the on time Ton, it becomes possible to stabilize the transition between both modes.

<Application to TV>
FIG. 15 is a block diagram illustrating a configuration example of a television equipped with the above switching power supply device. 16A to 16C are a front view, a side view, and a rear view of a television on which the above-described switching power supply device is mounted, respectively. The TV A in this configuration example includes a tuner unit A1, a decoder unit A2, a display unit A3, a speaker unit A4, an operation unit A5, an interface unit A6, a control unit A7, and a power supply unit A8. Have.

  The tuner unit A1 selects a broadcast signal of a desired channel from a reception signal received by an antenna A0 externally connected to the television A.

  The decoder unit A2 generates a video signal and an audio signal from the broadcast signal selected by the tuner A1. The decoder unit A2 also has a function of generating a video signal and an audio signal based on an external input signal from the interface unit A6.

  The display unit A3 outputs the video signal generated by the decoder unit A2 as a video.

  The speaker unit A4 outputs the audio signal generated by the decoder unit A2 as audio.

  The operation unit A5 is one of human interfaces that accept user operations. As the operation unit A5, a button, a switch, a remote controller, or the like can be used.

  The interface unit A6 is a front end that receives an external input signal from an external device (such as an optical disk player or a hard disk drive).

  The control unit A7 comprehensively controls the operations of the units A1 to A6. As the control unit A7, a CPU [central processing unit] or the like can be used.

  The power supply unit A8 supplies power to the units A1 to A7. As the power supply unit A8, the above-described switching power supply device 1 can be suitably used.

<Other variations>
In the above embodiment, the configuration in which the present invention is applied to the step-down switching power supply apparatus has been described as an example. However, the application target of the present invention is not limited to this, and for example, the switching power supply apparatus The output stage may be a step-up type, a step-up / step-down type, or an inversion type.

  Further, in the above-described embodiment, the switching power supply device (on-time setting circuit) of the fixed on time is described as an example, but the application target of the present invention is not limited to this, and is the same as above. By changing the RC network based on the above technical idea, it is also possible to apply to a fixed off-time switching power supply (off-time setting circuit).

  As described above, the configuration of the present invention can be variously modified within the scope of the present invention in addition to the above-described embodiment. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The switching power supply according to the present invention is a power supply (for example, SOC [system-on-chip]) mounted on various electronic devices such as a liquid crystal display, a plasma display, a BD recorder / player, a set top box, and a personal computer. Or power supply for peripheral devices).

DESCRIPTION OF SYMBOLS 1 Switching power supply device 10 Semiconductor device (power supply control IC)
DESCRIPTION OF SYMBOLS 11 Ripple injection circuit 12 Reference voltage generation circuit 13 Main comparator 14 One shot pulse generation circuit 15 RS flip-flop 16 ON time setting circuit 17 Gate driver circuit 18 Backflow detection circuit 20 Switch output stage N1 N channel type MOS field effect transistor (output transistor) )
N2 N-channel MOS field effect transistor (synchronous rectification transistor)
L1 Coil R1, R2 Resistor C1 Capacitor T1-T8 External terminal X First voltage generator X1-X5 Resistor X6 Capacitor X7, X8 P-channel MOS field effect transistor X9-X12 N-channel MOS field effect transistor X13 Operational amplifier X14 Discharge control Unit Y Second voltage generation unit Y1 to Y3, Y18 Resistor Y4 to Y7, Y16, Y17, Y20 Capacitor Y8 to Y10, Y21 P channel type MOS field effect transistor Y11 to Y14, Y19, Y22 N channel type MOS field effect transistor Y15 Inverter Z Comparator A Television A0 Antenna A1 Tuner A2 Decoder A3 Display A4 Speaker A5 Operation A6 Interface A7 Controller A8 Power supply

Claims (6)

A method for setting an on-time in a switching power supply device with a fixed on-time that generates an output voltage from an input voltage by driving a coil by turning on and off an output transistor and a synchronous rectification transistor,
The current discontinuous mode is completed by comparing the first voltage of the ramp waveform that rises over the on-time with the second voltage that is lowered as the load is lighter in the current discontinuous mode. Then, the on-time setting method is characterized in that the on-time is shortened as the load is lighter.   A switch voltage appearing at a connection node between the output transistor and the synchronous rectifier transistor or a divided voltage thereof is integrated to generate the second voltage, and when switching is stopped, a current path from the switch voltage input terminal to the ground terminal is formed. 2. The on-time setting method according to claim 1, wherein the second voltage is instantaneously raised to a predetermined initial value by shutting off and capacitively dividing the output voltage when switching is resumed.   The on-time setting method according to claim 3, wherein the initial value is lower as the load is lighter.   4. The on-time according to claim 3, wherein the initial value is higher than an integral value of the switch voltage or a divided voltage thereof in a load region immediately before switching from the current discontinuous mode to the current continuous mode. Setting method.   The on-time setting method according to any one of claims 1 to 4, wherein the second voltage is transiently reduced when the current discontinuous mode is switched to the current continuous mode. A method for setting an on-time in a switching power supply device with a fixed on-time that generates an output voltage from an input voltage by driving a coil by turning on and off an output transistor and a synchronous rectification transistor,
Comparing the first voltage of the ramp waveform that rises over the on-time with the second voltage that is transiently lowered when switching from the current discontinuous mode to the current continuous mode, the on-time is terminated. Thus, the on-time setting method is characterized in that the on-time is transiently shortened when the current discontinuous mode is switched to the current continuous mode.